Laminated structure, method of producing same, and semiconductor device

Abstract

The laminated structure (100) is a laminated structure with ohmic characteristics, in which an n-type germanium layer (10) and a metal layer (20) are bonded via a layered compound layer (30), the layered compound layer (30) is formed of a compound represented by the general formula GexBi3-xTe4 (where 0 < x ≦ 1), and the n-type germanium layer (10) and the layered compound layer (30) are bonded via a van der Waals interface.

Description

[Technical Field]

[0001] This invention relates to a multilayer structure and a method for manufacturing the same, as well as a semiconductor device.

[0002] This application claims priority based on Japanese Patent Application No. 2024-115146, filed on July 18, 2024, the contents of which are incorporated herein by reference. [Previous Technology]

[0003] Germanium (Ge) has higher electron and hole mobility than silicon (Si), leading to the development of tiny transistors that operate at low voltage.

[0004] Previously, in the bonding of metals and Ge, Fermi level pinning (FLP) near the edge of the valence electron band caused a high Schottky barrier to be formed in the bonding of most metals with n-type Ge, regardless of the work function of the metal. Recent studies have shown that when bismuth (Bi), a half-metal with a low density of states, is in contact with Si and Ge, the Fermi level pinning effect can be suppressed, thereby reducing the Schottky barrier (Non-Patent Literature 1).

[0005] [Preferred Technical Documents]

[0006] [Non-patent literature]

[0007] [Non-patent document 1] T. Nishimura, [Summary of the Invention]

[0008] [The problem the invention aims to solve]

[0009] However, the contact resistance at the interface between the metal electrode and Ge often hinders the high performance of the device. This is believed to be mainly because the interface energy level and interface state between the metal electrode and Ge cannot be sufficiently eliminated.

[0010] As is well known, Ge outperforms Si in p-type FETs (field-effect transistors). However, in n-type FETs, the interface energy level and interface state between the metal electrode and Ge can lead to a fault-limited contact (FLP), resulting in a significant problem of high contact resistance. Due to FLP, a large Schottky barrier forms between the metal electrode and n-type Ge, and there is currently no clear method to completely eliminate this barrier. Furthermore, since the CMOS circuits constituting LSIs are composed of complementary combinations of n-type and p-type FETs, reducing the contact resistance of n-type Ge is necessary.

[0011] In view of the above, this disclosure provides a multilayer structure for reducing contact resistance in an n-type Ge contact structure, a method for manufacturing the same, and a semiconductor device.

[0012] [Solutions to the problem]

[0013] In order to solve the above-mentioned problems, this disclosure provides the following means.

[0014] The disclosed sample 1 is a laminated structure with ohmic properties, in which an n-type germanium layer and a metal layer are bonded through a layered compound layer. The aforementioned layered compound layer is formed by a compound represented by the general formula GexBi3-xTe4 (but 0 < x ≦ 1). The aforementioned n-type germanium layer and the aforementioned layered compound layer are laminated structures bonded through a van der Waals interface.

[0015] The disclosed sample 2 is a laminated structure with ohmic properties, in which an n-type germanium layer and a metal layer are bonded through a layered compound layer. The aforementioned layered compound layer is formed of Bi2Te3, and the aforementioned n-type germanium layer and the aforementioned layered compound layer are laminated structures bonded through an interface layer containing Ge, Bi, Te and O.

[0016] In the layered structure of the present disclosed sample 3, the thickness of the aforementioned layered compound layer is more than 1 nm and less than 50 nm.

[0017] In the layered structure of the present disclosed sample 4, the thickness of the aforementioned layered compound layer is more than 1 nm and less than 50 nm.

[0018] In the layered structure of the present disclosed sample 5, which is sample 2 or sample 4, the thickness of the aforementioned interface layer is 1 nm or more and 5 nm or less.

[0019] The state sample 6 disclosed herein is a semiconductor device comprising any of the stacked structures of state samples 1 to 5.

[0020] The state sample 7 disclosed herein is a semiconductor device comprising a field-effect transistor having any of the layered structures of state samples 1 to 5.

[0021] The method for manufacturing a laminated structure of any of the laminated structures of the present invention is a method for manufacturing a laminated structure having a process of crystallizing the aforementioned layered compound layer by heating to form a film or by heat treatment.

[0022] [Effects of the Invention]

[0023] According to the present invention, a multilayer structure for reducing contact resistance in an n-type Ge contact structure is provided.

Implementation Method

[0025] The contents of this disclosure will be described in detail below with reference to the drawings. To facilitate understanding of the features, the drawings used in the following description may be enlarged to highlight key points, and the dimensions and proportions of each component may differ from the actual dimensions. The dimensions shown in the following description are merely examples, and the contents of this disclosure are not limited thereto. Appropriate modifications can be made to achieve the effects of this disclosure.

[0026] Hereinafter, unless otherwise specified, the configuration described in one embodiment may be applied to other embodiments.

[0027] Figure 1 is a cross-sectional schematic diagram of the layered structure of the first embodiment.

[0028] The laminated structure 100 shown in Figure 1 is an n-type germanium layer 10 and a metal layer 20 bonded through a layered compound layer 30, exhibiting ohmic properties. The layered compound layer 30 is formed of a compound represented by the general formula GexBi3-xTe4 (but 0 < x ≦ 1), and the n-type germanium layer 10 and the layered compound layer 30 are bonded through a van der Waals interface.

[0029] The multilayer structure of the first embodiment can be included in various semiconductor devices (semiconductor elements).

[0030] In the past, the contact resistance at the interface between a general metal electrode and an n-type germanium layer has been a factor that has hindered the improvement of device performance. However, in the multilayer structure of the first embodiment, by sandwiching a layered compound layer in the contact portion of the n-type germanium layer, the Schottky barrier and contact resistance in the n-type germanium contact structure are reduced.

[0031] The material of metal 20 is not particularly limited. For example, tungsten (W), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), or alloys or laminated films containing two or more of the above elements can be used.

[0032] The material of the layered compound layer 30 is a compound represented by the general formula GexBi3-xTe4 (but 0<x≦1).

[0033] The thickness of the layered compound layer 30, for example, can be greater than 1 nm. Preferably, the thickness of the layered compound layer 30 can be less than 50 nm, less than 30 nm, and more preferably less than 20 nm.

[0034] Figures 2A and 2B show cross-sectional STEM (scanning transmission electron microscopy) images near the interface between the n-type germanium layer and the layered compound layer in the stacked structure of the first embodiment. Figure 2A is a 4 millionx cross-sectional STEM image, while Figure 2B is a 20 millionx cross-sectional STEM image.

[0035] The cross-sectional STEM images in Figures 2A and 2B show that a layered contact structure is forming.

[0036] Regarding the sample with the multilayer structure of the first embodiment, a layered material Bi2Te3 was sputtered onto the surface of an n-type germanium substrate (100), and a thickness of 20 nm was deposited at a film-forming temperature of 230°C (thermal film formation). A 30 nm thick layer of tungsten (W) was then deposited on the Bi2Te3 layer, followed by annealing at 400°C. The annealing process involved heating for 1 minute and holding the temperature in an Ar atmosphere for 10 minutes. Annealing at 400°C improved the crystallinity of the layered material layer and the interfacial properties between the n-type germanium layer and the layered compound layer.

[0037] The surface used for the n-type germanium substrate can be other than the (100) surface, such as the (111) surface.

[0038] As can be seen from the cross-sectional STEM image shown in Figure 2B, the interface between the n-type germanium layer 10 and the layered compound layer 30 (the thick arrow in the figure) is an atomically flat (or steep) interface. Furthermore, the atomic arrangement of either the n-type germanium layer 10 or the layered compound layer 30, including the interface, is disordered, indicating that the n-type germanium layer 10 and the layered compound layer 30 are bonded through a van der Waals interface. In this specification, an interface with atomically flat (steep) properties, including the interface, is referred to as a van der Waals interface.

[0039] Figure 3 shows the HAADF-STEM image of the layered compound layer 30 and the elemental mapping images (EDX images) of each constituent element. Figure 3(a) is the HAADF-STEM image, Figure 3(b) is the elemental mapping image (EDX image) of Te, Figure 3(c) is the elemental mapping image (EDX image) of Bi, Figure 3(d) is the overlap of the elemental mapping images (EDX images) of Te and Bi, Figure 3(e) is the elemental mapping image (EDX image) of Ge, and Figure 3(f) is the elemental mapping image (EDX image) of O.

[0040] Figure 4 shows a cross-sectional schematic diagram of the laminated structure of the second embodiment. Hereinafter, the same reference numerals are given to the same constituent elements as those described in Figures 1 to 3, and their descriptions are omitted.

[0041] The laminated structure 200 shown in Figure 4 is an n-type germanium layer 10 and a metal layer 20 bonded through a layered compound layer 30, exhibiting ohmic properties. The layered compound layer 30 is formed by a main layered compound layer 30A made of Bi₂Te₃ and an interface layer 30B containing Ge, Bi, Te, and O. The n-type germanium layer 10 and the layered compound layer 30 are bonded through the interface layer 30B.

[0042] The multilayer structure of the second embodiment can be included in various semiconductor devices (semiconductor elements).

[0043] In the past, the contact resistance at the interface between a general metal electrode and an n-type germanium layer has been a factor that has hindered the improvement of device performance. However, in the multilayer structure of the second embodiment, by sandwiching a layered compound layer in the contact portion of the n-type germanium layer, the Schottky barrier and contact resistance in the n-type germanium contact structure are reduced.

[0044] The layered compound layer 30 is formed by a main layered compound layer 30A formed of Bi2Te3 and an interface layer 30B containing Ge, Bi, Te and O.

[0045] The thickness of the layered compound layer 30, for example, can be greater than 1 nm. Preferably, the thickness of the layered compound layer 30 can be less than 50 nm, less than 30 nm, and more preferably less than 20 nm.

[0046] The thickness of the main layered compound layer 30A, for example, can be greater than 1 nm.

[0047] The thickness of the interface layer 30B, for example, can be above 1 nm and below 5 nm.

[0048] Figure 5 shows a cross-sectional STEM (scanning transmission electron microscope) image near the interface between the n-type germanium layer and the layered compound layer in the stacked structure of the second embodiment. Figure 5 is a cross-sectional STEM image at 20 millionx magnification.

[0049] Regarding the sample with the multilayer structure of the second embodiment, a layered material Bi2Te3 was sputtered onto the surface of an n-type germanium substrate (100), and a thickness of 20 nm was deposited at a film-forming temperature of 230°C (thermal film formation). A 30 nm thick layer of tungsten (W) was then deposited on the Bi2Te3 layer, followed by annealing at 300°C. The annealing process involved heating for 1 minute and holding the temperature in an Ar atmosphere for 10 minutes. Annealing at 300°C improved the crystallinity of the layered material layer and the interfacial properties between the n-type germanium layer and the layered compound layer.

[0050] As can be seen from the cross-sectional STEM image shown in Figure 5, the interface between the n-type germanium layer 10 and the layered compound layer 30 (thick arrow in the figure) has atomic-level flatness similar to that of the stacked structure in the first embodiment, but it can be described as having high flatness when most atomic images are visible. The n-type germanium layer 10 and the layered compound layer 30 are bonded through the interface layer 30B.

[0051] At the interface between the n-type germanium layer 10 and the layered compound layer 30 in the laminated structure of the second embodiment, the peel strength is expected to be higher than that of the van der Waals interface.

[0052] Figure 6 shows the HAADF-STEM image of the layered compound layer 30 and the elemental mapping images (EDX images) of each constituent element. Figure 6(a) is the HAADF-STEM image, Figure 6(b) is the elemental mapping image (EDX image) of Te, Figure 6(c) is the elemental mapping image (EDX image) of Bi, Figure 6(d) is the overlap of the elemental mapping images (EDX images) of Te and Bi, Figure 6(e) is the elemental mapping image (EDX image) of Ge, and Figure 6(f) is the elemental mapping image (EDX image) of O.

[0053] The element mapping image is different from that of the first embodiment, especially the element mapping image of Bi is significantly different.

[0054] Figure 7 shows a comparison of the current-voltage (IV) characteristics in a conventional stacked structure for a Ge Schottky diode and a stacked structure disclosed herein. Specifically, it shows a comparison of the current-voltage (IV) characteristics in a stacked structure (conventional structure) of an n-type germanium layer (e.g., with a resistivity of ~0.1 Ω·cm) and a metal layer (tungsten, for example) and a stacked structure (disclosed herein) with a layered compound (Bi2Te3) layer sandwiched between these layers.

[0055] The layered structure disclosed herein is made in the following manner.

[0056] A layered material Bi2Te3 was sputtered onto the surface of an n-type germanium substrate (100), and a thickness of 20 nm was deposited at a film deposition temperature of 230°C (thermal deposition). A 30 nm thick layer of tungsten (W) was then deposited on the layered material. Next, the electrode region was defined using optical microlithography. Electrode metal was formed by dry etching. Then, the sample was annealed at 300°C to 400°C to obtain the sample. The annealing process involved heating for 1 minute and holding the sample in an Ar atmosphere for 10 minutes.

[0057] As shown in Figure 7, in the stacked structure of the metal bonding (metal contact) with the conventional structure, the current is small when a reverse voltage is applied and it does not have ohmic characteristics. However, in the stacked structure of the present invention with the sandwiched layer of layered compound (Bi2Te3) layer, the current increases when a reverse voltage is applied, the relevant current difference is almost non-existent when a forward voltage is applied, and it has ohmic characteristics.

[0058] In this way, by using Bi2Te3 contacts, an ohmic contact for n-type Ge can be formed. This is direct evidence of the reduction of the Schottky barrier.

[0059] Figure 8A shows the temperature dependence of the current-voltage (IV) characteristics of the stacked structure disclosed herein.

[0060] In addition, Figure 8B shows the Arrhenius plot as a function of temperature.

[0061] It is known that the Schottky barrier between Bi₂Te₃ and Ge is below 0.1 eV. This can be attributed to the low density of states of the layered material Bi₂Te₃ and the formation of the Van der Waals interface.

[0062] Figure 9A shows the results of X-ray diffraction (XRD) of the laminated structures disclosed herein before annealing (As-deposited) and after annealing at temperatures of 250°C, 300°C, and 400°C. The annealing was performed by heating for 1 minute and holding for 10 minutes in an Ar atmosphere.

[0063] It can be seen that the peak value of the XRD pattern of the Bi2Te3 crystalline phase of the sample prepared at an annealing temperature of 300℃ is offset from the peak value of the XRD pattern of the Bi2Te3 crystalline phase of the sample prepared at an annealing temperature of 400℃.

[0064] Figure 9B shows the results of current-voltage (IV) characteristics for the stacked structure disclosed herein before deposition and before annealing (As-deposited), at annealing temperature of 300°C and at annealing temperature of 400°C.

[0065] It can be seen that the ohmic characteristics of the Ge Schottky diode fabricated at 400°C are improved compared to the Ge Schottky diode fabricated at an annealing temperature of 300°C. The ohmic characteristics of the Ge Schottky diode fabricated at 500°C are slightly worse than those of the Ge Schottky diode fabricated at 400°C.

[0066] Comparing the XRD results and the IV characteristic measurement results, and even with the aforementioned cross-sectional STEM images and elemental mapping images, it can be seen that in the laminated structure produced by post-annealing at 400°C, the ohmic properties are significantly improved because the n-type germanium layer and the layered compound layer are bonded by a van der Waals interface to form the laminated structure. On the other hand, the laminated structure produced by post-annealing at 300°C fails to achieve van der Waals bonding, and it is known that high ohmic properties can be obtained through bonding with a thin interface layer.

[0067] Using GeBi2Te4 (database) with the crystal structure shown in Figure 10A as a reference, assuming that y in Ge1-yBiy is mixed with Ge and Bi in increments of 0.1 between 0 and 1, the occupancy of Ge sites was simulated, and the results of the composition dependence study of its XRD pattern are shown in Figure 10B. Figure 10C shows the XRD pattern of the laminated structure prepared by post-annealing at 400℃.

[0068] As can be seen from the simulated XRD pattern shown in Figure 10B, as x increases, the peak value near 2θ=13˚ decreases, while the peak value near 2θ=20˚ increases.

[0069] In the simulated XRD pattern shown in Figure 10B, the intensity ratio of the peak near 2θ=13˚ and the peak near 2θ=20˚ is similar to that in the XRD pattern of Figure 10C when y=0.8.

[0070] Based on this result, it is speculated that the layered compound layer in the stacked structure produced by post-annealing at 400°C is formed by a compound represented by the general formula GexBi3-xTe4 (but 0 < x < 1).

[0071] (Method for manufacturing layered structures)

[0072] The method for manufacturing the laminated structure disclosed herein is characterized by having a process for crystallizing the layered compound layer in the laminated structure disclosed herein by means of heating to form a film or heat treatment.

[0073] Here, "heating to form a film" refers to heating the n-type Ge layer or the n-type Ge substrate to form a film while crystallizing the layered compound layer. "Heat treatment" refers to heat treatment performed after the layered compound layer has been formed to crystallize it.

[0074] (Applicable Example 1)

[0075] An example of the multilayer structure disclosed herein shown in FIG11A is applied to the top-gate field-effect transistor (FET) shown in FIG11B. FIG11A and FIG11B are schematic cross-sectional views. The constituent elements given the same symbols as above have the same functional uses, and therefore their descriptions are omitted.

[0076] In an example of the layered structure disclosed herein shown in FIG11A, metal layers, denoted by symbols 20A and 20B, are separately configured. Furthermore, layered compound layers, denoted by symbols 30A and 30B, are separately configured between the n-type germanium layer 10 and the metal layer 20A, and between the n-type germanium layer 10 and the metal layer 20B.

[0077] In the field-effect transistor shown in Figure 11B, metal layer 20A and metal layer 20B are the source / drain, the one indicated by symbol 40 is the gate insulating film, the one indicated by symbol 50 is the gate, the one indicated by symbol 60 is the interlayer insulating film, and symbols 20AA and 20BB are the plug electrodes connecting the source / drain 20A and 20B, respectively.

[0078] Known gate insulating film materials can be used as the material of the gate insulating film 40, such as oxide films such as SiO2, Al2O3, HfO2, ZrO2, Y2O3, and La2O3.

[0079] Alternatively, known interlayer insulating film materials can be used as the material of the interlayer insulating film 60, such as oxide films such as SiO2 and nitride films such as SiN.

[0080] Known gate materials can be used as the material of gate 50, such as tungsten (W), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), or alloys or laminated films containing two or more of the above elements.

[0081] (Applicable Example 2)

[0082] An example of the multilayer structure disclosed herein shown in FIG11A is applied to the field effect transistor (FET) shown in FIG12. FIG12 is a schematic cross-sectional view. The constituent elements given the same symbols as above have the same functional uses, so their description is omitted.

[0083] In the photoFET ​​shown in Figure 12, the symbol 70 represents the insulating film, such as an oxide film like SiO2 or a nitride film like SiN. Furthermore, the symbol 80 represents the semiconductor substrate, such as a substrate formed of silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), sapphire (Al2O3), or a glass substrate. [Simplified Explanation of the Diagram]

[0024] Figure 1 is a cross-sectional schematic diagram of the stacked structure of the first embodiment. Figure 2A is a 4 millionx cross-sectional STEM image of the interface between the n-type germanium layer and the layered compound layer in the stacked structure of the first embodiment. Figure 2B is a 20 millionx cross-sectional STEM image of the interface between the n-type germanium layer and the layered compound layer in the stacked structure of the first embodiment. Figure 3(a) is a HAADF-STEM image, (b) is an elemental mapping image (EDX image) of Te, (c) is an elemental mapping image (EDX image) of Bi, (d) is the overlap of the elemental mapping images (EDX images) of Te and Bi, (e) is an elemental mapping image (EDX image) of Ge, and (f) is an elemental mapping image (EDX image) of O. Figure 4 is a cross-sectional schematic diagram of the stacked structure of the second embodiment. Figure 5 is a 20-million-fold cross-sectional STEM image of the interface between the n-type germanium layer and the layered compound layer in the stacked structure of the second embodiment. Figure 6(a) is a HAADF-STEM image, (b) is an elemental mapping image (EDX image) of Te, (c) is an elemental mapping image (EDX image) of Bi, (d) is the overlap of the elemental mapping images (EDX images) of Te and Bi, (e) is an elemental mapping image (EDX image) of Ge, and (f) is an elemental mapping image (EDX image) of O. Figure 7 shows a comparison of the current-voltage (IV) characteristics in the conventional stacked structure and the stacked structure disclosed herein. Figure 8A shows the temperature dependence of the current-voltage (IV) characteristics of the stacked structure disclosed herein. Figure 8B is an Arrhenius plot of the temperature function. Figure 9A shows the X-ray diffraction (XRD) results for the stacked structure disclosed herein, before annealing and after annealing at temperatures of 250°C, 300°C, and 400°C. Figure 9B shows the current-voltage (IV) characteristics for the stacked structure disclosed herein, before annealing, at annealing temperatures of 300°C, and at annealing temperatures of 400°C. Figure 10A shows the crystal structure of GeBi2Te4 (database). Figure 10B shows the results of simulation based on the crystal structure shown in Figure 10A, investigating the compositional correlation of its XRD pattern. Figure 10C shows the XRD pattern of the stacked structure fabricated by annealing at 400°C. Figure 11A is a cross-sectional schematic diagram of an example of the stacked structure disclosed herein. Figure 11B is a cross-sectional schematic diagram of the example of the stacked structure disclosed herein shown in Figure 11A applied to a top-gate field-effect transistor. Figure 12 is a cross-sectional schematic diagram of an example of the multilayer structure disclosed herein shown in Figure 11A, applied to a photoelectric field-effect transistor.

Claims

1. A laminated structure, wherein an n-type germanium layer and a metal layer are bonded through layered compound layers, exhibiting ohmic properties, wherein: The aforementioned layered compound layer is formed by a compound represented by the general formula GexBi3-xTe4 (but 0 < x ≦ 1), and the aforementioned n-type germanium layer and the aforementioned layered compound layer are bonded through a van der Waals interface.

2. A laminated structure, wherein an n-type germanium layer and a metal layer are bonded through layered compound layers, exhibiting ohmic properties, wherein: The aforementioned layered compound layer is formed of Bi2Te3. The aforementioned n-type germanium layer and the aforementioned layered compound layer are bonded through an interface layer containing Ge, Bi, Te and O. The film thickness of the aforementioned layered compound layer is 1 nm or more and 50 nm or less.

3. As described in claim 1, the thickness of the aforementioned layered compound layer is 1 nm or more and 50 nm or less.

4. As described in claim 2, the thickness of the aforementioned interface layer is 1 nm or more and 5 nm or less.

5. A semiconductor device comprising a multilayer structure as described in any one of claims 1 to 4.

6. A semiconductor device comprising a field-effect transistor having a multilayer structure as described in any one of claims 1 to 4.

7. A method for manufacturing a laminated structure, comprising: A process of crystallizing the aforementioned layered compound layer by either heating to form a film or heat treatment.

Images