Method of forming a buried portion of a top electrode in semiconductor detectors

Abstract

This invention describes a detector for use in a critical-size scanning electron microscope (CD-SEM) and re-inspection SEM system. In one embodiment, the detector includes a semiconductor structure having a pn junction and an aperture through which a scanning beam is delivered to a target. The detector also includes a top electrode (e.g., an anode or cathode) for the pn junction, the top electrode providing an active region for detecting electrons or electromagnetic radiation (e.g., backscattering from the target). The top electrode has a doped layer and may also have a buried portion beneath the doped layer to reduce a series resistance of the top electrode without altering the active region. In another embodiment, an isolation structure may be formed in the semiconductor structure near the sidewalls of the aperture to electrically isolate the active region from the sidewalls. A method for forming the buried portion of the top electrode is also described.

Description

[Technical Field]

[0001] The present invention generally relates to radiation detectors, such as those that can be used in, for example, scanning electron microscope (SEM) systems. [Previous Technology]

[0002] Radiation detectors are used in a variety of applications. Here and elsewhere, the term "radiation" refers to electromagnetic waves and moving particles. For example, in the manufacturing process of integrated circuit (IC) components, unfinished or completed circuit components are inspected to ensure they are manufactured according to a specified design and are free of defects. Inspection systems such as SEM, which utilize optical microscopes or charged particle (e.g., electron) beam microscopes, can be used. As the physical size of various features of IC components continues to shrink, the accuracy and yield achieved by such inspection systems become increasingly important. Currently, such systems tend to be at least in part limited by the sensitivity and speed of semiconductor radiation detectors (or simply semiconductor detectors) used to detect backscattered or secondary electrons from the target being inspected. Therefore, there is a high demand for improvements in the performance of semiconductor detectors. [Summary of the Invention]

[0003] The following presents a simplified overview of one or more embodiments of the present invention to provide a basic understanding of such embodiments. This overview is not a comprehensive summary of all anticipated embodiments, nor is it intended to identify key or defining elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as an introduction to the more detailed description that follows.

[0004] One embodiment describes a detector having a semiconductor structure having an aperture through which a scanning beam is transmitted to a target, wherein the semiconductor structure includes a pn junction. The detector also has a top electrode for the pn junction, wherein the top electrode provides an active region for detecting electronic or electromagnetic radiation, wherein the top electrode includes a doped layer and a buried portion beneath the doped layer, and wherein the buried portion is configured to reduce a series resistance of the top electrode without changing the active region provided for detection.

[0005] Another embodiment describes a detector having a semiconductor structure having an aperture through which a scanning beam is transmitted to a target, wherein the semiconductor structure includes a pn junction. The detector also has a top electrode for the pn junction, wherein the top electrode provides an active region for detecting electronic or electromagnetic radiation, and wherein the top electrode includes a doped layer. The detector also has an isolation structure formed in the semiconductor structure near the sidewalls of the aperture, wherein the isolation structure is configured to electrically isolate the active region from the sidewalls of the aperture.

[0006] Another embodiment describes a detector having a semiconductor structure having an aperture through which a scanning beam is transmitted to a target, wherein the semiconductor structure includes a pn junction. The detector also has a top electrode for the pn junction, wherein the top electrode provides an active region for detecting electronic or electromagnetic radiation, wherein the top electrode includes a doped layer and a buried portion beneath the doped layer, and wherein the buried portion is configured to reduce a series resistance of the top electrode without altering the active region provided for detection. The detector also has an isolation structure formed in the semiconductor structure near the sidewalls of the aperture, wherein the isolation structure is configured to electrically isolate the active region from the sidewalls of the aperture.

[0007] Another embodiment describes a method for forming an embedded portion of a top electrode in a semiconductor detector, the method comprising: depositing a dopant layer on a surface of a semiconductor structure having an active region of the top electrode; and then applying a heat treatment to drive dopant from the dopant layer into the semiconductor structure and at least partially drive it under the detection layer of the top electrode to form the embedded portion of the top electrode.

[0008] According to another embodiment, a method for manufacturing a semiconductor detector is disclosed. The semiconductor detector includes an element for generating a signal in response to received radiation and circuitry electrically connected to the element. The circuitry includes at least one structure that cannot withstand a processing temperature exceeding a temperature T. The method includes the steps of: manufacturing a first portion of the circuit capable of withstanding the temperature T; performing a processing step at the temperature T; and manufacturing a second portion of the circuit, the second portion including a structure that cannot withstand the temperature T. Performing a processing step at the temperature T may include performing high-temperature chemical vapor deposition (HTCVD). Performing HTCVD may include performing HTCVD of boron. Performing HTCVD of boron may include HTCVD of pure boron. Manufacturing the first portion of the circuit may include partially manufacturing a CMOS circuit. Manufacturing the second portion of the circuit includes completing the manufacturing of the CMOS circuit. The temperature T may be higher than 700°C.

[0009] According to another embodiment, a method for manufacturing a semiconductor detector is disclosed. The detector includes an element for generating a signal in response to received radiation and a CMOS circuit electrically connected to the element. The CMOS circuit includes at least one structure that cannot withstand a processing temperature T exceeding 700°C. The method includes the steps of: manufacturing a first portion of the CMOS circuit that can withstand the temperature T; performing an HT PureB CVD processing step at the temperature T; and manufacturing a second portion of the CMOS circuit that includes a structure that cannot withstand the temperature T.

[0010] According to another embodiment, a process for manufacturing a single-crystal semiconductor radiation detector is disclosed. This process includes the following steps: providing a starter wafer; performing a first partial circuit formation step on a processed side of the starter wafer to form a first partial circuit layer, the first partial circuit formation step being limited to forming a circuit capable of withstanding a processing temperature T; bonding a first bonding wafer to the first partial circuit layer; etching away a portion of the starter wafer to expose the first partial circuit layer; depositing a boron layer on the first partial circuit layer; bonding a second bonding wafer to the boron layer; debonding the first bonding wafer from the first partial circuit layer; performing a second partial circuit formation step on the first partial circuit layer to form a complete circuit layer, the second partial circuit formation step including forming a circuit structure unable to withstand the processing temperature T; bonding a third bonding layer to the complete circuit layer; and debonding the second bonding wafer from the boron layer. Performing a first partial circuit formation step may include performing a first partial CMOS circuit formation step. Performing a second-part circuit formation step on the first-part circuit layer to form a complete circuit layer may include performing a second-part CMOS circuit formation step on the first-part circuit layer to form a complete CMOS circuit layer. Depositing a boron layer on the first-part circuit layer includes using HT PureB CVD. The temperature T can be higher than 700°C.

[0011] According to another embodiment, a single-crystal semiconductor detector is disclosed, comprising an element for generating a signal in response to received radiation and a CMOS circuit electrically connected to the element, the CMOS circuit including at least one structure that cannot withstand a processing temperature T exceeding 700°C, the detector being manufactured by a method comprising the following steps: manufacturing a first portion of the CMOS circuit that can withstand the temperature T; performing an HT PureB CVD processing step at the temperature T; and manufacturing a second portion of the CMOS circuit that includes a structure that cannot withstand the temperature T.

[0012] To achieve the foregoing and related objectives, the embodiments include features described below and specifically pointed out in the claims. The following description and accompanying drawings illustrate certain illustrative features of one or more embodiments in detail. However, these features only indicate a few of the various ways in which the principles of various embodiments can be used, and this description is intended to include all such embodiments and their equivalents.

Implementation Method

[0027] As mentioned above, inspection systems utilizing optical microscopes or charged particle (e.g., electron) beam microscopes (such as SEM) can be used to inspect completed or incomplete IC components (e.g., semiconductor wafer or die inspection). As the critical dimensions of IC components continue to shrink, leading to an increase in the number of transistors, and as the overall yield of inspection systems is pushed higher, the accuracy, yield, and speed achieved by such inspection systems become increasingly important. One of the key components of such systems is a semiconductor detector, which is used to profile any errors or inconsistencies arising from the manufacturing process by detecting backscattered or secondary electrons from the target being inspected. With higher yields, more sensitive or faster semiconductor detectors can help ensure that sufficient information is detected at a higher speed. Improvements in accuracy, yield, or speed can be achieved with semiconductor detectors having improved sensitivity or higher bandwidth, or other features described herein. This invention describes various techniques, such as those for improving the sensitivity of a semiconductor detector by, for example, increasing the operating area of ​​the semiconductor detector, or for improving the bandwidth of a semiconductor detector by, for example, reducing the series resistance of the semiconductor detector to shorten its time constant.

[0028] Examples of embodiments will now be described in detail with reference to the accompanying drawings. The following description refers to the accompanying drawings, wherein, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described below do not represent all embodiments of the invention. Instead, they are merely examples of structures and processes consistent with the disclosures set forth in the claims. For example, although some embodiments of the invention are described in the context of detection systems using electronic scanning and detection, such embodiments may also be applied to other types of detection systems.

[0029] Figure 1A shows a diagram 100a illustrating a general representation of a SEM system (e.g., an inspection system). An SEM system may also be referred to as an electron beam system / e-beam system. Diagram 100a includes a source 110 that provides a scanning beam 115 (e.g., an electron beam) that passes through an aperture 125 of a detector 120 (e.g., a semiconductor detector) and is aimed at a target 130 (e.g., a wafer or die being inspected). The aperture 125 may be located at the center of the detector 120 or at some other location within the detector 120. Because the detector 120 is aligned between the source 110 and the target 130, the detector 120 may be referred to as an in-lens detector. The axis formed by the vertical positioning of the source 110 and the detector 120 may be referred to as the optical axis of the SEM system.

[0030] The scanning beam 115 is used to characterize one or more features on the top surface of the target 130, thereby generating backscattered or secondary electrons 135, which reach the downward-facing surface of the detector 120 for detection. Based on the electrons 135 received by the detector 120, the detector 120 may then generate and provide a signal (not shown) conveying information associated with the detected features of the target 130, wherein this information is subsequently used to generate a SEM image of the scanned target. In some embodiments, the source 110 may generate and provide more than one scanning beam 115 to allow the detection of multiple targets.

[0031] Figure 1B shows a diagram 100b illustrating a general representation of an off-axis SEM system. In this example, the detector 120 can be placed in a secondary axis 170, which is different from the main axis 140 of the scanning beam 115. In this case, the detector 120 can be referred to as an off-axis detector and does not need to have an aperture 125 through which the scanning beam 115 passes.

[0032] The SEM system shown in Figure 100b also includes a source 110 (or a similar electronic or radiation source), a bore plate 145, a condenser lens 150, a source conversion unit 155, a primary projection system 160, and a target 130, all aligned with the main axis 140. A beam splitter 175 and a deflection scanning unit 180 may be housed within the primary projection system 160. The primary projection system 160 may also include an objective lens 185. The SEM system in Figure 100b also includes a secondary imaging system 165, which, together with the detector 120, is aligned with the secondary axis 170.

[0033] The beam splitter 175 can be configured to deflect the secondary electrons 135 (e.g., or a beam having the secondary electrons 135) at an angle α in the direction of the secondary imaging system 165. Angle α can be determined as the angle between the main axis 140 and the secondary axis 170; therefore, angle α can represent the separation angle between the on-axis scanning beam 115 and the secondary electrons 135 guided by the beam splitter 175 in the direction of the secondary imaging system 165 and the off-axis detector 120. In some embodiments, angle α can be set to a range of 5 degrees to 25 degrees.

[0034] The in-lens or off-axis detector 120 may be a secondary electron (SE) detector, comprising a single silicon PIN photodiode with a diameter of approximately 20 mm and an aperture 125 with a diameter of approximately 0.5 mm for allowing a primary electron beam to pass through (e.g., scanning beam 115). In this invention, the terms "about" or "approximately" may refer to a value relative to a nominal value, wherein the difference between the two values ​​may be less than 1%, between 1% and 5%, between 1% and 10%, or between 1% and 20%.

[0035] An aluminum (Al) coating of about 50 nanometers (nm) is typically present on the top of the surface of the PIN photodiode to improve series resistance and reflect any stray light (e.g., light from a laser and scattered inside the pillar of a SEM system).

[0036] Semiconductor detectors used for detector 120 (e.g., a single silicon PIN photodiode) have been primarily used as in-lens detectors in electron beam / e-beam wafer inspection systems. On the other hand, Everhart-Sornley detectors (ET detectors), composed of scintillators and photomultiplier tubes (PMTs), have been used in critical dimension SEM (CD-SEM) and re-inspection SEM systems. By using semiconductor detectors instead of ET detectors, wafer inspection systems can typically operate with high inspection yields, featuring 10 to 100 times higher beam current and higher detection bandwidth for imaging. Therefore, although semiconductor detectors offer a relatively higher noise floor compared to ET detectors, they are a natural choice due to their superior bandwidth and robustness against radiation damage.

[0037] As semiconductor wafer designs continue to miniaturize (e.g., reducing critical dimensions or CD), even electron beam wafer inspection systems now often operate at extremely low beam currents to ensure the necessary resolution for SEM images. As this trend continues, it will be necessary to reduce the noise floor of semiconductor detectors used for SEM scanning in order to prevent the SNR from exceeding the small output current generated by the semiconductor detectors.

[0038] In a typical wafer inspection system, a delayed objective SEM column configuration is used, in which the wafer being inspected (e.g., target 130) is biased to a negative high voltage of Vw to achieve a conduction drop energy (Vle) of V volts, consistent with the expression shown below: Vle = Vc - Vw, where Vc is the accelerating voltage of the electron beam cathode. Secondary electrons (e.g., electrons 135) emitted from the wafer surface in response to the scanning beam 115 are accelerated to (Vc - Vw) eV and strike the surface of the detector 120 with this kinetic energy.

[0039] In one example, the cathode voltage Vc may be -10 kilovolts (kV) or greater, such that the kinetic energy of electrons (e.g., electron 135) incident on detector 120 is kept at least above 8 keV. Electrons reaching the surface of detector 120 must reach the depletion region, which passes through the p++ layer and the thickness of the np junction, as well as the top aluminum coating used to reflect scattered photons. If the electron kinetic energy drops below 8 keV, the quantum efficiency drops sharply because the signal current change per electron decreases, thus degrading the SNR of the SEM image. However, there may be situations where, for the specific needs of constructing the SEM system and for system reliability and cost, it is necessary to keep the cathode voltage below 6 kV. In such cases, it may be necessary for detector 120 to allow most incident electrons to reach the depletion region with minimal energy loss in order to minimize the SNR degradation of the SEM image.

[0040] Although off-axis detectors (e.g., detector 120 in the sub-axis in diagram 100b of FIG. 1B) do not need to have holes, in-lens or on-axis detectors (e.g., in-lens detector 120 in diagram 100a of FIG. 1A) require holes (e.g., hole 125) for the primary electron beam (e.g., scanning beam 115) to pass through, wherein the distance between the inner diameter (ID) surface of the hole and the active detection surface must be properly designed to minimize additional dark current.

[0041] As mentioned above, the detector in an electron beam detection system needs to support high bandwidth to achieve high detection yield, which involves the use of relatively large beam current. The bandwidth of the detector depends at least in part on the junction capacitance and series resistance. Therefore, if the delay objective SEM column will be used with a cathode voltage fixed at a low value (such as 6KV), the series resistance needs to be reduced or lowered to provide a shorter time constant (e.g., faster response, higher bandwidth) for the detector within the lens, without reducing the probability that electrons reaching the detector surface also reach the depletion region to maintain high quantum efficiency.

[0042] For CD-SEM applications, there are several challenges related to the detector design required for resolution. CD-SEM applications require low beam or probe current to maintain good resolution, resulting in extremely low total beam dose. In this case, extremely low circuit noise levels are needed to maintain acceptable SNR and thus good image quality. Existing PIN photodiode detectors combined with preamplifier circuitry do not meet these requirements in terms of noise performance. In current preamplifier designs, detector capacitance is a significant factor affecting not only bandwidth but also noise.

[0043] To address at least some of these problems, a thin layer can be added to the detector to improve collection efficiency. In some implementations, this thin layer comprises boron (B), and a detector with a boron layer may be referred to as a pure B detector. The boron layer is typically a few nanometers of pure or nearly pure amorphous boron. Layers using other elements in pure or nearly pure form and providing functionality similar to that of a pure boron layer can also be used. However, this detector must still meet the requirements of low capacitance and fast response time. Due to the requirements of low beam or probe current, low conduction drop energy, and high bandwidth, the corresponding signal (e.g., secondary electrons or SE electrons) generated by detector 120 is much lower than in existing platforms. Therefore, it is necessary to keep the detector's collection efficiency as high as possible—the proposed boron layer in the pure B detector achieves this thanks to the unique design characteristics of the boron layer—and maximize the fill factor (e.g., the detector's detection or active area) by reducing any unused or non-active areas, which may include any "safety margin" from the active area to the edge of the hole 125 and any isolation areas between different segments of the detector.

[0044] In some cases, secondary or backscattered electrons from the top surface of target 130 will be accelerated back by a field of approximately 5 keV along the optical axis. The spatial distribution of secondary electrons on the surface of detector 120 is approximately Gaussian (see, for example, Figure 3), although the spread of the curve depends on the operating conditions, the distribution is centered on the optical axis. To increase signal power, and therefore improve SNR, it is desirable to make the non-active region as small as possible while still maintaining low leakage current.

[0045] The use of a pure boron layer as applied to electron detection results in a high sheet resistance (e.g., approximately 10 kΩ × cm) for a nano-thin boron layer. For fast-response electron detectors, a low series resistance on the top electrode (e.g., the anode) is generally preferred, allowing for a faster response time, along with a low capacitance per unit area. Current solutions to reduce the series resistance of the pure boron layer on the top electrode involve forming an aluminum (Al) grid on top of the boron layer (see, for example, Figure 2A). This results in a loss of active area because electrons deflected onto the aluminum grid will not reach the depletion region and will not be detected. The aluminum grid also creates a configuration in the active area that can interfere with the detection of incident electrons.

[0046] Figure 2A shows a schematic diagram 200a illustrating a partial cross-sectional view of a semiconductor detector (e.g., detector 120) having an external aluminum (Al) grid 240 on the top electrode 250. This semiconductor detector can be an in-lens / on-axis semiconductor detector (see, for example, Figure 1A) or an off-axis semiconductor detector (see, for example, Figure 1B). In schematic diagram 200a, detector 120 includes a semiconductor structure 210 (e.g., a silicon-based photodiode) and a top electrode 250. The semiconductor structure 210 can be a high resistivity (HR) semiconductor layer and includes a pn junction (not shown) that generates a depletion region (not illustrated). The pn junction can be a pin junction for forming a PIN photodiode in the semiconductor structure 210. An isolation layer 220 between the top electrode 250 and the semiconductor structure 210 is also shown in Figure 2A.

[0047] The top electrode 250 provides an effective region 245 for detecting electrons (or electromagnetic radiation). That is, the top electrode 250 is placed on the surface of the detector 120 facing the target 130 and receives secondary or backscattered electrons 135 from the target 130. The top electrode 250 includes a doped layer 230 (which may be referred to as a detection layer), which may be doped with pure boron to provide the boron layer discussed above for improving the collection efficiency of the detector 120.

[0048] As mentioned above, the use of the aluminum grid 240 results in a loss of the effective area 245. This is because the aluminum grid 240 blocks electrons that have been deflected onto the aluminum grid 240 from reaching the depletion region of the pn junction and thus will not be detected. In addition, the aluminum grid 240 also creates a configuration in the effective area (e.g., a height variation on the surface of the detector 120), which can interfere with the detection of incident electrons.

[0049] An alternative would be to form an "embedded grid" or "embedded portion" of the top electrode 250 (see, for example, FIG. 2B). This embedded grid is considered a better solution than the aluminum grid 240 to reduce the series resistance of the photodiode with a boron layer (e.g., doped layer 230) because it will not cause a loss of the active or detection area 245, thus there will be no configuration in the active area 245, and soft materials such as aluminum will not be used in the active area 245.

[0050] Figure 2B shows illustration 200b of a partial cross-sectional view of a semiconductor detector (e.g., detector 120) having an embedded portion 260 within a top electrode 250. In this example, the aluminum grid 240 shown in illustration 200a is absent. Instead, the top electrode 250 includes a doped layer 230 (e.g., a boron layer or other layer with similar functionality) and an embedded portion 260 beneath the doped layer 230, wherein the embedded portion 260 is configured to reduce the series resistance of the top electrode 250 without altering the active area 245 provided for detection.

[0051] In one embodiment, for the semiconductor detector in FIG2B, the semiconductor structure 210 is a silicon-based semiconductor structure, the top electrode 250 is an anode electrode, and the doped layer 230 is doped with a p-type dopant. The embedded portion 260 of the top electrode 250 is formed by heat treatment with a dopant of the same type as that of the doped layer 230 (see, for example, FIG6). Therefore, in this case, the embedded portion 260 of the top electrode 250 is a low resistivity (LR) p-type region, while the semiconductor structure 210 is a high resistivity (HR) n-type layer. The dopant used to form the embedded portion 260 of the top electrode 250 can be deposited onto the semiconductor structure 210 by various types of implantation processes, one of which can be a chemical vapor deposition (CVD) process. Furthermore, as mentioned above, the p-type dopant of the doped layer 230 includes boron. In some implementations, the p-type dopant of the doped layer 230 may be a different element (or a composite element or alloy), which may be at least partially selected from, for example, the same row of the periodic table as boron.

[0052] In another embodiment, for the semiconductor detector in FIG2B, the semiconductor structure 210 is again a silicon-based semiconductor structure, the top electrode 250 is now a cathode electrode, and the doped layer 230 is doped with an n-type dopant. In this embodiment, the doped layer 230 is not a boron layer because it is n-type doped, but when the top electrode 250 is an anode electrode, it plays the same or similar role as a boron layer. The embedded portion 260 of the top electrode 250 is again formed by heat treatment with a dopant of the same type as that of the doped layer 230 (see, for example, FIG6), and the dopant used to form the embedded portion 260 of the top electrode 250 can also be deposited onto the semiconductor structure 210 by a CVD process. Therefore, in this case, the embedded portion 260 of the top electrode 250 is an LR n-type region, and the semiconductor structure 210 is an HR p-type layer. The dopant used for the embedded portion 260 of the top electrode 250 and the doped layer 230 can be different n-type dopants. In addition, the n-type dopant of the doped layer 230 may include one or more of arsenic, phosphorus or antimony.

[0053] As should be understood from the diagrams 200a and 200b in Figures 2A and 2B respectively, the top electrode 250 may also include a top electrode metal contact 270 disposed above the periphery of the semiconductor structure 210 and partially overlapping the doped layer 230 of the top electrode, wherein the embedded portion 260 of the top electrode 250 enables the current generated by the pn junction according to the detection of electrons (or electromagnetic radiation) to be available at the top electrode metal contact 270.

[0054] Alternatively or additionally, the goal of reducing the series resistance of the top electrode 250 can be achieved by covering the pure boron layer (e.g., doped layer 230) of the top electrode 250 with a thin low resistivity (LR) layer and / or by controlled top electrode (e.g., anode) doping drive (e.g., when the top electrode 250 is an anode electrode). The corresponding reduction in electron relative gain is expected to be negligible with respect to the electron energy of interest, and therefore this approach should not significantly affect the collection efficiency. These three alternatives—the use of an embedded grid or embedded portion, a thin LR capping layer, and top electrode drive—can be used individually or in some combination to reduce the series resistance of the detector 120.

[0055] Figure 2C shows a partial cross-sectional view of a semiconductor detector (e.g., detector 120) having an embedded portion 260 within a top electrode 250 and a capping layer 280. As shown in Figure 200c, the capping layer 280, which may include one or more LR layers, may be disposed above the doped layer 230. Furthermore, the capping layer 280 may be made of a conductive material.

[0056] It should be understood that each of the semiconductor detectors shown in Figures 2A to 2C may be a secondary electron (SE) detector configured to detect secondary electrons and / or backscattered electrons from a target (e.g., target 130), or a radiation detector configured to detect electromagnetic radiation generated by or backscattered from the target (e.g., target 130).

[0057] Another relevant aspect of the present invention that directly affects the performance of a particular electron detector is the extent of the "non-active region" around the aperture (e.g., aperture 125 in diagram 100a of FIG. 1A) through which the primary beam transmission (e.g., scanning beam 115) passes. Ideally, this non-active region should be as small as possible, since the secondary electron (SE) position distribution is largely concentrated around the aperture. FIG. 3 shows a plot 300 of simulated electron position distribution on the detector plane, where it is evident that most electrons reach the center of the detector, and the larger the "non-active region" around the aperture, the fewer electrons will be detected. Therefore, another aspect of the present invention is to minimize any "non-active region" in the detector 120 to improve overall efficiency and / or sensitivity.

[0058] In existing semiconductor detector designs, the limitation to reducing this "non-active region" is the lateral extent of the deep depletion region required for a fast response (e.g., reduced junction capacitance). In fact, it is best if the depletion layer does not reach the surface of the hole 125 to prevent a significant increase in leakage current (e.g., in the segment of the detector 120 closest to the hole 125).

[0059] Figure 4A shows a schematic diagram 400a illustrating a partial cross-sectional view of a semiconductor detector (e.g., detector 120) having a large "non-active region" 410a around the aperture 125. In this example, the "non-active region" 410a covers the area between the top electrode metal contacts 270 of the top electrode 250, including the aperture 125 and the adjacent area. In this example, the first layer 420 and the second layer 425 form a pn junction, which generates a depletion region 427 extending into the second layer 425 with a certain depletion length (e.g., the depth or thickness of a depletion region 427) based on an applied reverse bias voltage. This depletion length is large enough to reduce the junction capacitance of the pn junction in the semiconductor structure 210. This increases the response time and bandwidth of the semiconductor detector. In some implementations, the first layer is a p-type doped layer of 420 and the second layer is an n-type doped layer of 425 (e.g., a high-resistivity n-type device layer), while in other implementations, the first layer is an n-type doped layer of 420 and the second layer is a p-type doped layer of 425. However, a large depletion region 427 also extends laterally. To prevent the depletion region 427 from reaching the sidewall 430 of the via 125, which would cause an increase in leakage current, the top electrode 250 is configured so that its active area is away from the via 125, thus creating a large "non-active region" 410a found in existing semiconductor detector designs.

[0060] This invention proposes an approach different from that described in Figure 400a. Figures 4B and 4C respectively illustrate partial cross-sectional views of semiconductor detectors (e.g., detector 120) with isolation structures used to create small or smaller "non-active regions" around the holes 125 of such semiconductor detectors. For example, the "non-active region" 410b in Figure 400b and the "non-active region" 410c in Figure 400c are smaller than the "non-active region" 410a in Figure 400a.

[0061] For example, in diagram 400b, an isolation structure 440 is included in semiconductor structure 210 to isolate depletion region 427 from sidewall 430 of via 125. Isolation structure 440 is formed near sidewall 430 of via 125 and includes a deep trench 445 and doped sidewall 450 to provide a defect-free stop plane that limits the lateral extension of depletion region 427 in the direction of via 125. Deep trench 445 may be filled with, for example, an insulating material, such as a dielectric material (e.g., an oxide). Doping of sidewall 450 may be, for example, a doping or doping type opposite to that of the second layer 425. This allows the "non-active region" 410b between via 125 and the active region provided by top electrode 250 to be reduced to tens of micrometers, and therefore, it is anticipated that having a smaller "non-active region" 410b will provide a significant improvement in the detection of secondary electrons and / or backscattered electrons (e.g., electron 135). In this example, the distance between the isolation structure 440 and the sidewall 430 of the hole 125 can be less than 60 micrometers. Therefore, the isolation structure 440 with deep trench 445 and doped sidewall 450 can be substantially parallel to the sidewall 430 of the hole 125 but not in contact with the sidewall 430 of the hole 125.

[0062] In diagram 400c, an isolation structure 460 is included in semiconductor structure 210 to isolate depletion region 427 from sidewall 430 of via 125. Isolation structure 460 is formed very close to sidewall 430 of via 125 and includes a doped layer that is generally parallel to and adjacent to sidewall 430 of via 125 and restricts the lateral extension of depletion region 427 in the direction of via 125. That is, the material, doping, and / or structural characteristics of isolation structure 460 are configured to confine the lateral extension of depletion region 427 as close as possible to sidewall 430 of via 125. This allows for a reduction in the "non-active region" 410c between via 125 and the active region provided by top electrode 250 and improves the detection of secondary electrons and / or backscattered electrons (e.g., electron 135). In this example, the distance between isolation structure 460 and sidewall 430 of via 125 may be less than 1 micrometer. However, in some cases, the isolation structure 460 may be in direct contact with the sidewall 430 of the hole 125.

[0063] As described above in conjunction with FIG. 2B, the semiconductor detector (e.g., detector 120) in FIG. 4B and FIG. 4C may have a semiconductor structure 210 as a silicon-based semiconductor structure, a top electrode 250 as an anode electrode, and a doped layer 230 doped with a p-type dopant (e.g., boron). Alternatively, it may have a semiconductor structure 210 as a silicon-based semiconductor structure, a top electrode 250 as a cathode electrode, and a doped layer 230 doped with an n-type dopant (e.g., one or more of arsenic, phosphorus, or antimony). In each of these cases, the embedded portion of the top electrode 250 (not shown in FIG. 4B and FIG. 4C) may be formed by heat treatment with a dopant of the same type as that of the doped layer 230.

[0064] In addition to the various features described above, the semiconductor detector (e.g., detector 120) may also have multiple segments. In each segment, a new anode (or cathode) electrode with position sensing functionality is introduced, which will allow for the resolution of electrons collected by the same segment. Different resolution profiles may be used as described below.

[0065] For example, FIG5A shows a top view illustration 500a illustrating an example of an embedded portion 260 of the top electrode, wherein multiple embedded sections are configured in a radial configuration. That is, the embedded portion 260 of the top electrode includes multiple embedded sections in the functional area 245 provided by the top electrode, and these sections are configured to form the radial configuration shown in FIG500a.

[0066] In another example, FIG5B shows a top view illustration 500b illustrating an example of an embedded portion 260 of the top electrode, wherein multiple embedded segments are configured in a grid configuration. That is, the embedded portion 260 of the top electrode includes multiple embedded segments in the operating area 245 provided by the top electrode, and these segments are configured to form the grid configuration shown in FIG500b.

[0067] In other instances, as in the examples in Figures 500a (FIG. 5A) and 500b (FIG. 5B), the various segments forming the embedded portion 260 of the top electrode do not need to intersect each other. For example, the various segments may include multiple lines (e.g., straight lines, curves) that do not overlap, intersect, and / or contact each other. Furthermore, the various segments forming the embedded portion 260 of the top electrode may include curved segments similar to the curved segments shown in the radial configuration of Figure 500a (FIG. 5A), straight segments similar to the straight segments shown in the grid configuration of Figure 500b (FIG. 5B), or a combination of curved segments and straight segments.

[0068] The embedded portion 260 of the top electrode, whether configured as a radial configuration, a grid configuration or some other configuration, is formed by heat treatment with a dopant of the same type as the doped layer 230. In some cases, the dopant is the same, but it is not always necessary to be in this case (see, for example, the description in Figure 2B).

[0069] Figure 6 is a flowchart illustrating an example of a method 600 for forming an embedded portion 260 within a top electrode 250 in a semiconductor detector (e.g., detector 120).

[0070] Method 600 includes at 610 depositing a dopant layer on the surface of an active region (e.g., active region 245) having a top electrode 250 of a semiconductor structure (e.g., semiconductor structure 210). This dopant layer is different from a doped layer such as doped layer 230.

[0071] Method 600 may include, as appropriate, depositing a capping layer (e.g., capping layer 280) over the dopant layer at 620, wherein the capping layer is deposited prior to the application of a heat treatment. Typically, the capping layer is a dielectric layer.

[0072] Method 600 includes applying a thermal treatment at 630 to drive dopant from the dopant layer into the semiconductor structure and beneath the detection layer (e.g., doped layer 230) of the top electrode 250 to form an embedded portion 260 of the top electrode 250.

[0073] In one state of method 600, the deposition of the dopant layer includes deposition of the dopant layer by a CVD process.

[0074] In another embodiment of method 600, the top electrode 250 may be an anode electrode and the dopant in the dopant layer may include a p-type dopant (e.g., boron). Furthermore, the dopant in the detection layer may be of the same type as the dopant in the dopant layer.

[0075] In another embodiment of method 600, the top electrode 250 may be a cathode electrode and the dopant in the dopant layer may include an n-type dopant (e.g., one or more of arsenic, phosphorus, or antimony). Furthermore, the dopant in the detection layer may be of the same type as the dopant in the dopant layer.

[0076] In another embodiment of method 600, the semiconductor detector may be an SE detector or a radiation detector.

[0077] As described above in conjunction with Figures 1 to 6, an embodiment supported by the present invention includes a detector comprising: a first layer of a first conductivity type (e.g., a p-type doped layer) on a first side of a substrate, which forms an anode to receive secondary electrons from a scanning electron microscope (SEM) detection system; an embedded portion (e.g., embedded portion 260) of the first conductivity type on the first side of the substrate, which reduces the series resistance of the anode; and a second layer of a second conductivity type (e.g., an n-type doped layer), which enables the formation of a pn diode including the first layer and the second layer. In another embodiment, the formation of the embedded portion may include embedding a dopant into the substrate, wherein the dopant may be, for example, boron. Furthermore, the embedded portion may form a grid (see, for example, Figure 5A) or other configurations.

[0078] In another embodiment supported by the present invention, a substrate includes a semiconductor structure (e.g., semiconductor structure 210) having a hole (e.g., hole 125), wherein the semiconductor structure also has a deep trench isolation (e.g., isolation structure 440) surrounding the hole; a first layer of a first conductivity type (e.g., a p-type or n-type doped layer) on a first side of the semiconductor structure for receiving secondary electrons from a SEM system; and a second layer of a second conductivity type (e.g., an n-type or p-type doped layer) for enabling the formation of a pn diode including the first layer and the second layer in the semiconductor structure, wherein the second layer is adjacent to the deep trench isolation.

[0079] As mentioned above, imaging systems for detecting backscattered electrons require detectors capable of reliably and rapidly detecting electrons. Ideally, this detector would combine an electron detector (i.e., a signal generated in response to received electrons) and a signal-receiving circuitry on a single die. However, a problem exists: to make the detector fast, a step called HT PureB CVD, representing high-temperature pure boron chemical vapor deposition, is required in the manufacturing process. As the name suggests, this step involves exposing the wafer on which the circuitry is formed to extremely high temperatures. A type of circuitry called CMOS circuitry is also required. Unfortunately, these high temperatures exceed the tolerance of CMOS circuitry. In the past, this was considered fundamentally incompatible. According to one of the disclosures herein, this fundamental incompatibility is resolved by dividing the circuit formation into two parts: (1) a first part, which involves producing only structures that can survive subsequent high-temperature steps; and (2) a second part, which is performed after the high-temperature steps, in which structures that did not survive the earlier high-temperature steps can be safely fabricated. Therefore, according to one approach, integrating the HT PureB CVD process into a standard BSI CMOS process allows for the production of highly sensitive, robust, radiation-hardened, extremely fast, and power-efficient detectors / imagers and readout electronics. In other words, the resulting detector will have higher sensitivity and faster response time, and a higher signal-to-noise ratio for optimal image quality. This process also allows for greater functionality within the detector.

[0080] In other words, as described, according to one embodiment, the SE detector within the lens can be configured as a single silicon PIN detector having a central aperture to allow the primary electron beam to pass through. An aluminum coating is present on the top of the diode surface to improve series resistance and reflect stray light from the laser beam scattered inside the column. The SE detector is the first stage for the overall image channel, and its signal-to-noise ratio (SNR) determines the upper limit of the SNR for the remaining portions of the channel.

[0081] Techniques exist for using a low-temperature (LT) PureB process and a standard CMOS process to produce single-die imagers for low-penetration-depth radiation (such as EUV / DUV photons and low-energy electrons), see U.S. Patent No. 9,331,117, issued May 3, 2016, entitled "Sensor and Lithographic Apparatus," the entire disclosure of which is hereby incorporated by reference. The integration of the LT PureB process and the standard CMOS process allows for the production of multi-pixel detectors (imagers) on a single die for imaging low-penetration-depth radiation. However, the LT PureB process is characterized by extremely high sheet resistance, which does not allow for high-speed imaging.

[0082] There is a technical need for extremely fast pixelated radiation detectors capable of detecting low-energy (low penetration depth) electrons. One solution for producing such a detector is to combine the HT PureB process with a standard CMOS process on a single silicon die. The HT PureB process provides shallow pn junctions for detecting any low-penetration-depth particles: charged and uncharged, such as (e.g.) DUV and EUV photons, or low-energy electrons. PureB technology (CVD boron deposition on crystalline silicon) is beneficial for high readout speeds, and a thin, dense protective and passivating amorphous boron layer is placed on top of the silicon. Positioning the CMOS readout electronics circuitry on the same silicon die as the radiation-response element results in a shorter signal path, thereby reducing parasitic resistance and capacitance, and enabling high-efficiency power and extremely fast signal processing.

[0083] However, one of the technical challenges in achieving these benefits is that the chemical vapor deposition (CVD) temperature used for boron on silicon in the HT PureB process is typically above 700°C. If this temperature is the initial processing temperature, it can destroy CMOS components.

[0084] According to one embodiment, the technical challenge is overcome by dividing the CMOS processing of the die into two parts: (1) a first part performed before the pure boron HT CVD, and (2) a second part performed after the pure boron HT CVD. The CMOS structure generated before the HT CVD boron is selected to be a CMOS structure that can withstand temperatures up to 800°C for further die processing. Next, the HT PureB CVD process is performed (e.g., at about 750°C), followed by the remaining high-temperature intolerant steps of the CMOS process. In this way, the order of wafer processing steps relative to temperature can be configured such that each step uses a lower temperature than the previous step.

[0085] One method for implementing this processing sequence is to use temporary wafer bonding-stripping. Figure 7 illustrates an example of the overall processing sequence for a single-die CMOS image sensor (CIS) performed using temporary wafer bonding-stripping via boron-integrated HT CVD. The process begins with an initial structure 700, which is a starting wafer W1. Next, an initial CMOS process 702 is performed on one surface of the starting wafer W1 to obtain an intermediate structure 710. This initial CMOS process may include steps for forming CMOS circuitry that will allow subsequent high-temperature CVD steps in the process. For example, this initial CMOS process may include polysilicon gate formation. Next, a first bonding wafer BW1 is bonded to a portion of the starting wafer W1 having the initial CMOS structure 702 to obtain an intermediate structure 720. Next, the portion of the starting wafer W1 excluding the CMOS structure 702 is etched away to form the intermediate structure 730. Next, a boron layer 742 is deposited on the CMOS layer 702 using HT PureB CVD to form an intermediate structure 740. Next, a second bonding wafer BW2 is bonded to the boron layer 742 to obtain the intermediate structure 750. Next, the first bonding wafer BW1 is stripped from the CMOS layer 702 to form the intermediate structure 760. Then, a second part of the CMOS processing is performed to produce a CMOS structure layer 772, thus obtaining the intermediate structure 770. Next, a third bonding wafer BW3 is bonded to the CMOS structure layer 772 to obtain the intermediate structure 780. Finally, the bonding layer BW2 is stripped from the boron layer 742 to obtain the final structure 790. It should be understood that this final structure may undergo additional processing steps. For each bonding / stripping step, an appropriate bonding / stripping technique must be selected relative to the appropriate thermal processing sequence before and after the bonding / stripping step.

[0086] Figures 8A to 8D show the overall process of Figure 7 in more detail. The top portion of Figure 8A shows the initial CMOS process 702 applied to one surface of the starting wafer W1 to obtain the intermediate structure 710. This initial CMOS process may include steps of forming a CMOS circuit that will allow subsequent high-temperature CVD steps in the process. For example, this initial CMOS process may extend to and include polysilicon gate formation. The lower portion of Figure 8A, moving downwards, shows the first bonding wafer BW1 being bonded to a portion of the starting wafer W1 having the initial CMOS structure 702 to obtain the intermediate structure 720. The lower portion of Figure 8A, moving downwards, shows the etching away of a portion of the starting wafer W1, excluding the CMOS layer 702, to form the intermediate structure 730.

[0087] Turning to Figure 8B, the top portion of Figure 8B shows the deposition of a boron layer 742 on the upper CMOS layer 702 using HT PureB CVD to form an intermediate structure 740. The lower portion of Figure 8B, moving downwards in this figure, shows a second bonding wafer BW2 being bonded to the boron layer 742 to obtain an intermediate structure 750.

[0088] Turning to Figure 8C, the top portion of Figure 8C shows the stripping of the first bonding wafer BW1 from the CMOS layer 702 to form the intermediate structure 760. The lower portion of Figure 8C, moving downwards in this figure, shows the second part of performing CMOS processing to produce the CMOS structure layer 772 and thus obtain the intermediate structure 770.

[0089] The top part of Figure 8D shows the third bonding wafer BW3 being bonded to the CMOS structure layer 772 to obtain the intermediate structure 780. Finally, the second bonding wafer BW2 is stripped from the boron layer 742 to obtain the final structure 790.

[0090] Figure 9 is a flowchart illustrating the steps of a process for fabricating a single-die CMOS detector using temporary wafer bonding-stripping according to one embodiment. In step S10, an initial CMOS process is performed on a starter wafer. This process is performed to form only a structure that will tolerate the high temperatures of subsequent steps (specifically, high-temperature CVD deposition steps). In step S20, a first bonding wafer is bonded to the processed side of the starter wafer. In step S30, the starter wafer is etched to expose a portion of the CMOS-processed surface. In step S40, a material layer such as pure boron is deposited on the CMOS-processed surface using, for example, HT PureB CVD. In step S50, a second bonding wafer is bonded to the boron layer. In step S60, the first bonding wafer is stripped from the combination of the second bonding wafer and its layers. In step S70, additional CMOS processing is performed on the CMOS-processed layer. In this step, because these steps have been performed, a structure that will not tolerate high-temperature steps such as HT PureB CVD can be formed. In step S80, the third bonding wafer is bonded to the CMOS processed layer. In step S90, the second bonding wafer is peeled off from the combination of the third bonding wafer and its layer.

[0091] The embodiments may be further described using the following clauses: 1. A detector comprising: a semiconductor structure having a pn junction; and a top electrode for the pn junction, the top electrode providing an active region for detecting electronic or electromagnetic radiation, the top electrode including a doped layer and an embedded portion at least partially beneath the doped layer, the embedded portion being configured to reduce a series resistance of the top electrode. 2. The detector of clause 1, wherein: the detector is configured for in-lens or on-axis operation in a scanning electron microscope (SEM) inspection system, and the semiconductor structure having an aperture through which a scanning beam is transmitted to a target. 3. The detector of clause 1, wherein the embedded portion is configured to reduce the series resistance of the top electrode without altering the active region provided for detection. 4. The detector of clause 1, wherein: the semiconductor structure is a silicon-based semiconductor structure, the top electrode is an anode electrode, and the doped layer is doped with a p-type dopant. 5. The detector of clause 4, wherein the embedded portion of the top electrode is formed by heat treatment with a dopant of the same type as the doped layer. 6. The detector of clause 5, wherein the dopant used to form the embedded portion of the top electrode is deposited onto the semiconductor structure by a chemical vapor deposition process. 7. The detector of clause 4, wherein the p-type dopant of the doped layer includes boron. 8. The detector of clause 1, wherein: the semiconductor structure is a silicon-based semiconductor structure, the top electrode is a cathode electrode, and the doped layer is doped with an n-type dopant. 9. The detector of clause 8, wherein the embedded portion of the top electrode is formed by heat treatment with a dopant of the same type as the doped layer. 10. The detector of claim 9, wherein the dopant used to form the embedded portion of the top electrode is deposited onto the semiconductor structure by a chemical vapor deposition process. 11. The detector of claim 9, wherein the dopant of the same type used for the embedded portion of the top electrode and the doped layer are different n-type dopants. 12. The detector of claim 8, wherein the n-type dopant of the doped layer includes one or more of arsenic, phosphorus, or antimony. 13. The detector of claim 1, further comprising a top electrode metal contact disposed above a periphery of the semiconductor structure and overlapping the doped layer portion of the top electrode, wherein the embedded portion of the top electrode reduces the series resistance of the top electrode to facilitate the availability of current generated by the pn junction at the top electrode metal contact based on the detection of electrons or electromagnetic radiation. 14. The detector of claim 1, further comprising a capping layer disposed above the doped layer. 15. The detector of clause 14, wherein the cover layer is a conductive layer. 16. The detector of clause 1, wherein the pn interface is a pin interface.17. The detector of clause 1, wherein: the detector is a secondary electron (SE) detector and the detection of such electrons includes the detection of backscattered electrons from the target, or the detector is a radiation detector and the detection of the electromagnetic radiation includes the detection of backscattered electromagnetic radiation from the target. 18. The detector of clause 1, wherein the embedded portion of the top electrode includes a plurality of embedded segments within the area of ​​action provided by the top electrode. 19. The detector of clause 18, wherein the plurality of embedded segments do not intersect each other. 20. The detector of clause 19, wherein the plurality of embedded segments include straight segments, curved segments, or both. 21. The detector of clause 19, wherein the plurality of embedded segments are configured in a grid configuration. 22. The detector of clause 19, wherein the plurality of embedded segments are configured in a radial configuration. 23. The detector of claim 1, wherein the detector is configured for off-axis operation in a SEM inspection system. 24. A detector comprising: a semiconductor structure having an aperture through which a scanning beam is transmitted to a target, the semiconductor structure having a pn junction; a top electrode for the pn junction, the top electrode providing an active region for detecting electronic or electromagnetic radiation, the top electrode including a doped layer; and an isolation structure formed in the semiconductor structure near the sidewalls of the aperture and configured to electrically isolate the active region from the sidewalls of the aperture. 25. The detector of claim 24, wherein the aperture is formed at the center of the semiconductor structure. 26. The detector of claim 24, wherein the isolation structure is configured to electrically isolate the active region from the sidewalls of the aperture by configuring to limit access from a depletion region formed from the pn junction to the sidewalls of the aperture. 27. The detector of claim 24, wherein the distance between the isolation structure and the sidewalls of the via is less than 60 micrometers. 28. The detector of claim 24, wherein the isolation structure is a deep trench structure generally parallel to the sidewalls of the via but not in contact with the sidewalls of the via. 29. The detector of claim 28, wherein the deep trench structure includes doped sidewalls and provides a defect-free stop plane to electrically isolate the active region by limiting the access of a depletion region formed by the pn junction to the sidewalls of the via. 30. The detector of claim 24, wherein the isolation structure is a doped layer generally parallel to and adjacent to the sidewalls of the via. 31. The detector of claim 30, wherein the distance between the isolation structure and the sidewalls of the via is less than 1 micrometer. 32. The detector of claim 30, wherein the doped layer is in contact with the sidewalls of the via. 33. The detector of clause 24, wherein: the semiconductor structure is a silicon-based semiconductor structure, the top electrode is an anode electrode, and the doped layer is doped with a p-type dopant.34. The detector of clause 33, wherein the p-type dopant of the doped layer includes boron. 35. The detector of clause 24, wherein: the semiconductor structure is a silicon-based semiconductor structure, the top electrode is a cathode electrode, and the doped layer is doped with an n-type dopant. 36. The detector of clause 35, wherein the n-type dopant of the doped layer includes one or more of arsenic, phosphorus, or antimony. 37. The detector of clause 24, wherein the pn junction is a pin junction. 38. The detector of clause 24, wherein: the detector is a secondary electron (SE) detector and the detection of such electrons includes the detection of backscattered electrons from the target, or the detector is a radiation detector and the detection of the electromagnetic radiation includes the detection of backscattered electromagnetic radiation from the target. 39. The detector of claim 24, wherein the detector is configured for in-lens or on-axis operation in a scanning electron microscope (SEM) inspection system. 40. A detector comprising: a semiconductor structure having an aperture through which a scanning beam is transmitted to a target, the semiconductor structure having a pn junction; a top electrode for the pn junction, the top electrode providing an active region for detecting electronic or electromagnetic radiation, the top electrode including a doped layer and a buried portion at least partially beneath the doped layer, the buried portion being configured to reduce a series resistance of the top electrode without altering the active region provided for detecting the backscattering; and an isolation structure formed in the semiconductor structure near the sidewalls of the aperture and configured to electrically isolate the active region from the sidewalls of the aperture. 41. The detector of claim 40, wherein the aperture is formed at the center of the semiconductor structure. 42. The detector of claim 40, wherein: the semiconductor structure is a silicon-based semiconductor structure, the top electrode is an anode electrode, the doped layer is doped with a p-type dopant, and the embedded portion of the top electrode is formed by a heat treatment with a dopant of the same type as the doped layer. 43. The detector of claim 42, wherein the dopant used to form the embedded portion of the top electrode is deposited onto the semiconductor structure by a chemical vapor deposition process. 44. The detector of claim 42, wherein the p-type dopant of the doped layer includes boron. 45. The detector of claim 40, wherein: the semiconductor structure is a silicon-based semiconductor structure, the top electrode is a cathode electrode, the doped layer is doped with an n-type dopant, and the embedded portion of the top electrode is formed by a heat treatment with a dopant of the same type as the doped layer. 46. ​​The detector of clause 45, wherein the dopant used to form the embedded portion of the top electrode is deposited onto the semiconductor structure by a chemical vapor deposition process.47. The detector of clause 45, wherein the dopants of the same type used for the buried portion of the top electrode and the doped layer are different n-type dopants. 48. The detector of clause 45, wherein the n-type dopant of the doped layer includes one or more of arsenic, phosphorus, or antimony. 49. The detector of clause 40, wherein the isolation structure is: a deep trench structure having doped sidewalls generally parallel to but not in contact with the sidewalls of the via, or a doped layer generally parallel to and adjacent to the sidewalls of the via. 50. The detector of clause 40, wherein: the detector is a secondary electron (SE) detector and the detection of the electrons includes the detection of backscattered electrons from the target, or the detector is a radiation detector and the detection of the electromagnetic radiation includes the detection of backscattered electromagnetic radiation from the target. 51. The detector of claim 40, wherein the detector is configured for in-lens or on-axis operation in a scanning electron microscope (SEM) inspection system. 52. A method of forming an embedded portion of a top electrode in a semiconductor detector, the method comprising: depositing a dopant layer on a surface of a semiconductor structure having an active region of the top electrode; and applying a thermal treatment to drive dopant from the dopant layer into the semiconductor structure and at least partially beneath the detection layer of the top electrode to form the embedded portion of the top electrode, the embedded portion of the top electrode including a plurality of embedded segments that reduce the series resistance of the top electrode. 53. The method of claim 52, wherein forming the plurality of embedded segments includes forming: a plurality of embedded segments that do not intersect each other; a plurality of embedded segments including straight segments, curved segments, or both; a plurality of embedded segments configured in a grid configuration; or a plurality of embedded segments configured in a radial configuration. 54. The method of claim 52, wherein depositing the dopant layer comprises depositing the dopant layer by a chemical vapor deposition process. 55. The method of claim 52, further comprising depositing a capping layer over the dopant layer, wherein the capping layer is deposited prior to the application of the heat treatment. 56. The method of claim 52, wherein the capping layer is a dielectric layer. 57. The method of claim 52, wherein: the top electrode is an anode electrode, and the dopants in the dopant layer include p-type dopants. 58. The method of claim 57, wherein the p-type dopants include boron. 59. The method of claim 57, wherein the dopants of the detection layer are of the same type as the dopants of the dopant layer. 60. The method of claim 52, wherein: the top electrode is a cathode electrode, and the dopants in the dopant layer include n-type dopants. 61. The method of paragraph 60, wherein the n-type dopants include one or more of arsenic, phosphorus or antimony.62. The method of claim 60, wherein the dopant of the detection layer is of the same type as those dopants in the dopant layer. 63. The method of claim 52, wherein: the detector is a secondary electron (SE) detector configured to detect electrons above the operating region, or the detector is a radiation detector configured to detect electromagnetic radiation above the operating region. 64. A detector comprising: a first layer of a first conductivity type on a first side of a substrate, configured to form an anode for receiving secondary electrons from a scanning electron microscope (SEM) detection system; an embedded portion of the first conductivity type on the first side of the substrate, configured to reduce the series resistance of the anode; and a second layer of a second conductivity type, configured to enable the formation of a pn diode including the first layer and the second layer. 65. The detector of claim 64, wherein forming the embedded portion includes embedding a dopant into the substrate. 66. The detector of claim 65, wherein the dopant comprises boron. 67. The detector of claim 64, wherein the embedded portion forms a grid. 68. A substrate comprising: a semiconductor structure including a hole, the semiconductor structure including a deep trench isolation surrounding the hole; a first layer of a first conductivity type on a first side of the semiconductor structure for receiving secondary electrons from a SEM system; and a second layer of a second conductivity type for enabling the formation of a pn diode including the first layer and the second layer in the semiconductor structure, wherein the second layer is adjacent to the deep trench isolation. 69. A method of manufacturing a semiconductor detector, the semiconductor detector comprising an element for generating a signal in response to received radiation and circuitry electrically connected to the element, the circuitry including at least one structure that cannot withstand a processing temperature exceeding a temperature T, the method comprising the steps of: manufacturing a first portion of the circuitry capable of withstanding the temperature T; performing a processing step at the temperature T; and manufacturing a second portion of the circuitry including a structure that cannot withstand the temperature T. 70. The method of claim 69, wherein performing a processing step at the temperature T comprises performing high-temperature chemical vapor deposition (HTCVD). 71. The method of claim 70, wherein performing HTCVD comprises performing HTCVD of boron. 72. The method of claim 71, wherein performing HTCVD of boron comprises HTCVD of pure boron. 73. The method of any one of claims 69 to 72, wherein manufacturing a first portion of the circuitry comprises partially manufacturing a CMOS circuit. 74. The method of any one of clauses 69 to 73, wherein a second part of manufacturing the circuit comprises completing the manufacturing of a CMOS circuit. 75. The method of any one of clauses 69 to 74, wherein the temperature T is higher than 700°C.76. A method of manufacturing a semiconductor detector, the semiconductor detector comprising an element for generating a signal in response to received radiation and a CMOS circuit electrically connected to the element, the CMOS circuit including at least one structure that cannot withstand a processing temperature T exceeding 700°C, the method comprising the steps of: manufacturing a first portion of the CMOS circuit capable of withstanding the temperature T; performing an HT PureB CVD processing step at the temperature T; and manufacturing a second portion of the CMOS circuit, the second portion including a structure that cannot withstand the temperature T. 77. A process for manufacturing a single-die semiconductor detector, the process comprising the steps of: providing a starter wafer; performing a first partial circuit formation step on a processed side of the starter wafer to form a first partial circuit layer, the first partial circuit formation step being limited to forming a circuit capable of withstanding a processing temperature T; bonding a first bonding wafer to the first partial circuit layer; etching away a portion of the starter wafer to expose the first partial circuit layer; depositing a boron layer on the first partial circuit layer; bonding a second bonding wafer to the boron layer; stripping the first bonding wafer from the first partial circuit layer; performing a second partial circuit formation step on the first partial circuit layer to form a complete circuit layer, the second partial circuit formation step comprising forming a circuit structure unable to withstand the processing temperature T; bonding a third bonding layer to the complete circuit layer; and stripping the second bonding wafer from the boron layer. 78. The process of claim 77, wherein performing a first partial circuit formation step comprises performing a first partial CMOS circuit formation step. 79. The process of any one of clauses 77 or 78, wherein performing a second partial circuit formation step on the first partial circuit layer to form a complete circuit layer includes performing a second partial CMOS circuit formation step on the first partial circuit layer to form a complete CMOS circuit layer. 80. The process of any one of clauses 77 to 79, wherein depositing a boron layer on the first partial circuit layer includes using HT PureB CVD. 81. The process of any one of clauses 77 to 80, wherein the temperature T is higher than 700°C. 82. A single-crystal semiconductor detector comprising an element for generating a signal in response to received radiation and a CMOS circuit electrically connected to the element, the CMOS circuit including at least one structure that cannot withstand a processing temperature T exceeding 700°C, the semiconductor detector being manufactured by a method comprising one of the following steps: manufacturing a first portion of the CMOS circuit capable of withstanding the temperature T; performing an HT PureB CVD processing step at the temperature T; and manufacturing a second portion of the CMOS circuit, the second portion including a structure that cannot withstand the temperature T.

[0092] The present invention (which includes Figures 1 to 9 and their respective descriptions) provides various techniques for improving the sensitivity, efficiency, and bandwidth of semiconductor detectors used in SEM systems. For example, the present invention describes the use of an "embedded grid" or "embedded portion" of the top electrode in conjunction with pure boron technology (e.g., a pure boron layer or a similar layer to the cathode electrode) to achieve low noise and high-speed response in electron detection, wherein there is no filtering / absorbing metal stack (e.g., an aluminum grid 240 is used in the active area (as is the case in extreme ultraviolet (EUV) applications)). Furthermore, the present invention describes the use of isolation structures to maximize the active area and new localization resolution of incident electrons within segments of the semiconductor detector (e.g., radial configurations).

[0093] Examples of the architecture, configuration, functionality, and operation of various embodiments are illustrated with reference to the figures. Regarding the flowcharts, each block may represent a part of the overall method or process. It should also be noted that in some alternative embodiments, the functions mentioned in the flowchart blocks may not occur in the order mentioned and / or may occur simultaneously with the functions of different blocks.

[0094] It should be understood that the described embodiments are not mutually exclusive, and the elements, components, materials or steps described in connection with one example embodiment may be combined with or eliminated from other embodiments in a suitable manner to achieve the desired design objectives.

[0095] As used herein, unless otherwise specifically stated, the term "or" covers all possible combinations unless impractical. For example, if a statement component may include A or B, then unless otherwise specifically stated or impractical, the component may include A, or B, or A and B. As a second example, if a statement component may include A, B, or C, then unless otherwise specifically stated or impractical, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C.

[0096] In addition, unless otherwise specified or obvious from the context to be directed to the singular form, the article “a” as used in this application and the appended claims should generally be interpreted as meaning “one or more”.

[0097] The use of figure numbers or reference numerals in the claims is intended to facilitate the interpretation of the claims. Such use is not to be construed as limiting the scope of the claims to the embodiments or implementations shown in the corresponding figures.

[0098] It should be further understood that various changes to the details, materials and configurations of the components described and explained for the purpose of explaining the nature of the described state or embodiment can be made by those skilled in the art without departing from the scope depicted in the following claims. [Simplified Explanation of the Diagram]

[0013] Figure 1A is a diagram illustrating the semiconductor detector in the SEM system.

[0014] Figure 1B is a diagram illustrating the semiconductor detector in an off-axis SEM system.

[0015] FIG2A is a partial cross-sectional view illustrating a semiconductor detector having an external Al grid on the top electrode according to some aspects of the present invention.

[0016] FIG2B is a diagram illustrating a partial cross-sectional view of a semiconductor detector having an embedded portion of a top electrode according to some embodiments of the present invention.

[0017] FIG2C is a diagram illustrating a partial cross-sectional view of a semiconductor detector having an embedded portion of a top electrode and a cover layer according to some embodiments of the present invention.

[0018] Figure 3 is a plot of the simulated electron position distribution on the detector plane according to some of the present invention.

[0019] FIG4A is a partial cross-sectional view illustrating a semiconductor detector having a large "non-active area" around a hole according to some aspects of the present invention.

[0020] Figures 4B and 4C are partial cross-sectional views illustrating some of the semiconductor detectors according to the present invention, which have an isolation structure to generate a small "non-active area" around the hole.

[0021] FIG5A is a top view illustration of an example of an embedded portion of a top electrode according to some configurations of the present invention, wherein multiple embedded sections are configured radially in the top electrode.

[0022] FIG5B is a top view illustration of an example of an embedded portion of a top electrode according to some configurations of the present invention, wherein multiple embedded sections in the top electrode are configured in a grid configuration.

[0023] Figure 6 is a flowchart illustrating an example of a method for forming an embedded portion of the top electrode in a semiconductor detector according to some forms of the present invention.

[0024] Figure 7 is a diagram illustrating an example of a method for forming a semiconductor detector according to some states of the present invention.

[0025] Figures 8A to 8D are diagrams illustrating examples of methods for forming semiconductor detectors according to some states of the present invention.

[0026] Figure 9 is a flowchart illustrating an example of a method for forming a semiconductor detector according to some states of the present invention.

Claims

1. A detector comprising: a semiconductor structure having a pn junction; and a top electrode for the pn junction, the top electrode providing an active region for detecting electronic or electromagnetic radiation, the top electrode including a doped layer and an embedded portion at least partially beneath the doped layer, the embedded portion being configured to reduce a series resistance of the top electrode.

2. As in the detector of request item 1, wherein: The detector is configured for in-lens or on-axis operation in a scanning electron microscope (SEM) inspection system, and the semiconductor structure has an aperture through which a scanning beam is transmitted to a target.

3. The detector as claimed in claim 1, wherein the embedded portion is configured to reduce the series resistance of the top electrode without altering the area of ​​action provided for detection.

4. As in the detector of request item 1, wherein: The semiconductor structure is a silicon-based semiconductor structure, the top electrode is an anode electrode, and the doped layer is doped with a p-type dopant.

5. The detector of claim 4, wherein the embedded portion of the top electrode is formed by heat treatment of a dopant of the same type as the doped layer.

6. The detector of claim 5, wherein the dopant used to form the embedded portion of the top electrode is deposited onto the semiconductor structure by a chemical vapor deposition process.

7. The detector as claimed in claim 4, wherein the p-type dopant of the doped layer includes boron.

8. The detector as requested in item 1, wherein: The semiconductor structure is a silicon-based semiconductor structure, the top electrode is a cathode electrode, and the doped layer is doped with an n-type dopant.

9. The detector of claim 8, wherein the embedded portion of the top electrode is formed by heat treatment of a dopant of the same type as the doped layer.

10. The detector of claim 9, wherein the dopant used to form the embedded portion of the top electrode is deposited onto the semiconductor structure by a chemical vapor deposition process.

11. The detector of claim 9, wherein the dopants of the same type used for the embedded portion of the top electrode and the doped layer are different n-type dopants.

12. The detector of claim 8, wherein the n-type dopant of the doped layer includes one or more of arsenic, phosphorus or antimony.

13. The detector of claim 1, further comprising a top electrode metal contact disposed above a periphery of one of the semiconductor structures and overlapping the doped layer portion of the top electrode, wherein the embedded portion of the top electrode reduces the series resistance of the top electrode to facilitate the availability of current generated by the pn junction at the top electrode metal contact based on the detection of such electrons or electromagnetic radiation.

14. The detector of claim 1 further includes a capping layer disposed above the doped layer.

15. The detector as described in claim 14, wherein the cover layer is a conductive layer.