Electronic package and manufacturing method thereof

TWI940205BActive Publication Date: 2026-09-21SILICONWARE PRECISION IND CO LTD
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Patent Information

Application Number
TW114127364
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-07-18
Publication Date
2026-09-21
Estimated Expiration
2045-07-17

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Abstract

This disclosure provides an electronic package and its manufacturing method, which mainly involves forming a plurality of conductive through holes inside an interposer and forming grooves on its surface to accommodate electronic components in the grooves. A circuit structure is formed on the electronic components and the interposer for a plurality of connectors to be placed and electrically connected to the circuit structure, thereby increasing the signal transmission rate per unit time by arranging a plurality of connectors.
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Claims

1. An electronic package, comprising: An intermediate plate has opposing first and second sides and a plurality of conductive through-holes formed therein, and a groove is formed on the first side; an electronic component is housed in the groove; a circuit structure is formed on the intermediate plate and the electronic component and electrically connects the plurality of conductive through-holes and the electronic component; and a plurality of connectors are disposed on the circuit structure and electrically connected to the circuit structure for connecting transmission lines, wherein the plurality of connectors are connected to the circuit structure through a plurality of conductive elements, the circuit structure is located between the plurality of conductive through-holes, the groove, the electronic component, the plurality of connectors and the plurality of conductive elements, and the circuit structure is electrically connected to the plurality of conductive through-holes in the intermediate plate and the electronic component in the groove, and is electrically connected to the plurality of connectors through the plurality of conductive elements.

2. The electronic package as described in claim 1, wherein, The interposer is a silicon interposer, and the plurality of conductive vias are conductive silicon vias.

3. The electronic package as described in claim 1, wherein, This electronic component is a switching chip.

4. The electronic package as described in claim 1, wherein, The electronic component has an active surface and a non-active surface, and the active surface is provided with a plurality of conductive bumps, and the non-active surface is attached to the bottom of the groove through an adhesive layer.

5. The electronic package as claimed in claim 1 further includes a filler material formed in the recess to cover the electronic component.

6. The electronic package as claimed in claim 1 further includes a wiring structure formed on the second side of the interposer and electrically connected to the plurality of conductive vias.

7. The electronic package as described in claim 6 further includes a plurality of conductors disposed on the wiring structure.

8. The electronic package as described in claim 1 further includes a substrate structure for mounting the interposer.

9. The electronic package as described in claim 8 further includes a plurality of passive components and heat sinks disposed on one surface of the substrate structure, and a plurality of conductive components disposed on the other surface of the substrate structure.

10. A method for manufacturing an electronic package, comprising: An intermediate plate is provided, having a first side and a second side opposite to each other and having a plurality of conductive through-holes formed therein, and a groove is formed on the first side; an electronic component is housed in the groove; a circuit structure electrically connecting the plurality of conductive through-holes and the electronic component is formed on the intermediate plate and the electronic component; and a plurality of connectors for connecting transmission lines and electrically connecting the circuit structure are provided on the circuit structure, wherein the plurality of connectors are connected to the circuit structure through a plurality of conductive elements, the circuit structure is located between the plurality of conductive through-holes, the groove, the electronic component, the plurality of connectors and the plurality of conductive elements, and the circuit structure electrically connects the plurality of conductive through-holes in the intermediate plate and the electronic component in the groove, and electrically connects the plurality of connectors through the plurality of conductive elements.

11. The method for manufacturing an electronic package as described in claim 10, wherein, The interposer is a silicon interposer, and the plurality of conductive vias are conductive silicon vias.

12. The method for manufacturing an electronic package as described in claim 10, wherein, This electronic component is a switching chip.

13. The method for manufacturing the electronic package as described in claim 10, wherein, The electronic component has an active surface and a non-active surface, and the active surface is provided with a plurality of conductive bumps, and the non-active surface is attached to the bottom of the groove through an adhesive layer.

14. The method of manufacturing an electronic package as described in claim 10 further includes forming a filler material covering the electronic component in the groove.

15. The method of manufacturing an electronic package as described in claim 10 further includes forming a wiring structure electrically connecting the plurality of conductive vias on a second side of the interposer.

16. The method of manufacturing an electronic package as described in claim 15 further includes providing a plurality of conductors on the wiring structure.

17. The method of manufacturing an electronic package as described in claim 10 further includes attaching the intermediate plate onto a substrate structure.

18. The method for manufacturing an electronic package as described in claim 17 further includes disposing of a plurality of passive components and heat dissipation components on one surface of the substrate structure, and disposing of a plurality of conductive components on another surface of the substrate structure.

Citation Information

Patent Citations

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  • Optical-electrical substrate providing interconnects for photonic integrated circuit and associated methods

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