Vertically charge transferring pixel sensors and manufacturing method thereof

Abstract

This invention relates to a vertical charge transfer imaging sensor and its fabrication method. In the vertical charge transfer imaging sensor, the substrate includes multiple pixel substrate units isolated by a deep trench isolation structure extending through it. The shallow trench isolation structure allows each pixel substrate unit to form a photosensitive area and a charge readout area. A floating gate transistor is formed corresponding to the charge readout area, and a stack of a floating gate, an inter-gate dielectric layer, and a control gate extends from the charge readout area of ​​the corresponding pixel substrate unit to the photosensitive area. A back-side electrical connection layer covers and connects each pixel substrate unit from the back of the substrate. The back-side electrical connection layer comprises a light-transmitting and conductive metal compound, facilitating the application of voltage to the capacitor plates formed by each pixel substrate unit. This reduces the fabrication difficulty of the vertical charge transfer imaging sensor and optimizes its performance.

Description

Technical Field

[0001] This invention relates to the field of photosensitive technology, and more particularly to a vertical charge transfer imaging sensor and a method for manufacturing a vertical charge transfer imaging sensor. Prior Technology

[0002] A vertically charge-transferring (VCT) image sensor is an image sensor that uses a substrate and a floating gate transistor structure to achieve imaging. Figure 1 is a schematic diagram of the pixel structure of a VCT. Referring to Figure 1, the pixel of the VCT includes two active regions formed in a doped substrate: a photosensitive region 11 and a charge readout region 12. The photosensitive region 11 and the charge readout region 12 are separated by a shallow trench isolation (STI) structure. A source electrode S and a drain electrode D are led out from the charge readout region 12. On the front side of the substrate, a floating gate transistor (also called a readout transistor) is formed corresponding to the charge readout region 12. The floating gate, the inter-gate dielectric layer, and the control gate stack of the floating gate transistor extend above the photosensitive region 11. The control gate CG, the substrate, and the insulating dielectric material between them form a capacitor. When the vertical charge transfer imaging sensor is working, light is incident from the back of the substrate, generating photoelectrons in the substrate corresponding to the pixel. By applying an appropriate bias voltage to the capacitor, the photoelectrons can be concentrated on the surface of the photosensitive area 11 or cross the potential energy barrier to enter the floating gate (FG), which will cause changes in the drain current and / or threshold voltage of the floating gate transistor, thereby enabling photoelectric sensing and imaging.

[0003] Compared to traditional photodiode-based sensing devices (such as CMOS image sensors), vertical charge transfer imaging sensors can achieve higher full-well charge (or potential well capacity) at the same pixel size, thus having a higher signal-to-noise ratio and a significant advantage in pixel miniaturization. At the same time, preventing crosstalk between adjacent pixels is also very important.

[0004] To avoid crosstalk between adjacent pixels, deep trench isolation structures that penetrate the substrate are commonly used to completely isolate the substrate portions corresponding to each pixel. Furthermore, to facilitate the application of voltage to the substrate portions corresponding to each pixel to enable the aforementioned capacitors to operate, current methods involve embedding metal electrodes between substrate units on the back side of the substrate or depositing low-temperature polycrystalline silicon on the back side of the substrate followed by laser crystallization to form a doped polycrystalline silicon layer. Moreover, a high dielectric constant layer is typically formed on the back side of the substrate or the back side of the doped polycrystalline silicon to reduce the potential energy barrier at the silicon interface and the probability of photoelectrons being trapped. This process is complex, and metal electrodes suffer from high interface defects and high contact resistance. Additionally, the conductivity uniformity of the doped polycrystalline silicon layer is poor. These factors combined result in complex fabrication processes, high manufacturing difficulty, and performance limitations for current vertical charge transfer imaging sensors. Summary of the Invention

[0005] To avoid crosstalk between adjacent pixels in a vertical charge transfer imaging sensor, while reducing the difficulty of device fabrication and improving performance, this invention provides a vertical charge transfer imaging sensor and its fabrication method.

[0006] On one hand, the present invention provides a vertical charge transfer imaging sensor, the vertical charge transfer imaging sensor comprising:

[0007] A substrate having a first doping type and comprising a front side and a back side opposite to each other;

[0008] A deep trench isolation structure extends through the substrate, the substrate comprising a plurality of pixel substrate units isolated by the deep trench isolation structure;

[0009] A shallow trench isolation structure is formed on the front side of the substrate, and each pixel substrate unit includes a photosensitive area and a charge readout area separated by the shallow trench isolation structure;

[0010] A floating gate transistor is formed corresponding to the charge readout region, and the floating gate, inter-gate dielectric layer, and control gate stack in the floating gate transistor extend from the charge readout region of the corresponding pixel substrate unit to the photosensitive region; and

[0011] A back-side electrical connection layer covers each of the pixel substrate units from the back side of the substrate to connect each of the pixel substrate units, the back-side electrical connection layer comprising a light-transmitting and conductive metal compound.

[0012] Optionally, the metal compound includes at least one of metal nitrides and metal oxides.

[0013] Optionally, the metal nitride includes at least one of titanium nitride (TiN), tantalum nitride (TaN), ruthenium nitride (RuN), tungsten nitride (WN), and molybdenum nitride (MoN).

[0014] Optionally, the metal oxide includes indium tin oxide.

[0015] Optionally, the light transmittance of the back electrical connection layer is greater than or equal to 50%.

[0016] Optionally, the substrate further includes a plurality of substrate lead-out units isolated by the deep trench isolation structure, and the back electrical connection layer covers and connects the substrate lead-out units from the back side of the substrate.

[0017] Optionally, the deep trench isolation structure includes an isolation dielectric disposed in the deep trench and a trench electrode buried in the isolation dielectric.

[0018] Optionally, the isolation dielectric includes a linear oxide layer covering the sidewalls of the deep trench, a front trench capping layer located on the side of the trench electrode adjacent to the front side of the substrate, and a back trench capping layer located on the side of the trench electrode adjacent to the back side of the substrate.

[0019] On the other hand, the present invention provides a method for fabricating a vertical charge transfer imaging sensor, the method comprising:

[0020] A substrate is provided, the substrate having a first doping type and including a front side and a back side opposite to each other;

[0021] A deep trench isolation structure and a shallow trench isolation structure are formed on the front side of the substrate, forming a plurality of pixel substrate units isolated by the deep trench isolation structure, and a photosensitive area and a charge readout area isolated by the shallow trench isolation structure are formed in each pixel substrate unit;

[0022] A floating gate transistor is formed on the front side of the substrate corresponding to the charge readout area, and the floating gate, the inter-gate dielectric layer, and the control gate stack in the floating gate transistor extend from the charge readout area of ​​the corresponding pixel substrate unit to the photosensitive area;

[0023] Thinning the substrate from the back side exposes the deep trench isolation structure and each of the pixel substrate units; and

[0024] A back electrical connection layer is formed on the back side of the substrate, the back electrical connection layer covering and connecting each pixel substrate unit, the back electrical connection layer comprising a light-transmitting and conductive metal compound.

[0025] Optionally, the deep trench isolation structure includes an isolation dielectric disposed in the deep trench and trench electrodes buried within the isolation dielectric; wherein, after exposing the trench electrodes by thinning the substrate from the back side and before forming the back side electrical connection layer, the fabrication method further includes:

[0026] Self-aligned etching of the trench electrodes in the deep trench isolation structure, corresponding to the formation of grooves in the deep trench isolation structure; and

[0027] The groove is filled with a back groove cover layer.

[0028] In the vertical charge transfer imaging sensor and its fabrication method provided by this invention, a deep trench isolation structure penetrating the substrate isolates multiple pixel substrate units in the substrate, so that there is no substrate portion connecting adjacent pixel substrate units, which helps to avoid crosstalk between different pixels. Furthermore, a back electrical connection layer is formed on the back side of the substrate, covering and connecting each pixel substrate unit to electrically interconnect the pixel substrate units, which facilitates the application of voltage to the capacitor plates formed by each pixel substrate unit. The back electrical connection layer includes a light-transmitting and conductive metal compound, which has a lower contact resistance than metal electrodes and improved conductivity uniformity compared to doped polycrystalline silicon. This eliminates the need for forming a high dielectric constant layer on the back side of the substrate, simplifies the process and structure, reduces fabrication difficulty, and optimizes the performance of the vertical charge transfer imaging sensor. Simple Explanation of the Diagram

[0029] Figure 1 is a planar schematic diagram of a vertical charge transfer imaging sensor. Figure 2 is a flowchart illustrating a method for fabricating a vertical charge transfer imaging sensor according to an embodiment of the present invention. Figures 3A to 3F are cross-sectional schematic diagrams of a method for fabricating a vertical charge transfer imaging sensor according to an embodiment of the present invention. Implementation

[0030] The vertical charge transfer imaging sensor and its fabrication method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. The embodiments of the present invention should not be considered as limited to the specific shapes of the areas shown in the drawings, but may include actual shapes, such as those caused by manufacturing deviations.

[0031] The following describes the fabrication method of the vertical charge transfer imaging sensor according to an embodiment of the present invention with reference to Figures 2 and 3A to 3F, wherein the cross-sectional positions shown in Figures 3A to 3F correspond, for example, to the positions of the XX' line in Figure 1.

[0032] Referring to Figures 2 and 3A, in the method for fabricating a vertical charge transfer imaging sensor according to an embodiment of the present invention, in step S1, a substrate (or base) 100 is provided. The substrate 100 has a first doping type and includes a front side 100a and a back side 100b that are opposite to each other. In step S2, a deep trench isolation structure (DTI) and a shallow trench isolation structure (STI) are formed on the front side 100a of the substrate 100, forming a plurality of pixel substrate units 10 isolated by the deep trench isolation structure (DTI), and in each pixel substrate unit 10, a photosensitive area 11 and a charge readout area 12 separated by the shallow trench isolation structure (STI) are formed.

[0033] The substrate 100 can be any suitable substrate in the art, and its material may include silicon, germanium, silicon-germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide, etc. The substrate 100 has a first doping type, such as p-type or n-type. In this embodiment, p-type is used as an example. The substrate 100 is, for example, a silicon substrate doped with p-type dopants such as boron or boron difluoride.

[0034] To form a deep trench isolation structure (DTI), a deep trench is formed on one side of the front side 100a of the substrate 10, and the deep trench is filled with an isolation dielectric (such as silicon oxide). In one embodiment, the deep trench is filled only with the isolation dielectric. However, it is not limited to this. As shown in FIG3A, a linear oxide layer 101 covering the sidewalls and bottom wall of the deep trench, a trench electrode TE covering the linear oxide layer 101 and located in the deep trench, and a front trench capping layer 102 located above the trench electrode TE may be formed in the deep trench. The linear oxide layer 101 and the front trench capping layer 102 are isolation dielectrics formed in the deep trench, and the trench electrode TE is buried in the isolation dielectric. The deep trench isolation structure (DTI) may extend to a trench electrode lead-out area (not shown) in the substrate 100. In the trench electrode lead-out area, the trench electrode extends to the front side of the substrate 100 to facilitate connection to external signals. The trench electrode TE provides an operable electrode end for the vertical charge transfer imaging sensor, and in conjunction with other electrodes in the sensor, it enables diverse operating modes. For example, by applying a positive bias voltage between the substrate 100 and the trench electrode TE, the potential energy barrier at the interface between the deep trench isolation structure DTI and the substrate 100 can be improved, reducing the probability of photoelectrons being trapped at this interface, which helps to improve photoelectric conversion efficiency and alleviate dark current and white pixel problems.

[0035] The shallow trench isolation structure (STI) can be formed by forming a shallow trench on one side of the front side 100a of the substrate 10 and filling the shallow trench with an isolation dielectric (such as silicon oxide). This application does not impose any special restrictions on the formation process of the deep trench isolation structure (DTI) and the shallow trench isolation structure (STI).

[0036] In this embodiment, from a top view, the deep trench isolation structure (DTI) is grid-like, with a portion of the grid being pixel areas. The substrate 100 is divided into multiple pixel substrate units 10 by this portion of the grid. The pixel substrate units 10 are used to form pixels of the vertical charge transfer imaging sensor. In addition, another portion of the grid can be set as a substrate pick-up area. The portion of the substrate 100 separated by this other portion of the grid is the substrate pick-up unit (not shown). The substrate pick-up unit is subsequently connected to a corresponding contact plug formed on the front side 100a of the substrate 100, so as to transmit external electrical signals to the back side 100b of the substrate 100 through the substrate contact plug and the substrate pick-up unit.

[0037] Referring to Figures 2 and 3B, step S3 is then performed, in which a floating gate transistor is formed on the front side 100a of the substrate 100 corresponding to the charge readout area 12. The floating gate transistor consists of a floating gate FG, an inter-gate dielectric layer 104, and a control gate CG stacked from the charge readout area 12 of the corresponding pixel substrate unit 10 across to the photosensitive area 11.

[0038] As an example, referring to Figures 3A and 3B, step S3 may include the following process:

[0039] First, based on the formation of deep trench isolation structure (DTI) and shallow trench isolation structure (STI) as shown in Figure 3A, a gate dielectric layer 103 is first formed on the surface of the photosensitive area 11 and charge readout area 12 of each pixel substrate unit 10. Then, a polycrystalline silicon material layer is formed on the front side 100a of the substrate 100. Through a planarization process, the upper surface of the polycrystalline silicon material layer is made flush with the upper surface of the deep trench isolation structure (DTI), thereby separating the polycrystalline silicon material layers on different pixel substrate units 10 by the deep trench isolation structure (DTI).

[0040] Subsequently, the isolation dielectric in the deep trench isolation structure (DTI) is etched back (specifically, the front trench capping layer 102 in this embodiment), so that the upper surface of the isolation dielectric is lower than the upper surface of the polycrystalline silicon material layer, as shown in Figure 3B;

[0041] Next, an inter-gate dielectric layer 104 is formed on the front side of the substrate 100, and then a control gate material layer is deposited;

[0042] Subsequently, the control gate material layer, the inter-gate dielectric layer 104, and the polysilicon material layer are etched. The control gate material layer forms the control gate CG on each pixel substrate unit 10, and the polysilicon material layer forms the floating gate FG on each pixel substrate unit 10. The remaining inter-gate dielectric layer 104 is located between the control gate CG and the floating gate FG. The control gate CG on each pixel substrate unit 10 can be connected to form multiple word lines WL.

[0043] Next, sidewalls are formed on the sides of the control gate CG, the inter-gate dielectric layer 104, and the floating gate FG, and source / drain ions are implanted in the charge readout region 12 to form source / drain regions on both sides of the control gate CG. The positions of the source / drain regions can be understood with reference to Figure 1.

[0044] After the above process, a floating gate transistor is formed corresponding to the gate dielectric layer 103, floating gate FG, inter-gate dielectric layer 104, control gate CG, and source / drain regions formed in the charge readout region 12. The stack of the floating gate FG, inter-gate dielectric layer 104, and control gate CG extends from the charge readout region 12 of the corresponding pixel substrate unit 10 to the photosensitive region 11. In addition to forming the floating gate transistor, the control gate CG, the pixel substrate unit 10 opposite to the control gate CG, and the insulating dielectric material between the control gate CG and its opposite pixel substrate unit 10 are also formed. For example, a capacitor is formed by the gate dielectric layer 103 and the inter-gate dielectric layer 104. In this embodiment of the invention, by forming the floating gate transistor and the capacitor, a voltage can be applied to the capacitor during photosensitization to form an electric field in the pixel substrate unit 10. This causes photoelectrons generated in the pixel substrate unit 10 due to light incident from the back side of the substrate 100 to move towards the floating gate FG side, which can cause changes in the drain current and / or threshold voltage of the floating gate transistor. By detecting the changes in the drain current and / or threshold voltage of the floating gate transistor, photoelectric signals can be detected.

[0045] After forming the floating gate transistor and the capacitor, an interlayer dielectric layer and contact plugs penetrating the interlayer dielectric layer can be further formed on the front side 100a of the substrate 100. The control gate CG and source / drain regions of the floating gate transistor are respectively connected to the corresponding contact plugs. In addition, the substrate lead-out units can be connected to the corresponding contact plugs. Furthermore, a metal interconnect structure and pads can be formed above the interlayer dielectric layer and the contact plugs so that the floating gate transistor and the substrate lead-out units can be connected to external signals through the corresponding pads.

[0046] Referring to Figures 2 and 3C, step S4 is performed to thin the substrate 100 from the back side 100b, exposing the deep trench isolation structure (DTI) and each pixel substrate unit 10. Before thinning the substrate 100, a carrier plate (not shown) may be bonded to the front side 100a of the substrate 100 as a support.

[0047] In one embodiment, as shown in FIG3C, the substrate 100 can be thinned using a CMP process to expose the deep trench isolation structure (DTI) and each pixel substrate unit 10 (i.e., the exposed deep trench isolation structure (DTI) is in a grid shape). The deep trench isolation structure (DTI) includes, for example, the trench electrode TE mentioned above. Through thinning, after the CMP process is completed, the trench electrode TE is exposed from the back side 100b of the substrate 100. The present invention is not limited to this. In another embodiment, the substrate 100 is first thinned to a first thickness using a CMP process. At this time, the grid shape of the deep trench isolation structure (DTI) is not exposed. Then, wet etching is performed to further thin the substrate 100 to a second thickness, exposing the deep trench isolation structure (DTI) (for example, exposing the trench electrode TE mentioned above) and each pixel substrate unit 10.

[0048] Research has found that before being exposed from the back side 100b of the substrate 100, the depth of the deep trench isolation structure (DTI) extending from the front side 100a of the substrate 100 into the substrate 100 is uneven at different positions on the grid lines. It is usually deeper at the grid intersections and shallower at the non-intersections. In this embodiment, by exposing the DTI grid from the back side 100b of the substrate 100, the lower surfaces of each pixel substrate unit 10 and the substrate lead-out unit are basically flush, so the thickness is basically consistent. This avoids the influence of the uneven depth of the DTI in the substrate 100 on the thickness of the pixel substrate unit 10, improves the consistency of the capacitance corresponding to each pixel, and facilitates the normal operation of each pixel.

[0049] In this embodiment, since a trench electrode TE is formed in the deep trench isolation structure DTI, in order to prevent the trench electrode TE from short-circuiting with the substrate pixel unit 10 through the subsequently formed back side electrical connection layer, after exposing the deep trench isolation structure DTI from the back side 100b of the substrate 100, the following process is further included:

[0050] As shown in Figure 3D, dry or wet etching can be used to self-align the trench electrode TE in the deep trench isolation structure DTI from the back side 100b of the substrate 100, so that the trench electrode TE is lower than the pixel substrate unit 10 from the back side 100b of the substrate 100, and a groove 20 is formed corresponding to the deep trench isolation structure DTI.

[0051] Then, as shown in FIG3E, a back trench capping layer 105 is filled in the groove 20. For example, a dielectric material (such as silicon oxide) can be deposited in the trench 20 and the back side 100b of the substrate 100 first, and then a CMP process is performed to expose each pixel substrate unit 10. The remaining dielectric material is filled in the groove 20 to form the back trench capping layer 105. The back trench capping layer 105 covers the trench electrode TE and its surface facing the back side 100b of the substrate 100 is flush with the back side of the pixel substrate unit 10.

[0052] Referring to Figures 1 and 3F, step S5 is performed to form a back electrical connection layer 106 on the back side 100b of the substrate 100. The back electrical connection layer 106 covers and connects each pixel substrate unit 10. The back electrical connection layer 106 includes a light-transmitting and conductive metal compound. In addition, a back dielectric layer 107 may be formed on the back electrical connection layer 106.

[0053] To avoid affecting light incidence from the back side 100b of the substrate 100, the back electrical connection layer 106 preferably has good light transmittance. As an example, the light transmittance of the back electrical connection layer 106 is greater than or equal to 50%. The light transmittance is the ratio of the intensity of the light remaining after passing through the back electrical connection layer 106 to the intensity of the incident light.

[0054] The metal compound may include at least one of a metal nitride and a metal oxide. The metal nitride may include, for example, at least one of titanium nitride (TiN), tantalum nitride (TaN), ruthenium nitride (RuN), tungsten nitride (WN), and molybdenum nitride (MoN). The metal oxide may include, for example, indium tin oxide (ITO). Optionally, the back electrical connection layer 106 may also include a metal, such as titanium (Ti). As an example, the back electrical connection layer 106 is a titanium nitride layer or a composite layer of titanium nitride and titanium.

[0055] The back electrical connection layer 106 can span the deep trench isolation structure (DTI) and directly cover part or all of the surface of each pixel substrate unit 10. By connecting the back electrical connection layer 106 to each pixel substrate unit 10, a voltage can be applied to each pixel substrate unit 10 through the back electrical connection layer 106. In conjunction with the voltage applied to the control gate CG, the purpose of applying voltage to the capacitor plates formed by the control gate CG and the pixel substrate unit 10 can be achieved. Furthermore, the back electrical connection layer 106 can be directly formed on the back side 100b of the substrate 100 through film deposition processes such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), without the need for laser crystallization or etching of the substrate 100 to form within the substrate 100. By selecting a suitable metal compound, the work function of the substrate 100 adjacent to the back electrical connection layer 106 can be adjusted, thereby eliminating the need to form a high dielectric constant layer. This simplifies the process, reduces the difficulty of device fabrication, improves conductivity uniformity, and optimizes the performance of the vertical charge transfer imaging sensor.

[0056] This invention also relates to a vertical charge transfer imaging sensor, which can be formed using the above-described method for fabricating a vertical charge transfer imaging sensor.

[0057] Referring to FIG3F, the vertical charge transfer imaging sensor of this embodiment includes a substrate 100, a deep trench isolation structure (DTI), a shallow trench isolation structure (STI), a floating gate transistor, and a back electrical connection layer 106. The substrate 100 has a first doping type and includes a front side 100a and a back side 100b opposite to each other. The deep trench isolation structure penetrates the substrate 100. The substrate 100 includes a plurality of pixel substrate units 10 defined by the deep trench isolation structure (DTI). The shallow trench isolation structure (STI) is formed on the front side 100a of the substrate 100. Each pixel substrate unit... The pixel 10 includes a photosensitive area 11 and a charge readout area 12 separated by the shallow trench isolation structure (STI). The charge readout area 12 is formed with the floating gate transistor. The floating gate transistor has a floating gate FG, an inter-gate dielectric layer 104, and a control gate CG stacked from the charge readout area 12 of the corresponding pixel substrate unit 10 to the photosensitive area 11. The back electrical connection layer 106 covers each pixel substrate unit 10 from the back side 100b of the substrate 100 to connect each pixel substrate unit 10. The back electrical connection layer 106 includes a light-transmitting and conductive metal compound.

[0058] The vertical charge transfer imaging sensor may further include an interlayer dielectric layer formed on the front side 100a of the substrate 100 and contact plugs (not shown) penetrating the interlayer dielectric layer. The control gate CG and source / drain regions of the floating gate transistor can be connected to the corresponding contact plugs. In some embodiments, the substrate 100 also includes a plurality of substrate lead-out units (not shown) isolated by a deep trench isolation structure (DTI). The interlayer dielectric layer covers the substrate lead-out units from the front side 100a of the substrate 100, and the substrate lead-out units can be connected to the corresponding contact plugs. A back electrical connection layer 106 can cover and connect the substrate lead-out units from the back side 100b of the substrate 100. Thus, the substrate lead-out units are connected to the corresponding contact plugs and the back electrical connection layer 106 on the front and back sides, respectively. Electrical signals can be transmitted to the back electrical connection layer 106 through the contact plugs and the substrate lead-out units, thereby achieving the purpose of applying voltage to each pixel substrate unit 10 covered by the back electrical connection layer 106.

[0059] In order not to affect the light incidence from the back side 100b of the substrate 100, the back electrical connection layer 106 preferably has good light transmittance. As an example, the light transmittance of the back electrical connection layer 106 is greater than or equal to 50%.

[0060] Optionally, the metal compound includes at least one of a metal nitride and a metal oxide. The metal nitride includes, for example, at least one of titanium nitride (TiN), tantalum nitride (TaN), ruthenium nitride (RuN), tungsten nitride (WN), and molybdenum nitride (MoN), and the metal oxide includes, for example, indium tin oxide (ITO). Optionally, the back electrical connection layer 106 may also include a metal, such as titanium (Ti). As an example, the back electrical connection layer 106 is a titanium nitride layer or a composite layer of titanium nitride and titanium.

[0061] As shown in Figure 3F, in some embodiments, the deep trench isolation structure (DTI) includes an isolation dielectric disposed in a deep trench penetrating the substrate 100 and a trench electrode TE buried within the isolation dielectric. Further, the isolation dielectric in the deep trench includes a linear oxide layer 101 covering the sidewalls of the deep trench, a front trench capping layer 102 located on the side of the trench electrode TE adjacent to the front face 100a of the substrate 100, and a back trench capping layer 105 located on the side of the trench electrode TE adjacent to the back face 100b of the substrate 100. The trench electrode TE is located between the front trench capping layer 102 and the back trench capping layer 105 and is isolated from the substrate 100 by the linear oxide layer 101.

[0062] In the vertical charge transfer imaging sensor of this invention, a deep trench isolation structure (DTI) penetrates the substrate 100 to isolate multiple pixel substrate units 10, which helps to avoid crosstalk between different pixels. Furthermore, a back electrical connection layer 106 is formed on the back side 100b of the substrate 100, covering and connecting each pixel substrate unit 10, which facilitates the uniform application of voltage to the capacitor plates formed by each pixel substrate unit 10. The back electrical connection layer 106 includes a light-transmitting and conductive metal compound, which is convenient to fabricate. By selecting a suitable metal compound, the work function of the substrate 100 adjacent to the back electrical connection layer 106 can be adjusted using the back electrical connection layer 106, thereby eliminating the need to form a high dielectric constant layer, simplifying the process and structure, improving conductivity uniformity, and optimizing the performance of the vertical charge transfer imaging sensor.

[0063] It should be noted that the embodiments in this specification are described in a progressive manner, with each part focusing on the differences from the preceding parts, and the similarities and similarities between the parts can be referred to each other.

[0064] The above description is merely a description of preferred embodiments of the present invention and is not intended to define the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

[0065] 10: Pixel substrate unit 11: Photosensitive area 12: Charge Reading Area 20: Groove 100: Substrate 100a: Front 100b: Back 101: Linear oxide layer 102: Front trench cover 103: Gate dielectric layer 104: Intergate dielectric layer 105: Back trench cover layer 106: Backside electrical connection layer 107: Backside dielectric layer CG: Control Gate D: Jiji DTI: Deep Trench Isolation Structure FG: Floating gate S: Source S1~S5: Steps STI: Shallow Trench Isolation Structure TE: Trench electrode WL: Word Line

Claims

1. A vertical charge transfer imaging sensor, characterized in that it comprises: A substrate having a first doping type and including a front side and a back side opposite to each other; A deep trench isolation structure extends through the substrate, the substrate including a plurality of pixel substrate units isolated by the deep trench isolation structure; a shallow trench isolation structure is formed on the front side of the substrate, each pixel substrate unit including a photosensitive area and a charge readout area separated by the shallow trench isolation structure; a floating gate transistor is formed corresponding to the charge readout area, and a stack of a floating gate, an inter-gate dielectric layer, and a control gate in the floating gate transistor extends from the charge readout area of ​​the corresponding pixel substrate unit across to the photosensitive area; and a back electrical connection layer covers each pixel substrate unit from the back side of the substrate to connect each pixel substrate unit, the back electrical connection layer comprising a light-transmitting and conductive metal compound. The deep trench isolation structure includes an isolation dielectric disposed in a deep trench and a trench electrode buried in the isolation dielectric. The isolation dielectric includes a linear oxide layer covering the sidewall of the deep trench, a front trench cover layer located on the side of the trench electrode adjacent to the front side of the substrate, and a back trench cover layer located on the side of the trench electrode adjacent to the back side of the substrate.

2. The vertical charge transfer imaging sensor as claimed in claim 1, wherein the metal compound comprises at least one of a metal nitride and a metal oxide.

3. The vertical charge transfer imaging sensor as claimed in claim 2, wherein the metal nitride comprises at least one of titanium nitride, tantalum nitride, ruthenium nitride, tungsten nitride, and molybdenum nitride.

4. The vertical charge transfer imaging sensor as claimed in claim 2, wherein the metal oxide comprises indium tin oxide.

5. The vertical charge transfer imaging sensor as claimed in claim 1, wherein the transmittance of the back electrical connection layer is greater than or equal to 50%.

6. The vertical charge transfer imaging sensor as claimed in claim 1, wherein the substrate further comprises a plurality of substrate lead-out units isolated by the deep trench isolation structure, and the back electrical connection layer covers and connects the substrate lead-out units from the back side of the substrate.

7. A method for fabricating a vertical charge transfer imaging sensor, characterized in that it includes: A substrate is provided, the substrate having a first doping type and including a front side and a back side opposite to each other; A deep trench isolation structure and a shallow trench isolation structure are formed on the front side of the substrate, forming a plurality of pixel substrate units isolated by the deep trench isolation structure. In each pixel substrate unit, a photosensitive area and a charge readout area are formed, separated by the shallow trench isolation structure. A floating gate transistor is formed on the front side of the substrate corresponding to the charge readout area, with a stack of a floating gate, an inter-gate dielectric layer, and a control gate in the floating gate transistor extending from the charge readout area of ​​the corresponding pixel substrate unit to the photosensitive area. The substrate is thinned from the back side to expose the deep trench isolation structure and each pixel substrate unit. A backside electrical connection layer is formed on the back side of the substrate, covering and connecting each pixel substrate unit. The backside electrical connection layer comprises a light-transmitting and conductive metal compound. The deep trench isolation structure includes an isolation dielectric disposed in a deep trench and a trench electrode buried in the isolation dielectric; wherein, after exposing the trench electrode by thinning the substrate from the back side and before forming the back side electrical connection layer, the fabrication method further includes: self-aligning etching the trench electrode in the deep trench isolation structure to form a groove corresponding to the deep trench isolation structure; and filling the groove with a back side trench cover layer.

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