Semiconductor devices and methods of manufacturing semiconductor devices

Abstract

In one example, a semiconductor device includes: a cavity substrate comprising a base and sidewalls defining a cavity; an electronic component situated in the cavity on a top side of the base; a cover over the cavity and over the sidewalls; and a valve for providing access to the cavity, wherein the valve has a plunger for providing a seal between the cavity environment and an external environment outside the cavity. Other examples and related methods are also disclosed herein.

Description

[Technical Field]

[0001] This disclosure generally relates to electronic devices, and more specifically to semiconductor devices and methods of manufacturing semiconductor devices. [Previous Technology]

[0002] Previous semiconductor packages and methods for forming semiconductor packages are unsuitable, for example, resulting in excessive cost, reduced reliability, relatively low performance, or excessively large package size. Other limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with the present invention and by referring to the drawings. [Summary of the Invention]

[0003] According to an embodiment of the present invention, a semiconductor device includes: a cavity substrate including a base and sidewalls to define a cavity; an electronic component on a top side of the base in the cavity; a cover above the cavity and above the sidewalls; and a valve for providing access to the cavity, wherein the valve has a plunger to provide a seal between the cavity environment and an external environment outside the cavity.

[0004] According to another aspect of the invention, a method includes: providing a cavity substrate, the cavity substrate including a base and sidewalls to define a cavity; providing an electronic component on a top side of the base in the cavity; providing a cover above the cavity in contact with the sidewalls; and providing a valve to provide access to the cavity, wherein the valve has a plunger to provide a seal between the cavity environment and an environment outside the cavity.

[0005] According to yet another aspect of the present invention, a semiconductor device includes: a substrate including a base and a sidewall extending perpendicularly from the base; a cover over the sidewall to define a cavity between the base, the sidewall and the cover; an electronic component in the cavity; a valve between the cavity and an external environment outside the cavity; a seal between the cover and the sidewall; and a plunger in the valve, wherein the seal and the plunger hermetically seal the cavity from the external environment.

Implementation Method

[0017] The following discussion presents various examples of providing semiconductor devices and methods of manufacturing semiconductor devices. Such examples are not limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are not limiting.

[0018] The figures illustrate general construction methods, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Furthermore, elements in the figures are not necessarily drawn to scale. For example, the dimensions of some elements in each figure may be enlarged relative to other elements to aid in understanding the examples discussed in this disclosure. The same reference numerals in different figures denote the same elements.

[0019] The term “or” means any one or more items in a list connected by “or”. As an example, “x or y” means any element in the three-element set {(x), (y), (x, y)}. As another example, “x, y, or z” means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. The terms “comprising” and / or “including” are “open” terms and specify the presence of the stated feature, but do not exclude the presence or addition of one or more other features. Various elements may be described herein using the terms “first,” “second,” etc., and these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, for example, a first element discussed in this disclosure may be referred to as a second element without departing from the teachings of this disclosure. Unless otherwise specified, the term “coupled” may be used to describe two elements in direct contact with each other or to describe two elements indirectly connected by one or more other elements. For example, if element A is coupled to element B, then element A can be directly in contact with element B or indirectly connected to element B through intervening element C. Similarly, the terms "above" or "on top of" can be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements.

[0020] In one example, a semiconductor device includes: a cavity substrate including a base and sidewalls to define a cavity; an electronic component in the cavity on a top side of the base; a cover above the cavity and above the sidewalls; and a valve for providing access to the cavity, wherein the valve has a plunger to provide a seal between the cavity environment and an external environment outside the cavity.

[0021] In another example, a method of manufacturing a semiconductor device includes: providing a cavity substrate, the cavity substrate including a substrate and sidewalls to define a cavity; providing an electronic component on a top side of the substrate in the cavity; providing a cover above the cavity that contacts the sidewalls; and providing a valve to provide access to the cavity, wherein the valve has a plunger to provide a seal between the cavity environment and the environment outside the cavity.

[0022] In another example, a semiconductor device includes: a substrate including a base and a sidewall extending perpendicularly from the base; a cover above the sidewall to define a cavity between the base, the sidewall and the cover; an electronic component in the cavity; a valve between the cavity and an external environment outside the cavity; a seal between the cover and the sidewall; and a plunger in the valve, wherein the seal and the plunger hermetically seal the cavity from the external environment.

[0023] Other examples are included in this invention. Such examples can be found in the drawings, claims, or the specification of this disclosure.

[0024] FIG1 shows a cross-sectional view of an example semiconductor device 10. In the example shown in FIG1, the semiconductor device 10 may include a cavity substrate 11, electronic components 15, interconnects 14, a cover 13, a seal 16, a valve 18, and a plunger 19.

[0025] The cavity substrate 11 may include a conductive structure 111 and a dielectric structure 112. The conductive structure 111 may include internal substrate terminals 1111, external substrate terminals 1112, conductive paths 1113, and a sealing substrate 1114 (optional). The conductive structure 111 may be in a substrate 112A and may be electrically coupled to an electronic component 15. The dielectric structure 112 may include a substrate 112A and sidewalls 112B. The cavity 113 may be defined by the substrate 112A and sidewalls 112B. A cavity environment or volume 1131 may be implemented in the cavity 113. The electronic component 15 may include component terminals 151. The valve 18 may include a tap 181. In some embodiments, the cavity substrate 11 may include a substrate 112A and sidewalls 112B to define the cavity 113.

[0026] In some embodiments, the cover 13 may be located above the cavity 113 and the sidewall 112B of the cavity substrate 11. The cavity substrate 11, cover 13, seal 16, valve 18, and plunger 19 may be referred to as a hermetically sealed semiconductor package and may provide protection for the electronic component 15 from exposure to external components or the environment. The valve 18 provides access to the cavity 113, and the plunger 19 provides a seal between the cavity environment and the external environment outside the cavity 113. The semiconductor package provides electrical coupling between the external electronic component and the external terminals 1112 of the substrate. In some embodiments, the electronic component 15 may be located on the top side of the substrate 112A. The electronic component 15 may include electronic or optical components as examples, and the scope of the disclosed protected object is not limited thereto.

[0027] Figures 2A to 2H show cross-sectional views of an example method for manufacturing a semiconductor device 10. Figure 2A shows a cross-sectional view of the semiconductor device 10 in an early stage of manufacturing.

[0028] In the example shown in FIG. 2A, a cavity substrate 11 may be provided, wherein the cavity substrate may include a substrate 112A and a sidewall 1114. The cavity substrate 11 may have a thickness ranging from about 100 micrometers (μm) to about 1500 μm. As described above, the cavity substrate 11 may include a conductive structure 111 and a dielectric structure 112.

[0029] The conductive structure 111 may include several elements, such as an internal substrate terminal 1111, an external substrate terminal 1112, a conductive path 1113, or a sealing substrate 1114. The internal substrate terminal 1111 may be located at the top of the substrate 112a of the dielectric structure 112 and within the cavity 113 of the dielectric structure 112. The external substrate terminal 1112 may be located at the bottom of the substrate 112A of the dielectric structure 112. The conductive path 1113 may pass through the dielectric structure 112 to couple the internal substrate terminal 1111 to the external substrate terminal 1112. In some embodiments, a sealing substrate 1114 may be provided at the top of the sidewall 112B along the periphery of the dielectric structure 112. In some embodiments, the sealing substrate 1114 may be in the sidewall 112B, wherein a seal 16 is provided between the sealing substrate 1114 and the cover 13. The conductive structure 111 or its elements may include, or may be referred to as, one or more conductive layers, traces, gaskets, vias, or leads. The internal terminal 1111 of the substrate may include, or may be referred to as, a pad or a trace. The external terminal 1112 of the substrate may also include, or may be referred to as a pad or a trace. The conductive path 1113 may include, or may be referred to as one or more vias or traces. The sealing substrate 1114 may include, or may be referred to as a conductive pad or conductive land. In some instances, the internal terminal 1111, the external terminal 1112, the conductive path 1113, or the sealing substrate 1114 may include copper, aluminum, nickel, gold, or silver. In some instances, the sealing substrate 1114 may include a copper, tungsten, or nickel-gold plating. The components of the conductive structure 111, such as the internal terminal 1111, the external terminal 1112, the conductive path 1113, or the sealing substrate 1114, may have a thickness ranging from about 10 μm to about 50 μm.

[0030] The dielectric structure 112 may include a substrate 112A and a sidewall 112B. The substrate 112A may have a substantially flat top side and a substantially flat bottom side opposite the top side. The sidewall 112B may extend upward or project along the periphery of the substrate 112A. The vertical thickness of the substrate 112A may be greater than the horizontal thickness of the sidewall 112B. In some embodiments, the sidewall 112B may be substantially rectangular when viewed in a planar manner. A conductive structure 111 may be accessible at the top and bottom sides of the substrate 112A. In some embodiments, an internal substrate terminal 1111 may be provided on the top side of the substrate 112A, an external substrate terminal 1112 may be provided on the bottom side of the substrate 112A, and a conductive path 1113 may pass through the substrate 112A. A sealing substrate 1114 may be provided on the top side of the sidewall 112B. As an example, the sealing substrate 1114 can be embedded in the sidewall 112B such that the top side of the sealing substrate 1114 is substantially coplanar with the top side of the sidewall 112B.

[0031] The dielectric structure 112 may include one or more dielectric layers, such as ceramic layers, molding resin layers, or laminate layers, stacked on top of each other. The dielectric structure 112 may have a thickness ranging from about 100 μm to about 1500 μm. The cavity 113 defined by the substrate 112A and the sidewall 112B may have a depth ranging from about 100 μm to about 1000 μm.

[0032] In examples where the dielectric structure 112 includes ceramic, the dielectric structure 112 may include or be referred to as alumina, silicon nitride, sapphire, or borosilicate glass. In some examples, the cavity substrate 11 may be manufactured in a manner similar to that of a low-temperature co-fired ceramic (LTCC) substrate. In some examples, the LTCC substrate may be co-fired at a generally low temperature of about 1000 °C or less. LTCC technology may include forming vias in a dielectric sheet having a thickness ranging from about 40 μm to 80 μm and filling the vias with a conductor or conductive paste to provide a conductive path 1113, printing conductor patterns to provide internal substrate terminals 1111, external substrate terminals 1112, or a sealing substrate 1114, coupling valve 18, lamination, and co-firing. In some examples, the operation of forming the sealing substrate 1114 using sputtering and electroplating may be performed separately. In some examples, the operation of coupling the valve 18 to the sidewall 112B of the substrate 11 may be performed.

[0033] In some instances, a “green sheet” or layer of ceramic and binder can be prepared prior to cryogenic co-firing. Through-holes of appropriate size can be formed in the green sheet using a punching tool or laser beam, and conductor paste can fill these through-holes. The conductor paste filling the through-holes can then form conductive paths 1113. A conductor pattern can then be printed. During the conductor pattern printing process, the conductor material can be provided as the desired circuit pattern, for example, using printing. This process provides internal substrate terminals 1111, external substrate terminals 1112, or a sealing substrate 1114. A valve 18 can be securely inserted into the sidewalls of one or more green sheets. The respective green sheets can be stacked and bonded to each other by applying heat and pressure. During the co-firing process, binder components can be eliminated or vaporized from the stack at temperatures ranging from about 300 °C to about 400 °C.

[0034] In some examples, the cavity substrate 11 may be formed as a molded resin substrate having a dielectric structure 112 having one or more layers of molding material. In some examples, the cavity substrate 11 may be a pre-formed or laminated substrate having one or more laminated layers as the dielectric structure 112. The pre-formed substrate may be manufactured before being attached to an electronic device and may include a dielectric layer between respective conductive layers. The conductive layer may include copper and may be formed using an electroplating process. The dielectric layer may be a relatively thick, non-photodefinable layer that may be attached as a pre-formed film rather than as a liquid and may contain a resin with fillers such as strands, braids, or other inorganic particles for rigid or structural support. Because the dielectric layer is non-photodefinable, features such as through-holes or openings may be formed using a drill or laser. In some examples, the dielectric layer may include a prepreg material or an Ajinomoto Buildup Film (ABF). The pre-formed substrate may include a permanent core structure or carrier, such as a dielectric material comprising bismaleimide triazine (BT) or FR4, and dielectric and conductive layers may be formed on the permanent core structure. In other instances, the pre-formed substrate may be a coreless substrate omitting the permanent core structure, and dielectric and conductive layers may be formed on a sacrificial carrier, which is removed after the dielectric and conductive layers are formed and before attachment to an electronic device. The pre-formed substrate may be referred to as a printed circuit board (PCB) or a laminated substrate. Such pre-formed substrates may be formed using a semi-additive process or a modified semi-additive process.

[0035] Valve 18 may be coupled via the sidewall 112B of dielectric structure 112. Valve 18 may be coupled to cavity 113 via the sidewall 112B of cavity substrate 11. In some embodiments, the inner end of valve 18 may be coplanar with the inner side of sidewall 112B. In some embodiments, the inner end of valve 18 may protrude from the inner side of sidewall 112B into cavity 113. In some embodiments, the outer end of valve 18 may protrude outward from the outer side of sidewall 112B. Valve 18 may include a passage 182 that allows air to be discharged from cavity 113 or allows a gas, such as an inert gas or air, to be introduced into cavity 113 to achieve a target pressure. Valve 18 may include, or may be referred to as, a conduit, pipe, or passage. Valve 18 may include an orifice or tap 181 leading to passage 182. Tap 181 may be provided on an area of ​​valve 18 located on the outer side of sidewall 112B. Valve 18 may include Kovar, steel, stainless steel, copper, aluminum, or nickel. In some instances, valve 18 may include a material similar to that of the lead frame. In some instances, valve 18 may include a dam 183 formed in the passage 182 corresponding to the area of ​​tap 181. A plunger may be positioned within the dam 183. In some instances, the dam 183 may include a periphery configured to constrain the plunger 19 from lateral displacement or expansion. The thickness or height of the dam 183 may be less than the thickness or height of the passage 182 of valve 18. Each of the dams 183 may have a thickness ranging from about 10 μm to about 100 μm. Valve 18 may have a diameter ranging from about 50 μm to about 200 μm.

[0036] The completed cavity substrate 11 may include a cavity 113 and a valve 18 providing access to the cavity 113 via a sidewall 112B of the substrate 11. In some instances where the dielectric structure 112 of the cavity substrate 11 comprises ceramic as the primary material, high thermal conductivity and chemical stability, as well as enhanced high-frequency performance and electrical performance, can be achieved.

[0037] FIG2B shows a cross-sectional view of the semiconductor device 10 at a later manufacturing stage. In the example shown in FIG2B, an electronic component 15 may be provided on a cavity substrate 11. In some examples, the electronic component 15 may be provided or attached to the top side of the substrate 112A of the cavity substrate 11 using an adhesive or thermal interface material. The electronic component 15 may include component terminals 151 on its top side. The electronic component 15 may include, or may be referred to as, a die, a wafer, or a package, wherein the die or wafer may include integrated circuitry separated from the semiconductor wafer. A package may be accomplished by covering the die or wafer with a protective material. The electronic component 15 may include, for example, a digital signal processor (DSP), a microprocessor, a network processor, a power management unit, an audio processor, a radio frequency (RF) circuit, a wireless baseband system-on-a-chip (SoC) processor, a sensor, or an application-specific integrated circuit (ASIC). The electronic component 15 may have a thickness ranging from about 100 μm to about 775 μm. Electronic component 15 can be positioned within cavity 113 of cavity substrate 11 to be protected from external environmental influences or to be provided with the required operating environment.

[0038] FIG. 2C shows a cross-sectional view of the semiconductor device 10 at a later manufacturing stage. In the example shown in FIG. 2C, an interconnect 14 may be coupled between the electronic component 15 and the cavity substrate 11. One end of the interconnect 14 may be electrically connected to a component terminal 151 of the electronic component 15, and the other end of the interconnect 14 may be electrically connected to an internal substrate terminal 1111 of the cavity substrate 11. The interconnect 14 may include, or may be referred to as, a wire or a bump. The interconnect 14 may include, or may be referred to as, gold, copper, aluminum, or solder. In some instances, if the component interconnect 151 of the electronic component 15 is facing upward, then the interconnect 14 may include, for example, a wire and may electrically connect the electronic component 15 and the cavity substrate 11. For example, one end of the interconnect 14 may first be ball-bonded to the component terminal 151, and the other end of the interconnect 14 may then be stitch-bonded to the internal substrate terminal 1111, or vice versa. In some instances, if the interconnect 151 of the electronic component 15 faces downward, then the interconnect 14 may include, for example, bumps and be electrically connected to the electronic component 15 and the cavity substrate 11. For example, a ball-shaped or cylindrical interconnect 14 may be attached to the component terminal 151 or the substrate internal terminal 1111, and the electronic component 15 may subsequently be attached to the cavity substrate 11 via a mass reflow process, thermoforming process, or laser-assisted bonding process. The interconnect 14 may have a diameter ranging from about 15 μm to about 50 μm.

[0039] Figures 2D and 2E show cross-sectional views of the semiconductor device 10 at a later manufacturing stage. In the example shown in Figures 2D and 2E, a cover 13 may be provided on the cavity substrate 11. The cover 13 may have a flat top side and a flat bottom side. The bottom side of the cover 13 may be attached to a sidewall 112B of the cavity substrate 11. The bottom side of the cover 13 may be attached to a sealing substrate 1114 provided on the sidewall 112B. The cover 13 may include, or may be referred to as, a cover or a top cover. The cover 13 may include, or may be referred to as, metal, plastic resin, or ceramic. The cover 13 may have a thickness ranging from about 100 μm to about 500 μm. The cover 13 may be attached to the sidewall 112B of the cavity substrate 11 using a seal 16. The seal 16 may be provided on the area of ​​the cover 13 corresponding to the sealing substrate 1114 located on the sidewall 112B. The seal 16 may include, or may be referred to as, solder or adhesive. In some instances, the seal 16 may be provided on one of the cap 13 or the sealing substrate 1114, and may subsequently be bonded to the other of the cap 13 or the sealing substrate 1114 via a batch reflow process, a thermoforming process, or a laser-assisted bonding process. The seal 16 may have a thickness ranging from about 10 μm to about 100 μm. The cap 13 and the seal 16 may cover the cavity 113 of the cavity substrate 11 to provide protection for the electronic components 15 and interconnects 14 from external environmental influences, or to maintain the desired environment 1113 within the cavity 113.

[0040] Figure 2F shows a cross-sectional view of the semiconductor device 10 at a later manufacturing stage. In the example shown in Figure 2F, a plunger 19 may be provided in the valve 18. The plunger 19 may be mounted on the tap 181 of the valve 18 to block the tap 181. The plunger 19 may include, or may be referred to as, a microball, solder, resin, or adhesive. In some instances, the plunger 19 may include a lead-free (Pb) solder alloy, such as a Sn-Ag-Cu alloy or AuSn solder. The diameter of the plunger 19 may be slightly larger than the diameter of the tap 181. The plunger 19 may have a diameter ranging from about 10 μm to about 150 μm. In this way, the tap 181 of the valve 18 may be temporarily blocked, while the passage 182 of the valve 18 may still be open.

[0041] Figure 2G shows a cross-sectional view of the semiconductor device 10 at a later manufacturing stage. In the example shown in Figure 2G, air in cavity 113 can be vented to the outside via valve 18 to create a vacuum in cavity 113. In the same or other examples, a desired gas, such as an inert gas or air, can be introduced into cavity 113 via valve 18 to achieve a target pressure. In some examples, the cavity environment may include a vacuum or an inert gas. In some examples, a vacuum device may be connected to valve 18 to release air from cavity 113, and a gas filling device may be connected to valve 18 to allow gas to fill cavity 113. Examples of inert gases may include nitrogen, argon, or helium. The internal gas pressure of cavity 113 may range from about 0 mbar to about 1100 mbar. A cavity environment 1131 may be provided, in which cavity 113 is maintained as a vacuum or filled with gas.

[0042] Figure 2H shows a cross-sectional view of the semiconductor device 10 at a later manufacturing stage. In the example shown in Figure 2H, the tap 181 and passage 182 of valve 18 can be blocked by plunger 19. In some examples, tap 181 and passage 182 can be blocked by using, for example, a laser beam to melt the plunger 19 to seal the plunger 19 within valve 18. The molten plunger 19 can be positioned or flowable between a pair of dams and subsequently solidified, and the solidified plunger 19 can block passage 182 and tap 181. The cavity environment 1131 provided in cavity 113 can be isolated from the external environment by the solidified plunger 19. In some examples, the laser beam source can include a carbon dioxide (CO2) laser, a fiber laser, or a yttrium aluminum garnet (YAG) laser, and the laser can oscillate in pulsed laser mode or continuous wave mode. In some examples, the laser output power can range from about 200 watts (W) to about 20 kilowatts (kW).

[0043] Figure 3 shows a cross-sectional view of an example method for manufacturing an example semiconductor device. In the example shown in Figure 3, a forced insertion process or a bolting process can be used instead of a laser beam process to block the tap 181 and passage 182 of valve 18. Air in cavity 113 can be removed from cavity 113 through valve 18, or gas can be introduced into cavity 113 through valve 18 to reach a target pressure, and then plunger 19 or 19A can be forced into or bolted into tap 181 and passage 182, thereby blocking tap 181 and passage 182 of valve 18. In this way, a vacuum can be provided in the cavity environment, or an inert gas can be provided in the cavity environment, and the cavity environment can be maintained by sealing plunger 19 or 19A into valve 18. In some examples, plunger 19 or 19A may include or be referred to as a soft metal ball, a soft plastic resin ball, or a soft metal ball encapsulated in soft plastic resin. If a plunger 19 or 19A made of a soft material is forced into tap 181, the shape of the plunger 19 or 19A changes so that tap 181 and passage 182 can be blocked by the plunger 19 or 19A. In some instances, the soft material may include or be referred to as solder, aluminum, gold, or silver, and the soft plastic resin may include or be referred to as polyimide (PI), polypropylene (PP), polyethylene (PE), or Teflon resin.

[0044] FIG4 shows a cross-sectional view of an example semiconductor device 20. The semiconductor device 20 shown in FIG4 may be similar to the example semiconductor device 10 shown in FIG1, and a valve 18 is provided between the cavity substrate 11 and the cover 13. In the example shown in FIG4, the semiconductor device 20 may be configured such that the valve 18 is positioned between the sidewall 112B of the cavity substrate 11 and the cover 13, rather than at the sidewall 112B of the cavity substrate 11. The valve 18 may be secured between the sidewall 112B of the cavity substrate 11 and the cover 13 by a seal 16.

[0045] Figures 5A to 5I show cross-sectional views illustrating an example method for manufacturing an example semiconductor device 20. The manufacturing method of the example semiconductor device 20 shown in Figures 5A to 5I may be similar to the corresponding operations or figures described, for example, for semiconductor device 10 in Figures 2A to 2H. However, Figures 5A to 5I show a valve 18 positioned between the cavity substrate 11 and the cover 13. The following description will focus on the differences between the methods.

[0046] FIG5A shows a cross-sectional view of the semiconductor device 20 in an early manufacturing stage. In the example shown in FIG5A, the cavity substrate 11 may not be attached to the valve 18. The cavity substrate 11 may include a conductive structure 111 and a dielectric structure 112. The sidewall 112B of the dielectric structure 112 may lack the passage to which the valve 18 is attached in the examples of FIG1 and 2.

[0047] FIG5B shows a cross-sectional view of the semiconductor device 20 at a later manufacturing stage. In the example shown in FIG5B, electronic components 15 may be provided on the cavity substrate 11. In some examples, electronic components 15 may be attached to the substrate 112A of the cavity substrate 11 using an adhesive or a thermally conductive material.

[0048] FIG5C shows a cross-sectional view of the semiconductor device 20 at a later manufacturing stage. In the example shown in FIG5C, interconnect 14 may be provided between electronic component 15 and cavity substrate 11.

[0049] FIG. 5D shows a cross-sectional view of the semiconductor device 20 at a later manufacturing stage. In the example shown in FIG. 5D, a valve 18 may be provided. In some examples, the valve 18 may be provided on or attached to the cavity substrate 11 on the top of the sidewall 112B or on the sealing substrate 1114. In some examples, the valve 18 may be coupled to the sealing substrate 1114 via a seal 16A, which may include or be referred to as solder or adhesive. In some examples, the inner end of the valve 18 may be substantially coplanar with the inner side of the sidewall 112B, or the outer end of the valve 18 may protrude through the outer side of the sidewall 112B. The valve 18 may include a passage 182 that allows air to be discharged from the cavity 113 to the outside, or allows a gas, such as an inert gas, to be injected into the cavity 113 from the outside of the cavity 113. The valve 18 may include a tap 181 or an orifice connected to the passage 182. Tap 181 can be provided on the area of ​​valve 18 located on the outside of sidewall 112B.

[0050] Figures 5E and 5F show cross-sectional views of the semiconductor device 20 at a later manufacturing stage. In the example shown in Figures 5E and 5F, a cover 13 may be provided on the cavity substrate 11 and the valve 18. The bottom side of the cover 13 may be attached to the sidewall 112B of the cavity substrate 11 and the valve 18. The bottom side of the cover 13 may be attached to a sealing substrate 1114 provided on the sidewall 112B or to the valve 18. The cover 13 may be attached to the sidewall 112B of the cavity substrate 11 or the valve 18 via a seal 16. The seal 16 may be provided on the area of ​​the cover 13 corresponding to the sealing substrate 1114 located on the sidewall 112B and on the area of ​​the cover 13 corresponding to the valve 18, respectively. In some instances, after the seal 16 is bonded to the cap 13 or to the sealing substrate 1114 and valve 18, the cap 13 can be bonded to the sealing substrate 1114, sidewall 112B, or valve 18 via a batch reflow process, hot pressing process, or laser-assisted bonding process. In some instances, the seal 16 bonded to the cap 13 can be integral with or coupled to the seal 16A bonded between the valve 18 and sidewall 112B. Because the valve 18 is positioned between the cap 13 and the cavity substrate 11, the thickness of the seal 16 can be greater than the thickness of the valve 18.

[0051] FIG. 5G shows a cross-sectional view of the semiconductor device 20 at a later manufacturing stage. In the example shown in FIG. 5G, a plunger 19 may be provided in the valve 18. The plunger 19 may be mounted on the tap 181 of the valve 18 to temporarily block the tap 181.

[0052] FIG5H shows a cross-sectional view of the semiconductor device 20 at a later manufacturing stage. In the example shown in FIG5H, air in cavity 113 can be discharged to the outside through valve 18, or a gas such as inert gas or air can be introduced into cavity 113 through valve 18.

[0053] FIG5I shows a cross-sectional view of the semiconductor device 20 at a later manufacturing stage. In the example shown in FIG5I, the tap 181 and passage 182 of valve 18 can be blocked by plunger 19. In some instances, tap 181 and passage 182 can be blocked by using, for example, a laser beam to melt plunger 19 or by performing a forced insertion or bolting process.

[0054] FIG6 shows a cross-sectional view of an example semiconductor device 30. The example semiconductor device 30 shown in FIG6 may be similar to the example semiconductor device 10 shown in FIG1, and the valve 38 may be incorporated in the cavity substrate 11. In the example shown in FIG6, the semiconductor device 30 may be configured such that the valve 38 includes an aperture provided at or therein, rather than at the sidewall 112B of the cavity substrate 11. The base 112A of the cavity substrate 11 may include the valve 38 and the valve base 31. The semiconductor device 30 may include a plunger 19 positioned in the valve 38.

[0055] Figures 7A to 7I show cross-sectional views of an example method for manufacturing an example semiconductor device 30. The manufacturing method of the example semiconductor device 30 shown in Figures 7A to 7I may be similar to the corresponding operations or figures described, for example, for semiconductor device 10 in Figures 2A to 2H. However, Figures 7A to 7I show a valve 38 located at the substrate 112A of the cavity substrate 11. The following description will focus on the differences between the two methods.

[0056] FIG7A shows a cross-sectional view of a semiconductor device 30 in an early manufacturing stage. In the example shown in FIG7A, a cavity substrate 11 may be provided. The cavity substrate 11 may include a substrate 112A and a sidewall 112B. The substrate 112A may have a substantially flat top side and a substantially flat bottom side opposite the top side. A valve 38 may be configured to pass perpendicularly through the top and bottom of the substrate 112A. In some instances, the valve 38 may be provided by a chemical etching process, a laser beam process, or a mechanical drilling process.

[0057] In some embodiments, valve 38 may include a first upper perforation 38A and a second lower perforation 38B connected to each other. The upper perforation 38A, connected to the top side of the substrate 112A, may have a constant width, and the lower perforation 38B, connected to the bottom side of the substrate 112A, may have a width that gradually increases toward the bottom side of the substrate 112A. The width of the second lower perforation 38B at the bottom side of valve 38 may be greater than the width of the first upper perforation 38A. Plunger 19 may be in the second lower perforation 38B to seal cavity 13. In some embodiments, lower perforation 38B may be substantially semi-circular or bowl-shaped around the bottom side of substrate 112A. In some embodiments, lower perforation 38B of valve 38 may include, or referred to as a dam or dam perimeter, configured to constrain plunger 19 from lateral displacement or expansion. Valve 38 may have a width ranging from about 50 μm to about 200 μm. The width of the lower perforation 38B may be greater than the width of the upper perforation 38A. In some embodiments, a valve substrate 31 may be provided on the side of the lower perforation 38B. In some embodiments, the valve substrate 31 may be metal, including copper or tungsten, or a nickel-gold plating formed on said side of the lower perforation 38B. In some embodiments, the valve substrate 31 may be provided in a manner similar to the conductive structure 111 described above. The valve substrate 31 may have a thickness ranging from about 10 μm to about 50 μm.

[0058] FIG7B shows a cross-sectional view of the semiconductor device 30 at a later manufacturing stage. In the example shown in FIG7B, electronic component 15 may be provided on cavity substrate 11. In some examples, electronic component 15 may be attached to substrate 112A of cavity substrate 11 using adhesive or thermally conductive material.

[0059] FIG7C shows a cross-sectional view of the semiconductor device 30 at a later manufacturing stage. In the example shown in FIG7C, interconnect 14 may be provided between electronic component 15 and cavity substrate 11.

[0060] Figures 7D and 7E show cross-sectional views of the semiconductor device 30 at a later manufacturing stage. In the example shown in Figures 7D and 7E, a cover 13 may be provided on the cavity substrate 11. The bottom side of the cover 13 may be attached to the sidewall 112B of the cavity substrate 11 using a seal 16. In some examples, the bottom side of the cover 13 may be attached to a sealing substrate 1114 provided on the sidewall 112B.

[0061] FIG7F shows a cross-sectional view of the semiconductor device 30 at a later manufacturing stage. In the example shown in FIG7F, the cavity substrate 11 is flipped so that the lower through-hole 38B provided on the substrate 112A faces upward.

[0062] FIG7G shows a cross-sectional view of the semiconductor device 30 at a later manufacturing stage. In the example shown in FIG7G, air in cavity 113 can be discharged from cavity 113 through valve 38, or a gas such as inert gas or air can be introduced into cavity 113 through valve 38 to achieve a target pressure.

[0063] FIG7H shows a cross-sectional view of the semiconductor device 30 at a later manufacturing stage. In the example shown in FIG7H, the plunger 19 may be provided at the valve 38 provided on the substrate 112A. In some examples, the plunger 19 may be positioned on the lower cup-shaped perforation 38B or on the valve substrate 31. Thus, the valve 38 may be blocked by the plunger 19.

[0064] FIG7I shows a cross-sectional view of the semiconductor device 30 at a later manufacturing stage. In the example shown in FIG7I, the valve 38 can be hermetically blocked by a molten plunger 19 or by forced insertion of the plunger 19 at the lower perforation 38B or by bolting.

[0065] FIG8 shows a cross-sectional view of an example semiconductor device 40. The example semiconductor device 40 shown in FIG8 may be similar to the example semiconductor device 10 shown in FIG1, and a valve 48 including a valve substrate 41 is provided between a cavity substrate 11 and a cover 13. In the example shown in FIG8, the semiconductor device 40 may be configured such that the valve 48 is positioned between a sidewall 112B of the cavity substrate 11 and a cover 13. The semiconductor device 40 may include a plunger 19 that blocks the valve 48.

[0066] Figures 9A to 9H show cross-sectional views of an example method for manufacturing an example semiconductor device 40. The manufacturing method of the example semiconductor device 40 shown in Figures 9A to 9H may be similar to the corresponding operations or figures described, for example, for semiconductor device 10 in Figures 2A to 2H. However, Figures 9A to 9H show a valve 48 positioned between the cavity substrate 11 and the cover 13. The following description will focus on the differences between the two methods.

[0067] FIG9A shows a cross-sectional view of a semiconductor device 40 in an early manufacturing stage. In the example shown in FIG9A, a cavity substrate 11 may be provided. The cavity substrate 11 may include a base 112A and a sidewall 112B, and a valve 48 may be provided at the top of the sidewall 112B. The valve 48 may include or have a groove 48A recessed in the sidewall 112B. In some examples, the groove 48A may have a bowl-shaped cross-section. The groove 48A may be provided by performing a chemical etching process, a laser beam process, or a mechanical drilling process on a region of the sidewall 112B.

[0068] In some embodiments, valve 48 may further include valve base 41 provided on the side of recess 48A. Valve base 41 may also have a bowl-shaped cross-section, similar to the side of recess 48A. In some embodiments, valve 48 may be connected to or may be a portion of sealing base 1114, which may be made of a material similar to sealing base 1114, or may have a thickness similar to sealing base 1114. In some embodiments, recess 48A may have a depth ranging from about 50 μm to about 200 μm. In some embodiments, valve base 41 may include a copper or tungsten, or nickel-gold plating layer formed on the side of recess 48A. Valve base 41 may have a thickness ranging from about 10 μm to about 50 μm.

[0069] FIG9B shows a cross-sectional view of the semiconductor device 40 at a later manufacturing stage. In the example shown in FIG9B, electronic component 15 may be provided on cavity substrate 11. In some examples, electronic component 15 may be attached to substrate 112A of cavity substrate 11 using adhesive or thermally conductive material.

[0070] FIG9C shows a cross-sectional view of the semiconductor device 40 at a later manufacturing stage. In the example shown in FIG9C, interconnect 14 may be provided between electronic component 15 and cavity substrate 11.

[0071] Figures 9D and 9E show cross-sectional views of the semiconductor device 40 at a later manufacturing stage. In the example shown in Figures 9D and 9E, a cover 13 may be provided on the cavity substrate 11. The bottom side of the cover 13 may be attached to a sidewall 112B or a sealing substrate 1114 using a seal 16. The seal 16 may include a gap between the sidewall 112B and the cover 13, and the gap may include or define a valve 48. The valve 48 may have a width ranging from about 50 μm to about 200 μm, including the width of the gap.

[0072] FIG9F shows a cross-sectional view of the semiconductor device 40 at a later manufacturing stage. In the example shown in FIG9F, air in cavity 113 may be discharged from cavity 113 through valve 38, or a gas such as inert gas or air may be introduced into cavity 113 through valve 38 to achieve a target pressure.

[0073] FIG9G shows a cross-sectional view of the semiconductor device 40 at a later manufacturing stage. In the example shown in FIG9G, a plunger 19 may be provided at a valve 48 located between the cavity substrate 11 and the cover 13. The plunger 19 may be mounted on the valve 48 located on the sidewall 112B of the cavity substrate 11. In some examples, the plunger 19 may be located at the inlet of the valve 48 or on the recess 48A. Thus, the valve 48 may be blocked by the plunger 19.

[0074] FIG9H shows a cross-sectional view of the semiconductor device 40 at a later manufacturing stage. In the example shown in FIG9H, the valve 48 can be hermetically blocked by a molten plunger 19 or by performing forced insertion or bolting of the plunger 19 into the valve 48 or recess 48A. In some instances, the recess 48A of the valve 48 may include, or be referred to as a dam or dam periphery, which is configured to constrain the plunger 19 from lateral displacement or expansion. In some instances, the plunger 19 may be made of the same or similar material as the seal 16.

[0075] FIG10 shows a cross-sectional view of an example semiconductor device 50. The example semiconductor device 50 shown in FIG10 may be similar to the example semiconductor device 10 shown in FIG1, and the valve 58 is provided at the cover 13 instead of the cavity substrate 11. In the example shown in FIG10, the semiconductor device 50 may include a cover 13 having a valve 58. The valve 58 of the cover 13 may further include a valve base 51. The semiconductor device 50 may include a plunger 19 that blocks the valve 58 of the cover 13.

[0076] Figures 11A to 11F show cross-sectional views of an example method for manufacturing an example semiconductor device 50. The manufacturing method of the example semiconductor device 50 shown in Figures 11A to 11F may be similar to the corresponding operation or diagram described, for example, for semiconductor device 10 in Figures 2A to 2H. However, the valve 58 is provided on the cover 13 instead of on the cavity substrate 11. The following description will focus on the differences between the two methods.

[0077] FIG11A shows a cross-sectional view of a semiconductor device 50 in an early manufacturing stage. In the example shown in FIG11A, a cover 13 having a valve 58 may be provided. The cover 13 may have a substantially flat top side and a substantially flat bottom side. A valve 58 may be provided including or having a perforation 58A through the top and bottom sides of the cover 13. The perforation 58A may be in the cover 13 between the cover 13 and the sidewall 112B of the cavity substrate 11. In some examples, the valve 58 may be substantially circular or bowl-shaped. In some examples, the perforation 58A through the substrate 112A of the valve 58 may be provided by a chemical etching process, a laser beam process, or a mechanical drilling process. In some examples, a valve substrate 51 may be further provided on the inner wall of the perforation 58A. In some examples, the valve substrate 51 may be made of a material similar to the sealing substrate 1114. In some examples, the valve substrate 51 may have a thickness ranging from about 10 μm to about 50 μm. The valve 58 provided on the cover 13 may correspond to or be aligned with a region of the sealing substrate 1114 provided on the cavity substrate 11.

[0078] Figures 11B and 11C show cross-sectional views of the semiconductor device 50 at a later manufacturing stage. In the example shown in Figures 11B and 11C, a cover 13 may be provided on the cavity substrate 11. The bottom side of the cover 13 may be attached to the sidewall 112B of the cavity substrate 11 or the top of the sealing substrate 1114 using a seal 16. The seal 16 may have a gap surrounding the valve 58 so that the valve 58 is not blocked by the seal 16.

[0079] FIG11D shows a cross-sectional view of the semiconductor device 50 at a later manufacturing stage. In the example shown in FIG11D, air in cavity 113 may be discharged from cavity 113 through valve 58, or a gas such as inert gas or air may be introduced into cavity 113 through valve 38 to achieve a target pressure.

[0080] FIG11E shows a cross-sectional view of the semiconductor device 50 at a later manufacturing stage. In the example shown in FIG11E, the plunger 19 can be provided at the inlet of the valve 58 through the cap 13 to block the valve 58.

[0081] FIG11F shows a cross-sectional view of the semiconductor device 50 at a later manufacturing stage. In the example shown in FIG11F, the valve 58 provided in the cover 13 and the gap created between the cover 13 and the cavity substrate 11 can be hermetically blocked by the plunger 19. In some instances, the valve 58 and the gap can be blocked by melting the plunger 19 or by performing forced insertion of the plunger 19 at the valve 58 or by bolting.

[0082] FIG11F shows a cross-sectional view of the semiconductor device 50 at a later manufacturing stage. In the example shown in FIG11F, the valve 58 can be hermetically blocked by a molten plunger 19 or by performing forced insertion or bolting of the plunger 19 into the valve 58 or through-hole 58A. In some instances, the plunger 19 may be made of the same or similar material as the seal 16.

[0083] This disclosure includes references to certain examples. However, those skilled in the art will understand that various changes can be made and equivalents can be substituted without departing from the scope of this disclosure. Furthermore, modifications can be made to the disclosed examples without departing from the scope of this disclosure. Therefore, it is intended that this disclosure is not limited to the disclosed examples, but rather that it encompasses all examples falling within the scope of the appended claims. [Simplified Explanation of the Diagram]

[0006] [Figure 1] shows a cross-sectional view of an example semiconductor device.

[0007] [Figures 2A to 2H] show cross-sectional views of an example method for manufacturing an example semiconductor device.

[0008] [Figure 3] shows a cross-sectional view of an example method for manufacturing an example semiconductor device.

[0009] [Figure 4] shows a cross-sectional view of an example semiconductor device.

[0010] [Figures 5A to 5I] show cross-sectional views illustrating an example method for manufacturing an example semiconductor device.

[0011] [Figure 6] shows a cross-sectional view of an example semiconductor device.

[0012] [Figures 7A to 7I] show cross-sectional views of an example method for manufacturing an example semiconductor device.

[0013] [Figure 8] shows a cross-sectional view of an example semiconductor device.

[0014] [Figures 9A to 9H] are cross-sectional views illustrating an example method for manufacturing an example semiconductor device.

[0015] [Figure 10] shows a cross-sectional view of an example semiconductor device.

[0016] [Figures 11A to 11F] are cross-sectional views illustrating an example method for manufacturing an example semiconductor device.

Claims

1. A semiconductor device, comprising: A cavity substrate, comprising a substrate base and substrate sidewalls protruding from the substrate base to define a cavity; Electronic components, located on the top side of the substrate within the cavity; A cover, which is located above the cavity and above the sidewall of the substrate; and a valve, which provides access to the cavity; wherein the valve is located between the bottom side of the cover and the bottom side of the substrate base; and wherein the valve extends beyond the outer lateral side of the sidewall of the substrate and comprises at least one of Kovar alloy, steel, stainless steel, copper, aluminum or nickel.

2. The semiconductor device according to claim 1, wherein the valve is located in the sidewall of the substrate.

3. The semiconductor device according to claim 1, wherein the valve is located between the top side of the substrate sidewall and the bottom side of the cover.

4. The semiconductor device according to claim 1, further comprising a sealing substrate in the sidewall of the substrate and a seal between the sealing substrate and the cover.

5. The semiconductor device according to claim 1, wherein the environment in the cavity includes a vacuum.

6. The semiconductor device according to claim 1, wherein the environment in the cavity comprises an inert gas.

7. The semiconductor device according to claim 1, further comprising a conductive structure electrically coupled to the electronic component in the substrate.

8. A semiconductor device, comprising: A cavity substrate, comprising a base and sidewalls to define a cavity; Electronic components, located on the top side of the substrate within the cavity; A cover, which is above the cavity and above the sidewall; and a valve, which provides access to the cavity; wherein the valve includes a perforation in the cover between the cover and the sidewall of the cavity substrate; and wherein the perforation in the cover is above the topmost side of the sidewall of the cavity substrate.

9. The semiconductor device according to claim 8, further comprising a sealing substrate in the sidewall and a seal between the sealing substrate and the cover.

10. The semiconductor device according to claim 8, wherein the environment in the cavity includes a vacuum.

11. The semiconductor device according to claim 8, wherein the valve is located between the sidewall of the cavity substrate and the top side of the cover.

12. The semiconductor device according to claim 8, wherein the valve includes a valve base on the inner wall of the cover at the perforation.

13. A method of manufacturing a semiconductor device, comprising: A cavity substrate is provided, comprising a substrate base and substrate sidewalls protruding from the substrate base to define a cavity; A valve is provided for providing access to the cavity; An electronic component is provided on the top side of the substrate within the cavity; The device includes a cover located above the cavity and above the sidewall of the substrate; wherein the valve is located between the bottom side of the cover and the bottom side of the substrate base; and wherein the valve extends beyond the outer lateral side of the sidewall of the substrate and comprises at least one of Kovar alloy, steel, stainless steel, copper, aluminum, or nickel.

14. The method according to claim 13, wherein the valve is in the sidewall of the substrate.

15. The method according to claim 13, wherein the valve is located between the top side of the substrate sidewall and the bottom side of the cover.

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