Semiconductor package and manufacturing method thereof

Abstract

This invention provides a semiconductor package and a method for manufacturing a semiconductor package. As a non-limiting example, various embodiments of the invention provide a semiconductor package and a method for manufacturing a semiconductor package, the method including shielding on multiple sides thereof.

Description

[Technical Field]

[0001] This invention relates to semiconductor packaging and a method for manufacturing the same. <Cross Reference to Related Applications / Incorporated by Reference>

[0002] This application refers to, claims priority to, and claims the benefit of Korean Patent Application No. 10-2015-0159058, filed on November 12, 2015 with the Korean Intellectual Property Office and entitled “Semiconductor Packaging and Manufacturing Method Thereof”, the contents of which are incorporated herein by reference in their entirety. [Previous Technology]

[0003] Current semiconductor packaging and methods for forming semiconductor packages are unsuitable, for example, causing excessive costs, reduced reliability, inadequate shielding, excessively large package sizes, etc. Further limitations and disadvantages of such methods will become apparent to those skilled in the art by comparing conventional and traditional methods with the present invention as illustrated in the remainder of this invention with reference to the drawings. [Summary of the Invention]

[0004] Various aspects of the present invention provide a semiconductor package and a method for manufacturing a semiconductor package. As a non-limiting example, various aspects of the present invention provide a semiconductor package and a method for manufacturing a semiconductor package, the method including shielding on multiple sides thereof.

[0005] According to a embodiment of the present invention, a semiconductor package includes: a substrate having a top substrate surface, a bottom substrate surface, and a plurality of lateral substrate surfaces; a first electronic device located on the top substrate surface and electrically connected to the substrate; a first molding article covering at least the top substrate surface and the first electronic device, the first molding article having a top first molding article surface, a bottom first molding article surface, and a plurality of lateral first molding article surfaces; a second molding article covering at least the bottom substrate surface, the second molding article having a top second molding article surface, a bottom second molding article surface, and a plurality of lateral second molding article surfaces, wherein the second molding article extends at least laterally to the lateral substrate surfaces; a plurality of first conductive bumps located on the bottom substrate surface, electrically connected to the substrate, and passing through the second molding article; and an electromagnetic interference (EMI) shielding layer covering at least the top first molding article surface, the lateral first molding article surfaces, the lateral substrate surfaces, and the lateral second molding article surfaces, wherein the EMI shielding layer is spaced apart from the first conductive bumps. In the semiconductor package, the entire bottom second molding article surface is exposed from the EMI shielding layer. In the semiconductor package, the top second molding surface includes the uppermost surface of the second molding; the bottom second molding surface includes the lowermost surface of the second molding; and each of the plurality of first conductive bumps is positioned in a corresponding aperture in the second molding, wherein the corresponding aperture extends from the uppermost surface of the second molding to the lowermost surface of the second molding. In the semiconductor package, on the bottom side of the semiconductor package, the electromagnetic interference shielding layer contacts only the bottom second molding surface. In the semiconductor package, the electromagnetic interference shielding layer covers at least a portion of the bottom second molding surface. The semiconductor package further includes a plurality of second conductive bumps, each of the plurality of second conductive bumps being coupled to a corresponding one of the first conductive bumps, and wherein: the electromagnetic interference shielding layer covers a portion of the bottom second molding surface and exposes the plurality of second conductive bumps to the outside of the electromagnetic interference shielding layer; and the electromagnetic interference shielding layer includes a rectangular exposure hole that exposes at least one of the second conductive bumps to the outside of the electromagnetic interference shielding layer. The semiconductor package further includes a plurality of second conductive bumps, each of the plurality of second conductive bumps being coupled to a corresponding one of the first conductive bumps, and wherein: the electromagnetic interference shielding layer covers a portion of the surface of the bottom second molded article and exposes the plurality of second conductive bumps to the outside of the electromagnetic interference shielding layer; and the electromagnetic interference shielding layer includes an ablated exposure hole that exposes at least one of the second conductive bumps to the outside of the electromagnetic interference shielding layer.The semiconductor package further includes a second electronic device located on the surface of the bottom substrate and electrically connected to the substrate, wherein each of the plurality of first conductive bumps extends at least vertically across the entire height of the second electronic device.

[0006] According to another aspect of the present invention, a method for manufacturing a semiconductor package, the semiconductor package comprising: a substrate having a top substrate surface, a bottom substrate surface, and a lateral substrate surface; including: a first electronic device located on the top substrate surface and electrically connected to the substrate; and including: a plurality of first conductive bumps located on the bottom substrate surface and electrically connected to the substrate, the method comprising: forming a first molding article, the first molding article at least covering the top substrate surface and the first electronic device, the first molding article having a top first molding article surface, a bottom first molding article surface, and a plurality of lateral first molding article surfaces; forming a second molding article, the second molding article at least covering the bottom substrate surface and the first conductive bumps, the second molding article having: The method comprises: a top second molded surface, a bottom second molded surface, and a plurality of lateral second molded surfaces; grinding the bottom second molded surface to expose the first conductive bump to the outside of the second molded surface; forming a plurality of second conductive bumps, each of the plurality of second conductive bumps being electrically connected to a corresponding one of the exposed first conductive bumps; placing a jig under the second molded surface to cover the plurality of second conductive bumps; and forming an electromagnetic interference (EMI) shielding layer that at least covers the top first molded surface, the lateral first molded surface, the lateral substrate surface, and the lateral second molded surface, the top first molded surface, the lateral first molded surface, the lateral substrate surface, and the lateral second molded surface being exposed to the outside by the jig. In this method, the second molded surface extends at least laterally to the lateral substrate surface. In this method, the jig is positioned to expose a portion of the bottom second molded surface and cover the second conductive bumps. In this method, on the bottom side of the semiconductor package, the formed EMI shielding layer only contacts the bottom second molded surface. In the method, the formed electromagnetic interference (EMI) shielding layer covers at least a portion of the surface of the bottom second molded article. In the method, each of the plurality of second conductive bumps is coupled to a corresponding one of the first conductive bumps; the EMI shielding layer covers a portion of the surface of the bottom second molded article and exposes the plurality of second conductive bumps to the outside of the EMI shielding layer; and the EMI shielding layer includes a rectangular exposure hole that exposes at least one of the second conductive bumps to the outside of the EMI shielding layer. In the method, each of the plurality of second conductive bumps is coupled to a corresponding one of the first conductive bumps; the EMI shielding layer covers a portion of the surface of the bottom second molded article and exposes the plurality of second conductive bumps to the outside of the EMI shielding layer; and the EMI shielding layer includes an ablated exposure hole that exposes at least one of the second conductive bumps to the outside of the EMI shielding layer.The method includes coupling a second electronic device to and electrically connecting it to the surface of the bottom substrate, wherein each of the plurality of first conductive bumps spans at least vertically across the entire height of the second electronic device.

[0007] According to yet another aspect of the present invention, a method for manufacturing a semiconductor package, the semiconductor package comprising: a substrate having a top substrate surface, a bottom substrate surface, and lateral substrate surfaces; including: a first electronic device located on the top substrate surface and electrically connected to the substrate; and including: a plurality of first conductive bumps located on the bottom substrate surface and electrically connected to the substrate, the method comprising: forming a first molding article, the first molding article at least covering the top substrate surface and the first electronic device, the first molding article having a top first molding article surface, a bottom first molding article surface, and a plurality of lateral first molding article surfaces; forming a second molding article, the second molding article at least covering the bottom substrate surface and the first conductive bumps, the second molding article... The article has a top second molded article surface, a bottom second molded article surface, and a plurality of transverse second molded article surfaces; the bottom second molded article surface is ground to expose a first conductive bump to the outside of the second molded article; an electromagnetic interference (EMI) shielding layer is formed, the EMI shielding layer at least covering the top first molded article surface, the transverse first molded article surfaces, the transverse substrate surface, the transverse second molded article surfaces, and the bottom second molded article surface; at least one exposure hole is formed in the EMI shielding layer to expose the first conductive bump to the outside of the EMI shielding layer; and a plurality of second conductive bumps are formed, each of the plurality of second conductive bumps being electrically connected to a corresponding one of the first conductive bumps exposed through at least one exposure hole in the EMI shielding layer. In the method, the second molded article extends at least laterally to the transverse substrate surface. In the method, forming at least one exposure hole in the EMI shielding layer includes ablating the at least one exposure hole in the EMI shielding layer. The method further includes coupling a second electronic device to and electrically connecting it to the bottom substrate surface, wherein each of the plurality of first conductive bumps at least vertically spans the entire height of the second electronic device.

Implementation Method

[0016] The following discussion illustrates various aspects of the invention by way of examples. Such examples are non-limiting, and thus the scope of various aspects of the invention should not be limited by any particular feature of the examples provided. In the following discussion, the terms “for example,” “e.g.,” and “exemplary” are non-limiting and are generally synonymous with “by way of example and not limiting,” “for example and not limiting,” etc.

[0017] As used herein, “and / or” means any one or more items in a list linked by “and / or”. As an example, “x and / or y” means any element in the three-element set {(x), (y), (x, y)}. In other words, “x and / or y” means “one or both of x and y”. As another example, “x, y and / or z” means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y and / or z” means “one or more of x, y and z”.

[0018] The terminology used herein is for the purpose of describing particular instances only and is not intended to limit the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising,” “including,” “having,” etc., when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0019] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, for example, without departing from the teachings of the invention, the first element, first member, or first part discussed below may be referred to as the second element, second member, or second part. Similarly, various spatial terms, such as “upper,” “lower,” “side,” etc., may be used to distinguish one element from another in a relative manner. However, it should be understood that members may be oriented in different ways; for example, without departing from the teachings of the invention, a semiconductor device may be laterally rotated such that its “top” surface is horizontal and its “side” surface is vertical.

[0020] In the drawings, the thickness or size of layers, areas, and / or components may be enlarged for clarity. Therefore, the scope of the invention should not be limited by such thickness or size. Additionally, in the drawings, similar element symbols may refer to similar elements throughout the discussion.

[0021] Furthermore, it should be understood that when element A is referred to as being “connected to” or “coupled to” element B, element A may be directly connected to element B or indirectly connected to element B (e.g., insert element C (and / or other elements) may exist between element A and element B).

[0022] Some embodiments of the present invention relate to semiconductor packaging and methods of manufacturing the same.

[0023] Various electronic devices used for exchanging signals and multiple semiconductor packages manufactured in various structures are integrated into various electronic systems, and therefore electromagnetic interference (EMI) can inevitably be generated when the semiconductor packages and electronic devices are electrically operated.

[0024] EMI can generally be defined as the combined radiation of an electric field and a magnetic field. EMI can be generated by an electric field and a magnetic field, the electric field being formed by the current flowing in a conductive material.

[0025] If EMI is generated from semiconductor packages and electronic devices densely packaged on the motherboard, then other adjacent semiconductor packages may be directly or indirectly affected by EMI and may be damaged.

[0026] Various embodiments of the present invention provide a semiconductor package and a method for manufacturing the same, which can prevent warping by forming a molding on two surfaces of a substrate and can shield EMI by forming an electromagnetic interference (EMI) shielding layer covering the molding and the substrate.

[0027] According to one aspect of the present invention, a semiconductor package is provided, the semiconductor package comprising: a substrate having a first surface and a second surface opposite to the first surface; at least one first electronic device formed on the first surface and electrically connected to the substrate; a first molding article formed on the first surface to cover the first electronic device; a second molding article formed to cover the second surface; a plurality of first conductive bumps formed on the second surface and electrically connected to the substrate and passing through the second molding article; an electromagnetic interference (EMI) shielding layer formed around the surface of the substrate, the first molding article and the second molding article to be spaced apart from the first conductive bumps; and a plurality of second conductive bumps formed on a surface of the second molding article to be correspondingly electrically connected to the plurality of first conductive bumps.

[0028] According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided, the semiconductor package comprising: a substrate having a first surface and a second surface opposite to the first surface; at least one first electronic device formed on the first surface and electrically connected to the substrate; and a plurality of first conductive bumps formed on the second surface and electrically connected to the substrate, the method comprising: forming a first molding article on the first surface to cover the first electronic device and forming a second molding article on the second surface to cover the first conductive bumps; grinding the second molding article to expose the plurality of first conductive bumps to the outside; forming a plurality of second conductive bumps correspondingly electrically connected to the exposed plurality of first conductive bumps; placing a jig under the second molding article to surround the plurality of second conductive bumps; and forming an EMI shielding layer to cover the surface of the substrate, the first molding article and the second molding article, the surface of the substrate, the first molding article and the second molding article being exposed to the outside by the jig.

[0029] According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided, the semiconductor package comprising: a substrate having a first surface and a second surface opposite to the first surface; at least one first electronic device formed on the first surface and electrically connected to the substrate; and a plurality of first conductive bumps formed on the second surface and electrically connected to the substrate, the method comprising: forming a first molding article on the first surface to cover the first electronic device and forming a second molding article on the second surface to cover the first conductive bumps; grinding the second molding article to expose the plurality of first conductive bumps to the outside; forming an EMI shielding layer to completely cover the surface of the substrate, the first molding article and the second molding article; forming a plurality of exposure holes in the EMI shielding layer to expose the plurality of first conductive bumps to the outside; and forming a plurality of second conductive bumps, the second conductive bumps being electrically connected to the exposed plurality of first conductive bumps respectively through the plurality of exposure holes.

[0030] As described above, in the semiconductor packaging and manufacturing method of the present invention, warping can be prevented by forming a molding on both surfaces of the substrate and electromagnetic interference can be shielded by forming an electromagnetic interference (EMI) shielding layer to cover the molding and the substrate.

[0031] Other embodiments, features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings.

[0032] Referring to FIG1, a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention is shown.

[0033] As illustrated in Figure 1, the semiconductor package 100 includes a substrate 110, a first electronic device 120, a second electronic device 130, a first molding article 140, a second molding article 150, a first conductive bump 160, a second conductive bump 170, and an electromagnetic interference (EMI) shielding layer 180.

[0034] The substrate 110 is formed into a panel having a first surface 110a and a second surface 110b opposite to the first surface 110a. Here, the first surface 110a of the substrate 110 may be a top surface, and the second surface 110b may be a bottom surface, and vice versa. The substrate 110 includes a plurality of first wire patterns 111 formed on the first surface 110a and a plurality of second wire patterns 112 formed on the second surface 110b. In addition, the substrate 110 may further include a plurality of conductive patterns 113 electrically connecting the first wire patterns 111 formed on the first surface 110a of the substrate 110 and the second wire patterns 112 formed on the second surface 110b. The conductive patterns 113 may be configured to penetrate or partially penetrate between the first surface 110a and the second surface 110b of the substrate 110 to connect the plurality of wire patterns formed by multiple layers. In other words, when the substrate 110 is a single layer, the conductive pattern 113 can be directly connected to the first wire pattern 111 and the second wire pattern 112, or an additional wire pattern can be used to connect the first wire pattern 111 and the second wire pattern 112. That is to say, the first wire pattern 111, the second wire pattern 112 and the conductive pattern 113 of the substrate 110 can be implemented in various structures and types, but the various forms of the present invention are not limited thereto.

[0035] Multiple first electronic devices 120 are mounted on a first surface 110a of a substrate 110 to be electrically connected to a first wiring pattern 111 of the substrate 110. The multiple first electronic devices 120 may include semiconductor dies 121 and passive elements 122, which may be modified in various ways depending on the type of semiconductor package 100, but the embodiments of the present invention are not limited thereto. In the following description, multiple first electronic devices 120 comprising two semiconductor dies 121 and two passive elements 122 will be described by way of example. Additionally, the semiconductor dies 121 are formed in a flip-chip type and may be mounted such that conductive bumps of the semiconductor dies 121 are soldered to the first wiring pattern 111 of the substrate 110. The semiconductor dies 121 may include bonding pads and may be wire-bonded to the first wiring pattern 111. However, the present invention does not limit the connection relationship between the semiconductor dies 121 and the first wiring pattern 111 to the manner disclosed herein.

[0036] (A plurality of) second electronic devices 130 are mounted on the second surface 110b of the substrate 110 to be electrically connected to the second wire pattern 112 formed on the substrate 110. The (a plurality of) second electronic devices 130 comprising a single semiconductor die have been described. However, the (a plurality of) second electronic devices 130 may be composed of multiple semiconductor dies or may further include passive elements, but the embodiments of the present invention are not limited thereto.

[0037] A first molding article 140 may be formed on a first surface 110a of a substrate 110 to cover (a plurality of) first electronic devices 120 mounted on the first surface 110a of the substrate 110. The first molding article 140 may be made of a general molding compound resin, such as an epoxy resin, but the scope of the invention is not limited thereto. The first molding article 140 protects the first electronic devices 120 from external influences.

[0038] A second molding article 150 may be formed on a second surface 110b of a substrate 110 to cover a second electronic device 130 mounted on the second surface 110b of the substrate 110. The second molding article 150 exposes a first conductive bump 160 formed on the second surface 110b of the substrate 110 to the outside while completely covering the second electronic device 130. The second molding article 150 and the first conductive bump 160 may have the same height. The second molding article 150 and the first molding article 140 may be made of the same material. The second molding article 150 protects the second electronic device 130 from external influences.

[0039] The first conductive bump 160 may include a plurality of first conductive bumps formed on the second surface 110b of the substrate 110 to be electrically connected to the second wire pattern 112 formed on the substrate 110. The first conductive bump 160 is configured such that its side portions are surrounded by the second molding article 150 and a portion of its bottom surface is exposed to the outside through the second molding article 150. The exposed first conductive bump 160 is electrically connected to the second conductive bump 170. That is, the first conductive bump 160 is electrically connected to the second conductive bump 170 and the second wire pattern 112 formed on the substrate 110. The first conductive bump 160 may include conductive pillars, copper pillars, conductive balls, or copper balls, but the embodiments of the present invention are not limited thereto.

[0040] A second conductive bump 170 may be formed on the bottom surface of the second molding article 150 to be electrically connected to a first conductive bump 160 exposed to the outside through the second molding article 150. In the case where the semiconductor package 100 is mounted on an external device (e.g., a motherboard), the second conductive bump 170 may be used to electrically connect the semiconductor package 100 to the external device.

[0041] The EMI shielding layer 180 may be formed to completely cover a predetermined thickness of the semiconductor package 100, except for the bottom surface of the second molding 150. That is, the EMI shielding layer 180 is formed to cover the entire top surface and four side surfaces of the semiconductor package 100. In addition, the EMI shielding layer 180 may be made of a conductive material and may be electrically connected to the ground or external ground of the semiconductor package 100. The EMI shielding layer 180 may shield against EMI induced to (or generated by) the semiconductor package 100. In addition, the semiconductor package 100 may include a first mold 140 and a second mold 150 to cover both the first surface 110a and the second surface 110b of the substrate 110, thereby preventing warping of the semiconductor package 100, which may occur when the molding is formed on only one surface of the substrate 110.

[0042] Referring to FIG2, a flowchart illustrating a method for manufacturing the semiconductor package illustrated in FIG1 is shown. As illustrated in FIG2, the method (S10) for manufacturing the semiconductor package 100 includes forming a molding article (S11), grinding a second molding article (S12), forming a second conductive bump (S13), placing a fixture (S14), and forming an EMI shielding layer (S15).

[0043] Referring to Figures 3A to 3E, cross-sectional views are shown illustrating various steps of a method for manufacturing the semiconductor package illustrated in Figure 2.

[0044] First, before forming the molded article (S11), a first electronic device 120 is mounted on a first surface 110a of the substrate 110 to be electrically connected to a first wire pattern 111, a second electronic device 130 is mounted on a second surface 110b of the substrate 110 to be electrically connected to a second wire pattern 112, and a plurality of first conductive bumps 160 are subsequently formed on the second surface 110b of the substrate 110 to be electrically connected to the second wire pattern 112.

[0045] As illustrated in FIG3A, in forming the molded article (S11), the first molded article 140 is formed to cover the first surface 110a of the substrate 110 and the first electronic device 120, and the second molded article 150 is formed to cover the second surface 110b of the substrate 110, the second electronic device 130, and a plurality of first conductive bumps 160. The first molded article 140 and the second molded article 150 can be formed simultaneously. For example, the mold is placed around the substrate 110 and includes the first electronic device 120, the second electronic device 130, and the first conductive bumps 160, and the molding resin is injected into the space in the mold, thereby simultaneously forming the first molded article 140 and the second molded article 150. Here, the first electronic device 120, the second electronic device 130, the first conductive bumps 160, and the substrate 110 are spaced apart from the inner surface of the mold so as not to contact the inner surface of the mold, and the molding resin is injected into the mold, thereby forming the first molded article 140 and the second molded article 150. That is, the first molding article 140 is formed to completely cover the first surface 110a and the first electronic device 120 of the substrate 110, and the second molding article 150 is formed to completely cover the second surface 110b, the second electronic device 130 and the first conductive bump 160 of the substrate 110.

[0046] As illustrated in FIG. 3B, in the grinding (S12) of the second molded article, the bottom surface of the second molded article 150 is ground to expose the first conductive bump 160 to the outside of the second molded article 150. That is, in the grinding (S12) of the second molded article, the second molded article 150 is ground to expose the first conductive bump 160 to the outside. At this time, the bottom portion of the first conductive bump 160 may also be partially ground. The bottom surface of the first conductive bump 160 and the bottom surface of the second molded article 150 may be coplanar. In addition, the second electronic device 130 may be placed inside the second molded article 150, and the second electronic device 130 may, for example, not be exposed to the outside. The grinding can be performed using, for example, a diamond grinding machine and its equivalents, but the embodiments of the present invention are not limited thereto.

[0047] As illustrated in FIG3C, in the formation of the second conductive bump (S13), a plurality of second conductive bumps 170 are formed to be electrically connected to a plurality of first conductive bumps 160 that are exposed to the outside in the grinding (S12) of the second molded article. The second conductive bumps 170 can be formed using ball dropping, screen printing, electroplating, vacuum evaporation, electroplating and equivalents thereof, but the embodiments of the present invention are not limited thereto. In addition, the second conductive bumps 170 can be made of metallic materials, such as lead / tin (Pb / Sn) or lead-free Sn and equivalents thereof, but the embodiments of the present invention are not limited thereto.

[0048] As illustrated in FIG3D, during the placement of the fixture (S14), the fixture 10 is loaded and positioned to cover the bottom surface 150b of the second molded article 150. The fixture 10 is formed as a substantially rectangular frame and may have an internal space 11 and a flat portion 12, the internal space having a predetermined depth in the top-to-bottom direction, and the flat portion extending outward along the outer circumference by a predetermined length. The flat portion 12 may be made to contact the outer circumference of the bottom surface 150b of the second molded article 150 for subsequent fixation, and a second conductive bump 170 formed on the bottom surface 150b of the second molded article 150 may be inserted into the internal space 11. That is, during the placement of the fixture (S14), the fixture 10 is positioned to cover the bottom surface 150b of the second molded article 150, and the side surfaces of the first molded article 140, the substrate 110, and the second molded article 150 are exposed to the outside.

[0049] As illustrated in FIG3E, in the formation of the EMI shielding layer (S15), the EMI shielding layer 180 is formed on the side surfaces of the first molding article 140, the substrate 110, and the second molding article 150. During the placement of the jig (S14), the side surfaces of the first molding article 140, the substrate 110, and the second molding article 150 are exposed to the outside. The EMI shielding layer 180 is formed to completely cover all the side surfaces of the first molding article 140, the substrate 110, and the second molding article 150, except that the bottom surface 150b of the second molding article 150 is covered by the jig 10. That is, the EMI shielding layer 180 is formed to completely cover all four side surfaces and the top surface of the semiconductor package 100, except for the bottom surface of the semiconductor package 100. The EMI shielding layer 180 can be formed to a predetermined thickness by plasma deposition or spraying, but the embodiments of the present invention are not limited thereto. Additionally, after forming the EMI shielding layer (S15), cleaning may be performed to remove any metal residues produced during the formation of the EMI shielding layer 180 made of conductive material. Furthermore, after forming the EMI shielding layer 180 and performing cleaning, the jig 10 placed under the second molding article 150 is separated to complete the semiconductor package 100 having the EMI shielding layer 180. In Figures 3A to 3E, a single semiconductor package 100 is manufactured; however, multiple semiconductor packages may be formed on the substrate 110 to be subsequently separated into discrete semiconductor packages 100 by a separation process.

[0050] Referring to FIG4, a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention is shown.

[0051] As illustrated in FIG. 4, the semiconductor package 200 includes a substrate 110, a first electronic device 120, a second electronic device 130, a first molding compound 140, a second molding compound 150, a first conductive bump 160, a second conductive bump 170, and an EMI shielding layer 280. The semiconductor package 200, including the substrate 110, the first electronic device 120, the second electronic device 130, the first molding compound 140, the second molding compound 150, the first conductive bump 160, and the second conductive bump 170, has the same configuration as the semiconductor package 100 illustrated in FIG. 1. Therefore, the following description of the semiconductor package 200 will focus on the EMI shielding layer 280, which is a feature different from that of the semiconductor package 100 illustrated in FIG. 1.

[0052] The EMI shielding layer 280 is formed to cover the top surface, four side surfaces, and bottom surface of the semiconductor package 200 to a predetermined thickness and may expose the second conductive bump 170 to the outside. That is, the EMI shielding layer 280 may be formed to completely cover the semiconductor package 200 except for the second conductive bump 170. In addition, the EMI shielding layer 280 may be made of a conductive material and may be electrically connected to the ground or external ground of the semiconductor package 200.

[0053] The EMI shielding layer 280 may include a plurality of exposure holes 280a. The second conductive bump 170 may be exposed to the outside of the EMI shielding layer 280 through the exposure holes 280a. That is, the exposure holes 280a of the EMI shielding layer 280 may be positioned to correspond to the second conductive bump 170.

[0054] Furthermore, the exposure hole 280a may have a width larger than the diameter of the second conductive bump 170. That is, the EMI shielding layer 280 may be spaced apart from the second conductive bump 170 by a predetermined distance (d) through the exposure hole 280a and may be electrically disconnected from the second conductive bump 170 made of conductive material. Here, the portion of the second molded article 150 surrounding the second conductive bump 170 may be exposed to the outside of the exposure hole 280a of the EMI shielding layer 280.

[0055] The EMI shielding layer 280 is formed to cover the entire surface of the semiconductor package 200, except for the second conductive bump 170 which serves as an external terminal, thereby shielding EMI induced by the semiconductor package 200 (or induced on the semiconductor package).

[0056] The semiconductor package 200 illustrated in FIG. 4 can be manufactured by the semiconductor package manufacturing method illustrated in FIG. 2. Referring to FIGS. 5A and 5B, cross-sectional views are shown illustrating the various steps in the method for manufacturing the semiconductor package illustrated in FIG. 4 by the semiconductor package manufacturing method illustrated in FIG. 2. Hereinafter, the method for manufacturing the semiconductor package 200 will be described with reference to FIGS. 2, 5A and 5B.

[0057] As illustrated in FIG2, the method (S10) for manufacturing a semiconductor package 200 includes forming a molded article (S11), grinding a second molded article (S12), forming a second conductive bump (S13), placing a fixture (S14), and forming an EMI shielding layer (S15). Here, the forming of the molded article (S11), the grinding of the second molded article (S12), and the forming of the second conductive bump (S13) are the same steps as the corresponding steps in the method for manufacturing a semiconductor package 100 illustrated in FIGS. 3A to 3C. Therefore, referring to FIGS. 5A and 5B, the following description of the method (S10) for manufacturing a semiconductor package 200 will focus on the placement of the fixture (S14) and the formation of the EMI shielding layer (S15), which are features different from those in the method for manufacturing a semiconductor package 100 illustrated in FIGS. 3A to 3C.

[0058] As illustrated in FIG5A, during the placement of the fixture (S14), the fixture 20 is loaded and positioned to cover the bottom portion of the second molded article 150. As illustrated in FIG6, the fixture 20 is shaped as a substantially rectangular frame and may have a plurality of recesses 21 having a depth in the top-to-bottom direction. The fixture 20 may include a plurality of recesses 21 positioned to correspond to a second conductive bump 170 of the semiconductor package 200, and the second conductive bump 170 may be inserted into the plurality of recesses 21 accordingly. That is, the second conductive bump 170 may be surrounded by the fixture 20. Here, in order to allow the second conductive bump 170 to enter the plurality of recesses 21 of the fixture 20, the plurality of recesses 21 preferably have a diameter larger than that of the second conductive bump 170.

[0059] Additionally, the clamp 20 is formed as a rectangular ring, the central portion of which is opened through a centrally formed hole 22. That is, the central portion of the bottom surface 150b of the second molded article 150, which is not adjacent to (or immediately adjacent to) the second conductive bump 170, is exposed to the outside through the hole 22 of the clamp 20. The EMI shielding layer 280 can also be formed on the bottom surface of the semiconductor package 200 through the hole 22 of the clamp 20.

[0060] In the placement of the fixture (S14), the fixture 20 is placed under the second molded article 150 to cover the second conductive bump 170 and expose the first molded article 140, the substrate 110 and the second molded article 150 to the outside.

[0061] As illustrated in FIG5B, in the formation of the EMI shielding layer (S15), the EMI shielding layer 280 is formed on the first molding article 140, the substrate 110, and the second molding article 150. During the placement of the jig (S14), the first molding article 140, the substrate 110, and the second molding article 150 are exposed to the outside. That is, in the formation of the EMI shielding layer (S15), the jig 20 is used as a shield, and the EMI shielding layer 280 is formed to cover the top surface, four side surfaces, and bottom surface of the semiconductor package 200, except for the second conductive bump 170. The EMI shielding layer 280 can be formed to a predetermined thickness by plasma deposition or spraying, but the embodiments of the present invention are not limited thereto. Furthermore, after the formation of the EMI shielding layer (S15), cleaning can be performed to remove any metal residues produced during the formation of the EMI shielding layer 280 made of conductive material. Furthermore, after forming the EMI shielding layer 280 and performing cleaning, the jig 20 placed under the second molded article 150 is separated to complete the semiconductor package 200 having the EMI shielding layer 280. Additionally, once the jig 20 is separated, since the EMI shielding layer 280 is not formed on the second conductive bump 170 surrounded by the jig 20 and the portion surrounding the second conductive bump 170, an exposure hole 280a exposing the second conductive bump 170 is provided in the EMI shielding layer 280. Subsequently, the EMI shielding layer 280 can be electrically disconnected from the second conductive bump 170 through the exposure hole 280a and can be spaced apart from the second conductive bump 170 by a predetermined distance (d).

[0062] Referring to FIG7, a flowchart illustrating a method for manufacturing the semiconductor package illustrated in FIG4 according to another embodiment of the present invention is shown. As illustrated in FIG7, the method (S20) for manufacturing the semiconductor package 200 includes forming a molding article (S11), grinding a second molding article (S12), forming an EMI shielding layer (S23), forming an exposure hole (S24), and forming a second conductive bump (S25). Here, the forming of the molding article (S11) and grinding of the second molding article (S12) illustrated in FIG7 are the same as the corresponding steps in the method for manufacturing the semiconductor package 100 illustrated in FIGS. 2, 3A, and 3B.

[0063] Referring to Figures 8A to 8C, cross-sectional views illustrating the steps of forming an EMI shielding layer (S23), forming an exposure hole (S24), and forming a second conductive bump (S25) of Figure 7 are shown. Therefore, a method (S20) for manufacturing a semiconductor package 200 will be described with reference to Figures 7 and 8A to 8C.

[0064] As illustrated in FIG8A, in the formation of the EMI shielding layer (S23), the EMI shielding layer 280 is formed to completely cover the substrate 110, the first molding article 140, and the second molding article 150. The EMI shielding layer 280 can be formed to a predetermined thickness by plasma deposition or spraying, but the present invention is not limited thereto.

[0065] As illustrated in FIG8B, during the formation of the exposure holes (S24), the EMI shielding layer 280 can be partially removed to expose the first conductive bump 160 to the outside. That is, the first conductive bump 160 is exposed to the outside by forming a plurality of exposure holes 280a in the EMI shielding layer 280. The plurality of exposure holes 280a of the EMI shielding layer 280 are formed by etching or laser removal of a portion of the EMI shielding layer 280. In addition, the formation of the exposure holes 280a can be performed by any process known in the art, as long as the EMI shielding material can be patterned into a desired pattern, but not limited to the etching or laser disclosed herein. As illustrated in FIG8B, the width (d1) of each exposure hole 280a is preferably greater than the diameter (d2) of each first conductive bump 160. In order to electrically disconnect the first conductive bump 160 from the second conductive bump 170 as described later, the exposure holes 280a are preferably formed to have a sufficiently large width (i.e., d1). In addition, after the exposure hole 280a is formed, a cleaning process for removing metal residue can be performed.

[0066] As illustrated in FIG8C, in the formation of the second conductive bump (S25), the second conductive bump 170 is formed to be electrically connected to the first conductive bump 160 exposed to the outside through the exposure hole 280a. The second conductive bump 170 is preferably formed to have a larger diameter (d3) than the width (d1) of the exposure hole 280a. That is, the second conductive bump 170 can be spaced apart from the EMI shielding layer 280 by a predetermined distance to be electrically disconnected from the EMI shielding layer 280.

[0067] The discussion herein includes numerous illustrative diagrams showing the various parts of electronic package assemblies and methods of their manufacture. For clarity, these diagrams do not show all aspects of each example assembly. Any example assembly and / or method provided herein may share any or all of its features with any or all other assemblies and / or methods provided herein.

[0068] In summary, various embodiments of the present invention provide a semiconductor package and a method for manufacturing a semiconductor package. As a non-limiting example, various embodiments of the present invention provide a semiconductor package and a method for manufacturing a semiconductor package, the method including shielding on multiple sides thereof. Although the above has been described with reference to certain embodiments and examples, those skilled in the art will understand that various modifications and substitutions for equivalents can be made without departing from the scope of the invention. Furthermore, many modifications can be made to adapt specific situations or materials to the teachings of the invention without departing from the scope of the invention. Therefore, it is intended that the invention be limited to the specific examples disclosed, but rather that the invention encompass all examples falling within the scope of the appended claims. [Simplified Explanation of the Diagram]

[0008] [Figure 1] is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0009] [Figure 2] is a flowchart illustrating a method for manufacturing the semiconductor package illustrated in Figure 1.

[0010] [Figures 3A to 3E] are cross-sectional views illustrating the various steps of the method for manufacturing the semiconductor package illustrated in Figure 2.

[0011] [Figure 4] is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention.

[0012] [Figures 5A and 5B] are cross-sectional views illustrating the various steps in manufacturing the semiconductor package illustrated in Figure 4 using the semiconductor packaging manufacturing method illustrated in Figure 2.

[0013] [Figure 6] shows a plan view and a cross-sectional view illustrating the structure of the fixture described in Figure 5A.

[0014] [Figure 7] is a flowchart illustrating a method for manufacturing the semiconductor package illustrated in Figure 4 according to another embodiment of the present invention.

[0015] [Figures 8A to 8C] are cross-sectional views illustrating the various steps of the method for manufacturing the semiconductor package illustrated in Figure 7.

Claims

1. A semiconductor package comprising: A bottom substrate comprising: a top side of the substrate including a first conductive pattern; a bottom side of the substrate including a second conductive pattern; and a lateral side of the substrate; a first electronic device on the top side of the substrate and coupled to the first conductive pattern; a first molding article encapsulating at least the top side of the substrate and the first electronic device, wherein the first molding article includes: a bottom side of the first molding article facing the top side of the substrate; the top side of the first molding article; and a lateral side of the first molding article; a second electronic device mounted on the second conductive pattern on the bottom side of the substrate, the second electronic device having a top side and a bottom side, the top side facing the bottom side of the substrate; a plurality of conductive pillars on the bottom side of the substrate and including a top side of the plurality of conductive pillars coupled to the second conductive pattern; and a second molding article encapsulating at least the bottom side of the substrate and the second electronic device, wherein the second molding article includes: a top side of the second molding article facing the bottom side of the substrate; The bottom side of the second molded article, wherein the bottom sides of the plurality of conductive pillars are exposed at the lowest portion of the bottom side of the second molded article; and the lateral side of the second molded article; and the metal layer below the bottom side of the second electronic device.

2. The semiconductor package as described in claim 1, wherein the plurality of conductive pillars are copper pillars.

3. The semiconductor package as claimed in claim 1, wherein the second molding contacts the lateral side of the plurality of conductive pillars.

4. The semiconductor package as claimed in claim 1, comprising conductive bumps on the bottom side of the plurality of conductive pillars.

5. The semiconductor package as described in claim 4, wherein the conductive bumps comprise a metallic material that is different from the material of the plurality of conductive pillars.

6. The semiconductor package as claimed in claim 1, comprising a metal material on the bottom side of the plurality of conductive pillars, wherein the metal material is different from the material of the plurality of conductive pillars.

7. The semiconductor package as claimed in claim 1, further comprising an electromagnetic interference shield formed as the boundary of the top side of the first molding article, the lateral side of the first molding article, and the lateral side of the substrate.

8. A semiconductor package comprising: A bottom substrate, the bottom substrate comprising: a substrate top side including a first conductive pattern; a substrate bottom side including a second conductive pattern; and a substrate lateral side; a first electronic device on the substrate top side and coupled to the first conductive pattern; a first molding article encapsulating at least the substrate top side and the first electronic device, wherein the first molding article includes: a first molding article bottom side facing the substrate top side; the first molding article top side; and the first molding article lateral side; a second electronic device on the substrate bottom side and coupled to the second conductive pattern, the second electronic device having a top side and a bottom side, the top side facing the substrate bottom side; a plurality of conductive pillars on the substrate bottom side and including a top side of the plurality of conductive pillars coupled to the second conductive pattern; a second molding article encapsulating at least the substrate bottom side and the second electronic device, wherein the second molding article includes: a second molding article top side facing the substrate bottom side; and a second molding article bottom side; The second molded article has a lateral side; and a plurality of holes extending from the uppermost portion of the top side of the second molded article to the lowermost portion of the bottom side of the second molded article, wherein each of the plurality of holes is filled by a different conductive post of the plurality of conductive posts; and a metal layer beneath the bottom side of the second electronic device.

9. The semiconductor package as described in claim 8, wherein the plurality of conductive pillars are copper pillars.

10. The semiconductor package as claimed in claim 8, wherein the second molding contacts the lateral side of the plurality of conductive pillars.

11. The semiconductor package as claimed in claim 8, comprising conductive bumps on the bottom side of the plurality of conductive pillars.

12. The semiconductor package as claimed in claim 11, wherein the conductive bumps comprise a metallic material that is different from the material of the plurality of conductive pillars.

13. The semiconductor package as claimed in claim 8, comprising a metal material on the bottom side of the plurality of conductive pillars, wherein the metal material is different from the material of the plurality of conductive pillars.

14. The semiconductor package as claimed in claim 8, further comprising an electromagnetic interference shield formed as the boundary of the top side of the first molding article, the lateral side of the first molding article, and the lateral side of the substrate.

15. A method for manufacturing a semiconductor package, comprising: A bottom substrate is provided, the bottom substrate comprising: a top side of the substrate including a first conductive pattern; a bottom side of the substrate including a second conductive pattern; and a lateral side of the substrate; a first electronic device is provided on the top side of the substrate and coupled to the first conductive pattern; a first molding article is provided that at least encloses the top side of the substrate and the first electronic device, wherein the first molding article comprises: a bottom side of the first molding article facing the top side of the substrate; the top side of the first molding article; and a lateral side of the first molding article; a second electronic device is provided on the bottom side of the substrate and coupled to the second conductive pattern, the second electronic device having a top side and a bottom side, the top side facing the bottom side of the substrate; a plurality of conductive pillars are provided on the bottom side of the substrate and include a top side of the plurality of conductive pillars coupled to the second conductive pattern; a second molding article is provided that at least encloses the bottom side of the substrate and the second electronic device, wherein the second molding article comprises: a top side of the second molding article facing the bottom side of the substrate; and a bottom side of the second molding article; The second molded article has a lateral side; and a plurality of holes extending from the uppermost portion of the top side of the second molded article to the lowermost portion of the bottom side of the second molded article, wherein each of the plurality of holes is filled by a different conductive post of the plurality of conductive posts; and a metal layer is provided below the bottom side of the second electronic device.

16. The method as described in claim 15, wherein the plurality of conductive pillars are copper pillars.

17. The method as described in claim 15, wherein the second molded article contacts the lateral side of the plurality of conductive posts.

18. The method as described in claim 15, comprising providing conductive bumps on the bottom side of the plurality of conductive posts, wherein the conductive bumps comprise a metallic material different from the material of the plurality of conductive posts.

19. The method as described in claim 15, comprising providing a metallic material on the underside of the plurality of conductive pillars, wherein the metallic material is different from the material of the plurality of conductive pillars.

20. The method as described in claim 15, comprising providing an electromagnetic interference shield formed as a boundary of the top side of the first molding article, the lateral side of the first molding article, and the lateral side of the substrate.

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