Single-photon avalanche diode (SPAD) devices including a superlattice at multiplication region interface and related methods

Abstract

A single-photon avalanche diode (SPAD) device may include: a semiconductor substrate having a first conductivity type; a deep well region in the semiconductor substrate having a second conductivity type different from the first conductivity type; and a multiplication region in the deep well region having the second conductivity type. The SPAD device may further include a central active region located on the multiplication region and having the first conductivity type; a guard ring surrounding the central active region and the multiplication region and having the first conductivity type; and a superlattice layer adjacent to an interface between the multiplication region and the central active region. The superlattice layer may include a plurality of stacked layer groups, each layer group comprising a plurality of stacked substrate semiconductor monolayers collectively defining a substrate semiconductor portion, and including at least one non-semiconductor monolayer confined within a lattice of an adjacent substrate semiconductor portion.

Claims

1. A single-photon avalanche diode (SPAD) device, comprising: A semiconductor substrate having a first conductivity type; a deep well region in the semiconductor substrate having a second conductivity type different from the first conductivity type; a multiplication region in the deep well region having the second conductivity type; a central active region located on the multiplication region and having the first conductivity type; a guard ring surrounding the central active region and the multiplication region and having the first conductivity type; and a superlattice layer adjacent to an interface between the multiplication region and the central active region, the superlattice layer comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked substrate semiconductor monolayers collectively defining a substrate semiconductor portion, and comprising at least one non-semiconductor monolayer confined in a lattice of an adjacent substrate semiconductor portion.

2. The SPAD element of claim 1, wherein the superlattice layer is located at the interface between the multiplication region and the central active region.

3. The SPAD element as claimed in claim 2, wherein the superlattice layer is located inside the protective ring.

4. The SPAD element as claimed in claim 2, wherein the superlattice layer extends beyond the protective ring.

5. The SPAD element of claim 1, wherein the superlattice layer is embedded within the central active region.

6. The SPAD element as claimed in claim 1 includes a plurality of contact areas adjacent to the protective ring.

7. The SPAD element of claim 1, wherein the first conductivity type includes p-type and the second conductivity type includes n-type.

8. The SPAD element of claim 1, wherein the substrate semiconductor comprises silicon.

9. The SPAD element of claim 1, wherein the substrate semiconductor comprises germanium.

10. The SPAD element of claim 1, wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen.

11. The SPAD element of claim 1, wherein the at least one non-semiconductor monolayer comprises oxygen.

12. A method for manufacturing a single-photon avalanche diode (SPAD) element, comprising: A deep well region is formed in a semiconductor substrate having a first conductivity type, the deep well region having a second conductivity type different from the first conductivity type; a multiplication region is formed in the deep well region having the second conductivity type; a central active region having the first conductivity type is formed on the multiplication region; a guard ring having the first conductivity type is formed around the central active region and the multiplication region; and a superlattice layer is formed adjacent to an interface between the multiplication region and the central active region, the superlattice layer comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked substrate semiconductor monolayers collectively defining a substrate semiconductor portion, and comprising at least one non-semiconductor monolayer confined in a lattice of an adjacent substrate semiconductor portion.

13. The method of claim 12, wherein the superlattice layer is located at the interface between the multiplication region and the central active region.

14. The method of claim 13, wherein the superlattice layer is located inside the protective ring.

15. The method of claim 13, wherein the superlattice layer extends beyond the protective ring.

16. The method of claim 12, wherein the superlattice layer is embedded within the central active region.

17. The method of claim 12 further includes forming a plurality of contact areas adjacent to the protective ring.

18. The method of claim 12, wherein the first conductivity type includes p-type and the second conductivity type includes n-type.

19. The method of claim 12, wherein the substrate semiconductor comprises silicon.

20. The method of claim 12, wherein the substrate semiconductor comprises germanium.

21. The method of claim 12, wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen.

22. The method of claim 12, wherein the at least one non-semiconductor monolayer comprises oxygen.

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