Fuse arrays improve write speed

Abstract

A fuse array includes multiple word lines, multiple select lines, multiple bit lines, and multiple sub-fuse arrays. The sub-fuse arrays are disposed in a semiconductor region and include a first fuse gate, a second fuse gate, a doped well region, a dielectric layer, a first heavily doped region, a second heavily doped region, a third heavily doped region, a fourth heavily doped region, and a fifth heavily doped region. The second heavily doped region is located within the doped well region. The first, second, third, fourth, and fifth heavily doped regions are respectively coupled to a first select line, a first bit line, a second select line, a third select line, and a fourth select line. The doped well region can be replaced by a lightly doped region, and the second heavily doped region penetrates the portion of the lightly doped region that does not overlap with the first and second fuse gates.