Plasma processing apparatus and plasma processing method

Abstract

This invention provides a plasma processing apparatus and a plasma processing method, which appropriately control the tilt angle of the edge region of a substrate during plasma processing and suppress discharge between the substrate and the edge ring. The plasma processing apparatus includes: a processing chamber; a platform disposed inside the processing chamber, having electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck to surround a substrate placed on the electrostatic chuck; a high-frequency power supply for supplying high-frequency power for generating plasma from gas inside the processing chamber; a DC power supply for applying a negative DC voltage to the edge ring; and a control unit for controlling the DC voltage. The processing includes the following steps: (a) stopping the supply of high-frequency power and stopping the application of DC voltage; and (b) starting the supply of high-frequency power, and after a predetermined delay time, starting the application of DC voltage.

Description

Technical Field

[0001] This invention relates to a plasma treatment apparatus and a plasma treatment method. Prior Technology

[0002] Patent Document 1 discloses a plasma processing apparatus comprising a stage for holding a wafer disposed within a processing chamber, and an edge ring disposed on the stage in a manner surrounding the wafer, for performing plasma processing on the wafer. In this plasma processing apparatus, by applying a negative DC voltage to the edge ring consumed by plasma, the deformation of the sheath layer is resolved, allowing ions to be incident perpendicularly across the entire surface of the wafer. [Known Technical Literature] [Patent Literature]

[0003] Patent Document 1: Japanese Patent Application Publication No. 2008-227063 Summary of the Invention

[0004] [The problem that this invention aims to solve]

[0005] The technology disclosed in this invention appropriately controls the tilt angle of the edge region of the substrate during plasma processing and suppresses discharge between the substrate and the edge ring. [Technical means to solve the problem]

[0006] One aspect of the present invention is an apparatus for performing plasma treatment on a substrate, comprising: a processing chamber; a platform disposed inside the processing chamber, including electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck to surround a substrate placed on the electrostatic chuck; a high-frequency power supply for supplying high-frequency power for generating plasma from gas inside the processing chamber; a DC power supply for applying a negative DC voltage to the edge ring; and a control unit for controlling the high-frequency power and the DC voltage; the control unit controls the apparatus to perform a process comprising the following steps: (a) stopping the supply of the high-frequency power and stopping the application of the DC voltage; and (b) starting the supply of the high-frequency power and, after a predetermined delay time, starting the application of the DC voltage. [Effects of the Invention]

[0007] According to the present invention, the tilt angle of the edge region of the substrate can be appropriately controlled during plasma processing, and the discharge between the substrate and the edge ring can be suppressed. Simple Explanation of the Diagram

[0008] Figure 1 is a longitudinal sectional view showing the general structure of the plasma processing apparatus of this embodiment. Figure 2 is an illustration of the power supply system for applying DC voltage to the edge ring in this embodiment. Figures 3(a) and (b) are explanatory diagrams showing the conventional RF ON / OFF, DC ON / OFF, and electrical neutralization ON / OFF. Figures 4(a) and (b) are explanatory diagrams showing the RF on / off, DC on / off, and electrical neutralization on / off in this embodiment. Figure 5 is an explanatory diagram showing the time-dependent changes in high-frequency power and DC voltage in this embodiment. Figure 6 is a table showing the RF on / off, DC on / off, and electrical neutralization on / off states in Figure 5. Figure 7 is an explanatory diagram showing the state of the DC power supply circuit and the electrical neutralization circuit in Figure 5. Figures 8(a) to (c) are illustrations of power supply systems that apply DC voltage to the edge ring in other embodiments. Figures 9(a) and (b) are illustrations of power supply systems that apply DC voltage to the edge ring in other embodiments. Figure 10 is an illustration of a power supply system that applies a DC voltage to the edge ring in other embodiments. Implementation

[0009] In the manufacturing process of semiconductor devices, plasma processing is performed on semiconductor wafers (hereinafter referred to as "wafers"). In plasma processing, plasma is generated by exciting processing gases, and the wafer is processed by the plasma.

[0010] Plasma processing is performed using a plasma processing apparatus. A plasma processing apparatus generally includes a processing chamber, a platform, and a radio frequency (RF) power supply. In one example, the RF power supply includes a first RF power supply and a second RF power supply. The first RF power supply provides first RF power to generate plasma in the gas within the processing chamber. The second RF power supply provides second RF power for biasing the lower electrode to introduce ions into the wafer. The processing chamber defines its internal space as the processing space for generating plasma. The platform is disposed within the processing chamber. The platform includes a lower electrode and an electrostatic chuck. The electrostatic chuck is disposed on the lower electrode. An edge ring is disposed on the electrostatic chuck in a manner that surrounds the wafer placed on the electrostatic chuck. The edge ring is provided to improve the uniformity of plasma processing on the wafer.

[0011] The edge ring is consumed over time during plasma processing. Once the edge ring is consumed, its thickness decreases. As the edge ring thickness decreases, the shape of the sheath layer above the edge ring and the edge region of the wafer changes. Consequently, once the shape of the sheath layer changes, the incident direction of ions in the edge region of the wafer becomes tilted relative to the vertical direction. As a result, the opening formed in the edge region of the wafer is tilted relative to the thickness direction of the wafer.

[0012] In order to form an opening extending parallel to the thickness direction of the wafer in the edge region, it is necessary to control the shape of the edge ring and the sheath layer above the edge region of the wafer, and adjust the tilt angle (hereinafter referred to as "tilt angle") of the incident direction of ions towards the edge region of the wafer. Therefore, in order to control the shape of the edge ring and the sheath layer above the edge region of the wafer, for example, Patent Document 1 proposes a plasma processing apparatus configured to apply a negative DC voltage to the edge ring from a DC power supply.

[0013] In conventional plasma processing apparatuses, high bias voltages are generated. Therefore, when high-frequency power is pulsed onto the wafer, there is a concern that discharge may occur due to the potential difference between the wafer and the edge ring. Thus, plasma processing apparatuses are equipped with the following functions: synchronizing with the pulse of the high-frequency power supply, applying a DC voltage when high-frequency power is supplied, and further neutralizing the edge ring electrically when the high-frequency power supply is stopped.

[0014] However, when high-frequency power is supplied in a pulsed manner, the bias voltage does not rise immediately due to the reflection of the high-frequency power (reflected power). Furthermore, when the high-frequency power supply is stopped, the charge on the wafer is not immediately removed. Therefore, if a DC voltage is immediately applied to the edge ring in sync with the high-frequency power supply, or if the edge ring is electrically neutralized, a potential difference will be generated between the wafer and the edge ring, raising concerns about potential discharge. As a result, wafer damage may occur.

[0015] The technology disclosed in this invention can appropriately control the tilt angle of the edge region of the substrate during plasma processing and suppress discharge between the substrate and the edge ring. Hereinafter, the plasma processing apparatus and plasma processing method of this embodiment will be described with reference to the drawings. Furthermore, in this specification and drawings, elements having substantially the same functional configuration are given the same reference numerals to omit redundant descriptions.

[0016] <Plasma Treatment Device> First, the plasma processing apparatus of this embodiment will be described. Figure 1 is a longitudinal sectional view showing the general structure of the plasma processing apparatus 1. Figure 2 is an explanatory diagram of the power supply system for applying DC voltage to the edge ring 14. The plasma processing apparatus 1 is a capacitively coupled type plasma processing apparatus. In the plasma processing apparatus 1, plasma processing is performed on the wafer W, which serves as a substrate. The plasma processing is not particularly limited, and for example, etching, film formation, diffusion, etc., are performed.

[0017] As shown in Figure 1, the plasma processing apparatus 1 includes a slightly cylindrical processing chamber 10. The processing chamber 10 defines a processing space S for generating plasma within it. The processing chamber 10 is, for example, made of aluminum. The processing chamber 10 is connected to a grounding potential.

[0018] Inside the processing chamber 10, a platform 11 for mounting the wafer W is housed. The platform 11 includes a lower electrode 12, an electrostatic chuck 13, and an edge ring 14. Alternatively, an electrode plate (not shown) made of aluminum may be provided on the bottom surface of the lower electrode 12.

[0019] The lower electrode 12 is made of a conductive metal, such as aluminum, and has a slightly circular plate shape.

[0020] A refrigerant flow path 15a is formed inside the lower electrode 12. Refrigerant is supplied from a quench cooler unit (not shown) located outside the processing chamber 10 to the refrigerant flow path 15a via a refrigerant inlet pipe 15b. The refrigerant supplied to the refrigerant flow path 15a returns to the quench cooler unit via a refrigerant outlet flow path 15c. By circulating the refrigerant, such as cooling water, within the refrigerant flow path 15a, the electrostatic chuck 13, the edge ring 14, and the wafer W can be cooled to the desired temperature.

[0021] An electrostatic chuck 13 is disposed on the lower electrode 12. The electrostatic chuck 13 is a component that can hold the wafer W and the edge ring 14 together by electrostatic force. The top surface of the central portion of the electrostatic chuck 13 is formed to be higher than the top surface of the edge portion. The top surface of the central portion of the electrostatic chuck 13 becomes the wafer mounting surface for placing the wafer W; the top surface of the edge portion of the electrostatic chuck 13 becomes the edge ring mounting surface for placing the edge ring 14.

[0022] Inside the electrostatic chuck 13, a first electrode 16a is provided at the center for adsorbing and holding the wafer W. Inside the electrostatic chuck 13, a second electrode 16b is provided at the edge for adsorbing and holding the edge ring 14. The electrostatic chuck 13 has a configuration that clamps the electrodes 16a and 16b between insulating materials made of insulating material.

[0023] A DC voltage from a DC power supply (not shown) is applied to the first electrode 16a. The resulting electrostatic force attracts and holds the wafer W to the top surface of the center portion of the electrostatic chuck 13. Similarly, a DC voltage from a DC power supply (not shown) is applied to the second electrode 16b. The resulting electrostatic force attracts and holds the edge ring 14 to the top surface of the edge portion of the electrostatic chuck 13.

[0024] In this embodiment, the central part of the electrostatic chuck 13 where the first electrode 16a is provided is integrated with the edge part where the second electrode 16b is provided, but the central part and the edge part can also be different components.

[0025] The edge ring 14 is an annular member arranged to surround the wafer W placed on the top surface of the center of the electrostatic chuck 13. The edge ring 14 is provided to improve the uniformity of the plasma processing. Therefore, the edge ring 14 is made of a material appropriately selected for the plasma processing, such as Si or SiC.

[0026] The platform 11, constructed as described above, is fastened to a slightly cylindrical support member 17 located at the bottom of the processing chamber 10. The support member 17 is made of an insulator, for example, ceramic or quartz.

[0027] Alternatively, although the illustration is omitted, platform 11 may also include a temperature control module configured to adjust at least one of the electrostatic chuck 13, edge ring 14, and wafer W to a desired temperature. The temperature control module may also include a heater, a flow path, or a combination thereof. Temperature-controlled fluids such as refrigerant or heat transfer gas flow through the flow path.

[0028] A shower head 20 is installed above the platform 11, facing it. The shower head 20 has an electrode plate 21 arranged facing the processing space S, and an electrode support 22 disposed above the electrode plate 21. The electrode plate 21 functions as an upper electrode paired with the lower electrode 12. As described later, when the first high-frequency power supply 50 is electrically connected to the lower electrode 12, the shower head 20 is connected to ground potential. Furthermore, the shower head 20 is supported on the upper part (ceiling surface) of the processing chamber 10 via an insulating shielding member 23.

[0029] The electrode plate 21 is provided with a plurality of gas outlets 21a for supplying the processing gas conveyed from the gas diffusion chamber 22a (described later) to the processing space S. The electrode plate 21 is, for example, made of a conductor or semiconductor with low resistivity that generates little Joule heat.

[0030] Electrode support 22 supports electrode plate 21 in a detachable manner. Electrode support 22 may have, for example, a plasma-resistant film formed on the surface of a conductive material such as aluminum. This film may be a ceramic film formed by anodizing or by yttrium oxide. A gas diffusion chamber 22a is formed inside electrode support 22. A plurality of gas flow holes 22b communicating with gas outlet 21a are formed from gas diffusion chamber 22a. Furthermore, a gas inlet hole 22c connected to the gas supply pipe 33 (described later) is formed in gas diffusion chamber 22a.

[0031] In addition, the gas supply source group 30 that supplies processing gas to the gas diffusion chamber 22a is connected to the electrode support 22 via the flow control machine group 31, the valve group 32, the gas supply pipe 33, and the gas inlet port 22c.

[0032] The gas supply source group 30 includes a plurality of gas supply sources required for plasma treatment. The flow control machine group 31 includes a plurality of flow controllers, and the valve group 32 includes a plurality of valves. The plurality of flow controllers in the flow control machine group 31 are either mass flow controllers or pressure-controlled flow controllers. In the plasma treatment apparatus 1, the treatment gas from one or more gas supply sources selected from the free gas supply source group 30 is supplied to the gas diffusion chamber 22a via the flow control machine group 31, the valve group 32, the gas supply pipe 33, and the gas inlet port 22c. Then, the treatment gas supplied to the gas diffusion chamber 22a is dispersed into the treatment space S in a spray-like manner via the gas flow port 22b and the gas outlet 21a.

[0033] At the bottom of the processing chamber 10, between the inner wall of the processing chamber 10 and the support member 17, a baffle 40 is provided. The baffle 40 is constructed, for example, by coating aluminum with a ceramic such as yttrium oxide. A plurality of through holes are formed in the baffle 40. The processing space S communicates with the exhaust port 41 through the baffle 40. An exhaust device 42, such as a vacuum pump, is connected to the exhaust port 41, configured to depressurize the pressure within the processing space S by means of the exhaust device 42.

[0034] In addition, a wafer W loading / unloading inlet 43 is formed on the side wall of the processing chamber 10, which can be opened and closed by a gate valve 44.

[0035] The plasma processing apparatus 1 further includes a first high-frequency power supply 50, a second high-frequency power supply 51, and a matching device 52. The first high-frequency power supply 50 and the second high-frequency power supply 51 are connected to the lower electrode 12 via the matching device 52. Furthermore, the first high-frequency power supply 50 and the second high-frequency power supply 51 constitute the high-frequency power supply of the present invention.

[0036] The first high-frequency power supply 50 is a power source for generating high-frequency electricity for plasma generation. From the first high-frequency power supply 50, high-frequency electricity (HF) with a frequency of 27MHz to 100MHz (in one example, 40MHz) can be supplied to the lower electrode 12. The first high-frequency power supply 50 is connected to the lower electrode 12 via the first matching circuit 53 of the matching unit 52. The first matching circuit 53 is a circuit used to match the output impedance of the first high-frequency power supply 50 with the input impedance of the load side (lower electrode 12 side). Alternatively, the first high-frequency power supply 50 may not be electrically connected to the lower electrode 12, or it may be connected to the upper electrode, i.e., the shower head 20, via the first matching circuit 53.

[0037] The second high-frequency power supply 51 generates a high-frequency power (high-frequency bias power) LF for introducing ions into the wafer W, and supplies this high-frequency power LF to the lower electrode 12. The frequency of the high-frequency power LF can be in the range of 400kHz to 13.56MHz, and in one example it is 400kHz. The second high-frequency power supply 51 is connected to the lower electrode 12 via a second matching circuit 54 of a matching circuit 52. The second matching circuit 54 is a circuit used to match the output impedance of the second high-frequency power supply 51 with the input impedance on the load side (lower electrode 12 side).

[0038] Furthermore, in the following description, the state in which one or both of the high-frequency power HF from the first high-frequency power source 50 and the high-frequency power LF from the second high-frequency power source 51 are supplied to the lower electrode 12 is referred to as "RF ON". Additionally, the state in which neither high-frequency power HF nor high-frequency power LF is supplied to the lower electrode 12 is referred to as "RF OFF". Furthermore, the high-frequency power HF and high-frequency power LF are collectively referred to as "high-frequency power RF".

[0039] As shown in Figures 1 and 2, the plasma processing apparatus 1 further includes a direct current (DC) power supply 60, a switching unit 61, a first RF filter 62, and a second RF filter 63. The DC power supply 60 is electrically connected to the edge ring 14 via the switching unit 61, the second RF filter 63, and the first RF filter 62. In this embodiment, two RF filters 62 and 63 are provided for the DC power supply 60, but the number of RF filters is not limited to this configuration; for example, it could be one.

[0040] Furthermore, in this embodiment, the DC power supply 60 is connected to the edge ring 14 via the switching unit 61, the first RF filter 62, and the second RF filter 63, but the power supply system applying DC voltage to the edge ring 14 is not limited to this embodiment. For example, the DC power supply 60 may also be electrically connected to the edge ring 14 via the switching unit 61, the second RF filter 63, the first RF filter 62, and the lower electrode 12.

[0041] The DC power supply 60 is a power source that generates a negative DC voltage (DC) applied to the edge ring 14. Furthermore, the DC power supply 60 is a variable DC power supply, allowing adjustment of the DC voltage level.

[0042] The switching unit 61 is configured to stop the application of DC voltage from DC power supply 60 to the edge ring 14. Specifically, the switching unit 61 switches the connection between the edge ring 14 and the DC power supply circuit 64 or the electrical neutralization circuit 65.

[0043] The DC power supply circuit 64 is connected to the DC power supply 60 and is used to apply a DC voltage (DC) to the edge ring 14 from the DC power supply 60. In one example, the DC power supply circuit 64 includes a switching element 64a and a damping element 64b. For example, a field-effect transistor (FET) is used for the switching element 64a. However, in addition to using a FET, an insulated-gate bipolar transistor (IGBT) or a relay can also be used for the switching element 64a. When the switching element 64a is closed (open state), the edge ring 14 is connected to the DC power supply 60, and a DC voltage (DC) is applied to the edge ring 14. On the other hand, when the switching element 64a is open (closed state), no DC voltage (DC) is applied to the edge ring 14. Furthermore, in the following description, the state where the switching element 64a is open is referred to as "DC ON," and the state where the switching element 64a is closed is referred to as "DC OFF." Furthermore, the damping element 64b, such as a resistor or coil, can have its value and location determined arbitrarily by the designer.

[0044] The electrical neutralization circuit 65 is used to neutralize the edge ring 14. In one example, the electrical neutralization circuit 65 includes a switching element 65a and a damping element 65b. For example, a field-effect transistor (FET) is used for the switching element 65a. However, in addition to using a FET, an insulated-gate bipolar transistor (IGBT) or a relay can also be used for the switching element 65a. When the switching element 65a is closed (open state), the edge ring 14 is connected to the electrical neutralization circuit 65, and the charge in the edge ring 14 flows to the electrical neutralization circuit 65, neutralizing the edge ring 14. On the other hand, when the switching element 65a is open (closed state), the edge ring 14 is not electrically neutralized. Additionally, in the following description, the state in which the switching element 65a is turned on is referred to as "electrical neutralization ON," and the state in which the switching element 65a is turned off is referred to as "electrical neutralization OFF." Furthermore, the value and position of the damping element 65b, such as a resistor or a coil, can be arbitrarily determined by the designer.

[0045] The first RF filter 62 and the second RF filter 63 are filters that reduce or block high frequencies, respectively, and are provided to protect the DC power supply 60. For example, the first RF filter 62 reduces or blocks a 40MHz high frequency from the first high-frequency power supply 50. For example, the second RF filter 63 reduces or blocks a 400kHz high frequency from the second high-frequency power supply 51. Furthermore, the circuit configuration of the first RF filter 62 and the second RF filter 63 can be designed arbitrarily by those skilled in the art.

[0046] As shown in Figure 1, the plasma processing apparatus 1 further includes a pulse signal source 70. The pulse signal source 70 sends pulse signals, i.e., signals controlling the pulse timing, to the first high-frequency power supply 50, the second high-frequency power supply 51, and the DC power supply 60. The first high-frequency power supply 50 and the second high-frequency power supply 51 supply high-frequency power HF and high-frequency power LF respectively in a pulsed manner according to the pulse signal. Furthermore, the DC power supply 60 applies a DC voltage DC in a pulsed manner according to the pulse signal. The pulse signal source 70 can control the synchronization timing of the high-frequency power HF and high-frequency power LF with the DC voltage DC. Alternatively, this pulse signal source can be integrated into the first high-frequency power supply 50, the second high-frequency power supply 51, and the DC power supply 60 respectively.

[0047] The plasma processing apparatus 1 further includes a measuring device (not shown) for measuring the self-bias voltage of the edge ring 14 (or the self-bias voltage of the lower electrode 12 or the wafer W). Furthermore, the configuration of the measuring device can be arbitrarily designed by those skilled in the art.

[0048] A control unit 100 is provided in the aforementioned plasma processing apparatus 1. The control unit 100, for example, is a computer equipped with a CPU or memory, and has a program storage unit (not shown). The program storage unit stores the program for controlling the plasma processing in the plasma processing apparatus 1. Furthermore, the aforementioned program is recorded on a computer-readable recording medium, and can also be installed onto the control unit 100 from the recording medium.

[0049] <Plasma Treatment Methods> Next, the plasma treatment performed using the plasma treatment apparatus 1 configured as described above will be explained.

[0050] First, wafer W is moved into the processing chamber 10 and placed on an electrostatic chuck 13. Then, by applying a DC voltage DC to the first electrode 16a of the electrostatic chuck 13, the wafer W is electrostatically attracted to the chuck 13 by Coulomb force and held in place. Furthermore, after the wafer W is moved in, the vacuum level inside the processing chamber 10 is reduced to the desired vacuum level using an exhaust device 42.

[0051] Next, processing gas is supplied to the processing space S from the gas supply source group 30 via the shower head 20. Furthermore, high-frequency power HF for plasma generation is supplied to the lower electrode 12 by the first high-frequency power supply 50 to excite the processing gas and generate plasma. At this time, high-frequency power LF for iontophoresis can also be supplied by the second high-frequency power supply 51. Then, plasma processing is performed on the wafer W by the action of the generated plasma.

[0052] Upon completion of plasma processing, firstly, the supply of high-frequency power HF from the first high-frequency power source 50 and the supply of processing gas from the gas supply source group 30 are stopped. Furthermore, if high-frequency power LF is supplied during plasma processing, that high-frequency power LF is also stopped. Next, the supply of heat transfer gas to the back side of the wafer W is stopped, and the adsorption and holding of the wafer W by the electrostatic chuck 13 is stopped.

[0053] Subsequently, wafer W is removed from processing chamber 10, ending a series of plasma processes on wafer W.

[0054] In addition, in plasma processing, there are also cases where high-frequency power HF from the first high-frequency power source 50 is not used, but only high-frequency power LF from the second high-frequency power source 51 is used to generate plasma.

[0055] <Tilt Angle Control Method> Next, the method for controlling the tilt angle in the above plasma processing will be explained. The tilt angle is the degree of tilt (angle) of the incident direction of ions toward the edge region of wafer W relative to the vertical direction.

[0056] In one example, with the edge ring 14 in an unconsumed state, the shape of the sheath remains flat above the wafer W and the edge ring 14. Therefore, ions are incident in a direction slightly perpendicular to the entire surface of the wafer W (vertical direction). That is, the tilt angle is 0 (zero).

[0057] On the other hand, if the edge ring 14 is consumed and its thickness decreases, the thickness of the sheath layer in the edge region of wafer W and above the edge ring 14 becomes smaller, and the shape of the sheath layer changes to a downward convex shape. As a result, the incident direction of ions in the edge region of wafer W is tilted relative to the vertical direction. Subsequently, an opening tilted relative to the thickness direction is formed in the edge region of wafer W.

[0058] Furthermore, in the central region of wafer W, the thickness of the sheath increases in the edge region of wafer W and above the edge ring 14, and the shape of the sheath may also become an upward convex shape.

[0059] In the plasma processing apparatus 1 of this embodiment, the DC voltage DC from the DC power supply 60 is adjusted to control the tilt angle.

[0060] As shown in Figure 2, the DC voltage DC applied to the edge ring 14 in the DC power supply 60 is set to a voltage with the absolute value of the sum of the absolute value of the self-bias voltage Vdc and the set value ΔV as its negative polarity, that is, it is set to -(|Vdc|+ΔV). In Figure 2, the dotted lines above the wafer W and the edge ring 14 represent the potential of the wafer W and the potential of the edge ring 14, respectively. The self-bias voltage Vdc is the self-bias voltage of the wafer W, which is supplied by the high-frequency power RF of one or both of them, and is the self-bias voltage of the lower electrode 12 when the DC voltage DC from the DC power supply 60 is not applied to the lower electrode 12. The set value ΔV is given by the control unit 100.

[0061] The control unit 100 uses a pre-determined function or table to specify a setpoint ΔV based on the consumption of the edge ring 14 (the reduction amount calculated from the initial value of the thickness of the edge ring 14) and the consumption of the edge ring 14 estimated by the plasma processing conditions (e.g., processing time). That is, the control unit 100 determines the setpoint ΔV by inputting the consumption of the edge ring 14 and the self-bias voltage into the aforementioned function, or by referring to the aforementioned table using the consumption of the edge ring 14 and the self-bias voltage.

[0062] In determining the setpoint ΔV, the control unit 100 may use the difference between the initial thickness of the edge ring 14 and the thickness of the edge ring 14 measured by a measuring instrument such as a laser measuring instrument or a camera as the consumption amount of the edge ring 14. Alternatively, the control unit 100 may use other predetermined functions or tables to determine the consumption amount of the edge ring 14 from specific parameters in order to determine the setpoint ΔV. These specific parameters may be any of the following: self-bias voltage Vdc, wave height Vpp of high-frequency power HF or LF, load impedance, or the peripheral electrical characteristics of the edge ring 14. The peripheral electrical characteristics of the edge ring 14 may be any of the following: voltage or current value at any point around the edge ring 14, or resistance value including the edge ring 14. The other functions or tables are predetermined in a way that determines the relationship between the specific parameters and the consumption amount of the edge ring 14. To determine the consumption of edge ring 14, before actual plasma treatment or during maintenance of plasma treatment apparatus 1, the plasma treatment apparatus 1 is operated under the setting of measurement conditions used to determine the consumption, namely, high-frequency power HF, high-frequency power LF, pressure within the treatment space S, and flow rate of the treatment gas supplied to the treatment space S. Then, the specific parameters mentioned above are obtained, and these specific parameters are input into the other functions mentioned above, or the specific parameters are used in conjunction with the table mentioned above to specify the consumption of edge ring 14.

[0063] In the plasma processing apparatus 1, during plasma processing, that is, during the period when high-frequency power (HF) and high-frequency power (LF) are supplied, a DC voltage (DC) is applied to the edge ring 14 from the DC power supply 60. This controls the shape of the sheath layer above the edge ring 14 and the edge region of the wafer W, reduces the tilt angle of the incident direction of ions towards the edge region of the wafer W, and controls the tilt angle. As a result, an opening is formed covering the entire area of ​​the wafer W, slightly parallel to the thickness direction of the wafer W.

[0064] More specifically, during plasma processing, the self-bias voltage Vdc is measured using a measuring instrument (not shown). Furthermore, a DC voltage DC is applied to the edge ring 14 from the DC power supply 60. The value of the DC voltage DC applied to the edge ring 14 is, as described above, -(|Vdc|+ΔV). |Vdc| is the absolute value of the self-bias voltage Vdc measured by the measuring instrument immediately preceding it; ΔV is a set value determined by the control unit 100. Thus, the DC voltage DC applied to the edge ring 14 is determined by the self-bias voltage Vdc measured during plasma processing. In this way, even if the self-bias voltage Vdc changes, the DC voltage DC generated by the DC power supply 60 is corrected, and the tilt angle is appropriately adjusted.

[0065] <Control Methods for High-Frequency Power and DC Voltage> Next, the timing of the high-frequency power RF supply, the timing of the DC voltage application, and the timing of the electrical neutralization of the edge ring 14 in the above-mentioned plasma processing will be explained. The supply of high-frequency power RF refers to supplying the lower electrode 12 with one or both of the high-frequency power HF from the first high-frequency power source 50 and the high-frequency power LF from the second high-frequency power source 51. The timing of the high-frequency power RF supply is the same as the timing of RF on and off. The application of DC voltage involves connecting the edge ring 14 to the DC power source 60 (DC power supply circuit 64); the timing of DC voltage application is the same as the timing of DC on and off. The electrical neutralization of the edge ring 14 involves connecting the edge ring 14 to the electrical neutralization circuit 65; the timing of the electrical neutralization of the edge ring 14 is the same as the timing of electrical neutralization on and off.

[0066] [The principle of delay time Dt] Here, as described above, in order to control the tilt angle, the DC voltage DC applied from the DC power supply 60 to the edge ring 14 is adjusted to set a potential difference, i.e., a set value ΔV, between the wafer W and the edge ring 14. At this time, for example, if the aforementioned potential difference becomes too large, or if the timing of the applied DC voltage deviates, resulting in an unexpected potential difference, there is a concern that discharge may occur between the wafer W and the edge ring 14. As a result, the wafer W may suffer damage.

[0067] In this embodiment, by utilizing the dead time function of the pulse timing on the DC power supply 60 side, a floating potential state is formed at the output terminal of the DC power supply 60, and the edge ring 14 has the ability to track the potential changes of the wafer W.

[0068] Furthermore, the delay time function generally provided by the switching unit 61 is to delay the switching of the DC power supply circuit 64 and the electrical neutralization circuit 65 so that the two circuits do not turn on simultaneously. If the two circuits turn on simultaneously, a short circuit will occur, hence this delay time function is provided. When supplying high-frequency power RF in a pulsed manner, a pulse signal is sent from the pulse signal source 70 and used as a synchronization signal in the first high-frequency power supply 50, the second high-frequency power supply 51, and the DC power supply 60. The aforementioned delay time function sets a delay time for this pulse signal. During this delay time, the DC power supply 60 is not in an on or off state, but in an indeterminate state. In the following description, the general delay time is referred to as "delay time Do", and the delay time of this embodiment is referred to as "delay time Dt".

[0069] In this embodiment, the timing of RF on / off, DC on / off, and electrical neutralization on / off is controlled. Figure 3, as a comparative example of this embodiment, shows an explanatory diagram of conventional RF on / off, DC on / off, and electrical neutralization on / off. Figure 3 has the delay time Do generally present in the switching unit 61 described above, but the delay time Dt of this embodiment is not set. On the other hand, Figure 4 is an explanatory diagram showing the RF on / off, DC on / off, and electrical neutralization on / off in this embodiment. In Figures 3 and 4, the dotted line graphs shown above the wafer W and the edge ring 14 respectively illustrate the time-dependent changes in the potential of the wafer W and the potential of the edge ring 14. That is, the vertical axis of the dotted line graph is potential, and the horizontal axis is time. In addition, in Figures 3 and 4, the illustrations of the first RF filter 62 and the second RF filter 63 are omitted for ease of understanding.

[0070] Previously, as shown in Figure 3(a), when high-frequency power RF was supplied to the lower electrode 12 (RF on), a DC voltage DC was applied to the edge ring 14 (DC on, neutral off). In this case, if RF was turned on, the high-frequency power RF was reflected, and the high-frequency power RF supplied to the lower electrode 12 rose slowly. Therefore, the potential generated on the wafer W by the high-frequency power RF also rose slowly and gradually with the timing of RF on. In contrast, the DC power supply 60 generally rises rapidly, so the potential of the edge ring 14 rises sharply and becomes the same as the potential of the DC power supply 60. Therefore, a larger potential difference than expected is generated between the wafer W and the edge ring 14, raising concerns about discharge between the wafer W and the edge ring 14.

[0071] Furthermore, in the past, as shown in Figure 3(b), when the supply of high-frequency power RF to the lower electrode 12 was stopped (RF off), the application of DC voltage DC to the edge ring 14 was stopped (DC off), and the edge ring 14 was electrically neutralized (electrical neutralization on). In this case, if RF is turned off, electrical neutralization occurs gradually due to the time constant of the hardware (device) and plasma, so the potential of the wafer W decreases slowly and gradually. In contrast, the potential of the edge ring 14 drops sharply, becoming approximately 0 (zero) V. Therefore, a larger potential difference than expected is generated between the wafer W and the edge ring 14, raising concerns about discharge occurring between the wafer W and the edge ring 14.

[0072] In contrast, in this embodiment, when high-frequency power RF is supplied to the lower electrode 12 (RF on) and a DC voltage DC is applied to the edge ring 14 (DC on), DC on is performed after a first delay time Dt1 following the RF on. Here, in the case of the delay time Do of the general switching unit 61, the DC power supply 60 is not in an indeterminate state between on and off, so the delay time Do should be shortened as much as possible. In contrast, in this embodiment, the first delay time Dt1, as shown in FIG4(a), is achieved by first opening the switching element 64a of the DC power supply circuit 64 and the switching element 65a of the electrical neutralization circuit 65, thus making the output of the DC power supply 60 a floating potential during the indeterminate state. That is, by first setting the DC power supply circuit 64 and the electrical neutralization circuit 65 to an idle state, the output of the DC power supply 60 becomes a floating potential during the first delay time Dt1. In this floating potential state, edge ring 14 experiences the same potential change as wafer W, so the potential difference between wafer W and edge ring 14 is small at the point after the first delay time Dt1. Then, after the first delay time Dt1, DC switching is initiated. In this case, the potential of edge ring 14 becomes equal to the potential of wafer W (the potential of the plasma and sheath), that is, it can be made to have a self-biased voltage Vdc based on the high-frequency power RF (excluding generated reflectors). The potential of edge ring 14 rises gently, tracking the potential of wafer W. Therefore, the potential difference between wafer W and edge ring 14 can be suppressed.

[0073] Furthermore, in this embodiment, when the supply of high-frequency power RF to the lower electrode 12 is stopped (RF off), the application of DC voltage DC to the edge ring 14 is stopped (DC off), and the edge ring 14 is further electrically neutralized (electrical neutralization on), the electrical neutralization is turned on after a second delay time Dt2 following the DC off. That is, during the second delay time Dt2, as shown in FIG4(b), by first opening the switching element 64a of the DC power supply circuit 64 and the switching element 65a of the electrical neutralization circuit 65, the output terminal of the DC power supply 60 becomes a floating potential in an indeterminate state. In other words, by first setting the idle state of both the DC power supply circuit 64 and the electrical neutralization circuit 65, the output terminal of the DC power supply 60 becomes a floating potential during the second delay time Dt2. Then, after the floating potential state during this second delay time Dt2, the electrical neutralization is turned on. In this situation, the potential of edge ring 14 is to become equal to the potential of wafer W, and it gradually decreases in sync with the potential of wafer W. Therefore, the potential difference between wafer W and edge ring 14 can be suppressed.

[0074] [Timing sequence of RF on / off, DC on / off, and electrical neutralization on / off] As described above, in this embodiment, the potential difference between the wafer W and the edge ring 14 is suppressed by setting delay times Dt1 and Dt2 when the RF is turned on and off, respectively. The timing sequence of the RF on / off, DC on / off, and electrical neutralization on / off in the plasma processing described above will be specifically explained below.

[0075] Figure 5 is an explanatory diagram showing the changes in high-frequency power RF and DC voltage over time. In the upper graph of Figure 5, the vertical axis represents high-frequency power RF, and the horizontal axis represents time t. In the lower graph of Figure 5, the vertical axis represents DC voltage, and the horizontal axis represents time t. Figure 6 is a table showing the states of RF on / off, DC on / off, and electrical neutralization on / off in Figure 5. Figure 7 is an explanatory diagram showing the states of DC power supply circuit 64 and electrical neutralization circuit 65 in Figure 5.

[0076] (Step S1) Step S1 is the step of electrically neutralizing the edge ring 14. In step S1, the switching element 64a of the DC power supply circuit 64 is turned off (DC off), and the switching element 65a of the electrical neutralization circuit 65 is turned off (electrical neutralization on). In this way, the edge ring 14 is connected to the electrical neutralization circuit 65, and the charge on the edge ring 14 is removed through the electrical neutralization circuit 65. In addition, in this step S1, the supply of high-frequency power RF to the lower electrode 12 is stopped (RF off).

[0077] (Step S2) Step S2 refers to the period between supplying high-frequency power RF to the lower electrode 12 (RF on) and applying DC voltage DC to the edge ring 14 (DC on), which is the first delay time Dt1. In step S2, the switching element 64a of the DC power supply circuit 64 is kept open (DC off), and the switching element 65a of the electrical neutralization circuit 65 is open (electrical neutralization off). That is, by keeping the edge ring 14 in a state where neither the DC power supply circuit 64 nor the electrical neutralization circuit 65 is connected, the output terminal of the DC power supply 60 becomes a floating potential. If RF is turned on, the high-frequency power RF is reflected, so the potential of the wafer W rises slowly. When the DC power supply 60 is in a floating potential state, the potential of the edge ring 14 rises slowly, tracking the potential of the wafer W. Therefore, at the point after the first delay time Dt1, reducing the potential difference between the wafer W and the edge ring 14 can suppress discharge.

[0078] (Step S3) Step S3 involves supplying high-frequency power RF to the lower electrode 12 (RF on) and applying a DC voltage DC to the edge ring 14 (DC on) to perform plasma treatment on the wafer W. In step S3, the switching element 65a of the electrical neutralization circuit 65 is kept open (electrical neutralization off), and the switching element 64a of the DC power supply circuit 64 is closed (DC on). In this way, by appropriately controlling the tilt angle of the edge region of the wafer W with the DC voltage DC, the incident direction of ions can be appropriately adjusted, and plasma treatment can be performed uniformly on the wafer W.

[0079] (Step S4) Step S4 refers to the steps between stopping the supply of high-frequency power RF to the lower electrode 12 (RF off) and stopping the application of DC voltage DC to the edge ring 14 (DC off), and before performing electrical neutralization of the edge ring 14 (electrical neutralization on), which is the second delay time Dt2. In step S4, the switching element 65a of the electrical neutralization circuit 65 is kept open (electrical neutralization off), and the switching element 64a of the DC power supply circuit 64 is kept open (DC off). That is, by keeping the edge ring 14 in a state where neither the DC power supply circuit 64 nor the electrical neutralization circuit 65 is connected, the output terminal of the DC power supply 60 becomes a floating potential. If RF is turned off, the potential of the wafer W decreases slowly. While the DC power supply 60 is in a floating potential state, the potential of the edge ring 14 decreases slowly, tracking the potential of the wafer W. Therefore, at the point after the second delay time Dt2, reducing the potential difference between the wafer W and the edge ring 14 can suppress discharge.

[0080] (Step S5) Step S5 is the step of neutralizing the charge on the edge ring 14. In step S5, similar to step S1, the switching element 64a of the DC power supply circuit 64 is kept open (DC off), and the switching element 65a of the neutralization circuit 65 is closed (neutralization on). This connects the edge ring 14 to the neutralization circuit 65, and the charge on the edge ring 14 is removed via the neutralization circuit 65.

[0081] (Step S6) Step S6 is the step between the second time (the first delay time Dt1) after the lower electrode 12 is supplied with high-frequency power RF (RF on) and before the edge ring 14 is applied DC voltage DC (DC on). That is, it is the same step as step S2.

[0082] Repeat steps S1 to S4 as described above to complete a series of plasma treatments.

[0083] In this embodiment, when a high-frequency power RF is supplied to the lower electrode 12 (RF on) and a DC voltage DC is applied to the edge ring 14 (DC on), DC on is performed after a first delay time Dt1 following the RF on. In this case, the potential of the edge ring 14 rises gradually, tracking the potential of the wafer W. Therefore, the potential difference between the wafer W and the edge ring 14 can be suppressed.

[0084] Furthermore, the supply of high-frequency power RF to the lower electrode 12 is stopped (RF off), the application of DC voltage DC to the edge ring 14 is stopped (DC off), and the edge ring 14 is further electrically neutralized (electrical neutralization on). After a second delay time Dt2 following the DC off state, electrical neutralization is turned on. In this case, the potential of the edge ring 14 gradually decreases, tracking the potential of the wafer W. Therefore, the potential difference between the wafer W and the edge ring 14 can be suppressed.

[0085] Furthermore, when setting up the functions of this embodiment using existing functions, it is generally necessary to use timing signals of two pulses to determine the three states, including DC on, DC off, and floating potential. Therefore, the device configuration becomes very complex.

[0086] In this embodiment, by using delay times Dt1 and Dt2, the timing of the edge ring 14's potential tracking relative to the wafer W's potential can be determined regardless of the DC power supply. Furthermore, since the timing of the floating potential is established on the DC power supply 60 side, the same pulse timing signal as high-frequency power RF can be used. In other words, an existing pulse signal source 70 can be used, eliminating the need to recreate the pulse signal source 70.

[0087] <Specific example of delay time Dt> Next, specific examples of the first delay time Dt1 when the RF is turned on and the second delay time Dt2 when the RF is turned off will be explained.

[0088] First, a comparison of delay times Dt1 and Dt2 is made, and a specific example of the delay time Do possessed by the general switching unit 61 is explained. The factor determining the delay time Do is the switching speed of the FET possessed by the switching unit 61. In detail, the delay time Do is the rise time and fall time of the FET, plus the idle time (margin). For example, in the case where the timing of indicating the turn-on of the electrical neutralization circuit 65 is reached after the time until the FET of the DC power supply circuit 64 is completely turned off (fall time), the fall time plus the margin time constitutes the delay time Do. These rise and fall times vary depending on the type of component, for example, from 1ns to 10ns. In addition, the delay time Do is, for example, from 1ns to 100ns.

[0089] The common constraint for delay times Dt1 and Dt2 is the ratio of the delay times Dt1 and Dt2 relative to the time when a DC voltage (DC turn-on time) is applied to the edge ring 14. Delay times Dt1 and Dt2 represent the time when no DC voltage (DC) is applied; therefore, if delay times Dt1 and Dt2 become longer, it deviates from the state of applying a DC voltage synchronized with the high-frequency power (RF). Thus, delay times Dt1 and Dt2 are determined based on the DC turn-on time. Furthermore, the minimum ratio of delay times Dt1 and Dt2 is determined based on the process evaluation results of plasma processing.

[0090] The specific method for determining the first delay time Dt1 when the RF is turned on is as follows. That is, the reflection time from the supply of high-frequency power RF is measured in advance, and this reflection time is determined as the first delay time Dt1. Alternatively, the potential of the edge ring 14 can be measured, and the first delay time Dt1 is determined based on the potential of the high-frequency power RF and the edge ring 14. Then, the first delay time Dt1 is determined, for example, to be 0.1μs~1000μs, more preferably 0.1μs~100μs or 1μs~300μs. In addition, the upper limit of the first delay time Dt1 is determined to be the time required for the potential difference between the second DC voltage DC2 and the first DC voltage DC1 to be neutralized by plasma as described later.

[0091] The specific method for determining the second delay time Dt2 when the RF is turned off is as follows. That is, the second delay time Dt2 is determined by measuring the potential of the edge ring 14 and neutralizing the edge ring 14 electrically after the potential of the edge ring 14 has sufficiently decreased. Alternatively, the high-frequency power RF can be measured, and the second delay time Dt2 can be determined solely based on the high-frequency power RF. The second delay time Dt2 is, for example, determined to be 0.1μs~1000μs, and more preferably 0.1μs~100μs or 1μs~300μs.

[0092] <Other Implementation Forms> The plasma processing apparatus 1 described above includes a DC power supply 60, a DC power supply circuit 64, and an electrical neutralization circuit 65. However, the power supply system that applies a DC voltage to the edge ring 14 is not limited to this embodiment. Figures 8 to 10 are explanatory diagrams of a power supply system that applies a DC voltage to the edge ring 14 in another embodiment. Furthermore, in Figures 8 to 10, the illustrations of the first RF filter 62 and the second RF filter 63 are omitted for ease of understanding.

[0093] As shown in Figure 8, the plasma processing apparatus 1 can also replace the DC power supply 60, the DC power supply circuit 64, and the electrical neutralization circuit 65, and thus include a DC power supply 200 and a DC power supply circuit 210. That is, the plasma processing apparatus 1 of this embodiment does not include an electrical neutralization circuit. The DC power supply circuit 210 includes a switching element 210a and a damping element 210b.

[0094] As shown in Figure 8(a), immediately after supplying high-frequency power RF to the lower electrode 12 (RF on), the switching element 210a is turned off, and no DC voltage DC is applied to the edge ring 14 (DC off).

[0095] Subsequently, as shown in Figure 8(b), after a delay time Dt, switching element 210a is closed, and a DC voltage DC (DC off) is applied to edge ring 14. In this case, the potential of edge ring 14 tracks the potential of wafer W before the DC voltage DC is applied to edge ring 14. As a result, the potential difference between wafer W and edge ring 14 is reduced, suppressing discharge. Then, plasma treatment is performed on wafer W.

[0096] Subsequently, as shown in Figure 8(c), when the application of high-frequency power RF to the lower electrode 12 is stopped (RF off), the switching element 210a is made open, and the DC voltage DC to the edge ring 14 is stopped.

[0097] Alternatively, as shown in Figure 9, instead of the DC power supply 60, DC power supply circuit 64, and electrical neutralization circuit 65, it can include a first DC power supply 300, a second DC power supply 301, a first DC power supply circuit 310, a second DC power supply circuit 311, and an electrical neutralization circuit 320. The first DC power supply 300 applies a first DC voltage DC1 to the edge ring 14. The second DC power supply 301 applies a second DC voltage DC2, different from the first DC voltage DC1, to the edge ring 14. The first DC power supply circuit 310 includes a switching element 310a and a damping element 310b. The second DC power supply circuit 311 includes a switching element 311a and a damping element 311b. The electrical neutralization circuit 320 includes a switching element 320a and a damping element 320b.

[0098] For example, when supplying high-frequency power RF to the lower electrode 12 (RF on), if it is desired to switch the DC voltage DC applied to the edge ring 14 at high speed, the first DC power supply circuit 310 and the second DC power supply circuit 311 are switched, and the first DC voltage DC1 and the second DC voltage DC2 are switched. For example, if the first DC voltage DC1 is smaller than the second DC voltage DC2, the first DC voltage DC1 can be applied to the edge ring 14 as shown in FIG. 9(a), and then the second DC voltage DC2 can be applied to the edge ring 14 as shown in FIG. 9(b).

[0099] In this embodiment, as in the embodiments described above, a first delay time Dt1 is set when the RF is turned on, and a second delay time Dt2 is set when the RF is turned off. Specifically, the first delay time Dt1 is set from the time the high-frequency power RF is supplied to the lower electrode 12 until the first DC voltage DC1 is applied to the edge ring 14. Furthermore, the second delay time Dt2 is set from the time the supply of high-frequency power RF to the lower electrode 12 is stopped and the application of the second DC voltage DC2 to the edge ring 14 is stopped until the electrical neutralization of the edge ring 14 is performed. Further, a delay time Dt can also be set between the application of the first DC voltage DC1 and the second DC voltage DC2.

[0100] Furthermore, if the first DC voltage DC1 is smaller than the second DC voltage DC2, the switching from the second DC voltage DC2 to the first DC voltage DC1 must be interspersed with the electrical neutralization of the edge ring 14 performed by the electrical neutralization circuit 320. That is, the application of the second DC voltage DC2, the electrical neutralization of the edge ring 14, and the application of the first DC voltage DC1 must be performed sequentially.

[0101] Furthermore, in the case where the voltage applied to the edge ring 14 is switched from the second DC voltage DC2 to the first DC voltage DC1, the potential difference between the second DC voltage DC2 and the first DC voltage DC1 is neutralized by plasma. As shown in Figure 10, the neutralization circuit 320 can be omitted. In this case, a delay time Dt is set between applying the second DC voltage DC2 to the edge ring 14 and applying the first DC voltage DC1.

[0102] The plasma treatment apparatus 1 described above is a capacitively coupled plasma treatment apparatus, but the plasma treatment apparatus used in this invention is not limited to this type. For example, the plasma treatment apparatus can also be an inductively coupled plasma treatment apparatus.

[0103] It should be understood that the embodiments disclosed herein are merely illustrative and not intended to limit the invention. The above embodiments may also be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended patent application.

[0104] 1: Plasma treatment device 10: Processing Room 11: Platform 12: Lower electrode 13: Electrostatic chuck 14: Edge ring 15a:Refrigerant flow path 15b:Refrigerant inlet piping 15c: Refrigerant outlet flow path 16a, 16b: Electrodes 17: Supporting components 20: Shower head 21: Electrode plate 21a: Gas ejection outlet 22: Electrode support 22a: Gas diffusion chamber 22b: Gas flow hole 22c: Gas inlet port 23: Insulating shielding components 30: Gas supply source group 31: Flow control machine group 32: Valve Group 33: Gas supply pipe 40: baffle 41: Exhaust port 42: Exhaust device 43:Move-in exit 44: Gate valve 50: First High-Frequency Power Supply 51: Second High-Frequency Power Supply 52: Matcher 53, 54: Matching circuits 60, 200, 300, 301: DC power supply 61: Switching Unit 62, 63: RF filters 64, 210, 310, 311: DC power supply circuits 64a, 65a, 210a, 310a, 311a, 320a: Switching elements 64b, 65b, 210b, 310b, 311b, 320b: Damping elements 65,320: Electrical neutralization circuit 70: Pulse Signal Source 100: Control Department DC: Direct current voltage RF: High Frequency Power S: Processing space S1~S6: Steps Vdc: Self-bias voltage W: Wafer ΔV: Set value

Claims

1. A plasma processing apparatus for performing plasma processing on a substrate, comprising: a processing chamber; a platform disposed inside the processing chamber, including electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck to surround a substrate placed on the electrostatic chuck; a high-frequency power supply for supplying high-frequency power for generating plasma from gas inside the processing chamber; a DC power supply for applying a negative DC voltage to the edge ring; and a control unit for controlling the high-frequency power and the DC voltage; the control unit controls the plasma processing apparatus to perform a process comprising the following steps: (a) stopping the supply of the high-frequency power and stopping the application of the DC voltage; and (b) starting the supply of the high-frequency power, and after a predetermined delay time, starting the application of the DC voltage; the delay time being 0.1 μs to 1000 μs.

2. The plasma treatment apparatus as claimed in claim 1, wherein, The control unit determines the delay time based on the ratio of the delay time to the application time of the DC voltage.

3. The plasma treatment apparatus as described in claim 2, wherein, The control unit measures the reflection time from the time the high-frequency power is supplied, and determines the delay time as the time exceeding the reflection time.

4. A plasma processing apparatus for performing plasma processing on a substrate, comprising: a processing chamber; a platform disposed inside the processing chamber, including electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck to surround a substrate placed on the electrostatic chuck; a high-frequency power supply for supplying high-frequency power for generating plasma from gas inside the processing chamber; a DC power supply for applying a negative DC voltage to the edge ring; and a control unit for controlling the high-frequency power and the DC voltage; the control unit controls the plasma processing apparatus to perform a process comprising the following steps: (a) stopping the supply of the high-frequency power and stopping the application of the DC voltage; and (b) starting the supply of the high-frequency power, and after a predetermined delay time, starting the application of the DC voltage; the control unit determines the delay time based on the ratio of the delay time to the application time of the DC voltage; the control unit measures the reflection time from the supply of the high-frequency power and determines the delay time as the reflection time or longer.

5. The plasma treatment apparatus as described in claim 2 or 3, wherein, The control unit measures the potential of the edge ring and determines the delay time based on the potential of the edge ring.

6. The plasma treatment apparatus as claimed in claim 4, wherein, The delay time ranges from 0.1 μs to 1000 μs.

7. The plasma treatment apparatus as claimed in item 1 or 4, wherein, It also includes a DC power supply circuit for applying the DC voltage to the edge ring; but does not include an electrical neutralization circuit for electrically neutralizing the edge ring.

8. A plasma processing apparatus for performing plasma processing on a substrate, comprising: a processing chamber; a platform disposed inside the processing chamber, including electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck to surround a substrate placed on the electrostatic chuck; a high-frequency power supply for supplying high-frequency power for generating plasma from gas inside the processing chamber; a DC power supply for applying a negative DC voltage to the edge ring; and a control unit for controlling the high-frequency power and the DC voltage; the control unit controls the plasma processing apparatus to perform a process comprising the steps of: (a) stopping the supply of the high-frequency power and stopping the application of the DC voltage; and (b) starting the supply of the high-frequency power, and after a predetermined delay time, starting the application of the DC voltage; the plasma processing apparatus further comprising: a DC power supply circuit for applying the DC voltage to the edge ring; an electrical neutralization circuit for electrically neutralizing the edge ring; and a switching unit for switching the connection of the edge ring with the DC power supply circuit or the electrical neutralization circuit; The control unit further controls the plasma treatment apparatus to perform a process comprising the following steps: in step (a), stopping the supply of high-frequency power and stopping the application of DC voltage, and further neutralizing the edge ring electrically; in step (b), starting the supply of high-frequency power and stopping the electrical neutralization of the edge ring, and after a predetermined first delay time, starting the application of DC voltage; and (c) stopping the supply of high-frequency power and stopping the application of DC voltage, and after a predetermined second delay time, starting the electrical neutralization of the edge ring.

9. The plasma processing apparatus as claimed in item 1 or 4, wherein, It further includes: a DC power supply circuit for applying the DC voltage to the edge ring; an electrical neutralization circuit for electrically neutralizing the edge ring; and a switching unit for switching the connection of the edge ring with the DC power supply circuit or the electrical neutralization circuit; the control unit further controls the plasma processing apparatus to perform a process including the following steps: in step (a), stopping the supply of high-frequency power and stopping the application of the DC voltage, and further electrically neutralizing the edge ring; in step (b), starting the supply of high-frequency power and stopping the electrical neutralization of the edge ring, and starting the application of the DC voltage after a predetermined first delay time; and (c) stopping the supply of high-frequency power and stopping the application of the DC voltage, and starting the electrical neutralization of the edge ring after a predetermined second delay time.

10. The plasma treatment apparatus as claimed in claim 8, wherein, The control unit determines the second delay time based on the ratio of the second delay time to the application time of the DC voltage.

11. The plasma treatment apparatus as claimed in claim 10, wherein, The control unit measures the potential of the edge ring and determines the second delay time based on the potential of the edge ring.

12. The plasma processing apparatus as claimed in claim 10 or 11, wherein, The control unit measures the high-frequency power and determines the second delay time based on the high-frequency power.

13. The plasma processing apparatus as claimed in claim 10, wherein, The second delay time ranges from 0.1 μs to 1000 μs.

14. The plasma processing apparatus as described in claims 1, 4, or 8, wherein, The DC power supply includes: a first DC power supply that applies a first DC voltage; and a second DC power supply that applies a second DC voltage different from the first DC voltage; wherein either the first DC voltage or the second DC voltage is applied during the application of the DC voltage.

15. A plasma processing apparatus for performing plasma processing on a substrate, comprising: a processing chamber; a platform disposed inside the processing chamber, including electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck to surround a substrate placed on the electrostatic chuck; a high-frequency power supply for supplying high-frequency power for generating plasma from gas inside the processing chamber; a DC power supply for applying a negative DC voltage to the edge ring; and a control unit for controlling the high-frequency power and the DC voltage; the control unit controls the plasma processing apparatus to perform a process comprising the steps of: (a) stopping the supply of the high-frequency power and stopping the application of the DC voltage; and (b) starting the supply of the high-frequency power, and after a predetermined delay time, starting the application of the DC voltage; the DC power supply comprising: a first DC power supply for applying a first DC voltage; and a second DC power supply for applying a second DC voltage different from the first DC voltage; wherein the application of the DC voltage includes either the first DC voltage or the second DC voltage.

16. The plasma processing apparatus as claimed in claim 15, wherein, The delay time ranges from 0.1 μs to 1000 μs.

17. The plasma processing apparatus as described in claims 1, 4, or 15, wherein, The delay time is 0.1μs to 100μs.

18. The plasma processing apparatus as described in claims 1, 4, or 15, wherein, The delay time is 1μs~300μs.

19. The plasma processing apparatus as claimed in claim 8, wherein, The first delay time is 0.1μs to 1000μs.

20. The plasma processing apparatus as claimed in claim 8, wherein, The first delay time is 0.1μs to 100μs.

21. The plasma treatment apparatus as claimed in claim 8, wherein, The first delay time is 1μs~300μs.

22. A plasma processing apparatus as described in any of claims 1, 4, 8, or 15, wherein, The high-frequency power supply includes: a first high-frequency power supply for supplying first high-frequency power for generating the plasma; and a second high-frequency power supply for supplying second high-frequency power for introducing ions to a substrate placed on the electrostatic chuck; wherein the supply of the high-frequency power includes one or both of the first high-frequency power and the second high-frequency power.

23. A plasma processing method for performing plasma processing on a substrate using a plasma processing apparatus; the plasma processing apparatus comprising: a processing chamber; a platform disposed inside the processing chamber, including electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck to surround a substrate placed on the electrostatic chuck; a high-frequency power supply for supplying high-frequency power for generating plasma from gas inside the processing chamber; and a DC power supply for applying a negative DC voltage to the edge ring; the plasma processing method comprising the steps of: (a) stopping the supply of the high-frequency power and stopping the application of the DC voltage; and (b) starting the supply of the high-frequency power, and after a predetermined delay time, starting the application of the DC voltage; the delay time being 0.1 μs to 1000 μs.

24. A plasma processing method for performing plasma processing on a substrate using a plasma processing apparatus; the plasma processing apparatus comprising: a processing chamber; a platform disposed inside the processing chamber, including electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck to surround a substrate placed on the electrostatic chuck; a high-frequency power supply for supplying high-frequency power for generating plasma from gas inside the processing chamber; and a DC power supply for applying a negative DC voltage to the edge ring; the plasma processing method comprising the steps of: (a) stopping the supply of the high-frequency power and stopping the application of the DC voltage; and (b) starting the supply of the high-frequency power, and after a predetermined delay time, starting the application of the DC voltage; the plasma processing method determining the delay time based on the ratio of the delay time to the application time of the DC voltage; the plasma processing method measuring the reflection time from the supply of the high-frequency power and determining the delay time as the reflection time or longer.

25. A plasma processing method, wherein a plasma processing apparatus is used to perform plasma processing on a substrate; the plasma processing apparatus includes: a processing chamber; a platform disposed inside the processing chamber, including electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck to surround a substrate placed on the electrostatic chuck; a high-frequency power supply for supplying high-frequency power for generating plasma from gas inside the processing chamber; and a DC power supply for applying a negative DC voltage to the edge ring; the plasma processing method includes the following steps: (a) stopping the supply of the high-frequency power and stopping the application of the DC voltage; and (b) starting the supply of the high-frequency power, and after a predetermined delay time, starting the application of the DC voltage; the plasma processing apparatus further includes: a DC power supply circuit for applying the DC voltage to the edge ring; an electrical neutralization circuit for electrically neutralizing the edge ring; and a switching unit for switching the connection of the edge ring with the DC power supply circuit or the electrical neutralization circuit; the plasma processing method further includes the following steps: In step (a), the supply of high-frequency power is stopped, and the application of DC voltage is stopped, further neutralizing the edge ring; in step (b), the supply of high-frequency power is started, and the neutralization of the edge ring is stopped, and after a predetermined first delay time, the application of DC voltage is started; and (c) the supply of high-frequency power is stopped, and the application of DC voltage is stopped, and after a predetermined second delay time, the neutralization of the edge ring is started.

26. A plasma processing method for performing plasma processing on a substrate using a plasma processing apparatus; the plasma processing apparatus comprising: a processing chamber; a platform disposed inside the processing chamber, including electrodes, an electrostatic chuck disposed on the electrodes, and an edge ring disposed on the electrostatic chuck to surround a substrate placed on the electrostatic chuck; a high-frequency power supply for supplying high-frequency power for generating plasma from gas inside the processing chamber; and a DC power supply for applying a negative DC voltage to the edge ring; the plasma processing method comprising the steps of: (a) stopping the supply of the high-frequency power and stopping the application of the DC voltage; and (b) starting the supply of the high-frequency power, and after a predetermined delay time, starting the application of the DC voltage; the DC power supply comprising: a first DC power supply for applying a first DC voltage; and a second DC power supply for applying a second DC voltage different from the first DC voltage; wherein the first DC voltage or the second DC voltage is applied during the application of the DC voltage.

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