Process for depositing a bronze alloy on a printed circuit board and printed circuit board obtained using this process

Abstract

This invention discloses a process for depositing a bronze alloy onto a printed circuit board (5). This process includes an operation of electrodepositing at least one bronze layer (12) onto a copper sheet (10). The bronze layer (12), after deposition, comprises 45% to 65% copper, 30% to 45% tin, and 2% to 11% zinc. This invention discloses a printed circuit board (5) obtained using this process.

Description

Technical Field

[0001] This invention relates to the field of printed circuit boards for connectors or antennas (e.g., connectors and antennas for chip cards) or for devices intended for medical applications (e.g., detecting glucose in blood) or for connecting objects to the Internet (IoT or Internet of Things). Prior Technology

[0002] For example, a printed circuit board according to the present invention may include conductive tracks and / or contact lands etched in a conductive material sheet pre-deposited on a dielectric substrate, or other circuitry including one or more lead frames, each lead frame consisting of a conductive material sheet that has been cut out and then co-laminated with a dielectric substrate. Such printed circuit boards are used, for example, to manufacture contacts for electronic chip card modules, chip card antennas, and hybrid circuits including both contacts and antennas.

[0003] By illustration, taking a chip card as an example, these typically consist of a rigid carrier, such as one made of plastic, forming the main part of the card into which a separately manufactured electronic module is incorporated. This electronic module includes a generally flexible printed circuit board equipped with a chip (integrated circuit) and having components for connecting the chip to a device to allow data to be read from the chip and / or written to the chip. These connecting components or connectors are, for example, contacts, which take the form of conductive metal tracks exposed on the surface of the electronic module held on the carrier. Besides requiring excellent mechanical strength and corrosion resistance, and for good electrical conduction both between the chip and the contacts and between the contacts and a read / write device, chip card manufacturers wish to match the color of the contacts to (some) colors of the card. For this purpose, the contacts are generally covered with a gold layer to obtain a gold finish, or covered with a silver or palladium layer to obtain a silver finish. However, this type of finish causes problems. For example, palladium is a relatively expensive metal; as for gold, it must be deposited on a nickel layer, which is magnetic, which is a disadvantage in radio frequency applications and / or applications requiring non-magnetic properties, and also problematic in the medical field if it must be placed in contact with or close to the skin. Summary of the Invention

[0004] One objective of this invention is to produce flexible printed circuit boards in which palladium and / or nickel are not used or are not used in large quantities, while retaining electrical and mechanical properties compatible with their applications, particularly in chip card modules with contacts.

[0005] Therefore, a process for depositing a white bronze alloy onto a printed circuit board is presented below. This process specifically includes:

[0006] - A dielectric substrate is provided, the dielectric substrate including a first main surface and a second main surface, and at least one first sheet of a first conductive material (e.g., copper, aluminum or an alloy thereof, steel, etc.) is provided on at least the first main surface.

[0007] - At least one operation of electrodepositing at least one layer of at least one second conductive material on at least one region of the first sheet.

[0008] Furthermore, in this process, the at least one operation of electrodepositing at least one layer of at least one second conductive material includes an operation of electrodepositing a bronze layer, which, after deposition, comprises 45% to 65% by weight, advantageously 45% to 62% by weight and more preferably 45% to 50% by weight of copper, 30% to 45% by weight, and advantageously 40% to 45% by weight of tin, and 2% to 11% by weight, advantageously 6% to 11% by weight of zinc.

[0009] This process (and all or most of the operations described in this document) can be performed reel-to-reel.

[0010] A bronze layer advantageously replaces, for example, a palladium layer on the visible surface of a contact pad. It can also, where appropriate, allow for the absence of nickel deposition (in contrast, nickel is indispensable in layers beneath, for example, gold). Bronze layers are more economical than palladium layers. The absence of nickel is preferable in radio frequency applications and in certain medical applications.

[0011] The aforementioned process advantageously includes any of the following features, which are considered independently of or in combination with one or more other features:

[0012] - This includes a finishing operation in which a surface treatment is performed after the deposition of a bronze layer to form, for example, a protective layer comprising an organic solderable corrosion inhibitor (OST) or a self-assembled monolayer (SAM);

[0013] - This surface treatment is performed directly on at least one segment of the bronze layer (i.e., without any other material between the protective layer and the bronze layer);

[0014] - Alternatively, if the at least one operation of electrodepositing at least one layer of at least one second conductive material also includes electrodepositing a surface layer comprising at least one element selected from the list of gold, silver, palladium, ruthenium, and rhodium, then the surface treatment can be performed directly on at least one segment of this surface layer;

[0015] - The at least one operation of electrodepositing at least one layer of at least one second conductive material also includes electrodepositing at least one element selected from the list of gold, silver and palladium in the form of a thin layer with a thickness of less than 15 nanometers.

[0016] - The at least one operation of electrodepositing at least one layer of at least one second conductive material includes one operation of electrodepositing a bronze layer, and one operation of electrodepositing a nickel layer and a nickel-phosphorus layer prior to the deposition of the bronze layer.

[0017] According to another embodiment, a printed circuit board is described below. It includes contact pads configured to form contacts for at least one chip card module. Thus, this printed circuit board includes...

[0018] - On one of the main surfaces of a dielectric substrate, a sheet of a first conductive material, at least a portion of the surface of which is covered by a stack of layers including at least a nickel layer, a nickel-phosphorus layer and a bronze layer.

[0019] This printed circuit board may further include any of the following features, which are considered independently of or in combination with one or more other features:

[0020] - It includes connecting wells, comprising at least one of the following layers stacked at the bottom of the connecting wells: a nickel layer, a nickel-phosphorus layer, and a surface layer comprising at least one of the following elements: gold, silver, rhodium, ruthenium, and palladium;

[0021] -It includes a thin layer of gold, silver, or palladium with a thickness of less than or equal to 15 nanometers beneath the bronze layer and surface layer;

[0022] - It includes a second sheet of a first conductive material on the other side of the main surface of the dielectric substrate, at least a portion of the surface of the second sheet being covered with a stack of at least one of the following layers: a nickel layer, a nickel-phosphorus layer, and a metal surface layer including at least one of the following elements: gold, silver, palladium, rhodium, and ruthenium;

[0023] - The bronze layer has a thickness of either 150 nanometers or less than 600 nanometers. Simple Explanation of the Diagram

[0024] Other features and advantages of the invention will become apparent upon reading the detailed description and the accompanying drawings, wherein:

[0025] Figure 1 schematically illustrates, in perspective view, one example of a chip card including a module according to the present invention;

[0026] Figure 2 schematically shows a segment of one example of a printed circuit board according to the present invention, as seen from above;

[0027] Figure 3 shows, in a cross-section, a schematic example of a single-sided printed circuit board used for a connector in one of the chip card modules, such as those shown in Figure 1;

[0028] Figure 4 shows, in a cross-section, a schematic example of a double-sided printed circuit board used in a connector for a chip card module, such as that shown in Figure 1;

[0029] Figure 5 shows, in a cross-section, a partial and schematic example of a double-sided printed circuit board, such as the one in Figure 4, on which multiple layers have been electrodeposited; and its single-sided variant, ignoring the sheets and layers located below the dashed lines;

[0030] Figure 6 shows, in a cross-section, a partial and schematic representation of another example of a double-sided printed circuit board, such as the one in Figure 4, on which multiple layers have been electrodeposited; and its single-sided variant, omitting the sheet and layers positioned below the dashed lines;

[0031] Figure 7 shows, in a cross-section, a partial and schematic representation of another example of a double-sided printed circuit board, such as the one in Figure 4, on which multiple layers have been electrodeposited; and its single-sided variant, omitting the sheet and layers positioned below the dashed lines;

[0032] Figure 8 shows, in a cross-section, a partial and schematic representation of another example of a double-sided printed circuit board, such as the one in Figure 4, on which multiple layers have been electrodeposited; and its single-sided variant, omitting the sheet and layers positioned below the dashed lines;

[0033] Figure 9 shows, in a cross-section, a schematic example of a single-sided printed circuit board, such as the one in Figure 3, on which multiple layers have been electrodeposited; and

[0034] Figure 10 shows, in a cross-section, another example of a single-sided printed circuit board, such as the one in Figure 3, on which multiple layers have been electrodeposited. Implementation

[0035] In this document, by way of example, the printed circuit board according to the present invention is applicable to the field of chip cards, but those skilled in the art will be able to apply this example to other applications of such printed circuit boards (contacts for USB sockets, antennas, devices for medical applications, such as pressure sensors intended to be placed in contact with the skin, bracelets for detecting glucose or other compounds in the blood, electrodes for performing electroencephalograms, etc.).

[0036] According to one application example of the printed circuit board (an example of which is illustrated in FIG. 1) according to the present invention, a chip card 1 includes a module 2 having a connector 3. In this example, the chip card 1 is a bank card in ID-1 format. The module 2 is, for example, an EMV module conforming to standard ISO 7810 (EMV stands for EuroPay MasterCard Visa). The module 2 generally takes the form of a separate element inserted into a cavity in the card. This element includes a dielectric substrate 4 (see FIG. 2) of PET, polyimide, glass-reinforced epoxy, etc., and the thickness of the dielectric substrate 4 is, for example, between 25 micrometers and 150 micrometers (therefore, it is generally flexible). The connector 3 is manufactured on the dielectric substrate 4, and a chip (not shown) is then connected to the connector 3 via a side of the substrate opposite to the side including the connector 3.

[0037] Therefore, Figure 2 illustrates one example of a segment of a printed circuit board 5 having one of six connectors 3. Each connector 3 includes a contact pad 8 formed by conductive tracks 6. In the example illustrated here, eight conductive tracks 6 are intended to form electrical contacts 7 (identified as C1 to C8, as defined in standard ISO 7816-2).

[0038] The connector 3 can be formed using a single-sided structure (where a conductive material sheet is only on one of the main surfaces of a dielectric substrate 4) or a double-sided structure (where a conductive material sheet is on each of the two main surfaces of a dielectric substrate 4).

[0039] Figure 3 illustrates an example of a single-sided structure. This single-sided structure is manufactured, for example, using the following process: a dielectric substrate 4 is provided, on which an adhesive layer 9 is coated; then, the dielectric substrate 4 with the adhesive layer 9 is perforated to create a connection well 14 and, if applicable, a cavity 15, in which a wafer is subsequently housed; then, before, if applicable, the dielectric substrate 4 with the adhesive layer 9 is combined (laminated) with a first sheet 10 of a first conductive material (such as a sheet of copper, aluminum, or an alloy thereof, or even steel). Alternatively, a cladding layer can be used directly; however, in this case, the connection well 14 and / or cavity 15 are formed, for example, using a laser configured to perforate only the dielectric substrate 4. In all cases, a conductive surface is thus formed at the bottom of the connection well 14 and / or cavity 15, on which a conductive material layer can be electrodeposited, if applicable, for electrical connection, for example, using a wire bonding technique.

[0040] Figure 4 illustrates an example of a double-sided structure. This double-sided structure is manufactured, for example, using the following process: a dielectric substrate 4 is provided, on which a second sheet 11 of a first conductive material, such as copper, aluminum, or an alloy thereof, or even a sheet of steel, is carried on one of its main surfaces (which will correspond to the back side); thus, it is, for example, a cladding issue; an adhesive layer 9 is coated on the other of its main surfaces (which will correspond to the front side); then, depending on the situation, this cladding with the adhesive layer 9 is perforated to create a connection well 14 and, depending on the situation, a cavity 15, in which a chip is then accommodated; then, the cladding with the adhesive layer 9 is combined (laminated) with the first sheet 10 of a conductive material (this sheet is, for example, made of the same conductive material as the first conductive material, even though the thicknesses of the first and second sheets 10, 11 may be different; however, it should be noted that the first and second sheets 10, 11 may be made of different conductive materials) and laminated. The bottom of the connection well 14 and / or cavity 15 thus forms a conductive surface, on which a conductive material layer can be electrodeposited, as appropriate, for electrical connection, for example, using a one-wire bonding technique. Alternatively, a double-bread layer can be used directly; however, in this case, the connection well 14 and / or cavity 15 are formed, for example, using a laser configured to perforate only the dielectric substrate 4 and the second sheet 11 of conductive material.

[0041] For example, as shown in the cross-sections of Figures 5 to 10, a connector 3 (i.e., a module 2 that is essentially chipless) has a multilayer structure formed by a dielectric substrate 4, an adhesive layer 9 (which is optional and not shown in Figures 5 to 10), and a first 10 (and, if applicable, a second 11) sheet. The first 10 (and, if applicable, the second 11) sheet is made of a first conductive material and at least one layer 12 of a second conductive material is deposited thereon by electrodeposition. For example, the first conductive material is made of copper or a copper alloy. The second conductive material layer 12 is made of bronze, which, after deposition, comprises 45% to 65% by weight, advantageously 45% to 62% by weight, and more preferably 45% to 50% by weight of copper, 30% to 45% by weight, and advantageously 40% to 45% by weight of tin, and 2% to 11% by weight, advantageously 6% to 11% by weight of zinc. The compositions of the bronze layers 12 in the first and second sheets 10 and 11 are not necessarily the same. Specifically, the composition of the bronze layer 12 deposited on the second sheet 11 can be determined according to the desired improvement in solderability. For example, the bronze layer 12 is deposited using a bath of Miralloy®, such as that sold by Umicore®, at a temperature similar to or equal to 60°C and a current density of 4 A / dm². Other materials can be electrodeposited between the first conductive material and the bronze layer 12, or even on top of the bronze layer 12.

[0042] For example, bronze layer 12 can be used to replace a precious or rare metal (gold, silver, palladium) in a multilayer structure (such as a structure used to produce a chip card module) on at least one side, or to replace nickel in a multilayer structure (such as a structure used in a device targeted for, for example, medical or radio frequency applications) on at least one side.

[0043] In the example illustrated in Figure 5, the multilayer structure is a double-sided structure. It includes a dielectric substrate 4, one of the properties mentioned above. For example, this dielectric substrate 4 is perforated to form connection wells 14, each allowing a chip positioned on a back side (or bonding side) to be electrically connected to a contact pad 8 positioned on a front side (or contact side). This dielectric substrate 4 includes, on each of its main surfaces, first and second sheets 10 and 11, both formed of a first conductive material (e.g., copper or a copper alloy; alternatively, the first conductive material may be aluminum or an alloy thereof, steel, etc.).

[0044] Multiple layers of conductive material are deposited by electrodeposition on at least specific areas of the free surfaces of each of the two thin sheets 10, 11 of the first conductive material. In the example illustrated in FIG5, therefore, a nickel layer 16, a nickel-phosphorus layer 17, a thin layer 18 in the form of a flash of one of the metals selected from gold, silver, and palladium, and finally, a surface layer 19 comprising at least one metal selected from gold, silver, palladium, rhodium, and ruthenium. On the front side, the printed circuit board successively receives the nickel layer 16, the nickel-phosphorus layer 17, a thin layer 18 in the form of a flash of gold, and a bronze layer 12 (the composition of which is mentioned above). Where appropriate, the front side undergoes a protective treatment and is therefore covered with a protective layer 20.

[0045] The following table summarizes examples of the characteristic thicknesses of the layers in the structure shown in Figure 5. front back Adhesive 9: 10 µm to 25 µm Copper sheet 10: 12 micrometers to 70 micrometers Copper sheet 11: 12 micrometers to 70 micrometers Nickel layer 16: 0.5 micrometers to 6 micrometers Nickel layer 16: 1 micrometer to 15 micrometers Nickel-phosphorus layer 17: 0.05 micrometers to 0.6 micrometers Nickel-phosphorus layer 17: 0.05 micrometers to 0.6 micrometers Thin film 18: gold or silver or palladium: 0 to 15 nanometers Thin film 18: gold or silver or palladium: 0 to 15 nanometers Bronze layer 12: 100 nanometers to 3 micrometers Surface layer 19 containing at least one of the following elements: Au, Ag, Pd, Rh or Ru: 10 nanometers to 1 micrometer (Ag up to 3 micrometers). Protective layer 20 (Optional)

[0046] According to this example, the stacking of layers on the back side is the same, whether at the bottom of the connecting well 14 or on the second main surface of the substrate.

[0047] According to a variant of the embodiment illustrated in Figure 5, the back side of the dielectric substrate 4 remains exposed (without the second sheet 11 of the first conductive material and without layers (16 to 19) electrodeposited on that surface); in contrast, a stack is placed at the bottom of the connection well 14, the stack comprising a nickel layer 16, a nickel-phosphorus layer 17, a thin layer 18 in the form of a shimmering metal selected from gold, silver, and palladium, and finally, a surface layer 19 comprising at least one metal selected from gold, silver, rhodium, ruthenium, and palladium. Thus, it presents the problem of a single-sided structure.

[0048] In the example illustrated in Figure 6, the multilayer structure is a double-sided structure. It includes a dielectric substrate 4 as mentioned above. As in the previous example, the dielectric substrate 4 is perforated and includes a first sheet 10 and a second sheet 11, both formed of a first conductive material (e.g., copper or a copper alloy as described above), on each of its main surfaces. The first and second sheets 10 and 11 are attached to the dielectric substrate 4 in one of the ways described above.

[0049] Multiple conductive material layers are deposited by electrodeposition on at least specific areas of the free surfaces of each of the two sheets 10, 11 of the first conductive material. In the example illustrated in Figure 6, bronze layers 12 are received on both the front and back sides. A protective layer 20 may be received on both the front and back sides, depending on the application. The protective layer 20 is optional and may be deposited on one or both sides. This embodiment is particularly advantageous if it is desired to replace the nickel and palladium on the front side. It is also advantageous in terms of production costs due to the lower number of electrodeposition operations.

[0050] The following table summarizes examples of the characteristic thicknesses of the layers in the structure shown in Figure 6. front back Adhesive 9: 10 microns to 25 microns Copper sheet 10: 12 micrometers to 70 micrometers Copper sheet 11: 12 micrometers to 70 micrometers Bronze layer 12: 100 nanometers to 3 micrometers Bronze layer 12: 50 nanometers to 6 micrometers Protective layer 20 (Optional) Protective layer 20 (Optional)

[0051] According to a variant of the embodiment illustrated in Figure 6, the back side of the dielectric substrate 4 remains exposed and a stack is placed at the bottom of the connection well 14, the stack including a bronze layer 12 and an optional post-processing layer 20. Thus, it presents a problem of a single-sided structure.

[0052] In the example illustrated in Figure 7, the multilayer structure is a double-sided structure. It includes a dielectric substrate 4 as mentioned above. As in the previous example, the dielectric substrate 4 is perforated and includes a first sheet 10 and a second sheet 11, both formed of a first conductive material (e.g., copper or a copper alloy as described above), on each of its main surfaces. The first and second sheets 10 and 11 are attached to the dielectric substrate 4 in one of the ways described above.

[0053] Multiple layers of conductive material are deposited by electrodeposition on at least specific areas of the free surfaces of each of the two sheets 10, 11 of the first conductive material. In the example illustrated in FIG7, bronze layers 12 are received on both the front and back sides. A protective layer 20 may be received on the front side. This embodiment is particularly advantageous if it is desired to replace the nickel and palladium on the front side. On the back side, at least one layer comprising at least one metal from the following list may be received on the bronze layer 12: gold, silver, palladium, rhodium, ruthenium.

[0054] The table below summarizes examples of the characteristic thicknesses of the layers in the structure shown in Figure 7. front Connect to the back Adhesive: 10 microns to 25 microns Copper sheet 10: 12 micrometers to 70 micrometers Copper sheet 11: 12 micrometers to 70 micrometers Bronze layer 12: 100 nanometers to 3 micrometers Bronze layer 12: 50 nanometers to 6 micrometers Protective layer 20 (Optional) Thin films of gold, silver, or palladium, ranging from 18 to 15 nanometers. (Optional) Surface layers containing Au, Ag, Pd, Rh, or Ru, ranging from 19.10 nanometers to 1 micrometer (Ag up to 3 micrometers). (Optional)

[0055] According to a variant of the embodiment illustrated in Figure 7, the back side of the dielectric substrate remains exposed (without the second sheet 11 of the first conductive material and without layers (18 to 19) electrodeposited on that side); in contrast, a stack is placed at the bottom of the connection well, the stack comprising a bronze layer 12, a selected thin layer 18 in the form of a glitter of one of the metals selected from gold, silver, and palladium, and finally, at least one layer 19 comprising one of the metals or compounds from the following list: gold, silver, palladium, rhodium, ruthenium. Thus, it is a problem of a single-sided structure.

[0056] In the example illustrated in Figure 8, the multilayer structure is a double-sided structure. Its difference from the structure described with respect to Figure 7 is essentially that, on the front side, the bronze layer 12 is covered with a thin layer 18 in the form of a shimmering luster selected from one of the metals: gold, silver, and palladium. This thin layer 18 itself is covered with at least one layer 19 comprising metals from one of the following list: gold, silver, palladium, ruthenium, and rhodium. Where appropriate, a protective layer 20 is then received on the front side.

[0057] The following table summarizes examples of the characteristic thicknesses of the layers in the structure shown in Figure 8. front back Adhesive: 10 microns to 25 microns Copper sheet 10: 12 micrometers to 70 micrometers Copper sheet 11: 12 micrometers to 70 micrometers Bronze layer 12: 100 nanometers to 3 micrometers Bronze layer 12: 50 nanometers to 6 micrometers Thin film 18: gold, silver, or palladium 0 to 15 nanometers (Optional) Thin film 18: gold, silver, or palladium 0 to 15 nanometers (Optional) Surface layer containing Au, Ag, Pd, Rh or Ru 19: 10 nanometers to 1 micrometer Surface layers containing Au, Ag, Pd, Rh, or Ru, ranging from 19.10 nanometers to 1 micrometer (Ag up to 3 micrometers). (Optional) Protective layer 20 (Optional)

[0058] As described above, a single-sided structure is obtained by means of a variant, by not using a second sheet 11 composed of a first conductive material and a selective layer deposited on the first conductive material to cover the second main surface (back side) of the dielectric substrate.

[0059] In the example illustrated in Figure 9, the multilayer structure is a single-sided structure. It includes a dielectric substrate 4, as mentioned above. On the front side, a first sheet 10 made of a first conductive material is attached to the dielectric substrate 4 in one of the ways described above.

[0060] Multiple layers of conductive material are deposited by electrodeposition on at least specific areas of the free surface of the first sheet 10. In the example illustrated in FIG9, a bronze layer 12 is received on the front side, followed by a thin layer 18 in the form of a glittering metal selected from gold, silver, and palladium, and finally, a surface layer 19 comprising at least one metal selected from the list of: gold, silver, palladium, rhodium, and ruthenium. A protective layer 20 is then received on the front side, if applicable.

[0061] The table below summarizes examples of the characteristic thicknesses of the layers in the structure shown in Figure 9. front Adhesive: 10 microns to 25 microns Copper sheet 10: 12 micrometers to 70 micrometers Bronze layer 12: 100 nanometers to 3 micrometers Thin layer 18: gold, silver, or palladium: 0 to 15 nanometers (Optional) Surface layer containing Au, Ag, Pd, Rh or Ru 19: 10 nanometers to 1 micrometer (Ag up to 3 micrometers) Protective layer 20 (Optional)

[0062] In the example illustrated in Figure 10, the multilayer structure is a single-sided structure. It differs substantially from the structure described above in that it does not include a thin layer 18 in the form of a glittering metal selected from gold, silver, and palladium, and it does not include a surface layer 19 containing a metal selected from the following list: gold, silver, palladium, rhodium, and ruthenium.

[0063] In contrast, depending on the situation, a protective layer 20 can then be received on the front side.

[0064] The table below summarizes examples of the characteristic thicknesses of the layers in the structure shown in Figure 10. front Adhesive: 10 microns to 25 microns Copper sheet 10: 12 micrometers to 70 micrometers Bronze layer 12: 100 nanometers to 3 micrometers Protective layer 20 (Optional)

[0065] In the embodiments presented above using its equivalent variations, when a protection process 20 is implemented, the protection process 20 may correspond non-exhaustively to passing through;

[0066] - One bath of organic solderable corrosion inhibitors (such as benzotriazole or imidazole (e.g., alkylbenzimidazole, arylbenzimidazole, etc.));

[0067] - Suitable for forming a bath of self-assembled monolayers, such as a mixture of polyethylene glycol ether and propylene glycol, or a mixture of octylphenoxyethanol and octadecyl-1-thiol, or polyoxyethylene sorbitan monooleate (polysorbate 80, CAS No. 9005-65-6), or a mixture of alcohol (C12-18) ethoxylated and propoxylated (CAS No. 69227-21-0) with polyoxyethylene lauryl ether (CAS No. 9002-92-0) and 1-octadecyl mercaptan (CAS No. 2885-00-9).

[0068] For example, according to standard ISO 10373, before and after being subjected to a salt spray test for 24 hours, a stack of chip card modules has a contact resistance of less than 500 mohm (CRM). The stack consists of a dielectric 4 covered with a copper sheet 10, a nickel layer 16, a nickel-phosphorus layer 17, a gold layer 18, and a 0.5 µm bronze layer 12 electrodeposited on the copper sheet 10. The bronze layer 12 comprises 45 wt% to 50 wt% copper, 40 wt% to 45 wt% tin, and 6 wt% to 11 wt% zinc (structure in Figure 5).

[0069] 1: Chip Card 2: Module 3: Connector 4: Dielectric substrate / dielectric material 5: Printed Circuit Board 6: Conductive track 7: Electrical contacts 8: Contact pad 9: Adhesive layer / adhesive 10: First thin sheet / copper sheet 11: Second thin sheet / copper sheet 12: Bronze Layer / Layer 14: Connecting Well 15: cavity 16: Nickel layer 17: Nickel-phosphorus layer 18: Thin-layer / Gold-plated 19: Surface layer / layer 20: Protective layer / Post-processing layer / Protective treatment

Claims

1. A process for depositing a bronze alloy onto a printed circuit board (5), comprising: A dielectric substrate (4) is provided, the dielectric substrate (4) including a first main surface and a second main surface, at least one first sheet (10) of a first conductive material is present on at least the first main surface, and at least one operation is performed to electrodeposit at least one layer (12) of at least one second conductive material on at least one region of the first sheet (10), characterized in that the at least one operation of electrodepositing at least one layer (12) of at least one second conductive material includes an operation of electrodepositing a bronze layer, the bronze layer comprising 45% to 65% copper, 30% to 45% tin and 2% to 11% zinc after deposition.

2. The process of claim 1, which includes a finishing operation in which a surface treatment is performed after the deposition of the bronze layer (12).

3. The process of claim 2, wherein the finishing operation includes applying a protective layer (20) comprising an organic solderable corrosion inhibitor.

4. The process of claim 2, wherein the finishing operation includes applying a protective layer (20) comprising a self-assembling monolayer.

5. The process of any one of claims 2 to 4, wherein the surface treatment is performed directly on at least one segment of the bronze layer (12).

6. The process of any one of claims 1 and 2, wherein the at least one operation of electrodepositing at least one layer of at least one second conductive material also includes electrodepositing a surface layer comprising at least one element selected from the list of gold, silver, palladium, ruthenium, and rhodium (19).

7. A process in which any one of claims 2 to 4 is combined with claim 6, wherein the surface treatment is performed directly on at least one segment of the surface layer (19).

8. The process of claim 6, wherein the at least one operation of electrodepositing at least one layer of at least one second conductive material also includes electrodepositing at least one element selected from the list of gold, silver and palladium in the form of a thin layer (18) with a thickness of less than 15 nanometers.

9. The process of any one of claims 1 to 4, wherein the at least one operation of electrodepositing at least one layer of at least one second conductive material includes, prior to the deposition of the bronze layer (12), an operation of electrodepositing one of a nickel layer (16) and a nickel-phosphorus layer (17).

10. A printed circuit board (5) obtained using a process as claimed in any one of claims 1 to 9, comprising a contact pad (7) configured to form contacts for at least one chip card module (2), the printed circuit board (5) comprising a first sheet (10) of a first conductive material on one of the main surfaces of the dielectric substrate (4), at least a portion of the surface of the first sheet (10) being covered with a stack comprising at least one of the following layers: a nickel layer (16), a nickel-phosphorus layer (17), and the bronze layer (12).

11. The printed circuit board (5) of claim 10, comprising a connection well (14) comprising at least one of the following layers stacked at the bottom of the connection well (14): a nickel layer (16), a nickel-phosphorus layer (17) and a surface layer (19) comprising at least one of the following elements: gold, silver, rhodium, ruthenium and palladium.

12. The printed circuit board of claim 11 further includes a thin layer (18) of gold, silver or palladium having a thickness of less than or equal to 15 nanometers under the bronze layer (12) and the layer (19).

13. The printed circuit board (5) of any one of claims 10 to 12, comprising a second sheet (11) of a first conductive material on the other of the main surfaces of the dielectric substrate, at least a portion of the surface of the second sheet (11) being covered with a stack comprising at least one of the following layers: a nickel layer (16), a nickel-phosphorus layer (17) and a surface layer (19) comprising at least one of the following elements: gold, silver, rhodium, ruthenium and palladium.

14. The printed circuit board (5) of any one of claims 10 to 12, wherein the bronze layer has a thickness of 150 nanometers or more and 600 nanometers or less.

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