Three dimensional (3D) vertical spiral inductor, method for fabricating the same and transformer

Abstract

A device including a vertical spiral inductor is disclosed. The vertical spiral inductor may include: a plurality of dielectric layers formed on a substrate, each of the plurality of conductive layers being disposed on each of the plurality of dielectric layers; a plurality of insulating layers, each of the plurality of insulating layers being disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers spacers each of the plurality of dielectric layers. A first spiral coil is arranged in a first plane perpendicular to the substrate, wherein the first spiral coil is formed by a first portion of the plurality of conductive layers and a first set of vias of a plurality of vias, the first set of vias being configured to connect the first portions of the plurality of conductive layers.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor devices, and more specifically, but not exclusively, to 3D spiral inductors and transformer devices including such spiral inductors and methods of manufacturing thereof. Prior Technology

[0002] Integrated circuitry and packaging technologies have made significant progress in improving computing power and reducing power consumption through the miniaturization and scaling down of active components. This disclosure generally relates to inductor structures with a high quality factor (Q) and a planar spiral inductor configuration, as well as device package structures that can accommodate said spiral inductors. These spiral inductors can also be coupled in some way via corresponding input and output taps, thereby forming a transformer configuration.

[0003] An inductor is an impedance device, and it can also include transformers and other induced reactors. Inductors are used in many important circuit applications, such as filters, power regulation, and impedance matching circuits.

[0004] Inductor structures are used in semiconductor devices, which are typically made of a core and a semiconductor substrate, with conductor layers of various patterns and geometries formed on the semiconductor substrate, connected and separated through dielectric layers, metal layers and other insulating layers.

[0005] Various inductors are formed into coils, and these coils are then wound around a core material such as ferrite. The core is typically formed into a rod, cylinder, or toroidal shape. Generally, the more windings a coil has, the higher its inductance value.

[0006] Therefore, there is a need for devices and methods that overcome the shortcomings of conventional methods as provided and discussed in this disclosure. Summary of the Invention

[0007] The following is a simplified summary relating to one or more aspects and / or examples associated with the apparatus and methods disclosed herein. Thus, this summary should not be considered a broad overview relating to all anticipated aspects and / or examples, nor should it be considered an identification of key or essential elements relating to all anticipated aspects and / or examples, or a depiction of the scope relating to any particular aspect and / or example. Therefore, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects and / or examples associated with the devices and methods disclosed herein, prior to the detailed description presented below.

[0008] According to various aspects disclosed herein, at least one aspect includes an apparatus having a spiral inductor, the spiral inductor comprising: a plurality of dielectric layers formed on a substrate; a plurality of conductive layers, each of the plurality of conductive layers being disposed on each of the plurality of dielectric layers; a plurality of insulating layers, each of the plurality of insulating layers being disposed on each of the plurality of conductive layers and configured to space apart each of the plurality of dielectric layers; a plurality of through-holes; and a first spiral coil arranged in a first plane perpendicular to the substrate, wherein the first spiral coil is formed by a first portion of the plurality of conductive layers and a first set of through-holes of the plurality of through-holes, the first set of through-holes being configured to connect the first portions of the plurality of conductive layers.

[0009] According to various aspects disclosed herein, at least one aspect includes a method for manufacturing a spiral inductor, the method comprising: depositing a plurality of dielectric layers on a substrate; depositing a plurality of conductive layers, each of the plurality of conductive layers being disposed on each of the plurality of dielectric layers; depositing a plurality of insulating layers, each of the plurality of insulating layers being disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers separates each of the plurality of dielectric layers; forming a plurality of vias; and forming a first spiral coil in a first plane perpendicular to the substrate, wherein the first spiral coil is formed by a first portion of the plurality of conductive layers and a first set of vias of the plurality of vias, the first set of vias being configured to connect the first portions of the plurality of conductive layers.

[0010] Based on the diagrams and detailed description, other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art. Simple Explanation of the Diagram

[0011] When considered in conjunction with the diagrams, a more complete understanding of the various aspects of this disclosure and its many associated technical advantages will be readily apparent through reference to the following detailed description. These diagrams are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0012] Figure 1 shows a partial cross-sectional view of a conventional horizontally oriented planar spiral inductor.

[0013] Figure 2 illustrates a partial cross-sectional view of a vertically oriented 3D spiral inductor according to at least one aspect of the present disclosure.

[0014] Figure 3 illustrates a partial cross-sectional view of vertical 3D spiral inductors connected in series according to at least one aspect of the present disclosure.

[0015] Figure 4 illustrates a partial cross-sectional view of a vertical 3D spiral inductor according to at least one aspect of the present disclosure.

[0016] Figure 5 illustrates a partial cross-sectional view of a vertical 3D spiral inductor according to at least one aspect of the present disclosure.

[0017] Figure 6 shows another partial cross-sectional view of a vertical 3D spiral inductor comprising two nested coils located in a plane, according to at least one aspect of the present disclosure.

[0018] Figure 7 illustrates a partial cross-sectional view of a vertical 3D spiral inductor according to at least one aspect of the present disclosure.

[0019] Figure 8 illustrates a partial cross-sectional view of a vertical 3D spiral inductor according to at least one aspect of the present disclosure.

[0020] Figure 9 illustrates a partial cross-sectional view of vertically connected 3D spiral inductors in parallel according to at least one aspect of the present disclosure.

[0021] Figure 10 illustrates a partial cross-sectional view of a vertical 3D spiral inductor according to at least one aspect of the present disclosure.

[0022] Figure 11 illustrates a partial cross-sectional view of a vertical 3D spiral inductor according to at least one aspect of the present disclosure.

[0023] Figure 12 illustrates a partial cross-sectional view of a vertical 3D spiral inductor according to at least one aspect of the present disclosure.

[0024] Figure 13 illustrates a partial cross-sectional view of a vertical 3D spiral inductor according to at least one aspect of the present disclosure.

[0025] Figure 14 illustrates a partial cross-sectional view of a vertical 3D spiral transformer according to at least one aspect of the present disclosure.

[0026] Figure 15 illustrates an exemplary method for manufacturing a package according to at least one aspect of this disclosure.

[0027] Figure 16 illustrates an operational device according to at least one aspect of this disclosure.

[0028] Figure 17 illustrates various electronic devices that can be integrated with any of the 3D spiral inductors disclosed herein, according to some examples of this disclosure.

[0029] By convention, features depicted in the drawings may not be drawn to scale. Therefore, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not depict all elements of a particular device or method. Furthermore, the same reference numerals denote the same features throughout the specification and drawings. Implementation

[0030] Various aspects of this disclosure are illustrated in the following descriptions and related diagrams, which pertain to specific aspects. Alternative aspects or features may be devised without departing from the scope of the teachings herein. Furthermore, well-known elements of the illustrative aspects herein may not be described in detail or may be omitted to avoid obscuring the relevant details of the teachings within this disclosure.

[0031] In some of the example implementations described, instances are identified where various component structures and operational parts can be taken from known conventional techniques and then arranged according to one or more exemplary aspects. In such cases, the internal details of known conventional component structures and / or operational parts may be omitted to help avoid potential confusion with the concepts illustrated in the illustrative aspects disclosed herein.

[0032] The terminology used herein is for descriptive purposes only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It will also be understood that, when used herein, the terms “comprising” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0033] This disclosure describes helical inductor and transformer structures for high-quality factor (Q) inductors and transformers. The structures include multiple helical traces supported by multiple respective substrates. These helical structures have a helical design implemented on a single plane, wherein the helix includes one or more turns within the plane of the inductor.

[0034] The inductance of an inductor is proportional to the length of the metal used to form the inductor. The inductance is also affected by many factors, such as the width of the metal forming the inductor coils, the space between the coils, the dimensions (e.g., diameter) of the metal conductor, and the number of turns in the helix. This type of helical inductor can have more or less loop or helical windings, depending on the desired circuit application and its associated inductance requirements.

[0035] Spiral traces are semiconductor representations or implementations of inductors, coils, or windings, also known in related fields.

[0036] For simplicity, the term spiral inductor will be used to encompass both spiral inductors and transformers. A transformer is formed using a spiral inductor, wherein the spiral inductor is magnetically coupled and electrically connected using at least one input tap and at least one output tap selected for the desired specific transformer application.

[0037] Figure 1 illustrates a conventional horizontal planar spiral inductor, showing two spiral structures (102 and 104) in a planar configuration that are parallel to each other and electrically connected or coupled to each other (connection or coupling shown in 106). This conventional inductor configuration requires a bottom wafer substrate mask of polysilicon or some other suitable material (e.g., metal) to provide the necessary shielding to mitigate the detrimental effects of magnetic flux and current (the mask is not shown) on eddy current losses in the silicon substrate.

[0038] A shield is necessary to prevent any harmful effects from the emitting inductor from propagating through to sensitive electronic components or signals / circuits located below the inductor via a path. These harmful effects are manifested by the energy flow and magnetic flux lines flowing through the spiral inductor (108). These harmful effects lead to design constraints and requirements for establishing forbidden zones (KOZs) on the sides and under the inductor structure to prevent such interference from occurring in the conventional configuration shown in Figure 1.

[0039] In conventional techniques, a grid-like structure (similar to a Faraday cage) is sometimes used, along with a conventional shielding structure required for this horizontal spiral inductor configuration, to prevent the generated electric and magnetic flux fields from penetrating the entire substrate structure. We know from the physics and material properties of devices that these electromagnetic flux fields can generate eddy currents (also known as Foucault currents). These are current loops induced within a conductor by a changing, fluctuating, or flowing magnetic field operating according to Faraday's law of induction. Eddy currents typically flow in a plane perpendicular to the magnetic field and in closed loops within the conductor.

[0040] These eddy currents can cause unwanted types of interference and degraded operating properties in devices. Therefore, various shielding structures are needed at the bottom of the package, and possibly also at the top of the package (e.g., in the form of molded compounds) to mitigate the harmful effects of these electric and magnetic fields.

[0041] At least one technical advantage of each aspect of this disclosure is that it mitigates or prevents these harmful events and eliminates the need for devices requiring masks and KOZ as used in conventional designs.

[0042] Figure 2 illustrates a vertically oriented 3D spiral inductor 200 configuration, showing three spiral conductive structures (e.g., coils 202, 204, and 206) parallel to each other and coupled in series with each other using conductors 208 and 210. Figure 2 shows the current flux line 212 flowing through the three spiral conductive structures. The 3D spiral inductor 200 is positioned in a plane with a vertical orientation. It should be understood that the disclosed aspects are not limited to the configuration illustrated. For example, in some aspects, coils 202, 204, and 206 may be coupled in parallel, or in other aspects, coils 202, 204, and 206 may be configured to form a transformer or as part of a transformer.

[0043] According to the disclosures herein and the various aspects discussed below, back-end process (BEOL) procedures may include forming one or more intermetallic dielectric (IMD) layers, which may have one or more metal layers (e.g., Mx, Mx-1, Mx-2, etc.) and one or more vias, said one or more metal layers and one or more vias being used to form the various coils, inductors, and transformers discussed herein. In some aspects, the metal layers may be formed of any highly conductive material, such as copper (Cu), aluminum (Al), silver (Ag), gold (Au), cobalt (Co), ruthenium (Ru), tungsten (W), or other conductive materials, alloys, or combinations thereof. In some aspects, the IMD layers may be formed of materials such as doped silicon dioxide (SiO2) or its fluorine-doped, carbon-doped, and carbon-doped forms, as well as spin-coated organic polymer dielectrics such as polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), and / or silicon-based polymer dielectrics.

[0044] Those skilled in the art will understand that, depending on the final design parameters and inductance value used for a given circuit application, the number of spiral trace layers and the density of the spiral winding or coiling in the IMD can achieve higher or lower inductance levels.

[0045] Furthermore, those skilled in the art will appreciate that other geometries for the spiral pattern shown in FIG2 may also be used without departing from the spirit and scope of the invention. For example, some other shapes that can be achieved include (but are not limited to) triangles, rectangles, squares, circles, ellipses, and other higher or lower order polygons.

[0046] Figure 3 illustrates another implementation of a vertical 3D spiral inductor 300 configuration, illustrating three spiral conductive structures (e.g., spiral coils 302, 304, and 306) that are parallel to each other and coupled to each other in a parallel configuration using conductors 310 and 312 and positioned in a vertical orientation perpendicular to a substrate layer (not shown). The arrangement of the spiral conductive structures in relation to their orientation on multiple metal layers is shown as Mx, Mx-1, Mx-2, Mx-3, and Mx-4. These metal layers are presented for illustrative purposes, and more or fewer metal layers may be used depending on the disclosed aspects. The disclosed aspects allow for a higher Q factor and a lower resistance (R) compared to conventional designs. In some aspects, the substrate may include one or more of active elements, passive elements, and / or metal wiring located beneath one or more spiral coils (e.g., spiral coils 302, 304, and 306), which in conventional designs would require the previously discussed shielding protective layer and associated KOZ. In contrast to the prior art, in the illustrated aspect there are three parallel spiral coils 302, 304 and 306, which can be considered as a spiral inductor or an individual spiral inductor, and again, the use of the upper bottom shield substrate is not required.

[0047] Figure 4 illustrates a partial cross-sectional view of an inductor 300 according to various aspects of this disclosure, showing a vertical 3D spiral inductor along the X-X' auxiliary line in Figure 3. Similarly, exemplary metal layers are shown as Mx, Mx-1, Mx-2, Mx-3, and Mx-4. Dielectric insulating layers (e.g., IMD) are shown as 402, 404, 406, 408, and 410. Insulating layers 411, 413, 415, 417, and 419 may be disposed on the respective dielectric layers (402, 404, 406, 408, and 410). Insulating layers 411, 413, 415, 417, and 419 may also serve as diffusion barrier layers to cover the top of the metal layers and may be, for example, silicon carbonitride (SiCN). Insulating layers 411, 413, 415, 417, and 419 may also serve as contact etch stop layers. Similarly, as discussed earlier in Figure 3, the solid continuous line of the through hole and connector shown as 312 is illustrated in this respect to show the spiral inductors connected in parallel configuration.

[0048] In Figure 4, a first portion 451 of the first helical coil 302 in a given metal layer is shown in cross-section. A second portion 452 of similar shape and size for the second helical coil 304 and a third portion 453 for the third helical coil 306 are also shown in Figure 4, but none are labeled with unique reference numerals. It should be understood that the various portions (e.g., 451, 452, and 453) can be formed by patterning and etching various metal layers (e.g., Mx, Mx-1, Mx-2, Mx-3, and Mx-4) to form various inductor portions and interconnecting various coils (e.g., 312 and 310). These bonding layer portions (e.g., 451, 452, and 453) are coupled through vias to form vertical coils (e.g., 302, 304, and 306). It should be understood that during conventional BEOL processing, the various portions, interconnects, and vias can be fabricated in a back-end process (BEOL) stack.

[0049] Figure 5 illustrates another view of a vertical 3D spiral inductor 300 in a Y-Y' reference frame according to various aspects of this disclosure, as shown by the Y-Y' auxiliary line in Figure 3. In the illustrated aspect, the cross-sectional view of the spiral coil 302 includes cross-sectional views of dielectric layers 402, 404, 406, 408, and 410, insulating layers 411, 413, 415, 417, and 419, and metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4. The spiral coil 302 is formed by Mx, Mx-1, Mx-2, Mx-3, and Mx-4, and a first set of through-holes 505 of a plurality of through-holes, the first set of through-holes 505 being configured to couple the various portions of the metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4 to form a spiral coil 302 configured as a single continuous coil. Through-holes 505 penetrate dielectric and insulating layers (e.g., 402 and 413) to couple various portions of the metal layers (e.g., MX and MX-1). The ends of the helical coil 302 are coupled to conductors 310 and 312, which are coupled to other helical coils connected in parallel. For simplicity, each through-hole 505 and its associated couplings will not be discussed in detail herein. Furthermore, it should be understood that each helical coil will have a set of through-holes to couple various portions of the metal layers forming the helical coil. For example, a first set of through-holes 505 may couple to the first portion 451 of the metal layers (layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4) in the first helical coil 302. A second set of through-holes may couple to the second portion 452 of the metal layers (layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4) in the second helical coil 304. The third set of through-holes can couple to the second portion 453 of the metal layers (layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4) in the second helical coil 306. It should be understood that the terms "first," "second," and "third" are used for convenience only and do not necessarily assign any order, nor should they be construed as limiting the aspects to the configuration illustrated.

[0050] As can be understood from the disclosure herein, various aspects may include an apparatus comprising a spiral inductor (e.g., 300) having a plurality of dielectric layers (e.g., 402, 404, 406, 408, and 410) formed on a substrate. A plurality of conductive layers (e.g., Mx, Mx-1, Mx-2, Mx-3, and Mx-4) may be provided, each of the conductive layers being disposed on each of the dielectric layers. A plurality of insulating layers (e.g., 411, 413, 415, 417, and 419) may be provided, each of the insulating layers being disposed on each of the conductive layers and configured to space apart each of the dielectric layers. A plurality of vias (e.g., 505) may be provided. A first spiral coil (e.g., 302) is arranged in a first plane perpendicular to the substrate. The first helical coil (e.g., 302) is formed by a first portion of a plurality of conductive layers (e.g., 451) and a first set of vias (e.g., 505) of a plurality of vias, the first set of vias being configured to couple the first portions of the plurality of conductive layers (e.g., Mx, Mx-1, Mx-2, Mx-3, and Mx-4). As noted above, the 3D vertical inductor configuration provides at least the technical advantage of reducing electromagnetic interference of the device layers above and / or below the 3D vertical inductor, which reduces or eliminates the need for KOZ of adjacent inductors. It should be understood that the illustrated configurations provided herein are merely for providing examples and facilitating discussion of the disclosed aspects. However, the disclosed aspects are not limited to the specific illustrated configurations.

[0051] Figure 6 illustrates another configuration of a vertical 3D spiral inductor 600 according to various aspects of this disclosure. It should be understood that the vertical 3D spiral inductor 600 can be similar to inductor 300, and coils 620 and 630 can be illustrated in a similar Y-Y' reference frame, similar to coil 302, as shown by the Y-Y' auxiliary line in Figure 3. Figure 6 can also be referred to as a vertical stacked inductor configuration or a vertical stacked transformer configuration. In the illustrated aspects, the cross-sectional views of the spiral coils 620 and 630 include cross-sectional views of dielectric layers 602, 604, 606, 608, and 610, insulating layers 611, 613, 615, 617, and 619, and metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4. Helical coils 620 and 630 are formed by Mx, Mx-1, Mx-2, Mx-3, and Mx-4 and a through-hole 605, which is coupled to portions formed by metal layers Mx, Mx-1, Mx-3, and Mx-4 to form helical coils 620 and 630 configured as two interleaved continuous coils. The through-hole 605 penetrates dielectric and insulating layers (e.g., 602 and 613) to couple portions of the metal layers (e.g., MX and MX-1). For simplicity, each through-hole 605 and its associated coupling will not be discussed in detail herein. Helical coil 620 has a first end 621 and a second end 622, which may in some respects be configured as an input tap or an output tap. Helical coil 630 has a first end 631 and a second end 632, which may in some respects be configured as an input tap or an output tap. The helical coils shown in Figure 6 are illustrated in either a parallel connection or an open-end configuration. In some aspects, coils 620 and 630 are in a vertically stacked transformer configuration. In other aspects, the ends may be connected such that coils 620 and 630 are in a series configuration. In still other aspects, it should be understood that the ends (e.g., 621, 622, 631, 632) may be connected to other coils (not shown) in series or parallel configurations based on various design considerations. Therefore, it should be understood that the disclosed aspects are not limited to the configurations illustrated.

[0052] Figure 7 illustrates a partial cross-sectional view of a vertical 3D spiral inductor 700 according to at least one aspect of the present disclosure. The cross-sectional view of the inductor 700 is in a similar X-X' reference frame, as illustrated with respect to the inductor of Figure 3. In Figure 7, various metal layers, such as metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4, are shown. For simplicity, no metal portions are illustrated in layers Mx and Mx-4. However, it should be understood that these layers can be used for additional electrical wiring and connections. Dielectric layers 721, 723, 725, 727, and 729, and insulating layers 711, 713, 715, 717, and 719 are also illustrated. In the illustrated aspect, three coils 702, 704, and 706 are shown in the X-X' reference frame.

[0053] As previously stated, for ease of illustration in Figure 7, 707 refers to how the helical conductor element looks in cross-sectional view. Other helical conductor elements of similar shape and size are also shown in Figure 7, but none of them are labeled with unique reference numerals. Conductor 712, connecting coils 702, 704, and 706 in parallel, is also illustrated. It should be understood that in the illustrated configuration, only three metal layers (Mx-1, Mx-2, and Mx-3) are used to form the inductor. While reducing inductance, this illustrates that the disclosed aspects can use three or more metal layers, allowing for additional wiring flexibility on unused metal layers. Furthermore, it should be understood that the metal layers used can be any combination of metal layers (such as (Mx, Mx-1, and Mx-2), (Mx-2, Mx-3, and Mx-4), (Mx, Mx-2, and Mx-4), etc.). Therefore, the disclosed aspects are not limited to the illustrated configuration.

[0054] Figure 8 illustrates a partial cross-sectional view of a vertical 3D spiral inductor 700 according to at least one aspect of the present disclosure. The cross-sectional view of the inductor 700 is situated in a similar Y-Y' reference frame including a coil 702, which is in a similar reference frame to coil 302, as illustrated with respect to inductor 300 in Figure 3. In the illustrated aspect, five metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4 are present. For simplicity, no metal portions are illustrated in layers Mx and Mx-4. However, it should be understood that these layers can be used for additional electrical wiring and connections. Dielectric layers 721, 723, 725, 727, and 729, and insulating layers 711, 713, 715, 717, and 719 are also illustrated. Coil 702 is formed from three metal layers (Mx-1, Mx-2, and Mx-3, as shown). The conductor 712, which connects coils 702, 704, and 706 in parallel at the first end, is shown in cross section. Additionally, the conductor 714, which connects coils 702, 704, and 706 in parallel at the second end of the inductor, is also shown in cross section, but only the connection to inductor 702 is illustrated.

[0055] Figure 9 illustrates a partial cross-sectional view of a vertical 3D spiral inductor 900 according to at least one aspect of this disclosure. Three spiral coils 902, 904, and 906 are positioned in a vertical orientation and are connected in series with each other through conductors 903 and 905 in the configuration. A first end 908 and a second end 909 of the inductor 900 are also illustrated. Ends 908 and 909 can be used to couple the inductor to other components and / or additional coils.

[0056] Figure 10 illustrates a partial cross-sectional view of a vertical 3D spiral inductor 900 in the X-X' reference frame illustrated in Figure 9, according to at least one aspect of the present disclosure. Similarly, cross-sectional views of dielectric layers 1002, 1004, 1006, 1008, and 1010, insulating layers 1011, 1013, 1015, 1017, and 1019, and metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4 are illustrated. As noted above, coils 902, 904, and 906 are connected in a series-coupled configuration. Specifically, a first conductor 903 couples coil 902 to coil 904. A second conductor 905 couples coil 904 to coil 906. The first conductor 903 and the second conductor 905 are formed by portions of metal layers (e.g., Mx, Mx-1, Mx-2) disposed between the coupled respective coils and vias 1005. For example, as illustrated, a first conductor 903 is disposed between coils 902 and 904, while a second conductor 905 is disposed between coils 904 and 906. Furthermore, as illustrated, a first end 908 is coupled to coil 902 to provide an external coupling point. For ease of illustration in FIG10, 1003 refers to how a portion of the helical conductor element appears in cross-sectional view. Other helical conductor elements of similar shape and size are also shown in FIG10, but they are not labeled with unique reference numerals. It should be understood that the aspects illustrated are provided for illustrative purposes only, and the disclosed aspects are not limited to the illustrated configuration. For example, conductors 903 and 905 may be located in different layers, and coil coupling may be performed at other locations. Therefore, it should be understood that the disclosed aspects are not limited to the illustrated configuration.

[0057] Figure 11 illustrates a partial top view of a vertical 3D spiral inductor 900 in a Y-Y' reference frame according to at least one aspect of this disclosure. Similarly, cross-sectional views of dielectric layers 1002, 1004, 1006, 1008, and 1010, insulating layers 1011, 1013, 1015, 1017, and 1019, and metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4 are illustrated. As noted above, coils 902, 904, and 906 are connected in a series-coupled configuration; however, only coil 902 is illustrated in the view. As illustrated, a first conductor 903 is coupled to the top portion of coil 902 in metal layer Mx, forming part of a connection with coil 904 (not shown). Furthermore, as illustrated, a first end 908 is coupled to coil 902 toward the center of the coil in metal layer Mx-2 to provide an external coupling point, as discussed above. Once again, it should be understood that the explanations provided are for the purpose of clarification, not limitation, of the aspects disclosed.

[0058] Figure 12 illustrates a partial cross-sectional view of a vertically parallel 3D spiral inductor 1200 in an X-X' reference frame according to at least one aspect of the present disclosure. The cross-sectional view of the inductor 1200 is in a similar X-X' reference frame, as illustrated with respect to the inductor in Figure 9. In Figure 12, various metal layers, such as metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4, are shown. For simplicity, no metal portions are illustrated in layers Mx and Mx-4. However, it should be understood that these layers can be used for additional electrical wiring and connections. Dielectric layers 1202, 1204, 1206, 1208, and 12010, and insulating layers 1211, 1213, 1215, 1217, and 1219 are also illustrated. In the illustrated aspect, three coils 1202, 1204, and 1206 are shown in an X-X' reference frame.

[0059] Furthermore, as illustrated, coils 1202, 1204, and 1206 are connected in a series-coupled configuration. Specifically, a first conductor 1203 couples coil 1202 to coil 1204. A second conductor 1205 couples coil 1204 to coil 1206. The first conductor 1203 and the second conductor 1205 are formed by portions (e.g., Mx-2 and Mx-3) of metal layers disposed between the coupled respective coils and vias. For example, as illustrated, the first conductor 1203 is disposed between coils 1202 and 1204, while the second conductor 1205 is disposed between coils 1204 and 1206. Additionally, as illustrated, a first end 1201 is coupled to coil 1202 to provide an external coupling point. While the inductance of the coils is reduced due to the fewer turns, the configuration illustrates that the disclosed aspects can utilize three or more metal layers, allowing for additional wiring flexibility on unused metal layers. Furthermore, it should be understood that the metal layers used can be any combination of metal layers (such as (Mx, Mx-1 and Mx-2), (Mx-2, Mx-3 and Mx-4), (Mx, Mx-2 and Mx-4), etc.). Therefore, the disclosed aspects are not limited to the configuration illustrated.

[0060] Figure 13 illustrates a partial cross-sectional view of a vertical 3D spiral inductor 1200 according to at least one aspect of the present disclosure. The cross-sectional view of the inductor 1200 is in a similar Y-Y' reference frame including a coil 1202, which is in a similar reference frame to coil 902, as illustrated with respect to inductor 900 in Figure 9. In the illustrated aspect, there are five metal layers Mx, Mx-1, Mx-2, Mx-3, and Mx-4. For simplicity, the metal portions in layers Mx and Mx-4 are not shown. However, it should be understood that these layers can be used for additional electrical wiring and connections. Dielectric layers 1202, 1204, 1206, 1208, and 12010 and insulating layers 1211, 1213, 1215, 1217, and 1219 are also illustrated. Coil 1202 is formed from three metal layers (Mx-1, Mx-2, and Mx-3, as shown). The first end 1201 connecting coil 1202 to an external component is shown in cross section. Also shown in cross section is conductor 1203 that couples coils 1202 and 1204 in series, but only the connection to inductor 1202 is shown.

[0061] Figure 14 illustrates a partial cross-sectional view of a vertical 3D spiral transformer 1400 according to at least one aspect of this disclosure. In this respect, spiral windings 1402, 1404, and 1406 are connected in a transformer configuration. Specifically, windings 1402 and 1406 are coupled together to form a first coil (coil 1) of transformer 1400. Spiral winding 1404 forms a second coil (coil 2) of transformer 1400. Arrangements using metal layers to vertically form spiral windings 1402, 1404, and 1406 are shown as Mx, Mx-1, Mx-2, Mx-3, and Mx-4. Various input and output taps can be selected to form a desired transformer configuration (not shown). Furthermore, additional windings can be added to the first and / or second coils. Therefore, the disclosed aspects are not limited to the configuration illustrated.

[0062] Figure 15 illustrates an exemplary method 1500 for manufacturing a spiral inductor according to one aspect of this disclosure. Other manufacturing methods are possible, and the methods discussed are presented only for illustrative purposes to understand the various aspects disclosed herein. Method 1500 begins by depositing a plurality of dielectric layers on a substrate in block 1502. The method continues in block 1504 by depositing a plurality of conductive layers, each of the plurality of conductive layers being disposed on each of the plurality of dielectric layers. The method continues in block 1506 by depositing a plurality of insulating layers, each of the plurality of insulating layers being disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers spaced apart from each of the plurality of dielectric layers. The method continues in block 1508 by forming a plurality of vias. The method continues in block 1510 by forming a first spiral coil in a first plane perpendicular to the substrate, wherein the first spiral coil is formed by a first portion of the plurality of conductive layers and a first set of vias of the plurality of vias, the first set of vias being configured to couple to the first portion of the plurality of conductive layers.

[0063] It should be understood that the aforementioned manufacturing process is provided only as a general description of some aspects of this disclosure and is not intended to limit the scope of this disclosure or the appended patent applications. Furthermore, many details of the manufacturing process known to those skilled in the art may have been omitted or combined in the summary procedure section to aid in understanding the disclosed aspects without requiring a detailed reproduction of every detail and / or all possible procedure variations.

[0064] The aforementioned devices or variations, as well as other similar aspects, may be incorporated into devices selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablets, computers, wearable devices, Internet of Things (IoT) devices, laptops, servers, and devices in autonomous vehicles.

[0065] Figure 16 illustrates an exemplary mobile device according to some examples of the present disclosure. Referring now to Figure 16, a block diagram of a mobile device configured according to exemplary aspects is depicted and is generally designated as mobile device 1600. In some aspects, mobile device 1600 may be configured as a wireless communication device. As shown, mobile device 1600 includes a processor 1601. Processor 1601 is shown as including an instruction pipeline 1612, a buffer processing unit (BPU) 1608, a branch instruction queue (BIQ) 1611, and a throttle 1610, all known in the art. For clarity, other well-known details of these blocks (e.g., counters, items, confidence regions, weighted sums, comparators, etc.) are omitted from this view of processor 1601. Processor 1601 may be communicatively coupled to memory 1632 via a link, which may be a die-to-die or wafer-to-wafer link. Mobile device 1600 also includes display 1628 and display controller 1626, wherein display controller 1626 is coupled to processor 1601 and display 1628.

[0066] In some aspects, FIG16 may include an encoder / decoder (CODEC) 1634 (e.g., an audio and / or voice CODEC) coupled to processor 1601; a speaker 1636 and a microphone 1638 coupled to CODEC 1634; a wireless antenna 1642 coupled to wireless circuitry 1640 coupled to processor 1601 (which may include a modem, RF circuitry, filters, etc., which may use various 3D spiral inductors and / or transformers disclosed herein).

[0067] In certain aspects where one or more of the aforementioned blocks exist, the processor 1601, display controller 1626, memory 1632, CODEC 1634, and wireless circuitry 1640 may be included in a system-in-package or monolithic system device 1622. Input devices 1630 (e.g., physical or virtual keyboards), power supply 1644 (e.g., battery), display 1628, input devices 1630, speaker 1636, microphone 1638, wireless antenna 1642, and power supply 1644 may be external to the monolithic system device 1622 and may be coupled to elements of the monolithic system device 1622, such as interfaces or power management controllers. Various 3D spiral inductors disclosed herein can be used in various parts of power coupling circuits.

[0068] It should be noted that although Figure 16 depicts a mobile device, the processor 1601 and memory 1632 can also be integrated into set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed location data units, computers, laptops, tablets, communication devices, mobile phones, or other similar devices.

[0069] Figure 17 illustrates various electronic devices that can be integrated with any of the aforementioned transistor units, according to some examples of this disclosure. For example, mobile phone device 1702, laptop device 1704, and fixed-location terminal device 1706 may include semiconductor device 1700, which includes various 3D spiral inductors and / or transformers as described herein (e.g., 200, 300, 600, 700, 900, 1200, 1400). Semiconductor device 1700 may be, for example, an integrated circuit, a die, an integrated device, an integrated device package, an integrated circuit device, a package, an integrated circuit package, or a package-on-package device. Devices 1702, 1704, and 1706 illustrated in Figure 17 are merely exemplary. Other electronic devices may also feature semiconductor device 1700, including but not limited to a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, devices supporting Global Positioning System (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smartphones, tablets, computers, wearable devices, servers, routers, electronic devices implemented in autonomous vehicles (e.g., autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0070] The aforementioned disclosed devices and functionalities can be designed and configured as computer files (e.g., register transfer level (RTL), geometric data flow (GDS) Gerber, etc.) stored on a computer-readable medium. Some or all of these files can be provided to a manufacturing process that manufactures devices based on such files. The resulting products may include semiconductor wafers, which are subsequently diced into semiconductor dies and packaged into semiconductor packages, integrated devices, single-chip system devices, etc., which can then be used in the various devices described herein.

[0071] It should be understood that the aspects disclosed herein can be described as functional equivalents of structures, materials, and / or devices described and / or recognized by those skilled in the art. For example, in one aspect, an apparatus may include components for performing the various functions discussed above. It should be understood that the foregoing aspects are provided by way of example only, and the claimed aspects are not limited to the specific references and / or descriptions cited as examples.

[0072] One or more of the elements, processes, features, and / or functions illustrated in Figures 2-17 may be rearranged and / or combined into a single element, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, processes, and / or functions may be added without departing from this disclosure. It should also be noted that Figures 1-16 and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some implementations, Figures 2-17 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce integrated devices. In some implementations, a device may include a die, an integrated device, a die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, and / or an inserter.

[0073] As used herein, the terms “user equipment” (or “UE”), “user device,” “user terminal,” “user terminal equipment,” “communication device,” “wireless device,” “wireless communication device,” “handheld device,” “mobile device,” “mobile terminal,” “mobile station,” “mobile phone,” “access terminal,” “user device,” “user terminal,” “user station,” “terminal,” and variations thereof may interchangeably refer to any suitable mobile or fixed device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed-location terminals, tablets, computers, wearable devices, laptops, servers, autonomous vehicle equipment in autonomous vehicles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices that communicate with another device capable of receiving wireless communication and / or navigation signals via short-range wireless, infrared, wired, or other connections, whether satellite signal reception or auxiliary data reception and / or location-related processing occurs on said device or said other device. Furthermore, these terms are intended to encompass all devices capable of communicating with the core network via a radio access network (RAN), including both wireless and wired communication devices, and through the core network, the UE can connect to external networks such as the Internet and other UEs. Of course, other mechanisms for connecting the UE to the core network and / or the Internet are also possible, such as via a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE 802.11), etc. The UE can be embodied in any of a variety of devices, including but not limited to printed circuit (PC) cards, compact flash memory devices, external or internal modems, wireless or wired telephones, smartphones, tablets, tracking devices, asset tags, etc.

[0074] Wireless communication between electronic devices can be based on different technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi) and IEEE 802.15.4 (Zigbee / Thread), or other protocols that can be used in wireless communication networks or data communication networks.

[0075] The term "exemplary" is used herein to mean "as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as superior to other examples. Similarly, the term "example" does not mean that all examples include the features, advantages, or modes of operation discussed. Furthermore, specific features and / or structures may be combined with one or more other features and / or structures. Moreover, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0076] It should be noted that unless a connection is explicitly disclosed as a direct connection, the terms “connection,” “coupled,” or any variation thereof mean any direct or indirect connection or coupling between elements, and may cover the presence of an intermediate element between two elements that is “connected” or “coupled” together via the intermediate element.

[0077] Any references to elements using names such as "first," "second," etc., in this document do not limit the number and / or order of these elements. Rather, these names are used as a convenient way to distinguish between two or more elements and / or as instances of elements. Furthermore, unless otherwise stated, a group of elements may include one or more elements.

[0078] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to include more features than are expressly mentioned in each clause. Rather, aspects of this disclosure may include fewer features than those in a single disclosed example clause. Therefore, the following clauses should be considered incorporated into the specification, where each clause may serve as a separate example. Although each subsidiary clause may refer to a specific combination with one of the other clauses in the clause, the aspects(s) of the subsidiary clause are not limited to that specific combination. It should be understood that other example clauses may also include combinations of aspects(s) of subsidiary clauses with the subject matter of any other subsidiary or independent clause, or any feature combined with other subsidiary and independent clauses. The aspects disclosed herein expressly include these combinations unless expressly stated or readily inferred that a particular combination is not intended (e.g., contradictory aspects, such as defining an element as both an insulator and a conductor). Furthermore, even if a clause is not directly subordinated to an independent clause, aspects of the clause may be included in any other independent clause.

[0079] An implementation example is described in the following numbered clauses:

[0080] Clause 1. An apparatus including a spiral inductor, comprising: a plurality of dielectric layers formed on a substrate; a plurality of conductive layers, each of the plurality of conductive layers being disposed on each of the plurality of dielectric layers; a plurality of insulating layers, each of the plurality of insulating layers being disposed on each of the plurality of conductive layers and configured to space apart each of the plurality of dielectric layers; a plurality of through-holes; and a first spiral coil disposed in a first plane perpendicular to the substrate, wherein the first spiral coil is formed by first portions of the plurality of conductive layers and a first set of through-holes of the plurality of through-holes, the first set of through-holes being configured to connect the first portions of the plurality of conductive layers.

[0081] Clause 2. The apparatus according to Clause 1 further includes: a second spiral coil disposed in a second plane perpendicular to the substrate, wherein the second spiral coil is formed by a second portion of a plurality of conductive layers and a second set of vias of a plurality of vias, the second set of vias being configured to connect the second portions of the plurality of conductive layers.

[0082] Clause 3. The apparatus according to Clause 2, wherein the first helical coil is electrically coupled to the second helical coil.

[0083] Clause 4. The apparatus according to any one of Clauses 2 to 3, wherein the first helical coil and the second helical coil are coupled in series.

[0084] Clause 5. The apparatus according to any one of Clauses 2 to 3, wherein the first helical coil and the second helical coil are coupled in parallel.

[0085] Clause 6. An apparatus according to any one of Clauses 2 to 5, wherein the first helical coil is magnetically coupled to the second helical coil.

[0086] Clause 7. The apparatus according to Clause 6, wherein the first helical coil and the second helical coil are arranged in a transformer configuration and include at least one input tap and one output tap.

[0087] Clause 8. The apparatus according to any one of Clauses 2 to 7 further includes: a third spiral coil disposed in a third plane perpendicular to the substrate, wherein the third spiral coil is formed by a third portion of a plurality of conductive layers and a third set of vias of a plurality of vias, the third set of vias being configured to connect the third portions of the plurality of conductive layers.

[0088] Clause 9. The apparatus according to Clause 8, wherein the third helical coil and the second helical coil are magnetically coupled to each other, and wherein the first helical coil and the third helical coil are electrically coupled to each other.

[0089] Clause 10. An apparatus according to any one of Clauses 8 to 9, wherein the first helical coil, the second helical coil, and the third helical coil are electrically coupled.

[0090] Clause 11. The apparatus according to Clause 10, wherein the first helical coil, the second helical coil and the third helical coil are coupled in series.

[0091] Clause 12. The apparatus according to Clause 10, wherein the first helical coil, the second helical coil, and the third helical coil are coupled in parallel.

[0092] Clause 13. An apparatus according to any one of Clauses 2 to 12, wherein the first helical coil and the second helical coil are arranged in a nested coil configuration on the same plane.

[0093] Clause 14. The apparatus according to Clause 13, wherein the first helical coil is magnetically coupled to the second helical coil in a transformer configuration.

[0094] Clause 15. An apparatus according to any one of Clauses 13 to 14, wherein the first helical coil is electrically coupled to the second helical coil.

[0095] Clause 16. An apparatus according to any one of Clauses 1 to 15, wherein the substrate includes at least one of an active element, a passive element, or a metal wiring located below the first helical coil.

[0096] Clause 17. An apparatus according to any one of Clauses 1 to 16, wherein the first helical coil is formed in a back-end process (BEOL) stack.

[0097] Clause 18. A device according to any one of Clauses 1 to 17, wherein the device is selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptops, servers, and devices in autonomous vehicles.

[0098] Clause 19. A method for manufacturing a spiral inductor, the method comprising: depositing a plurality of dielectric layers on a substrate; depositing a plurality of conductive layers, each of the plurality of conductive layers being disposed on each of the plurality of dielectric layers; depositing a plurality of insulating layers, each of the plurality of insulating layers being disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers spaced apart from each of the plurality of dielectric layers; forming a plurality of vias; and forming a first spiral coil in a first plane perpendicular to the substrate, wherein the first spiral coil is formed by a first portion of the plurality of conductive layers and a first set of vias of the plurality of vias, the first set of vias being configured to connect the first portions of the plurality of conductive layers.

[0099] Clause 20. The method according to Clause 19 further includes: forming a second spiral coil in a second plane perpendicular to the substrate, wherein the second spiral coil is formed by a second portion of a plurality of conductive layers and a second set of vias of a plurality of vias, the second set of vias being configured to connect the second portions of the plurality of conductive layers.

[0100] Clause 21. The method according to Clause 20 further includes: electrically coupling the first helical coil to the second helical coil.

[0101] Clause 22. The method according to Clauses 20 to 21 further includes: electrically coupling the first helical coil and the second helical coil in series.

[0102] Clause 23. The method according to any one of Clauses 20 to 21 further includes: electrically coupling the first helical coil and the second helical coil in parallel.

[0103] Clause 24. The method according to any one of Clauses 20 to 23, wherein the first helical coil is magnetically coupled to the second helical coil.

[0104] Clause 25. The method according to any one of Clauses 20 to 24 further includes: forming a third spiral coil in a third plane perpendicular to the substrate, wherein the third spiral coil is formed by a third portion of a plurality of conductive layers and a third set of vias of a plurality of vias, the third set of vias being configured to connect the third portions of the plurality of conductive layers.

[0105] Clause 26. The method according to Clause 25, wherein the third helical coil is magnetically coupled to the second helical coil, and wherein the first helical coil and the third helical coil are electrically coupled to each other.

[0106] Clause 27. The method according to any one of Clauses 25 to 26, wherein the first helical coil, the second helical coil and the third helical coil are arranged in a transformer configuration and include at least one input tap and one output tap.

[0107] Clause 28. The method according to any one of Clauses 25 to 27 further includes: electrically coupling the first helical coil, the second helical coil, and the third helical coil.

[0108] Clause 29. The method according to Clause 28 further includes: electrically coupling the first helical coil, the second helical coil, and the third helical coil in series.

[0109] Clause 30. The method according to Clause 28 further includes: electrically coupling the first helical coil, the second helical coil, and the third helical coil in parallel.

[0110] Clause 31. The method according to any one of Clauses 20 to 30, wherein the first helical coil and the second helical coil are arranged on the same plane in a nested coil configuration.

[0111] Clause 32. The method according to Clause 31, wherein the first helical coil is magnetically coupled to the second helical coil in the transformer configuration.

[0112] Clause 33. The method according to any one of Clauses 31 to 32 further includes: electrically coupling the first helical coil to the second helical coil.

[0113] Clause 34. The method according to any one of Clauses 19 to 33, wherein the substrate includes at least one of an active element, a passive element, or a metal wiring located below the first helical coil.

[0114] Clause 35. The method of any one of Clauses 19 to 34, wherein the first spiral coil is formed in the back-end process (BEOL) stack.

[0115] Clause 36. The method according to any one of Clauses 19 to 35, wherein the spiral sensor is integrated into the device, and wherein the device is selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptops, servers, and devices in autonomous vehicles.

[0116] Those skilled in the art will understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0117] Nothing stated or described in this application is intended to offer any element, action, feature, benefit, advantage, or equivalent to the public, whether or not such element, action, feature, benefit, advantage, or equivalent is described in the claims.

[0118] Furthermore, those skilled in the art will understand that the various illustrative logic blocks, modules, circuits, and algorithmic actions described in conjunction with the examples disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various illustrative elements, blocks, modules, circuits, and actions have been described above generally according to their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole. Skilled artisans can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0119] Although some aspects have been described in conjunction with the device, it is self-evident that these aspects also constitute a description of the corresponding method, and therefore, blocks or elements of the device should also be understood as corresponding method actions or features as method actions. Similarly, aspects described in conjunction with or as method actions also constitute a description of the corresponding blocks, details, or features of the corresponding device. Some or all of the method actions can be performed by hardware devices (or using hardware devices), such as, for example, microprocessors, programmable computers, or electronic circuits. In some examples, some or more of the most important method actions can be performed by such devices.

[0120] As can be seen in the detailed description above, different features are combined together in the examples. This manner of disclosure should not be construed as an intention for the claimed examples to have more features than expressly mentioned in the corresponding claims. Rather, this disclosure may include all features less than those of the individual examples disclosed. Therefore, the following claims should be considered incorporated into the specification, where each claim may serve as a separate example on its own. Although each claim may serve as a separate example on its own, it should be noted that while subsidiary claims may refer to a specific combination with one or more claims in the claims, other examples may also cover or include combinations of said combinations of subsidiary claims with the subject matter of any other subsidiary claims or any features with other subsidiary and independent claims. Such combinations are presented herein unless expressly stated that no particular combination is intended to be used. Furthermore, it is intended that features of claims may be included in any other independent claims, even if said claims are not directly subordinate to independent claims.

[0121] It should also be noted that the methods, systems and apparatus disclosed in the specification or the claims can be implemented by a device that includes components for performing corresponding actions and / or functions of the disclosed methods.

[0122] Furthermore, in some examples, an individual action can be subdivided into multiple sub-actions or contain multiple sub-actions. Such sub-actions can be included in the public disclosure of the individual action and are part of the public disclosure of the individual action.

[0123] While the foregoing disclosure has shown illustrative examples of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined in the appended claims. The functions and / or actions of the methods described in the examples herein do not need to be performed in any particular order. Furthermore, well-known elements will not be described in detail or may be omitted to avoid obscuring the relevant details of the aspects and examples disclosed herein. Moreover, although elements of this disclosure may be described or claimed in the singular, plural forms are contemplated unless explicitly stated otherwise.

[0124] 102: Spiral structure 104: Spiral structure 106: Connection or coupling 108: Spiral Inductor 200:3D spiral inductor 202: Coil 204: Coil 206: Coil 208: Conductor 210: Conductor 212: Electricity flux line 300: Vertical 3D Spiral Inductor 302: Helical coil 304: Spiral Coil 306: Helical coil 310: Conductor 312: Conductor Mx: Metal layer Mx-1: Metal layer Mx-2: Metal layer Mx-3: Metal Layer Mx-4: Metallic layer 402: Dielectric insulating layer 404: Dielectric insulating layer 406: Dielectric insulating layer 408: Dielectric insulating layer 410: Dielectric insulating layer 411: Insulation layer 413: Insulation layer 415: Insulation layer 417: Insulation layer 419: Insulation layer 451: Part One 452: Part Two 453: Part Three 505: First group of through holes 600: Vertical 3D Spiral Inductor 602: Dielectric layer 604: Dielectric layer 605: Through hole 606: Dielectric layer 608: Dielectric layer 610: Dielectric layer 611: Insulation layer 613: Insulation layer 615: Insulation layer 617: Insulation layer 619: Insulation layer 620: Coil 621: First end 622: Second end 630: Coil 631: First end 632: Second end 700: Inductor 702: Coil 704: Coil 706: Coil 707: Spiral Conductor Element 711: Insulation layer 712: Conductor 713: Insulation layer 714: Conductor 715: Insulation layer 717: Insulation layer 719: Insulation layer 721: Dielectric layer 723: Dielectric layer 725: Dielectric layer 727: Dielectric layer 729: Dielectric layer 900: Vertical 3D Spiral Inductor 902: Spiral coil 903: Conductor 904: Spiral coil 905: Conductor 906: Spiral coil 908: First end 909: Second end 1002: Dielectric layer 1003: Spiral Conductor Element 1004: Dielectric layer 1005: Through hole 1006: Dielectric layer 1008: Dielectric layer 1010: Dielectric layer 1011: Insulation layer 1013: Insulation layer 1015: Insulation layer 1017: Insulation layer 1019: Insulation layer 1200: Vertical Parallel 3D Spiral Inductor 1201: First end 1202: Dielectric layer 1203: First Conductor 1204: Dielectric layer 1205: Second conductor 1206: Dielectric layer 1208: Dielectric layer 1210: Dielectric layer 1211: Insulation layer 1213: Insulation layer 1215: Insulation layer 1217: Insulation layer 1219: Insulation layer 1400: Vertical 3D Spiral Transformer 1402: Helical winding 1404: Helical winding 1406: Helical winding 1500: Method 1502: Square 1504: Square 1506: Square 1508: Square 1510: Square 1600: Mobile Devices 1601: Processor 1608: Buffer Processing Unit (BPU) 1610: Throttling device 1611: Branch Instruction Queue (BIQ) 1612: Instruction Pipeline 1622: Single-chip system device 1626: Display controller 1628: Monitor 1630: Input device 1632: Memory 1634: Encoder / Decoder (CODEC) 1636: Loudspeaker 1638: Microphone 1640: Wireless Circuit 1642: Wireless Antenna 1644: Power Supply 1700: Semiconductor Devices 1702: Mobile Phone Equipment 1704: Laptop devices 1706: Fixed-location terminal equipment

Claims

1. A device including a spiral inductor, comprising: Multiple dielectric layers are formed on the substrate; Multiple conductive layers, each of the multiple conductive layers being disposed on each of the multiple dielectric layers; A plurality of insulating layers, each of which is configured to separate two adjacent dielectric layers of the plurality of dielectric layers; a plurality of vias; a first spiral coil arranged in a first plane perpendicular to the substrate, wherein the first spiral coil is formed by a first portion of the plurality of conductive layers and a first set of vias of the plurality of vias, the first set of vias being configured to connect the first portion of the plurality of conductive layers; and a second spiral coil arranged in the first plane, wherein the second spiral coil is formed by a second portion of the plurality of conductive layers and a second set of vias of the plurality of vias, the second set of vias being configured to connect the second portion of the plurality of conductive layers, wherein the first spiral coil and the second spiral coil are arranged in a nested coil configuration.

2. The apparatus according to claim 1, wherein the first helical coil is electrically coupled to the second helical coil.

3. The apparatus according to claim 2, wherein the first helical coil and the second helical coil are coupled in series.

4. The apparatus according to claim 2, wherein the first helical coil and the second helical coil are coupled in parallel.

5. The apparatus according to claim 1, wherein the first helical coil is magnetically coupled to the second helical coil.

6. The apparatus according to claim 5, wherein the first helical coil and the second helical coil are arranged in a transformer configuration and include at least one input tap and one output tap.

7. The apparatus according to claim 1, further comprising: A third spiral coil is arranged in a second plane perpendicular to the substrate, wherein the third spiral coil is formed by a third portion of the plurality of conductive layers and a third set of through holes in the plurality of through holes, the third set of through holes being configured to connect the third portion of the plurality of conductive layers.

8. The apparatus according to claim 7, wherein the third helical coil and the second helical coil are magnetically coupled to each other, and wherein the first helical coil and the third helical coil are electrically coupled to each other.

9. The apparatus according to claim 7, wherein the first helical coil, the second helical coil, and the third helical coil are electrically coupled.

10. The apparatus according to claim 9, wherein the first helical coil, the second helical coil and the third helical coil are coupled in series.

11. The apparatus according to claim 9, wherein the first helical coil, the second helical coil, and the third helical coil are coupled in parallel.

12. The apparatus of claim 1, wherein the first helical coil is magnetically coupled to the second helical coil in a transformer configuration.

13. The apparatus of claim 1, wherein the substrate includes at least one of an active element, a passive element, or a metal wiring located below the first helical coil.

14. The apparatus of claim 1, wherein the first helical coil is formed in a back-end process (BEOL) stack.

15. The apparatus of claim 1, wherein the apparatus is selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptops, servers, and devices in autonomous vehicles.

16. A method for manufacturing a spiral inductor, the method comprising: Multiple dielectric layers are deposited on the substrate; Multiple conductive layers are deposited, each of the multiple conductive layers being disposed on each of the multiple dielectric layers; A plurality of insulating layers are deposited, each of the plurality of insulating layers being configured to separate two corresponding adjacent dielectric layers of the plurality of dielectric layers; a plurality of vias are formed; a first spiral coil is formed in a first plane perpendicular to the substrate, wherein the first spiral coil is formed by a first portion of the plurality of conductive layers and a first set of vias of the plurality of vias, the first set of vias being configured to connect the first portion of the plurality of conductive layers; and a second spiral coil is formed in the first plane, wherein the second spiral coil is formed by a second portion of the plurality of conductive layers and a second set of vias of the plurality of vias, the second set of vias being configured to connect the second portion of the plurality of conductive layers, wherein the first spiral coil and the second spiral coil are arranged in a nested coil configuration.

17. The method according to claim 16 further includes: The first helical coil is electrically coupled to the second helical coil.

18. The method according to claim 17, further comprising: The first spiral coil and the second spiral coil are connected in series for electrical coupling.

19. The method according to claim 17, further comprising: The first spiral coil and the second spiral coil are electrically coupled in parallel.

20. The method according to claim 16, wherein the first helical coil is magnetically coupled to the second helical coil.

21. The method according to claim 16 further includes: A third spiral coil is formed in a second plane perpendicular to the substrate, wherein the third spiral coil is formed by a third portion of the plurality of conductive layers and a third set of through holes in the plurality of through holes, the third set of through holes being configured to connect the third portion of the plurality of conductive layers.

22. The method according to claim 21, wherein the third helical coil is magnetically coupled to the second helical coil, and wherein the first helical coil and the third helical coil are electrically coupled to each other.

23. The method according to claim 21, wherein the first helical coil, the second helical coil and the third helical coil are arranged in a transformer configuration and include at least one input tap and one output tap.

24. The method according to claim 21 further includes: The first spiral coil, the second spiral coil, and the third spiral coil are electrically coupled.

25. The method according to claim 24, further comprising: The first spiral coil, the second spiral coil, and the third spiral coil are connected in series for electrical coupling.

26. The method according to claim 24 further includes: The first spiral coil, the second spiral coil, and the third spiral coil are electrically coupled in parallel.

27. The method according to claim 16, wherein the first helical coil is magnetically coupled to the second helical coil in a transformer configuration.

28. The method according to claim 16, wherein the substrate includes at least one of an active element, a passive element, or a metal wiring located below the first helical coil.

29. The method of claim 16, wherein the first spiral coil is formed in a back-end process (BEOL) stack.

30. The method according to claim 16, wherein the spiral inductor is integrated into a device, and wherein the device is selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptops, servers, and devices in autonomous vehicles.

Images