Self-aligned lateral contacts

Abstract

A technique for forming automatically aligned lateral contacts. In an example, a first trench contact contacts the source or drain region of a transistor. A second trench contact comprises discontinuous first and second portions, each portion having a top surface coplanar with the top surface of the first trench contact and the top surface of the gate structure. The sidewalls of the second trench contact are automatically aligned to and interface with the sidewalls of the first trench contact. A through-hole extends from the first portion of the second trench contact to the underlying power rail. In some cases, the second portion of the second trench contact extends over the source or drain region of another transistor without contacting that source or drain region. This overhanging portion of the second trench contact has a maximum height lower than the maximum height of the first trench contact.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit, and more specifically, to an automatically aligned lateral contact. Prior Technology

[0002] As integrated circuit dimensions continue to shrink, numerous challenges arise. For example, reducing the size of memory and logic cells becomes increasingly difficult. One possible solution for further scaling cell size involves buried or back-side power rail technology, or more generally, back-behind PCB (BPR) technology. In some cases, BPR technology involves burying conductors (sometimes called power rails) that carry power to the cell beneath a back-end process (BEOL) metal layer, typically at the same level as the device layer containing semiconductor fins. In other cases, BPR technology involves forming such power rails on the back side of the substrate beneath the device layer. Such BPR configurations leave space above to allow for more logic connections and further scaling of standard logic cells (e.g., memory and logic cells). BPR configurations also allow for relatively large power rails (e.g., thicker ones), which in turn exhibit lower resistance and power consumption. However, several significant challenges remain with BPR configurations. Summary of the Invention

[0003] and Simple Explanation of the Diagram

[0004] [Figures 1a to 1b] are cross-sectional views illustrating an example integrated circuit configured with automatically aligned lateral contacts, according to an embodiment of this disclosure.

[0005] [Figures 2 to 19b] together illustrate a cross-sectional or perspective view of an example process for forming an integrated circuit configured with automatically aligned lateral contacts, according to an embodiment of this disclosure. Implementation

[0006] This article provides techniques for forming automatically aligned lateral contacts. While these techniques can be used in any number of integrated circuit applications, they are particularly useful for contact schemes in logic and memory cells, such as those using FinFETs, all-around gate transistors, or other transistor technologies, where contacts are required from a given cell to the underlying conductive element (e.g., BPR). In the example, a first trench contact is located on the source or drain region of the transistor. A second trench contact comprises discontinuous first and second portions, each having a top surface coplanar with the top surface of the first trench contact and the top surface of the gate structure. One or both of the first and second portions of the second trench contact have a maximum height lower than the maximum height of the first trench contact. The sidewalls of the first portion of the second trench contact are automatically aligned to and interface with the sidewalls of the first trench contact to provide an electrical path (lateral contact) between the first and second trench contacts. Furthermore, a via extends from the first portion of the second trench contact to the underlying power rail or other conductor. Note that the via is automatically aligned to the first and second trench contacts. In some cases, a second portion of the second trench contact extends above the source or drain region of another transistor without contacting it. In this case, the fly-through portion of the second trench contact has a maximum height that is shorter than the maximum height of the first trench contact. Many variations and implementations will be apparent from this disclosure. General Overview

[0007] As mentioned above, several significant challenges remain in BPR configuration. More specifically, scaling of the standard cell can be achieved by forming power rails on lower layers, such as embedded or back-side power rails. This BPR configuration utilizes additional contact layers to achieve greater connectivity, such as contacts for the source or drain regions and the power rails, to allow power to be supplied from the power rails to the source or drain regions. This additional contact layer results in higher stacking, for example, a first contact layer contacting the source / drain region, and a second contact layer above the first contact layer contacting the underlying BPR. Furthermore, overlap errors limit the size of these additional layers, thereby reducing electrical performance (e.g., smaller conductors tend to have higher resistance).

[0008] Therefore, and according to embodiments of this disclosure, this document provides a technique for forming automatically aligned lateral contacts. The contacts are lateral because they are adjacent to each other in the same plane, rather than configured in a stacked configuration with one contact above another. In an example, a first trench contact is automatically aligned to the gate structure of a transistor and contacts the source or drain region of the transistor. A second trench contact is also automatically aligned to the gate structure and comprises discontinuous first and second portions, each portion having a top surface coplanar with the top surface of the first trench contact and a gate structure on the top surface. One or both of the first and second portions of the second trench contact have a maximum height lower than the maximum height of the first trench contact. The sidewall of the first portion of the second trench contact is automatically aligned to the sidewall of the first trench contact and interfaces with or otherwise contacts the sidewall of the first trench contact. For this purpose, the first portion of the second trench contact is electrically connected (short-circuited) to the first trench contact to provide a lateral contact and a conductive path. Furthermore, a through-hole extends from the first portion of the second trench contact to connect to the underlying power rail. For example, the power rail can be an embedded power rail or a back-side power rail. Note that the through-hole is automatically aligned to the first and second trench contacts. In some cases, the second portion of the second trench contact extends above the source or drain region of another transistor without contacting that source or drain region. In this example case, the second portion of the second trench contact has a maximum height that is shorter than the maximum height of the first trench contact.

[0009] Note that the first and second trench contacts may contain the same or different conductive materials. Exemplary conductive materials include, for example, ruthenium, tungsten, molybdenum, cobalt, and alloys thereof. Further note that one or both of the first and second trench contacts may contain conductive pads. Example pad materials include, for example, titanium silicate, titanium nitride, tungsten carbonitride (WCN), physical vapor deposition (PVD), or atomic layer deposition (ALD) tungsten and tantalum nitride. Any number of other conductive and pad materials may be used, and this disclosure is not intended to limit to any particular material. In any such case, a detectable interface will exist between the first and second trench contacts. For example, in an example where the first and second trench contacts are the same conductive material (e.g., ruthenium) and neither has a pad, a detectable grain boundary or set of grain boundaries will exist between the two separately deposited conductive materials. In another example, where the first and / or second trench contacts include a thin liner (e.g., 2 to 10 angstroms of titanium nitride or titanium silicon, or both), the liner material (or a combination thereof) will be detectable between the two trench contacts. The height difference between the first and second trench contacts may also vary from one embodiment to the next, but in some cases it is in the range of approximately 4 to 15 nanometers (nm), for example, approximately 8 to 11 nm.

[0010] This technology can be used for any type of planar and non-planar transistor, including fin field-effect transistors (sometimes called dual-gate or triple-gate transistors), nanowire and nanocharged transistors (sometimes called all-around gate transistors), and thin-film transistors, to name just a few. For example, the source and drain regions can be doped portions of a given fin or substrate, or epitaxial regions deposited during etching and replacement of the source / drain formation process. The type of dopant in the source and drain regions will depend on the polarity of the corresponding transistor. Gate structures can be implemented using a gate-before process or a gate-after process (sometimes called metal-gate removal or RMG process). Any number of semiconductor materials can be used to form transistors powered by buried or back-side power rails, such as group IV materials (e.g., silicon, germanium, silicon-germanium) or group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

[0011] Based on this disclosure, many benefits of this automatically aligned, laterally multi-level contact will be understood. For example, the automatic alignment scheme allows for maximum critical dimensions of each of the first trench contact, the second trench contact, and the via to reduce the electrical resistance attributable to these features. According to one embodiment, a cross-section parallel to the gate structure and centered on the source or drain region will show a multi-height contact scheme with full-height trench contacts and partially high trench contacts or other less high trench contacts. In some such cases, a portion of the shorter trench contact may also fly over uncontacted source or drain regions. Furthermore, according to one embodiment, the interface between laterally adjacent high and low contacts will be detectable (e.g., via cross-sectional imaging using a scanning electron microscope or SEM, a transmission electron microscope or TEM, or other suitable inspection tools). Architecture

[0012] Figure 1a is a cross-sectional view illustrating an example integrated circuit configured with automatically aligned lateral contacts, according to an embodiment disclosed herein. This cross-section is taken through the source or drain regions of an adjacent transistor and is parallel to the gate structure (not visible in this cross-section because it lies behind the depicted portion of the integrated circuit). The transistor in this example is a non-planar metal-oxide-semiconductor (MOS) transistor, such as a tri-gate or all-around gate transistor, although other transistor topologies and types may also benefit from the techniques provided herein, as will be understood (e.g., planar transistors, thin-film transistors, or any other transistors that can establish contacts).

[0013] As can be seen, the integrated circuit includes a substrate with first and second fins extending therefrom. Any number of fins can be included, but two are used here as an example. It can also be seen that the first and second fins are separated by dielectric filling, each fin having a source or drain region deposited or otherwise formed thereon. A first trench contact is on the left source or drain region and includes first and second sidewalls extending between the top and bottom surfaces of the first trench contact. A second trench contact includes first and second portions discontinuous from the sides of the first trench contact, each portion having a top surface coplanar with the top surface of the first trench contact and the top surface of the gate structure. The right sidewall of the first (left) portion of the second trench contact contacts the left sidewall of the first trench contact, thereby providing an interface therebetween. Similarly, in this example, the left sidewall of the second (right) portion of the second trench contact contacts the right sidewall of the first trench contact, thereby providing an interface therebetween. It can be further seen that a via extends from the first portion of the second trench contact to the underlying conductor, which in this example is a buried power rail (BPR).

[0014] Note the height difference (ΔH) between the first and second trench contacts. In some such examples, ΔH is in the range of 4 to 15 nm (e.g., 8 to 11 nm). Further note how the second portion of the second trench contact extends above the right source or drain region without contacting it. This is referred to herein as the fly-through portion. Further note that the right sidewall of the second portion of the second trench contact contacts an insulating material having a top surface coplanar with the top surfaces of the first trench contact, the second trench contact, and the gate structure. Further note that the insulating material has a maximum height extending from its top surface to its bottom surface, which is shorter than the maximum height of the first trench contact. In some examples, the maximum height of the insulating material is equal to or greater than the maximum height of the second trench contact and less than the maximum height of the first trench contact. For example, in such an example case, the maximum height of the first trench contact is approximately 22 to 26 nm, the maximum height of the second trench contact is approximately 11 to 15 nm, and the maximum height of the insulating material is approximately 14 to 18 nm. Here, ΔH is in the range of approximately 7 to 15 nm.

[0015] Each of the first and second trench contacts can contain any amount of conductive material, some examples of which include ruthenium, tungsten, cobalt, molybdenum, and their alloys. In some cases, the first and second trench contacts can contain relatively thin pads or barriers, such as titanium nitride, titanium silicon, tungsten carbonitride (WCN), PVD or ALD tungsten, or tantalum nitride. The pads or barriers can be, for example, 2 to 10 angstroms (e.g., 5 angstroms) thick. Other embodiments can include multilayer trench contacts with or without pads or barriers, such as a first layer of ruthenium on the source or drain region and a second layer of cobalt on the ruthenium layer. Any number of trench contact configurations can be used. The interface between the first and second trench contacts can vary depending on the configuration of the first and second trench contacts. For example, in an example where both the first and second trench contacts contain the same material (e.g., ruthenium, without pads or barriers), the interface therebetween can contain detectable grain boundaries or a set of grain boundaries or seams. In another example where the first and / or second trench contacts include a pad, the interface therebetween may contain detectable pad material (or multiple types). For example, such grain boundaries or a group of grain boundaries, seams, or pad materials can be detected by cross-sectional TEM imaging.

[0016] The via can be made of the same material as the first and / or second trench contacts, and similarly may or may not include gaskets or barriers. In one example embodiment, the via and the second trench contact are formed by the same deposition process, such that the first portion of the second trench contact and the via are a monolithic structure and there is virtually no discernible seam or interface between the first portion of the second trench contact and the via. However, note that the first portion of the second trench contact will still have a identifiable height, excluding the height of the via. In this sense, even though the second trench contact and the via are a monolithic conductive structure, the portion of this structure belonging to the first portion of the second trench contact can still be considered to have the same maximum height as the second portion of the second trench contact, excluding the height of the via.

[0017] The backplate (BPR) can be made of the same material as the via, the first trench contact, and / or the second trench contact, and similarly may or may not include gaskets or barriers. In one example embodiment, the BPR includes an insulating barrier or spacer to prevent the BPR from contacting any adjacent fin. In some such embodiments, oxide or nitride spacers, such as silicon dioxide or silicon nitride, are used. For a given application, the insulating spacer can be relatively thin, for example, 2 to 6 nm, or thinner, as long as it electrically isolates the BPR from adjacent fins. In other example embodiments, the BPR can be an accessible back-side power rail on the other (bottom) side of the substrate.

[0018] For example, the substrate can be a bulk substrate comprising a group IV semiconductor material (e.g., silicon, germanium, or silicon-germanium), a group III-V semiconductor material (e.g., gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors can be formed. Alternatively, the substrate can be a semiconductor-on-insulator substrate having a desired semiconductor layer (e.g., silicon over silicon dioxide) on a buried insulator layer. Alternatively, the substrate can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates can be used.

[0019] Any number of fins can be included, but two are used here as an example. For example, the fins can be of the substrate itself (formed by the substrate itself), such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins can be formed by material deposited onto the underlying substrate. In one such example, a silicon germanium (SiGe) overlay can be deposited onto the silicon substrate, then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, non-native fins can be formed in a so-called high aspect ratio trapping process, where native fins are etched away to leave fin-shaped trenches, which can then be filled with alternative semiconductor materials (e.g., group IV or group III-V materials). In yet another embodiment, the fins comprise alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires and nanoribbons during the gate formation process, where one type of alternating layer is selectively etched to free another type of alternating layer within the channel region so that a full-around gate process can be performed. Similarly, alternating layers can be deposited over a substrate and then etched into fins, or deposited into fin trenches. Other implementations can use a planar transistor architecture, eliminating the need for fins, nanowires, or stripes.

[0020] As can be further seen in this example, the source or drain region is an epitaxial source or drain region disposed on the fin during the etching and replacement process. In other embodiments, one or both of the source or drain regions may be, for example, native portions of the implanted doped fin or substrate. Any semiconductor material suitable for the source and drain regions (e.g., group IV and group III-V semiconductor materials) can be used. The source and drain regions may comprise multiple layers, such as pads and capping layers, to improve contact resistance. In any such case, the composition and doping of the source or drain regions may be the same or different, depending on the transistor polarity. For example, in one example, one transistor is a p-type MOS (PMOS) transistor, while the other transistor is an n-type MOS (NMOS) transistor. Any number of source and drain configurations and materials can be used.

[0021] The dielectric can be any suitable dielectric material, such as silicon dioxide or aluminum oxide. Similarly, the insulating filler can be any number of suitable insulating materials, such as silicon nitride or silicon oxynitride, or silicon oxynitride. As will be explained below, the insulating filler and dielectric materials can be selected to provide the desired etch selectivity (relative to other materials also exposed to the etchant used during a given removal process).

[0022] Figure 1b illustrates an integrated circuit similar to that shown in Figure 1a, but with various features depicted to reflect real-world manufacturing conditions. For example, while Figure 1a generally uses straight lines, right angles, and smooth surfaces to indicate various features, the actual integrated circuit structure configured according to the embodiments of this disclosure may have imperfect straight lines and right angles, and some features may have surface topography or roughness due to realistic manufacturing process limitations such as etching and deposition. As can be seen from Figure 1b, the top, bottom, and side surfaces are somewhat wavy or irregular rather than perfectly flat; similarly, fins and vias are tapered rather than rectangular, and source or drain regions are more like spots rather than perfectly faceted surfaces. Other such real-world features or defects may also be present, and this disclosure is not intended to limit to any particular shape or degree of perfection. As will be further understood, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configuration shown. Manufacturing method

[0023] Figures 2 through 19b collectively illustrate cross-sectional or perspective views of an example process for forming an integrated circuit configured with automatically aligned lateral contacts, according to an embodiment of this disclosure. Each figure shows an example structure produced by the process flow up to that point in time, and thus the depicted structure evolves as the process flow continues, ultimately forming the structure shown in Figures 19a through 19b. Such a structure may be part of an overall integrated circuit (e.g., a processor or memory chip) containing, for example, digital logic cells and / or memory cells, as well as analog mixed-signal circuitry. Therefore, the illustrated integrated circuit structure may be part of a larger integrated circuit that includes other integrated circuitry not depicted. Example materials and process parameters are given, but as will be understood, this disclosure is not intended to be limited to any particular such materials or parameters.

[0024] Figure 2 is a cross-sectional view through and perpendicular to a set of semiconductor fins extending from substrate 101, according to an embodiment of this disclosure. Previous discussions regarding the exemplary configurations and materials of substrate 101, fins, and dielectric 103 also apply here. Thus, the fins can be inherent to the substrate, non-substrate-inherent, or multilayer fins suitable for forming nanowires or nanoribbons. Similarly, the fins can, for example, alternate polarities relative to the transistor. For example, the two upper fins on the left can comprise PMOS material fins (e.g., SiGe fins) and NMOS material fins (e.g., silicon fins) for a first logic or memory cell, and the two upper fins on the right can comprise PMOS material fins and NMOS material fins for a second logic or memory cell. Many other configurations can be used, including fins contained within integrated circuit portions other than memory or logic portions, such as analog mixed-signal portions, input / output portions, RF or transducer portions. Further recall, the transistor can be a planar transistor, rather than a non-planar transistor.

[0025] In this example scenario, a protective layer or cap 105 remains on top of each fin to provide a degree of protection for the fin during subsequent processing. If the dielectric 103 is an oxide (e.g., silicon dioxide), the cap 105 can be, for example, a nitride, oxynitride, carbide, or carbonitride to provide etch selectivity relative to the dielectric 103. As can be further seen, a lithography mask 107 is patterned to provide openings for the trenches to be etched, for the location of the deposited embedded power rails. The lithography mask 107 can be any suitable mask, such as photoresist or one or more layers (e.g., a carbon hard mask or an antireflective coating or silicon oxynitride), which provide the desired etch selectivity to allow trench formation. Note how the mask 107 does not need to be perfectly aligned with the edge of the cap 105, given the similar etch selectivity of 105 and 107 relative to the trench etching scheme.

[0026] The trench can be etched at the location where the deposited embedded power rail will be deposited using any number of wet and / or dry etching techniques. In this example case, the etching scheme includes selective wet etching of the cap 105 and the mask 107 to remove any fins (e.g., silicon) and dielectric 103 (e.g., silicon dioxide) exposed by openings in the mask 107, or only removing the dielectric 103 where selected fins (or more) were removed in an earlier operation. Once the bottom of the substrate 101 is reached, the example etching scheme includes reactive ion etching (RIE) to etch the remaining portion of the trench within the substrate 101. While the dimensions can vary from one example embodiment to the next, in one example case, the total height from the bottom of substrate 101 to the top of cap 105 can be 250 nm or greater, the portion etched by RIE is in the range of 50 nm to 100 nm, and the fins above it have a height in the range of 50 to 200 nm (e.g., 60 to 130 nm), and cap 105 has a height in the range of 5 to 25 nm. The width of the fins can, for example, be in the range of 5 to 200 nm. For example, the pitch between adjacent fins can be in the range of 25 to 600 nm. In some such example embodiments, the aspect ratio of the fins is in the range of approximately 1:5 to 1:20, for example, in a particular example where the fins are approximately 25 nm wide at their midpoint and approximately 200 nm high, to provide an aspect ratio of 1:8.

[0027] Figure 3 is a cross-sectional view of the structure depicted in Figure 2 after the removal of mask 107 and the formation of spacer 109 and the deposition of BPR 111, according to an embodiment of this disclosure. Mask 107 can be removed by any suitable method, such as selective wet chemical etching. Once the structure is free of mask 107, spacer 109 can be formed. In one example case, spacer 109 is conformally deposited over the entire structure using atomic layer deposition (ALD) or chemical vapor deposition (CVD). Excess spacer 109 material in horizontal locations is then removed using selective directional etching of dielectric 103 and cap 105 in some embodiments, but this is not mandatory. The resulting spacer can have a thickness in the range of, for example, 0.05 to 5 nm. In a more general sense, spacer 109 can have any thickness suitable for insulating the BPR 111 material from multiple adjacent fins contacting the sidewalls defining the trench. In some example embodiments, spacer 109 can be implemented using, for example, oxides, nitrides, or carbides, such as silicon oxide or silicon nitride. In one such embodiment, where dielectric 103 is an oxide and cap 105 is silicon nitride, spacer 109 is implemented with dense silicon oxide to provide a degree of etch selectivity relative to dielectric 103 and cap 105. Once spacer 109 is formed, BPR 111 material can be deposited by, for example, electroplating, CVD, or ALD (for selective bottom-up deposition). BPR 111 can be any number of conductive materials, such as tungsten, molybdenum, ruthenium, cobalt, copper, aluminum, silver, or alloys thereof. Figure 4 is a cross-sectional view of the structure depicted in Figure 3 after removing excess BPR 111 material (e.g., by planarization / polishing techniques such as CMP), according to one embodiment. Further note that BPR 111 can extend parallel to the fins at any desired distance.

[0028] Figure 5 is a cross-sectional view of the structure depicted in Figure 4 after the BPR 111 material recess, according to one embodiment. In some examples, the recess is achieved using a selective isotropic metal etching process on the dielectric 103, cap 105, and spacer 109. The depth of the recess will depend on the desired height of the BPR, but in some examples it is in the range of 20 to 150 nm (e.g., 50 to 80 nm). The height of the BPR can also vary, but in some examples it is in the range of approximately 20 to 500 nm (e.g., 30 to 90 nm).

[0029] Figure 6 is a cross-sectional view of the structure depicted in Figure 5 after the trenches have been refilled with dielectric material and a CMP process has been performed to remove excess dielectric material and cover 105 to expose the top of the fin, followed by dielectric recesses to expose the top portion (channel region) of the fin, according to one embodiment. In some example cases, the trenches are refilled with a deposition containing dielectric material 104 (which may be the same as dielectric material 103, such as silicon dioxide). Excess dielectric material 104 can then be removed using a CMP process to expose the top of the fin. The exposed semiconductor fin material (or multiple materials) is then selectively recessed, depending on the depth of the recess, to recess dielectric material 104 and possibly dielectric material 103. Note that in this example, spacer 109 is also recessed in this process. In some such cases, the fin is silicon, and dielectric materials 103 and 104, along with spacer 109, are oxides (e.g., silicon dioxide) to allow for single etch selectivity with respect to silicon fins. In some example cases, the remaining thickness of the dielectric 104 held above the BPR 111 is in the range of approximately 5 to 25 nm (e.g., 15 nm).

[0030] Figure 7a is a cross-sectional view of the structure depicted in Figure 6 after the dummy gate structure 113 and gate cap 115 have been formed, according to an embodiment. It can be seen that the cross-section is parallel to and passes through the dummy gate structure 113 and perpendicular to the fin. The dummy gate structure 113 can be any standard or proprietary gate structure. According to one embodiment, the dummy gate structure 113 is formed by depositing a full-surface dummy gate material (or multiple types), followed by masking and etching to remove excess gate material (or multiple types), such that the dummy gate structure 113 retains only the channel region spanning the fin. The configuration of the dummy gate structure 113 can vary from one embodiment to the next, but in some embodiments it includes amorphous silicon, and in other embodiments (such as those best shown in Figures 7b to 7c) it includes a dummy gate electrode 113a (e.g., polycrystalline silicon), a dummy gate dielectric 113b (e.g., an oxide of fin material, such as silicon dioxide in the case of silicon fins), and a gate spacer 113c (e.g., silicon carbonitride, or other materials that are etch-selective relative to other dummy gate materials or multiple materials). Once the dummy gate structure 113 is formed, a dielectric 116 is deposited (e.g., CVD) using a CMP process and planarized down to a gate cap 115, as best shown in Figure 7c. The gate cap 115 protects the dummy gate structure during subsequent source and drain processes and can be any number of materials, such as silicon nitride. As will be understood, the dimensions of the dummy gate structure 113 can vary from one embodiment to the next. In some example cases, the distance from the top of a given fin to the top of the dummy gate structure 113 is in the range of 50 to 100 nm (e.g., 75 nm), and the distance from the top of a given fin to the bottom of the dummy gate structure 113 is in the range of 25 to 100 nm (e.g., 35 to 75 nm). The width of the dummy gate structure 113 will also vary depending on factors such as the desired channel length and / or fin thickness (for non-planar transistors), but in some cases is in the range of 20 to 100 nm. The thickness of the gate cap 115 can, for example, be in the range of 20 to 100 nm (e.g., 30 to 75 nm). If present, the dummy gate dielectric 113b can have, for example, one or more monolayers in thickness in the range of 10 nm. The gate spacer 113c, when present, can be conformally deposited and have any desired thickness, for example, in the range of 5 to 40 nm. As will be explained below, the gate spacer 113c can be conformally deposited in a blanket manner so as to also cover the exposed sidewalls of the fin portions that will form the source and drain regions, and thus can be used as a guide in the subsequent epitaxial source and drain formation process.

[0031] Figure 8a is a cross-sectional view of the structure depicted in Figures 7a to 7c after the epitaxial source or drain regions 117 and 119 have been formed, according to an embodiment. It can be seen that the cross-section is parallel to the dummy gate structure 113 and passes through the source or drain region. Note that the dielectric material above the fins in the source or drain region is not shown in Figure 8a, so the dummy gate structure 113 can be seen in the background of the cross-section. The source or drain regions 117 and 119 can be formed using any standard or proprietary source / drain processing method. In this example case, the source or drain regions 117 and 119 are formed by an etching and replacement process, in which the original fin material is etched away and replaced by epitaxial deposition of the desired source / drain material. As can be seen from the right side of the structure, during the epitaxial growth of source or drain regions 117 and 119, gate spacer 113c can be used as a guide, which confines source or drain regions 117 and 119 (note that the facets on the right-side source or drain regions 117 and 119 are less pronounced compared to the left-side source or drain regions 117 and 119). In some example embodiments, source or drain region 117 is an NMOS source or drain region (e.g., epitaxial silicon), and source or drain region 119 is a PMOS source or drain region (e.g., epitaxial SiGe) to provide complementary MOS (CMOS) logic or memory cells. In this case, note that the source / drain formation process can be bifurcated, first forming one of the PMOS or NMOS source / drain regions while the other regions are masked, and then forming the other of the PMOS or NMOS source / drain regions while the first formed region is masked. Figure 8b shows the same structure as in Figure 8a, but dielectric 120 is located above source or drain regions 117 and 119, so the dummy gate structure 113 is now hidden. For example, dielectric 120 may be the same dielectric material (e.g., silicon dioxide) used for dielectrics 103 and 104, but it is not required.

[0032] Figure 9a is a cross-sectional view of the structure depicted in Figures 8a-c after the final gate structure 121 and gate cap 123 have been formed, according to an embodiment. It can be seen that the cross-section is parallel to and passes through the final gate structure 121 and is perpendicular to the fin. The final gate structure 121 can be any standard or proprietary gate structure and can contain any number of gate cutouts. According to an embodiment, the final gate structure 121 is formed by a masking, etching, and deposition process (sometimes referred to as a post-gate or removed metal gate (RMG) process), which includes removing the gate cap 115 and the underlying dummy gate structure 113, except for the gate spacer 113c, followed by any desired channel treatment (e.g., channel shaping, encapsulation, or release of nanowires or strips) on the exposed channel region, then deposition of the gate dielectric 121b, and then deposition of the gate electrode 121a, as best shown in Figures 9b-c. In this case, the gate structure can be, for example, a dual-gate, triple-gate, or all-around gate. The second example channel region from the left in Figure 9a contains three released nanoribbons, each with a fully encircling gate configuration. The other three example channel regions are fins, each with a three-gate configuration. Once the final gate structure 121 is formed and planarized, it is recessed, a gate cap 123 is deposited (e.g., CVD), and the structure is planarized to dielectric 120 via a CMP process, as best shown in Figure 9c. The gate cap 123 protects the final gate structure during subsequent processing and can be any number of materials, such as silicon nitride. As will be understood, the dimensions of the final gate structure 121 can vary from one embodiment to the next. In some examples, the distance d1 from the top of a given fin (or top nanowire or strip) to the top of the final gate structure 121 ranges from 5 to 30 nm (e.g., 10 to 20 nm), and the distance d2 from the top of a given fin (or top nanowire or strip) to the bottom of the final gate structure 121 ranges from 25 to 100 nm (e.g., 40 to 55 nm, or 48 nm). The width of the final gate structure 121 between the gate spacers 113c will also vary depending on factors such as the desired channel length and / or fin thickness (for non-planar transistors), but in some cases is in the range of 5 to 35 nm (e.g., 8 to 15 nm, or 12 nm). The thickness of the gate cap 123 can, for example, range from 1 to 25 nm (e.g., 7 to 25 nm, or 16 nm). The thickness of the gate dielectric 121b can, for example, range from one or more monolayers to 10 nm. Gate spacer 113c, when present, can be conformally deposited and have any desired thickness, for example in the range of 5 to 40 nm (e.g., 5 to 15 nm).

[0033] Gate dielectric 121b may comprise any suitable dielectric (e.g., silicon dioxide and / or high-k dielectric materials). Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. In some embodiments, gate dielectric 121b may comprise one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some embodiments, an annealing process may be performed on gate dielectric 121b to improve its quality when using high-k dielectric materials. Gate electrode 121a may comprise a wide range of materials, such as various suitable metals or metal alloys, such as aluminum, tungsten, titanium, tantalum, copper, and their carbides and nitrides. In some embodiments, for example, the gate dielectric 121b and / or the gate electrode 121a may comprise a multilayer structure of two or more material layers. For example, in one embodiment, the gate dielectric comprises a first layer of silicon dioxide over the channel region and a second layer of hafnium oxide over the first layer. The gate electrode 121a may comprise, for example, a metal plug and one or more work function layers, resistance reduction layers, and / or barrier layers. In some embodiments, the gate dielectric 121b and / or the gate electrode 121a may comprise graded (e.g., increasing and / or decreasing) content / concentration of one or more materials in at least a portion of the features (or multiple features). Note that although the gate dielectric 121b is shown only below the gate electrode 121a in FIG. 9b, the gate dielectric 121b may also be present on one or both sides of the gate electrode 121a, such that the gate dielectric 121b is U-shaped (cross-shaped) and between the gate electrode 121a and the gate spacer 113c, as shown in FIG. 9c. Many gate configurations will be readily apparent in this disclosure.

[0034] Figure 10 is a cross-sectional view of the structure depicted in Figures 9a to 9c after mask 125 has been patterned and contact trenches have been etched over one or more of the source or drain regions 117 and 119, according to one embodiment. It can be seen that the cross-section is parallel to the final gate structure 121 but extends through the source or drain region. Mask 125 can be any suitable mask, such as photoresist or one or more layers (e.g., a carbon hard mask). Note that, according to the embodiment, mask 125 can be open above the gate structure 121 because the etching of the nitride-based material of the gate cap 123 and the gate spacer 113c is selective, thus only the oxide of the dielectric 120 is etched. In this sense, the contact trenches are automatically aligned to the gate structure 121. Any wet or dry etching scheme that is selective to the gate cap 123 and the gate spacer 113c and capable of removing the dielectric 120 can be used. In this example case, note that the leftmost source or drain region 117 is masked and therefore not contacted.

[0035] Figure 11 is a cross-sectional view of the structure depicted in Figure 10 after the trench contacts 127, 129, and 131 have been filled and planarized, according to one embodiment. In some embodiments, a selective liner deposition (e.g., titanium siliconide, titanium nitride, or tantalum nitride) is first provided, followed by a metallic filler (e.g., tungsten, molybdenum, cobalt, ruthenium, or alloys thereof). For example, a titanium siliconide liner may be deposited first on the exposed source / drain regions 117 and 119, followed by the deposition of ruthenium or a ruthenium alloy to fill the contact trenches. As will be understood, any suitable deposition technique, such as CVD or ALD, can be used. For example, planarization can be accomplished using CMP overpolishing and RIE removal.

[0036] Figure 12 is a cross-sectional view of the structure depicted in Figure 11 after mask 129 has been patterned and insulator trenches have been etched at different locations, according to an embodiment. It can be seen that the cross-section is parallel to the final gate structure 121 but extends through the source or drain region. Mask 129 can be any suitable mask, such as photoresist or one or more layers (e.g., a carbon hard mask). Note that, according to one embodiment, like mask 125, mask 129 can have an opening above the gate structure 121 because the etching of the nitride-based material of the gate cap 123 and the gate spacer 113c is selective, thus only the oxide of dielectric 120 is etched. In this sense, the insulator trenches are automatically aligned to the gate structure 121. The etching of the metal of the trench contacts 127, 129, and 131 is also selective. In this sense, the insulator trenches are automatically aligned to the trench contacts. Similarly, any wet or dry etching scheme that selectively removes the dielectric 120 from the gate cap 123 and the gate spacer 113c can be used. As will be understood from this disclosure, these insulating trenches will provide electrical isolation between the first and second trench contacts that are not electrically coupled.

[0037] Figure 13a is a cross-sectional view of the structure depicted in Figure 12 after the insulator filler 133 has been deposited and planarized, according to an embodiment. In some embodiments, an insulator deposit (e.g., silicon carbonitride, oxynitride, boron-doped nitride) is used to fill the insulator trench. For example, silicon carbonitride deposition is used to fill the insulator trench. As will be understood, any suitable deposition technique, such as CVD or ALD, can be used. For example, planarization can be accomplished using CMP. Figure 13b shows a cross-section through the gate structure and channel region and parallel to the fin. Note how the trench contacts 127 and 128 are automatically aligned to the gate structure. The underlying source and drain regions are not shown but will be below the contact trenches and adjacent to the channel region, as will be understood. Further note in this example that the channel region has been stripped and has a full-around gate configuration.

[0038] Figure 14a is a cross-sectional view of the structure depicted in Figure 13a after the insulator filler 133 has been recessed, according to an embodiment. In some embodiments, selective isotropic recess etching of the dielectric 120 (e.g., oxide, such as silicon dioxide) and trench contacts 127 to 131 (e.g., metal, such as ruthenium) is used to selectively recess the insulator trench 133 (e.g., carbonitride, such as silicon carbide). Figure 14b shows a cross-section through the gate structure and channel region and parallel to the fin. Note how the gate cap 123 (e.g., nitride, such as silicon nitride) and gate spacer 113c (e.g., carbonitride, such as silicon carbide) and the insulator filler 133 are also recessed. Further note that the depth of the recess is distance d3, which in some embodiments can be in the range of 10 to 15 nm (e.g., 12 nm).

[0039] Figure 15a is a cross-sectional view of the structure depicted in Figure 14a after the sacrificial insulator filler 135 has been deposited and planarized, according to an embodiment. In some embodiments, an insulator deposit (e.g., titanium oxide) is used to fill the recessed insulator trenches. For example, titanium oxide deposition is used to fill the recessed insulator trenches. As will be understood, any suitable deposition technique, such as CVD or ALD, can be used. For example, planarization can be accomplished using CMP. Figure 15b shows a cross-section through the gate structure and channel region and parallel to the fin. Note how the sacrificial insulator filler 135 is deposited and planarized over the gate structure and between the corresponding trench contacts of the transistor. Further note that the height of the sacrificial insulator filler 135 is distance d4, which in some embodiments can be in the range of 8 to 13 nm (e.g., 10 nm). According to one embodiment, the difference between distances d3 (e.g., 12 nm) and d4 (e.g., 10 nm) is due to height loss caused by CMP. The gate cap 123 may lose some thickness due to various CMP processes, but in some embodiments, its thickness (d5) is in the range of 4 to 8 nm (e.g., 5 nm). As can be further seen, the distance d6 from the top of the gate structure 121 to the top of the channel region (in this example, the nanoband) can be in the range of, for example, 10 to 30 nm (e.g., 20 nm) in some embodiments. These distances d4, d5, and d6 provide some CMP budget for subsequent processing, such as when the structure is planarized to expose the top of the gate structure 121, as will be discussed sequentially with reference to Figures 19a to 19b. For example, and briefly referring to Figure 19b, it is assumed that in this example, the distance d8 from the top of the gate structure 121 to the top of the channel region is 15 nm. Now, returning to Figure 15b, for this example, it is further assumed that the distance d4 is 10 nm, the distance d5 is 5 nm, and the distance d6 is 20 nm. This example provides a 20 nm CMP budget (in other words, when the structure in Figures 19a to 19b is formed, the total distance from the top of the structure to the top of the channel region, as shown in Figures 15a to 15b, will be reduced by 20 nm).

[0040] Figure 16 is a cross-sectional view of the structure depicted in Figure 15a after the dielectric 120 has been recessed, according to one embodiment. It can be seen that the cross-section is parallel to the final gate structure 121 but extends through the source or drain region. Note that the etching is selective for the gate cap 123 (e.g., titanium nitride) and gate spacer 113c (e.g., silicon carbonitride), as well as the sacrificial insulator filler 135 (e.g., titanium oxide) and trench contacts 127-131 (e.g., ruthenium), and therefore only the dielectric 120 (e.g., silicon oxide) is etched, according to one embodiment. In this sense, these second contact trenches are automatically aligned to the gate structure 121 and the trench contacts 127-131 and sacrificial insulator filler 135. Any wet or dry etching scheme selective in this manner can be used. Note further that the depth of the recess results in a distance d7 from the top of the source or drain regions 117 and 119 to the top of the recessed dielectric 120 that is in the range of 5 to 15 nm (e.g., 10 nm). As will be understood from this disclosure, this distance effectively determines the height of the second trench contact to be formed.

[0041] Figure 17 is a cross-sectional view of the structure depicted in Figure 16 after patterning mask 137 and etching via trenches over BPR 111, according to one embodiment. It can be seen that the cross-section is parallel to the final gate structure 121 but extends through the source or drain region. Mask 137 can be any suitable mask, such as photoresist or one or more layers (e.g., a carbon hard mask). Note that mask 137 can be open over the gate structure 121 because etching is selective for the gate cap 123 (e.g., silicon nitride) and gate spacer 113c (e.g., carbon oxide silicon oxide), as well as the exposed trench contacts 129 (e.g., ruthenium) and exposed sacrificial insulator filler 135 (e.g., oxides more etch-resistant than dielectrics 120 and 104, such as titanium oxide, nitrides or oxides), thus only dielectrics 120 and 104 (e.g., oxides, such as silicon dioxide) are etched, according to one embodiment. In this sense, the through-hole trench is automatically aligned with the gate structure 121 and the formed contacts. According to some embodiments, any anisotropic etching scheme selectively used in this manner can be employed.

[0042] Figure 18 is a cross-sectional view of the structure depicted in Figure 17 after the mask 137 has been removed and the conductive material 139 has been deposited into the second contact trench and the via trench, according to an embodiment. In some embodiments, a thin pad deposit (e.g., 4 to 10 angstroms of titanium, titanium silicon, titanium nitride, or tantalum nitride) is first provided, followed by a metal filler (e.g., tungsten, molybdenum, cobalt, ruthenium, or alloys thereof). For example, a titanium nitride pad with a thickness of about 5 angstroms can be deposited over the entire surface first, followed by the deposition of ruthenium or a ruthenium alloy to fill the via trench. As will be understood, any suitable deposition technique, such as CVD or ALD, can be used.

[0043] Figure 19a is a cross-sectional view of the structure depicted in Figure 18 after removing excess conductive material 139 (e.g., by planarization / polishing techniques such as CMP) to provide trench contacts 139a and vias 139b, according to one embodiment. Note that planarization removes the sacrificial insulator filler 135 and the tops of trench contacts 127 to 131. As a result, the tops of trench contacts 127 to 131 are coplanar with the tops of each portion of trench contact 139a, as well as the tops of insulator filler 133 and gate structure 121. Figure 19b shows a cross-section through the gate structure and channel region and parallel to the fins. Note how the sacrificial insulator filler 135 and gate cap 123 are planarized such that the top surface of gate structure 121 is coplanar with the top surfaces of trench contacts 127 and 128 on either side of gate structure 121. Note further that the distance d8 from the top of the gate structure 121 to the top of the channel region (in this example, the nanoband) can be in the range of, for example, 10 to 20 nm (e.g., 15 nm), in some embodiments.

[0044] Recall that trench contacts 127 to 131 can be implemented using the same material as the discontinuous portions of trench contact 139a. Since they are separate deposits, an interface will exist between them when they are laterally adjacent and in contact with each other. As discussed with reference to Figures 1a to 1b, this interface is detectable and may contain grain boundaries or a set of grain boundaries or padding material (or barrier material, as appropriate). Further note that the non-adjacent portions of trench contact 139a may be electrically connected to each other or not. In some cases, one or more portions (and possibly all portions) of trench contact 139a are electrically insulated from other portions of trench contact 139a. For example, the left two portions of trench contact 139a are electrically insulated from each other by the leftmost insulating filler 133. In some cases, one or more portions (and possibly all portions) of trench contact 139a are electrically connected to other portions of trench contact 139a. For example, trench contact 127 electrically connects the left adjacent portion of trench contact 139a to the right adjacent portion of trench contact 139a. Given this disclosure, many such lateral contact schemes will be understood.

[0045] Many further observations can be made of the example structure shown. For example, the sidewall of trench contact 129 is automatically aligned with and interfaces with the first (right) sidewall of the left adjacent portion of trench contact 139a to provide an electrical path (lateral contact) between these trenches. Further note that via 139b extends from that portion of trench contact 139a to the underlying BPR 111. Further note that via 139b is automatically aligned with trench contact 129 and its left adjacent trench contact 139a. Further note that the maximum height of trench contact 139a is less than the maximum height of trench contacts 127 to 131. For example, in some embodiments, the maximum height of the second portion of trench contact 139a is 5 to 15 nm (e.g., 8 to 10 nm) shorter than the maximum height of trench contacts 127 to 131. Furthermore, the second (left) sidewall of the trench contact 139a to the left side of the trench contact 129 is in contact with the insulating material filler 133, and the maximum height of the insulating filler 133 is less than the maximum height of the trench contacts 127 to 131, but greater than the maximum height of the trench contact 139a, in this example case. Further note that the leftmost portion of the trench contact 139a extends laterally between and interfaces with the insulating filler 133 (to the left) and the trench contact 127 (to the right), and extends at least partially 117 above the underlying source or drain region without contacting that source or drain region 117. Further example implementations

[0046] Example 1 is an integrated circuit comprising: a gate structure having a top surface; a first source or drain region; a second source or drain region; a first trench contact on the first source or drain region, the first trench contact having a top surface and sidewalls; a second trench contact comprising discontinuous first and second portions, each portion having a top surface coplanar with the top surface of the first trench contact and the top surface of the gate structure, wherein the sidewall of the first portion of the second trench contact contacts the sidewall of the first trench contact to provide an interface therebetween, and wherein the second portion of the second trench contact extends above the second source or drain region without contacting the second source or drain region; and a via extending from the first portion of the second trench contact to an underlying conductor.

[0047] Example 2 includes the target of Example 1, wherein the first trench contact is higher than the second portion of the second trench contact.

[0048] Example 3 includes the target of Example 1 or 2, wherein the first trench contact is 5 nanometers to 15 nanometers higher than the second portion of the second trench contact.

[0049] Example 4 includes the object of any one of Examples 1 to 3, wherein the sidewall of the first groove contact is a first sidewall, and wherein the sidewall of the second portion of the second groove contact contacts the second sidewall of the first groove contact to provide an interface therebetween.

[0050] Example 5 includes the subject of any one of Examples 1 to 4, wherein the interface between the sidewall of the first groove contact and the sidewall of the first portion of the second groove contact comprises a padding material. A similar feature may also be applied to the interface between the sidewall of the second portion of the second groove contact and the second sidewall of the first groove contact.

[0051] Example 6 includes the subject of any one of Examples 1 to 5, wherein the interface between the sidewall of the first trench contact and the sidewall of the first portion of the second trench contact comprises one or more grain boundaries. Similar features may also be applied to the interface between the sidewall of the second portion of the second trench contact and the second sidewall of the first trench contact.

[0052] Example 7 includes the subject of any one of Examples 1 to 6, wherein the sidewall of the first portion of the second trench contact is a first sidewall of the first portion of the second trench contact, the first portion of the second trench contact has a second sidewall in contact with an insulating material, the insulating material having a top surface coplanar with the top surface of the first portion of the second trench contact.

[0053] Example 8 includes the object of Example 7, wherein the insulating material has a maximum height extending from the top surface of the insulating material to the bottom surface of the insulating material, the maximum height of the insulating material being shorter than the maximum height of the first trench contact.

[0054] Example 9 includes a target of any one of Examples 1 to 8, wherein the source or drain region is a first source or drain region, and the integrated circuit includes: a third source or drain region; and a third trench contact on the third source or drain region, the third trench contact having a top surface coplanar with the top surface of the first trench contact, wherein the third trench contact is between the first and second portions of the second trench contact.

[0055] Example 10 includes a target of any one of Examples 1 to 9, wherein the first portion of the second trench contact has the same maximum height as the second portion of the second trench, and the through hole is not counted.

[0056] Example 11 includes the subject of any one of Examples 1 to 10, wherein the underlying conductor is an embedded power rail or a back-side power rail.

[0057] Example 12 is a microprocessor that includes any one of the integrated circuits in Examples 1 to 11.

[0058] Example 13 is a memory that includes any of the integrated circuits in Examples 1 through 11. In some such cases, the memory is located within the microprocessor of Example 12.

[0059] Example 14 is an integrated circuit comprising: a gate structure having a top surface; a source or drain region; a first trench contact on the source or drain region, the first trench contact having first and second sidewalls extending between the top surface and the bottom surface of the first trench contact, the first trench contact having a maximum height extending from the top surface to the bottom surface of the first trench contact; and a second trench contact comprising discontinuous first and second portions, each portion having a connection with the top surface of the first trench contact. The top surface of the second trench contact and the top surface of the gate structure are coplanar, wherein the sidewall of the first portion of the second trench contact contacts the first sidewall of the first trench contact to provide an interface therebetween, and wherein at least the second portion of the second trench contact has a maximum height extending from the top surface of the second portion to the bottom surface of the second portion, the maximum height of the second portion of the second trench being shorter than the maximum height of the first trench contact; and a through hole extending from the first portion of the second trench contact to the underlying conductor.

[0060] Example 15 includes the object of Example 14, wherein the source or drain region is a first source or drain region, and wherein the second portion of the second trench contact extends above the second source or drain region without contacting the second source or drain region.

[0061] Example 16 includes the subject of Example 14 or 15, wherein the sidewall of the second portion of the second groove contact contacts the second sidewall of the first groove contact to provide an interface therebetween.

[0062] Example 17 includes the subject of any one of Examples 14 to 16, wherein the interface between the first sidewall of the first trench contact and the sidewall of the first portion of the second trench contact comprises a padding material. Similar features may also be applied to the interface between the second portion of the second trench contact and the first trench contact.

[0063] Example 18 includes the subject of any one of Examples 14 to 17, wherein the first and second trench contacts are composed of the same material, and the interface between the first sidewall of the first trench contact and the sidewall of the first portion of the second trench contact comprises one or more grain boundaries. Similar features may also be applied to the interface between the second portion of the second trench contact and the first trench contact.

[0064] Example 19 includes the subject of any one of Examples 14 to 18, wherein the sidewall of the first portion of the second trench contact is a first sidewall of the first portion of the second trench contact, the first portion of the second trench contact has a second sidewall in contact with an insulating material, the insulating material having a top surface coplanar with the top surface of the first portion of the second trench contact.

[0065] Example 20 includes the object of Example 19, wherein the insulating material has a maximum height extending from the top surface of the insulating material to the bottom surface of the insulating material, the maximum height of the insulating material being shorter than the maximum height of the first trench contact.

[0066] Example 21 includes a target of any one of Examples 14 to 20, wherein the source or drain region is a first source or drain region, and the integrated circuit includes: a second source or drain region; and a third trench contact on the second source or drain region, the third trench contact having a top surface coplanar with the top surface of the first trench contact, wherein the third trench contact is between the first and second portions of the second trench contact.

[0067] Example 22 includes the target of any one of Examples 14 to 21, wherein the first portion of the second trench contact has the same maximum height as the second portion of the second trench, and the through hole is not counted.

[0068] Example 23 includes the target of any one of Examples 14 to 22, wherein the maximum height of the second portion of the second trench contact is 5 to 15 nanometers shorter than the maximum height of the first trench contact.

[0069] Example 24 includes the subject of any one of Examples 14 to 23, wherein the underlying conductor is an embedded power rail or a back-side power rail.

[0070] Example 25 is a processor that includes any one of the integrated circuits in Examples 14 to 23.

[0071] Example 26 is a memory that includes any of the integrated circuits in Examples 14 through 23. In some examples, the memory is contained within the microprocessor or Example 25.

[0072] Example 27 is an integrated circuit comprising: a gate structure having a top surface, the gate structure including a gate dielectric, a gate electrode, and a gate spacer; a first source or drain region in contact with a semiconductor material below the gate structure; a second source or drain region; a first trench contact on the source or drain region, the first trench contact having first and second sidewalls extending between the top surface and the bottom surface of the first trench contact, the first trench contact having a maximum height extending from the top surface of the first trench contact to the bottom surface of the first trench contact; and a second trench contact comprising discontinuous first and second portions, each portion having a connection with the top surface of the first trench contact. The gate structure has a top surface coplanar with the top surface of the gate structure, wherein the sidewall of the first portion of the second trench contact contacts the first sidewall of the first trench contact to provide an interface therebetween, and wherein at least the second portion of the second trench contact has a maximum height extending from the top surface of the second portion to the bottom surface of the second portion, the maximum height of the second portion of the second trench being shorter than the maximum height of the first trench contact, and wherein the second portion of the second trench contact extends above the second source or drain region without contacting the second source or drain region; and a through hole extending from the first portion of the second trench contact to the embedded power rail or back-side power rail.

[0073] Example 28 includes the object of Example 27, wherein the sidewall of the second portion of the second groove contact contacts the second sidewall of the first groove contact to provide an interface therebetween.

[0074] Example 29 includes the subject of Example 27 or 28, wherein the interface between the first sidewall of the first trench contact and the sidewall of the first portion of the second trench contact comprises a liner material and / or one or more grain boundaries. Similar features may also be applied to the interface between the second portion of the second trench contact and the first trench contact.

[0075] Example 30 includes the subject of any one of Examples 27 to 29, wherein the sidewall of the first portion of the second trench contact is a first sidewall of the first portion of the second trench contact, the first portion of the second trench contact has a second sidewall in contact with an insulating material, the insulating material has a top surface coplanar with the top surface of the first portion of the second trench contact, and wherein the insulating material has a maximum height extending from the top surface of the insulating material to the bottom surface of the insulating material, the maximum height of the insulating material being shorter than the maximum height of the first trench contact.

[0076] Example 31 includes a target of any one of Examples 27 to 30, wherein the source or drain region is a first source or drain region, and the integrated circuit includes: a third source or drain region; and a third trench contact on the third source or drain region, the third trench contact having a top surface coplanar with the top surface of the first trench contact, wherein the third trench contact is between the first and second portions of the second trench contact.

[0077] Example 32 includes the target of any one of Examples 27 to 31, wherein the first portion of the second trench contact has the same maximum height as the second portion of the second trench, and the through hole is not counted.

[0078] Example 33 includes the target of any one of Examples 27 to 32, wherein the maximum height of the second portion of the second trench contact is 5 to 15 nanometers shorter than the maximum height of the first trench contact.

[0079] Example 34 includes the subject of any one of Examples 27 to 33, wherein the underlying conductor is an embedded power rail or a back-side power rail.

[0080] Example 35 is a processor that includes any one of Examples 27 through 34 of the integrated circuit.

[0081] Example 36 is a memory that includes any one of the integrated circuits in Examples 27 through 34. In some examples, the memory is included in the microprocessor or in Example 35.

[0082] Example 37 is an integrated circuit comprising: a first trench contact having a first maximum height; and a second trench contact having a second maximum height, comprising discontinuous first and second portions, each portion having a top surface coplanar with the top surface of the first trench contact, wherein a sidewall of the first portion of the second trench contact contacts a sidewall of the first trench contact to provide an interface therebetween, and wherein the second portion of the second trench contact extends above a source or drain region without contacting the source or drain region, and wherein the second maximum height is shorter than the first maximum height.

[0083] Example 38 includes the object of Example 37 and further includes a gate structure having a top surface, wherein the top surface of the gate structure is coplanar with the top surface of the first trench contact and the top surface of each of the first and second portions of the second contact.

[0084] Example 39 includes the target of Example 37 or 38, and also includes a through-hole extending from the first portion of the second trench contact to the conductor.

[0085] Example 40 includes the object of Example 39, wherein the conductor is an embedded power rail or a back-side power rail.

[0086] The foregoing description of embodiments of the present disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. In view of the disclosure, many modifications and variations are possible. It is intended that the scope of the disclosure be limited not by this detailed description, but by the scope of the appended claims.

[0087] 101:Substrate 103: Dielectric 104: Dielectric 105: Cover 107: Mask 109: Spacers 111:BPR 113: Virtual Gate Structure 113a: Virtual gate structure 113b: Dummy gate dielectric 113c: Gate spacer 115: Gate cover 116: Dielectric 117: Source or Drain Region 119: Source or Drain Region 120: Dielectric 121: Final gate structure 121a: Gate electrode 121b: Gate dielectric 123: Gate cover 125: Mask 127: Groove Contact 128: Groove Contact 129: Groove Contact 131: Groove contact 133: Insulator filler 135: Sacrificial Insulator Filler 137: Mask 139: Conductive materials 139a: Groove contact 139b: Through hole ΔH: Height difference d1: Distance d2: Distance d3: Distance d4: Distance d5: Distance d6: Distance d7: Distance d8: Distance

Claims

1. An integrated circuit, comprising: A gate structure with a top surface; First source or drain region; Second source or drain region; A first trench contact on the first source or drain region, the first trench contact having a top surface and sidewalls; a second trench contact comprising discontinuous first and second portions, each portion having a top surface coplanar with the top surface of the first trench contact and the top surface of the gate structure, wherein the sidewall of the first portion of the second trench contact contacts the sidewall of the first trench contact to provide an interface therebetween, and wherein the second portion of the second trench contact extends above the second source or drain region without contacting the second source or drain region; and a through-hole extending from the first portion of the second trench contact to the underlying conductor.

2. As in request item 1, the integrated circuit, wherein, The first groove contact is higher than the second portion of the second groove contact.

3. As in request item 1, the integrated circuit, wherein, The first trench contact is 5 to 15 nanometers higher than the second portion of the second trench contact.

4. As in request item 1, the integrated circuit, wherein, The sidewall of the first groove contact is a first sidewall, and the sidewall of the second portion of the second groove contact contacts the second sidewall of the first groove contact to provide an interface therebetween.

5. As in request item 1, the integrated circuit, wherein, The interface between the sidewall of the first groove contact and the sidewall of the first portion of the second groove contact contains a padding material.

6. The integrated circuit as described in claim 1, wherein, The interface between the sidewall of the first trench contact and the sidewall of the first portion of the second trench contact contains one or more grain boundaries.

7. An integrated circuit as described in any of requests 1 to 6, wherein, The sidewall of the first portion of the second groove contact is the first sidewall of the first portion of the second groove contact. The first portion of the second groove contact has a second sidewall that contacts an insulating material. The insulating material has a top surface that is coplanar with the top surface of the first portion of the second groove contact.

8. The integrated circuit as described in claim 7, wherein, The insulating material has a maximum height extending from the top surface of the insulating material to the bottom surface of the insulating material, and the maximum height of the insulating material is shorter than the maximum height of the first groove contact.

9. An integrated circuit as described in any of requests 1 to 6, wherein, The integrated circuit includes: a third source or drain region; and a third trench contact on the third source or drain region, the third trench contact having a top surface coplanar with the top surface of the first trench contact, wherein the third trench contact is between the first and second portions of the second trench contact.

10. An integrated circuit as described in any of requests 1 to 6, wherein, The first portion of the second groove contact has the same maximum height as the second portion of the second groove contact, and the through hole is not counted.

11. An integrated circuit as described in any of requests 1 to 6, wherein, The underlying conductor is either an embedded power rail or a back-side power rail.

12. A microprocessor comprising integrated circuitry as claimed in any one of claims 1 to 6.

13. A memory comprising an integrated circuit as claimed in any one of claims 1 to 6.

14. An integrated circuit, comprising: A gate structure with a top surface; Source or drain region; A first trench contact on the source or drain region, the first trench contact having first and second sidewalls extending between the top surface and the bottom surface of the first trench contact, the first trench contact having a maximum height extending from the top surface of the first trench contact to the bottom surface of the first trench contact; A second trench contact includes discontinuous first and second portions, each portion having a top surface coplanar with the top surface of the first trench contact and the top surface of the gate structure, wherein a sidewall of the first portion of the second trench contact contacts the first sidewall of the first trench contact to provide an interface therebetween, and wherein at least the second portion of the second trench contact has a maximum height extending from the top surface of the second portion to the bottom surface of the second portion, the maximum height of the second portion of the second trench contact being shorter than the maximum height of the first trench contact; and a through-hole extending from the first portion of the second trench contact to the underlying conductor.

15. The integrated circuit as described in claim 14, wherein, The source or drain region is a first source or drain region, and wherein the second portion of the second trench contact extends above the second source or drain region without contacting the second source or drain region.

16. The integrated circuit as described in claim 14, wherein, The sidewall of the second portion of the second groove contact contacts the second sidewall of the first groove contact to provide an interface therebetween.

17. The integrated circuit as described in claim 14, wherein, The interface between the first sidewall of the first groove contact and the sidewall of the first portion of the second groove contact contains a padding material.

18. The integrated circuit as described in claim 14, wherein, The first and second trench contacts are made of the same material, and the interface between the first sidewall of the first trench contact and the sidewall of the first portion of the second trench contact contains one or more grain boundaries.

19. An integrated circuit as described in any of claims 14 to 18, wherein, The sidewall of the first portion of the second groove contact is the first sidewall of the first portion of the second groove contact. The first portion of the second groove contact has a second sidewall that contacts an insulating material. The insulating material has a top surface that is coplanar with the top surface of the first portion of the second groove contact.

20. The integrated circuit of claim 19, wherein, The insulating material has a maximum height extending from the top surface of the insulating material to the bottom surface of the insulating material, and the maximum height of the insulating material is shorter than the maximum height of the first groove contact.

21. An integrated circuit, comprising: A gate structure having a top surface, the gate structure comprising a gate dielectric, a gate electrode, and a gate spacer; A first source or drain region in contact with a semiconductor material below the gate structure; a second source or drain region; a first trench contact on the first source or drain region, the first trench contact having first and second sidewalls extending between the top surface and the bottom surface of the first trench contact, the first trench contact having a maximum height extending from the top surface of the first trench contact to the bottom surface of the first trench contact; A second trench contact comprising discontinuous first and second portions, each portion having a top surface coplanar with the top surface of the first trench contact and the top surface of the gate structure, wherein a sidewall of the first portion of the second trench contact contacts the first sidewall of the first trench contact to provide an interface therebetween, and wherein at least the second portion of the second trench contact has a maximum height extending from the top surface of the second portion to the bottom surface of the second portion, the maximum height of the second portion of the second trench contact being shorter than the maximum height of the first trench contact, and wherein the second portion of the second trench contact extends above the second source or drain region without contacting the second source or drain region; and a through-hole extending from the first portion of the second trench contact to an embedded power rail or a back-side power rail.

22. The integrated circuit as claimed in claim 21, wherein, The sidewall of the second portion of the second groove contact contacts the second sidewall of the first groove contact to provide an interface therebetween.

23. An integrated circuit, comprising: A first grooved contact with a first maximum height; And a second grooved contact having a second maximum height, comprising discontinuous first and second portions, each portion having a top surface coplanar with the top surface of the first grooved contact, wherein the sidewall of the first portion of the second grooved contact contacts the sidewall of the first grooved contact to provide an interface therebetween, and wherein the second portion of the second grooved contact extends above the source or drain region without contacting the source or drain region, and wherein the second maximum height is shorter than the first maximum height.

24. The integrated circuit of claim 23 further includes a gate structure having a top surface, wherein, The top surface of the gate structure is coplanar with the top surface of the first groove contact and the top surface of each of the first and second portions of the second groove contact.

25. The integrated circuit of claim 23 or 24 further includes a through-hole extending from the first portion of the second trench contact to the conductor.

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