Integrated current sharing schemes for multiplying power stages support of a multiphase controller

Abstract

This invention discloses a method and apparatus for controlling a device including a controller integrated into a first slave device. In one example, the controller can detect a sensed current in the first slave device. The controller can receive a voltage signal associated with a second slave device connected to the first slave device. The controller can generate a correction current based on the sensed current of the first slave device and the voltage signal. The controller can use the correction current to modulate a pulse width modulation (PWM) signal received by the first slave device. The controller can use the modulated PWM signal to control a power converter.

Description

[Technical Field]

[0001] This invention relates to a current sharing architecture in a multi-phase system. More specifically, this invention relates to a slave device integrated with a device that performs a current sharing architecture to balance the current among a plurality of slave devices in a multi-phase system. [Previous Technology]

[0002] Different electronic components can be connected to each other in different configurations (such as a master-slave configuration). In a master-slave configuration, one electronic component (such as a master device) controls another electronic component (such as a slave device). The master electronic component can be connected to the slave electronic component via a passive external network and respective connection points in the master and slave devices or electronic components. In some instances, a system having one master device controlling multiple slave devices can be referred to as a multiphase network or multiphase system.

[0003] One example of a multi-phase system is a multi-phase power regulator. A multi-phase power regulator may include a plurality of power stages, wherein such power stages may be slave devices controlled by a master or controller device. Power stages may be referred to as phases, wherein such phases may be connected in parallel and share the same input and output capacitors. In some instances, increasing the number of power stages or phases (or phase count) can reduce the ripple on the system's input voltage, thereby requiring fewer capacitors to keep the input voltage ripple within specifications. Traditionally, to double (or multiply) the power stage support of a multi-phase controller, an external device or component is used to balance the current in two power trains so that they can both be driven by a single PWM line. However, increasing the number of phases by using an external device also increases the bill of materials (BOM) cost and printed circuit board (PCB) area. For example, in the case of a 20-phase PWM controller supporting one of 40 power stages, more than 180 additional external components will be required. This invention describes various integrated current balancing architectures in a phase driven by a single control line (e.g., PWM output), which simplify design and significantly reduce component count and layout complexity, as well as improve system reliability. [Summary of the Invention]

[0004] In one example, a device for implementing a current-sharing architecture is generally described. A controller can be configured to detect a sensed current in a first slave device. The controller can be further configured to receive a voltage signal associated with a second slave device connected to the first slave device. The controller can be further configured to generate a correction current based on the sensed current of the first slave device and the voltage signal. The controller can be further configured to use the correction current to modulate a pulse-width modulation (PWM) signal received by the first slave device.

[0005] In one example, a system for implementing a current-sharing architecture is generally described. The system may include a master device, a first slave device connected to the master device, and a second slave device connected to both the master device and the first slave device. The first slave device may be configured to receive a first pulse-width modulation (PWM) signal. The first slave device may be further configured to detect a first sensed current. The first slave device may be further configured to receive a first voltage signal associated with the second slave device. The first slave device may be further configured to generate a first correction current based on the first sensed current and the first voltage signal. The first slave device may be further configured to modulate the first PWM signal using the first correction current. The second slave device may be configured to receive a second PWM signal. The second slave device may be further configured to detect a second sensed current. The second slave device may be further configured to receive a second voltage signal associated with the first slave device. The second slave device can be further configured to generate a second correction current based on the second sensed current and the second voltage signal. The second slave device can be further configured to use the second correction current to modulate the second PWM signal.

[0006] In one example, a method for controlling a device including a controller integrated into a first slave device is generally described. The method may include detecting a sensed current in the first slave device via the controller. The method may further include receiving a voltage signal associated with a second slave device connected to the first slave device via the controller. The method may further include generating a correction current via the controller based on the sensed current of the first slave device and the voltage signal. The method may further include modulating a pulse width modulation (PWM) signal received by the first slave device using the correction current via the controller. The method may further include controlling a power converter via the controller using the modulated PWM signal.

[0007] The foregoing overview is illustrative only and is not intended to be limiting in any way. Further embodiments, examples, and features, in addition to those described above, will become apparent from the accompanying drawings and the following detailed description. In the drawings, the same element symbols indicate the same or functionally similar elements.

Implementation Method

[0017] In some instances, the term electronic component, as used herein, may comprise any discrete means or device having several input and output connection points (such as terminals, leads, or pins) for influencing electrons and their associated fields. Electronic components may be housed in a package such as a semiconductor integrated circuit (IC). Multiple electronic components may be interconnected to form the devices, apparatuses, and systems described herein.

[0018] One example system 100 shown in Figure 1 can implement an integrated current sharing architecture for multiplying the power stage support of a multi-phase controller. For example, a 20-phase pulse width modulation (PWM) controller (e.g., a master device) with 20 PWM outputs can be expanded to support 40, 60, or more power stages in a multi-phase system (e.g., system 100) instead of 20 power stages. More specifically, multiple slave devices in system 100 can be integrated with a device that implements a current sharing architecture to balance the current among the multiple slave devices, wherein the multiple slave devices can be driven by the same control signal (e.g., PWM output) in a multi-phase system.

[0019] FIG1 illustrates an exemplary system 100 according to a configuration of the present invention, comprising a controller 102 configured to support multiple power stages in a multi-phase system. System 100 may be a system having a master-slave configuration, wherein a master device (or electronic component) controls one or more slave devices (or electronic components). In some configurations of the present invention, system 100 may be a power system comprising a converter (such as a DC-DC converter). In the example shown in FIG1, system 100 may include a master device 102, a slave device 110, and a slave device 120. In some instances, master device 102 may be connected to slave device 110 and slave device 120 via a passive external network (such as a resistor-capacitor (RC) network). Those skilled in the art will understand that system 100 may include additional sets of slave devices or power stages. For example, the master control device 102 (or controller) can control a first group of devices 110 and 120 via a first PWM line 111a, and can control another group of slave devices 110 and 120 that can be controlled by another second PWM line 111b. Separate control lines or PWM lines allow the master control device 102 to connect between the controller 102 and the slave devices 110 and 120 with a minimum number of external components to support an additional number of slave devices.

[0020] In one example, each of the slave devices 110 and 120 may be a current source type, a voltage source type, or a device implementing both current and voltage source control. A current source type slave device may be controlled by a constant input current output from a current source, wherein this constant input current may be independent of a voltage across the current source. A voltage source type slave device may be controlled by a constant voltage output from a voltage source. For a current source type slave device, a low-impedance resistor-capacitor (RC) network (e.g., a passive external network) having a resistor and capacitor connected in parallel may be connected between the master device and the current source type slave device. For a voltage source type slave device, a high-impedance resistor-capacitor (RC) network (e.g., a passive external network) may be connected between the master device and the current source type slave device.

[0021] System 100 may be implemented as a multi-phase power regulator (e.g., a multi-phase buck regulator) for a load 104. A multi-phase power regulator may include a plurality of power stages, wherein such power stages may be slave devices (e.g., slave devices 110 and 120) controlled by a master or controller device (e.g., master device 102). In one example, slave devices 110 and 120 may be intelligent power stage (SPS) devices configured to perform voltage regulation with additional features (such as temperature and current feedback control). Master device 102 may be one of the control devices in the multi-phase power regulator, such as a digital multi-phase controller for one or more power stage devices (e.g., slave devices 110 and 120). In some examples, master device 102 may also control additional slave devices (e.g., in addition to slave devices 110 and 120). Those skilled in the art will understand that system 100 may include additional master devices (e.g., a dual-master system), slave devices, and intermediate devices. Furthermore, the methods and systems described herein can be applied to other types of electronic components implemented as slave devices.

[0022] In a multi-phase power regulator, each power stage may include its own set of power converters (e.g., DC-DC converters or buck converters), wherein a power converter may include a set of switching elements, such as high-side (or upper) and low-side (or lower) metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, in FIG1, slave device 110 may include a power converter 112 and slave device 120 may include a power converter 122. In some instances, power stages may be referred to as phases, wherein these phases may be connected in parallel and share input and output capacitors. A system having one of two power stages may be referred to as a two-phase system. Some systems may contain eight or twelve power stages, depending on the application to which one of the multi-phase power regulator systems is to be used.

[0023] In some instances, increasing the number of power stages or phases can reduce ripple on the system's input voltage, thereby requiring fewer capacitors to keep the input voltage ripple within specifications. However, increasing the number of phases also increases bill of materials (BOM) cost and printed circuit board (PCB) area. Furthermore, as the number of phases increases, the risk of current imbalance within the phases also increases. To achieve optimal performance, the current within the phases needs to be uniformly balanced between phases to avoid thermal stress on any one phase, providing optimal ripple elimination to resolve current imbalances.

[0024] In one example, system 100 can operate in a synchronous mode or an interleaved mode. In the synchronous mode, multiple slave devices are driven by the same PWM signal provided by the master device, enabling the multiple slave devices to operate synchronously. In the interleaved mode, each slave device is driven by its own pulse width modulation (PWM) signal, wherein the PWM signals used to drive the multiple slave devices can be out of phase. In both the synchronous and interleaved modes, current imbalance may occur when at least one of the multiple slave devices does not simultaneously receive its PWM signal.

[0025] In the example shown in Figure 1, each slave device of system 100 (such as slave devices 110 and 120) may include a device 130 (e.g., 130A or 130B) that can be configured to perform current sharing and balancing among the slave devices of system 100. Device 130 may be an integrated circuit or a device embedded or integrated into each slave device of system 100. Device 130 may be configured to perform current sharing based on exchanging data or signals among the slave devices using a communication bus 132. In some instances, device 130 may be integrated or embedded in the controllers of slave devices 110 and 120. For example, slave device 110 may include a controller 114, wherein controller 114 may be integrated with device 130 (e.g., 130A). Slave device 120 may include a controller 124, which may be integrated with another copy of device 130 (e.g., 130B). In some instances, device 130 may include control logic or a controller having one or more integrated circuits and other electronic components. For example, device 130 may include one or more amplifiers, comparators, integrators, voltage followers, current sources, resistors, averaging circuits, pulse dividers, pulse width modulators, and / or other types of electronic components.

[0026] Using slave device 110 as an example, controller 114 can be configured to detect a phase current of slave device 110. The controller 114 of slave device 110 can output its phase current as a sensed current to master device 102. The controllers of each slave device in system 100 can sense their phase current and report the sensed current back to master device 102. Master device 102 can use the sensed current received from each group of slave devices to perform various control, error detection and correction functions, and current balancing (if more than one group) within each group of slave devices in system 100. Current balancing within the same group of slave devices (e.g., slave devices 110 and 120) is performed according to the present invention.

[0027] As will be described in more detail below, depending on the various attributes and operating modes of the slave devices of system 100, device 130 may be designed to include different electronic components. Furthermore, device 130 may be designed to process sensed currents from a corresponding slave device and sensed currents from other slave devices to perform a current sharing architecture. For example, communication bus 132 may be added to system 100 to connect slave devices to each other so that slave devices can exchange their sensed currents, or other signals or data may be processed by device 130 to perform a current sharing architecture. In one example, current sharing performed by device 130 may result in the generation of a correction current, which can be used to modulate a PWM signal received by the autonomous control device 102 or, in some examples, by another slave device connected to communication bus 132.

[0028] FIG2A illustrates a device that can implement a current-sharing architecture when the current sensing signal is a voltage source type output (e.g., on pin P3) according to the present invention. FIG2B illustrates another device that can implement a current-sharing architecture when the current sensing signal is a current source type output (e.g., flowing through pin P3) according to the present invention. In the examples shown in FIG2A and FIG2B, the main control device 102 may include one or more interfaces or pins, which may be connection points for connecting various components of the main control device 102 to components and devices outside the main control device 102. For example, the main control device 102 may include pins M1, M2 and M3. Furthermore, each slave device of system 100 (such as slave devices 110 and 120) may include its own set of interfaces or pins that connect various components of the slave device to the master device 102 or other components and devices outside the slave device. For example, each of slave devices 110 and 120 may include a set of pins labeled P1, P2 and P3.

[0029] In one example, pin M1 can be an output pin and pin P1 can be an input pin, so that the master control device 102 can transmit a PWM signal 206 to pin P1 of slave devices 110 and 120. In one example, a synchronization mode of slave devices 110 and 120 can be enabled, so that the master control device 102 can transmit the PWM signal 206 to slave devices 110 and 120 simultaneously. In the example shown in FIG2A, slave devices 110 and 120 can be voltage source type devices, so that a passive external network 201A connected between the master control device 102 and slave devices 110 and 120 can be a high-impedance network including a capacitor C and an external resistor REX for connecting to each slave device of the master control device 102, wherein the capacitor C can terminate at a voltage VT and the voltage VT can be connected to a supply voltage VCCS (e.g., 1.2 volts (V)) of the master control device 102. In the example shown in Figure 2B, slave devices 110 and 120 can be current source devices, such that another passive external network 201B connected between master device 102 and slave devices 110 and 120 can be a low-impedance network including capacitor C and a sensing resistor RSEN, wherein capacitor C and the sensing resistor RSEN are connected in parallel. Resistor RSEN can terminate at voltage VT.

[0030] Pin M2 of the master control device 102 may be a current sensing input pin configured to receive sensed current from a slave device. For example, slave device 110 may transmit a voltage signal ("V207") generated based on its own sensed current 207 from its pin P3 to pin M2 of the master control device 102, and slave device 120 may transmit a voltage signal ("V217") generated based on its own sensed current 217 from its pin P3 to pin M2 of the master control device 102. Pin M3 of the master control device 102 may be an output pin connected to an internal differential amplifier in the master control device 102.

[0031] The pins P2 of slave devices 110 and 120 can be connected to each other via the communication bus 132 shown in FIG1. ​​In one example, the communication bus 132 can be a common bus 203 shown in FIG2A and FIG2B, and devices 130A and 130B shown in FIG1 can be devices 230A and 230B shown in FIG2A and FIG2B, respectively. The common bus 203 can connect the P2 pins of all slave devices in system 100. The slave devices of system 100 can use the common bus 203 to exchange signals with each other (such as voltage signals based on their respective sensed currents). Device 230A may include an amplifier A1. The amplifier A1 may be a buffer amplifier configured to output a voltage V207 based on a sensed current 207, wherein the voltage V207 can be distributed as a voltage signal to the common bus 203. Device 230B may also include a copy of amplifier A1, wherein amplifier A1 in device 230B can be configured to output a voltage V217 based on sensed current 217, wherein voltage V217 can be distributed as another voltage signal to common bus 203. In both devices 230A and 230B, a diode D1 may be located between the output terminal of amplifier A1 and the non-inverting input terminal of amplifier A2. Diode D1 in device 230A can direct V207 to drive common bus 203, and diode D1 in device 230B can direct voltage V217 to drive common bus 203. The voltage of V207 and V217 corresponding to the higher sensed current dominates common bus 203.

[0032] In the examples shown in Figures 2A and 2B, the master device 102 can use PWM signal 206 to control slave devices 110 and 120, as well as any additional slave devices (not shown) of system 100. The slave device with the highest sensed current among the slave devices of system 100 can drive the common bus 203 using a voltage generated based on the highest sensed current. For example, the common bus 203 is dominated by the voltage generated by the highest sensed current. If slave device 120 has the highest sensed current, then a voltage or voltage signal V217 can drive the common bus 203 and be distributed to all slave devices in the same group of slave devices driven by the same control signal (e.g., PWM) that do not have the highest sensed current. Therefore, any slave device in the same group (driven by the same PWM line) of system 100 can become the slave device with the highest sensed current (e.g., one of the master devices among all slave devices).

[0033] In Figure 2B, if slave device 110 is a current source device, device 230A may include an internal resistor RINT, and device 230B may include an internal resistor RINT in response to slave device 120 being a current source device. In response to slave devices 110 and 120 being current source devices, resistor RINT may be finely adjusted and may be converted by amplifier A1 into voltage signals (e.g., sensed currents 207 and 217) to drive common bus 203.

[0034] Amplifier A2 of device 230A can generate an error between the voltage V207 generated by the sensed current 207 and the voltage generated by the highest sensed current (labeled 209) (in this example, it is V217). In response to voltage 209 being greater than V207, amplifier A2 can output a voltage that can generate a correction current IC1 to a pulse width modulator 202A of device 230A. Pulse width modulator 202A can receive a PWM signal 206 from pin P1 and can receive the correction current IC1. In one example, the correction current IC1 can represent a difference between the highest sensed current 217 and the sensed current 207. Pulse width modulator 202A can use the correction current IC1 to modulate the PWM signal 206 to generate a modulated PWM signal 220A. The pulse width modulator 202A can modulate the PWM signal 206 by applying an offset to one of the leading edges, one of the falling edges, or both the leading and falling edges, wherein the offset can be based on the correction current IC1.

[0035] In the example shown in Figure 2A, since the sensed current 217 is the highest sensed current, amplifier A2 in device 230B can output a voltage of a correction current IC2, which can be zero or a null current, to a pulse width modulator 202B in device 230B. Pulse width modulator 202B can receive a PWM signal 206 from pin P1 and can receive the correction current IC2. In response to the correction current IC2 being zero, pulse width modulator 202B may not need to modulate the PWM signal 206 and can output the PWM signal 206 as a modulated PWM signal 220B. Pulse width modulator 202B can modulate the PWM signal 206 by applying an offset to a leading edge, a falling edge, or both the leading and falling edges of the PWM signal 206, wherein the offset may be based on the correction current IC2.

[0036] Any additional slave device in system 100 may modulate a copy of its own PWM signal 206 based on the error between its own sensed current and the sensed current that generates the highest voltage 209 for driving the common bus 203. By having all slave devices in the same group modulate copies of their PWM signals 206 to match the highest sensed current, system 100 can output synchronized PWM signals (e.g., modulated PWM signals 220A and 220B) that can be used to drive power converters (e.g., power converters 112 and 122 shown in FIG. 1) in a synchronized manner and achieve current balance among the slave devices in the same group.

[0037] The examples shown in Figures 2A and 2B may include more than two slave devices. In one example where system 100 is a dual-phase counting (or two-phase counting) system, a common bus 203 can be used to connect individual pairs of slave devices. For example, if system 100 is a dual-phase counting system including eight slave devices, a first common bus (e.g., common bus 203) can connect a first pair of slave devices (e.g., slave devices 110 and 120), a second common bus can connect a second pair of slave devices (e.g., a third slave device and a fourth slave device), and so on. In another example where system 100 is a three-phase counting system, the common bus 203 can be used to connect individual slave device groups having three slave devices. For example, if system 100 includes a three-phase counting system with nine slave devices, a first common bus can connect to a first group of slave devices having a first, second, and third slave device, and a second common bus can connect to a second group of slave devices having a fourth, fifth, and sixth slave device, etc. In other words, an N-phase controller (e.g., master controller 102) can have N PWM lines (e.g., output N PWM signals) and can multiply the phase count by two, three, etc.

[0038] FIG3A illustrates a diagram of a device using an averaged current common architecture when the current sensing signal is a voltage source type output (e.g., on pin P3) according to the present invention. FIG3B illustrates a diagram of a device using an averaged current common architecture when the current sensing signal is a current source type output (e.g., flowing through pin P3) according to the present invention. In the examples shown in FIG3A and FIG3B, a synchronization mode for slave devices 110 and 120 can be enabled, so that the master control device 102 can simultaneously transmit the PWM signal 206 to slave devices 110 and 120. In the example shown in Figure 3A, slave devices 110 and 120 can be voltage source devices, such that the passive external network 201A connected between the master device 102 and slave devices 110 and 120 can be a high-impedance network including a capacitor C and external resistors REX for connecting to each slave device of the master device 102, wherein the capacitor C can terminate at a voltage VT and the voltage VT can be connected to a supply voltage VCCS of the master device 102. In the example shown in Figure 3B, slave devices 110 and 120 can be current source devices, such that the passive external network 201B connected between the master device 102 and slave devices 110 and 120 can be a low-impedance network including a capacitor C and a sensing resistor RSEN, wherein the capacitor C and the sensing resistor RSEN are connected in parallel. The resistor RSEN can terminate at the voltage VT.

[0039] In one example, the communication bus 132 shown in FIG1 may be a common bus 303 shown in FIG3A and FIG3B, and the devices 130A and 130B shown in FIG1 may be devices 330A and 330B shown in FIG3A and FIG3B, respectively. The common bus 303 may connect to the P2 pin of all slave devices in system 100. The slave devices of system 100 may use the common bus 303 to exchange signals with each other (such as voltage signals based on their respective sensed currents).

[0040] In the examples shown in Figures 3A and 3B, the common bus 303 may be a bidirectional communication bus containing one or more traces capable of transmitting signals in opposite directions. Therefore, any slave device of system 100 may output a voltage signal to and receive a voltage signal from the common bus 303. For example, slave devices 110 and 120 may receive the same external voltage signal 307 from the common bus 303. The external voltage signal 307 may be generated by an average current among the sensed currents of all slave devices in system 100. Each copy of device 330A or 330B in the slave devices of system 100 may include an average resistor RAVG. Each slave device in system 100 may apply a voltage proportional to its own sensed current through the average resistor RAVG. Therefore, the external voltage signal 307 on the common bus 303 can be based on an average current of the sensed current of all slave devices in system 100. Thus, all slave devices in system 100 can receive the same external voltage signal 307 based on the average current of the sensed current of all slave devices in system 100.

[0041] Device 330A may include an amplifier A3 (e.g., a buffer amplifier), wherein the amplifier A3 can output V207 to a common bus 303 via a resistor RAVG, such that V207 can be averaged to an external voltage signal 307 driving the common bus 303. The voltage V207 can also be input to an inverting input terminal of another amplifier A4. The external voltage signal 307 received by slave device 110 can be input to a non-inverting input terminal of amplifier A4 of device 230A.

[0042] Device 330B may also include amplifier A3, wherein amplifier A3 can output voltage V217 to common bus 303 via resistor RAVG, such that V217 can be averaged to drive external current 307 to common bus 303. Voltage V217 can also be input to an inverting input terminal of another amplifier A4 in device 330B. External current 307 received by slave device 120 can be input to a non-inverting input terminal of amplifier A4 in device 230B.

[0043] In FIG3B, device 330A may include an internal resistor RINT in response to slave device 110 being a current source device, and device 230B may include an internal resistor RINT in response to slave device 120 being a current source device. In response to slave devices 110 and 120 being current source devices, resistor RINT may be finely adjusted and may be converted by amplifier A3 into voltage signals (e.g., sensed currents 207 and 217) to drive common bus 303.

[0044] Amplifier A4 of device 330A can generate an error between voltage V207 and external voltage signal 307, and output a voltage representing a correction current IC3 indicating a difference between sensed current 207 and external current 307. Amplifier A4 can output the voltage generating correction current IC3 to pulse width modulator 302A of device 330A. Pulse width modulator 302A can receive PWM signal 206 from pin P1 and can receive correction current IC3. Pulse width modulator 302A can use correction current IC3 to modulate PWM signal 206 to generate a modulated PWM signal 320A. Pulse width modulator 302A can modulate PWM signal 206 by applying an offset to a leading edge, a falling edge, or both leading and falling edges of PWM signal 206, wherein the offset can be based on correction current IC3.

[0045] Amplifier A4 of device 330B can generate an error between V217 and external voltage signal 307, and its output can generate a voltage representing a correction current IC4 representing the difference between V217 and external voltage signal 307. Amplifier A4 can output the voltage generating correction current IC4 to a pulse width modulator 302B of device 330B. Pulse width modulator 302B can receive a PWM signal 206 from pin P1 and can receive correction current IC4. Pulse width modulator 302B can use correction current IC4 to modulate PWM signal 206 to generate a modulated PWM signal 320B. Pulse width modulator 302B can modulate PWM signal 206 by applying an offset to a leading edge, a falling edge, or both leading and falling edges of PWM signal 206, wherein the offset can be based on correction current IC4.

[0046] Device 330B of slave device 120 can operate in the same and similar manner as device 330A. In the examples shown in Figures 3A and 3B, the individual correction current of each slave device can compensate for a specific current difference between the sensed current of the corresponding slave device and an average current between sensed currents 207 and 217. For example, the correction current IC3 of slave device 110 can compensate for the difference between sensed current 207 and the average current between sensed currents 207 and 217, and the correction current IC4 of slave device 120 can compensate for the difference between sensed current 217 and the average current between sensed currents 207 and 217. By having all slave devices of system 100 modulate a copy of their PWM signal 206 using an individual correction current based on the same average current between sensed currents 207 and 217, system 100 can output synchronized PWM signals (e.g., modulated PWM signals 320A and 320B) that can be used to drive power converters (e.g., power converters 112 and 122 shown in FIG. 1) in a synchronized manner.

[0047] The examples shown in Figures 3A and 3B may include more than two slave devices. In one example where system 100 is a dual-phase counting (or two-phase counting) system, a common bus 303 can be used to connect individual pairs of slave devices. For example, if system 100 is a dual-phase counting system including eight slave devices, a first common bus (e.g., common bus 303) can connect a first pair of slave devices (e.g., slave devices 110 and 120), a second common bus can connect a second pair of slave devices (e.g., a third slave device and a fourth slave device), and so on. In another example where system 100 is a three-phase counting system, the common bus 303 can be used to connect individual slave device groups having three slave devices. For example, if system 100 includes a three-phase counting system with nine slave devices, a first common bus can connect to a first group of slave devices having a first, second, and third slave device, and a second common bus can connect to a second group of slave devices having a fourth, fifth, and sixth slave device, etc. In other words, an N-phase controller (e.g., master controller 102) can have N PWM lines (e.g., output N PWM signals) and can multiply the phase count by two, three, etc.

[0048] FIG4 illustrates a diagram of a device using an averaged proportionally adjusted current sharing architecture when the current sensing signal of a slave device is a current source type output (e.g., flowing through pin P3) according to the present invention. In the example shown in FIG4, a synchronization mode for slave devices 110 and 120 can be enabled, allowing the master device 102 to simultaneously transmit the PWM signal 206 to slave devices 110 and 120. In the example shown in FIG4, slave devices 110 and 120 can be current source type devices, such that the passive external network 201B connected between the master device 102 and slave devices 110 and 120 can be a low-impedance network including a capacitor C and a sensing resistor RSEN, wherein the capacitor C and the sensing resistor RSEN are connected in parallel. The resistor RSEN can terminate at a voltage VT.

[0049] In one example, the communication bus 132 shown in FIG1 may be a communication bus 403 shown in FIG4, and the devices 130A and 130B shown in FIG1 may be devices 430A and 430B shown in FIG4, respectively. The communication bus 403 may be connected to the M3 pin of the master device and to the P2 pin of all slave devices in the system 100.

[0050] In the example shown in Figure 4, each slave device 110 and 120 can generate a proportionally adjusted sensed current and feed this proportionally adjusted current to a trimmed resistor RSC, which is matched with an external resistor RSEN to generate a voltage signal that can be distributed to the communication bus 403. The resistor RSEN can be used to sum all sensed currents from the P3 pin of all slave devices in system 100, such that the trace or line connecting the P3 pin and the M2 pin can represent an average current or average voltage among the slave devices in system 100. Each slave device can generate an error voltage based on the voltage generated by the proportionally adjusted current (e.g., through the resistor RSC) and the average voltage at the P3 pin to generate a correction current. In one example, the current-sharing architecture shown in Figure 4 can proportionally adjust the voltage applied to the inverting input of an amplifier (e.g., amplifier A5 in Figure 4) as an attempt to minimize an error between the proportionally adjusted voltage and a voltage generated by a sensed current.

[0051] In one example, resistor RSC may have a resistance of 2RSENM, where M may be a scaling factor that can be used to proportionally adjust a sensed current and reduce current consumption as needed. For example, if system 100 is a two-phase counting system (e.g., with two slave devices), resistor RSC may have a resistance of 20RSEN (e.g., 20 kiloohms (kΩ)) and resistor RSEN may be maintained at RSEN (e.g., 1 kΩ). In another example, if system 100 has three phases (e.g., with three slave devices), resistor RSC may be maintained at (e.g.) 20 kΩ, and external resistor RSEN needs to be changed to (e.g.) one of RSEN(2 / 3) or 666 Ω.

[0052] The slave device 110 can generate a copy of its sensed current 207 and proportionally adjust it by dividing by M (e.g., labeled 207 / M) to generate a proportionally adjusted current. This proportionally adjusted current can flow through a resistor RSC to generate a voltage signal 409 that can be distributed to a communication bus 403. The voltage signal 409 generated by the proportionally adjusted current can be input to an inverting input terminal of an amplifier A5. The voltage generated by the sensed current 207, which can be received at pin P3, can be input to a non-inverting input terminal of amplifier A5. Amplifier A5 can output a voltage that can be generated to a correction current IC5 of a pulse width modulator 402A, wherein the correction current IC5 represents a difference between the sensed current 207 and the proportionally adjusted current 207 / M corresponding to the voltage signal 409. The pulse width modulator 402A can receive a PWM signal 206 from pin P1 and can receive the correction current IC5. The pulse width modulator 402A can use the correction current IC5 to modulate the PWM signal 206 to generate a modulated PWM signal 420A. The pulse width modulator 402A can modulate the PWM signal 206 by applying an offset to a leading edge, a falling edge, or both the leading edge and the falling edge of the PWM signal 206, wherein the offset can be based on the correction current IC5.

[0053] The slave device 120 can generate a copy of its sensed current 217 and proportionally adjust it by dividing by M (e.g., labeled 217 / M) to generate a proportionally adjusted current. This proportionally adjusted current can flow through a resistor RSC to generate a voltage signal 419 that can be distributed to a communication bus 403. The voltage signal 419 generated by the proportionally adjusted current 217 / M can be input to an inverting input terminal of an amplifier A5 in device 430b. The voltage signal 419 generated by the sensed current 217, which can be received at pin P3, can be input to a non-inverting input terminal of an amplifier A5 in device 430b. The amplifier A5 in device 430b can output a voltage that can generate a correction current IC6 in a pulse width modulator 402B, wherein the correction current IC6 can represent a difference or an error between the sensed current 217 and the proportionally adjusted current 217 / M corresponding to the voltage signal 419. The pulse width modulator 402B can receive a PWM signal 206 from pin P1 and can also receive a correction current IC6. The pulse width modulator 402B can use the correction current IC6 to modulate the PWM signal 206 to generate a modulated PWM signal 420B. The pulse width modulator 402B can modulate the PWM signal 206 by applying an offset to a leading edge, a falling edge, or both the leading and falling edges of the PWM signal 206, wherein the offset can be based on the correction current IC6.

[0054] The correction current IC5 may differ from the correction current IC6, but the modulated PWM signals 420A and 420B may be in phase. The correction currents IC5 and IC6 may respectively compensate for the different current differences between the proportionally adjusted currents 409 and 419, wherein the same average current is present at the P3 pin of all slave devices in system 100. Any additional slave device in system 100 may modulate its own copy of the PWM signal 206 based on a separate correction current generated by the same average current. By having all slave devices of system 100 modulate their copies of the PWM signal 206 using individual correction currents based on the same average current, system 100 may output synchronized PWM signals (e.g., modulated PWM signals 420A and 420B) that can be used to drive power converters (e.g., power converters 112 and 122 shown in FIG. 1) in a synchronized manner and achieve current balance among the same group of slave devices.

[0055] In some instances, the example shown in FIG4 may include more than two slave devices. In an example where system 100 may be a dual-phase counting (or two-phase counting) system, communication bus 403 may be used to connect individual pairs of slave devices. For example, if system 100 is a dual-phase counting system including eight slave devices, a first communication bus (e.g., communication bus 403) may connect a first pair of slave devices (e.g., slave devices 110 and 120), a second communication bus may connect a second pair of slave devices (e.g., a third slave device and a fourth slave device), and so on. In another example where system 100 may be a three-phase counting system, communication bus 403 may be used to connect individual slave device groups having three slave devices. For example, if system 100 includes a three-phase counting system with nine slave devices, then a common communication bus can connect to a first group of slave devices having a first, second, and third slave device, and a second communication bus can connect to a second group of slave devices having a fourth, fifth, and sixth slave device, etc.

[0056] FIG5 illustrates a diagram of a device that can implement a current-sharing architecture for a two-phase system according to the present invention. In the example shown in FIG5, a synchronization mode for slave devices 110 and 120 can be enabled, so that the master device 102 can simultaneously transmit PWM signals 206 to slave devices 110 and 120. In the example shown in FIG5, slave devices 110 and 120 can be voltage source type devices, such that the passive external network 201A connected between the master device 102 and slave devices 110 and 120 can be a high-impedance network including a capacitor C and external resistors REX for connecting to each slave device of the master device 102, wherein the capacitor C can terminate at a voltage VT and the voltage VT can be connected to a supply voltage VCCS of the master device 102.

[0057] In one example, the communication bus 132 shown in FIG1 may include a trace 503 and a trace 504 shown in FIG5, and the devices 130A and 130B shown in FIG1 may be devices 530A and 530B shown in FIG5, respectively. Trace 503 can connect the P2 pin of slave device 110 to the P3 pin of slave device 120. Trace 504 can connect the P3 pin of slave device 110 to the P2 pin of slave device 120. Slave device 110 can use trace 504 to output its sensed current 207 from its P3 pin to the P2 pin of slave device 120. Slave device 120 can use trace 503 to output its sensed current 217 from its P3 pin to the P2 pin of slave device 110.

[0058] Device 530A may include an averaging circuit 510A connected to pins P2 and P3 of slave device 110. The averaging circuit 510A of slave device 110 may receive voltage V207 generated based on sensed current 207 and voltage V217 generated based on sensed current 217, and determine an average current 507 between sensed current 207 and sensed current 217. Device 530A may further include an amplifier A6. The averaging circuit 510A may output a voltage generated based on average current 507 to an inverting input of amplifier A6. Amplifier A6 may generate and output a voltage representing a difference or error between sensed current 207 and average current 507. Amplifier A6 may output the voltage generated by generating a correction current IC7 to a pulse width modulator 502A of device 530A. The pulse width modulator 502A can receive the PWM signal 206 from pin P1 and the voltage generated by amplifier A6. The pulse width modulator 502A can use the correction current IC7 to modulate the PWM signal 206 to generate a modulated PWM signal 520A. The pulse width modulator 502A can modulate the PWM signal 206 by applying an offset to a leading edge, a falling edge, or both leading and falling edges of the PWM signal 206, wherein the offset can be based on the correction current IC7.

[0059] Device 530B may include an averaging circuit 510B connected to pins P2 and P3 of slave device 120. The averaging circuit 510B of slave device 120 may receive voltages V207 and V217 and determine an average current 507 between sensed current 207 and sensed current 217. Device 530B may further include an amplifier A6. The averaging circuit 510B may output a voltage generated based on the average current 507 to an inverting input of amplifier A6. Amplifier A6 of device 530B may generate and output a voltage representing the difference between sensed current 217 and average current 507. Amplifier A6 may output a voltage that generates a correction current IC8 to a pulse width modulator 502B of device 530B. Pulse width modulator 502B may receive a PWM signal 206 from pin P1 and may receive the voltage generated by amplifier A6. The pulse width modulator 502B can use the correction current IC8 to modulate the PWM signal 206 to generate a modulated PWM signal 520B. The pulse width modulator 502B can modulate the PWM signal 206 by applying an offset to a leading edge, a falling edge, or both the leading edge and the falling edge of the PWM signal 206, wherein the offset can be based on the correction current IC8.

[0060] The correction current IC7 may be different from the correction current IC8, but the modulated PWM signals 520A and 520B may be in phase. This is because the correction currents IC7 and IC8 respectively compensate for the different current differences between the sensed currents 207 and 217. By having the slave devices 110 and 120 of system 100 modulate copies of their respective PWM signals 206 using individual correction currents based on the same average current, system 100 can output synchronized PWM signals (e.g., modulated PWM signals 520A and 520B) that can be used to drive power converters (e.g., power converters 112 and 122 shown in FIG. 1) in a synchronized manner and achieve current balance among the same group of slave devices.

[0061] FIG6 illustrates a diagram of a device that can implement a current sharing architecture using an additional pulse divider according to the present invention. The example shown in FIG6 can be applied to one or more of the current sharing architectures using an additional pulse divider shown in FIG2A to FIG5. Furthermore, the example shown in FIG6 can alternatively output the PWM signal 206 to every other slave device (e.g., the second slave device 120 in each pair or group of slave devices) to achieve interleaved operation among the slave devices (e.g., 180-degree out-of-phase operation between two slave devices). In the example shown in FIG6, slave devices 110 and 120 can output out-of-phase PWM signals 620A and 620B. For example, the master device 102 can transmit the PWM signal 206 to slave device 110, and slave device 110 can split the PWM signal 206 and provide one of the split PWM signals to slave device 120. In the example shown in Figure 6, slave devices 110 and 120 can be current-source devices, such that the passive external network 201B connected between the master device 102 and slave devices 110 and 120 can be a low-impedance network including a capacitor C and a sensing resistor RSEN, wherein the capacitor C and the sensing resistor RSEN are connected in parallel. However, those skilled in the art will understand that the current sharing architecture described according to Figure 6 can be applied to a system with voltage-source slave devices. In one example, PWM signal dividers 610A and 610B and pin P4 can be added to the exemplary system shown in Figures 2A to 3B to facilitate current sharing using the pulse divider as described in the example of Figure 6. For example, by adding PWM signal dividers 610A and 610B and pin P4 to slave devices 110 and 120, the example in Figure 6 can be a modification of the exemplary system in Figure 2A.

[0062] In one example, the communication bus 132 shown in FIG1 may include a trace 603 and a trace 604 shown in FIG6, and the devices 130A and 130B shown in FIG1 may be devices 630A and 630B shown in FIG6, respectively. Trace 603 may be a common bus connecting the P2 pins of slave devices 110 and 120. Trace 604 may connect a pin P4 of slave device 110 to the P1 pin of slave device 120.

[0063] In the example shown in Figure 6, each slave device may include a PWM signal splitter. For example, slave device 110 may include a PWM signal splitter 610A and slave device 120 may include a PWM signal splitter 610B. Slave device 110 may receive a PWM signal 206 at pin P1, and the PWM signal 206 may be input to the PWM signal splitter 610A. The PWM signal splitter 610A may split or divide the PWM signal 206 into two PWM signals 607 and 608, which may be out of phase. The PWM signal splitter 610A may output the PWM signal 607 to a pulse width modulator 602A of device 630A, and may output the PWM signal 608 to the P1 pin of slave device 120 via the P4 pin of slave device 110. The P4 pin of slave device 120 can be connected to one of the supply voltage pins VCC of master device 102, allowing slave device 120 to enable its synchronization mode and potentially unsegment the PWM signal 608 by PWM signal splitter 610B. Those skilled in the art will understand that the roles of slave devices 110 and 120 are interchangeable. For example, master device 102 can send PWM signal 206 to slave device 120, where slave device 120 can perform PWM splitting and supply the split PWM signal to slave device 110.

[0064] In one example, the pulse divider architecture shown in FIG6 can be implemented using one or more current-shared architectures described herein (e.g., FIG2A to FIG5). For example, to implement the pulse divider of the current-shared architecture of FIG2B, a voltage generated by the highest sensed current among the sensed currents of devices 110 and 120 can drive the trace or common bus 603. In the example shown in FIG6, sensed current 217 can be the highest sensed current, such that a voltage signal 609 generated by sensed current 217 can drive common bus 603.

[0065] Slave device 110 may receive voltage signal 609 via its P2 pin. Device 630A may include an amplifier A7 (e.g., a buffer amplifier) ​​which outputs a voltage that generates a sensed current 207 to a common bus 603. The sensed current 207 may also be input to an inverting input terminal of another amplifier A8. The voltage signal 609 received by slave device 110 may be input to a non-inverting input terminal of amplifier A8 of device 630A. Amplifier A8 may generate a voltage representing an error between the sensed current 207 and a maximum sensed current (e.g., sensed current 217). The voltage output by amplifier A8 may indicate that the sensed current 217 is greater than the sensed current 207 in response to the sensed current 217 being the maximum sensed current. The voltage output by amplifier A8 may be a correction current IC9, which may be input to a pulse width modulator 602A of device 630A.

[0066] Slave device 120 may also receive voltage signal 609 via its P2 pin. Device 630B may also include amplifier A7, which outputs a voltage capable of generating sensed current 217 to common bus 603. Sensed current 217 may also be input to an inverting input terminal of amplifier A8 in device 630B. Voltage signal 609 received by slave device 120 may be input to a non-inverting input terminal of amplifier A8 in device 630B. Amplifier A8 in device 630B may generate a voltage representing an error between sensed current 217 and the highest sensed current (e.g., sensed current 217). In one example, in response to sensed current 217 being the highest sensed current among slave devices of system 100, a current based on voltage signal 609 may be the same as sensed current 217. Amplifier A2 of device 630B can output a voltage of a correction current IC10 that can generate a zero or null current to a pulse width modulator 602B of device 630B.

[0067] In Figure 6, device 630A is responsive to slave device 110 being a current source device and includes an internal resistor RINT, and device 230B is responsive to slave device 120 being a current source device and includes an internal resistor RINT. Resistor RINT can be fine-tuned to balance amplifier A7 in response to slave devices 110 and 120 being current source devices.

[0068] The pulse width modulator 602A can receive a PWM signal 607 from the PWM signal divider 610A and can receive a correction current IC9. In one example, the correction current IC9 can represent a difference between the external current 609 and the sensed current 207. The pulse width modulator 602A can use the correction current IC9 to modulate the PWM signal 607 to generate a modulated PWM signal 620A. The pulse width modulator 602A can modulate the PWM signal 607 by applying an offset to a leading edge, a falling edge, or both the leading and falling edges of the PWM signal 607, wherein the offset can be based on the correction current IC9.

[0069] The pulse width modulator 602B can receive a PWM signal 608 from the PWM signal divider 610B and can receive a correction current IC10. In response to a zero value in the correction current IC10, the pulse width modulator 602B may output the PWM signal 608 as a modulated PWM signal 620B without modulating the PWM signal 608. The pulse width modulator 602B can modulate the PWM signal 608 by applying an offset to a leading edge, a falling edge, or both the leading and falling edges of the PWM signal 608, wherein the offset may be based on the correction current IC10.

[0070] Any additional slave device in system 100 may modulate a copy of its own PWM signal based on a difference or error between the voltage generated by its own sensed current and the voltage signal 609 distributed on the common bus 603. By having all slave devices of system 100 modulate copies of their PWM signals to match the highest sensed current, system 100 can balance the current in the slave devices and use the PWM signal with the balanced current to drive the power converter (e.g., power converters 112 and 122 shown in FIG. 1).

[0071] The example shown in Figure 6 may include more than two slave devices. In one example where system 100 is a dual-phase counting (or two-phase counting) system, a common bus 603 and a trace 604 can be used to connect individual pairs of slave devices. For example, if system 100 is a dual-phase counting system including eight slave devices, a first common bus (e.g., common bus 603) and a first trace (e.g., trace 604) can connect a first pair of slave devices (e.g., slave devices 110 and 120), a second common bus and a second trace can connect a second pair of slave devices (e.g., a third slave device and a fourth slave device), and so on. In another example where system 100 is a three-phase counting system, the common bus 603 and the trace 604 can be used to connect individual slave device groups with three slave devices. For example, if System 100 includes a three-phase counting system with nine slave devices, a first common bus and a first trace can be connected to a first group of slave devices having a first, second, and third slave device, wherein one of the first, second, and third slave devices connects its P4 pin to the VCC of the master device, and a second common bus and a second trace can be connected to a second group of slave devices having a fourth, fifth, and sixth slave device, wherein one of the fourth, fifth, and sixth slave devices connects its P4 pin to the VCC (i.e., 3.3 V) of the master device, etc.

[0072] The systems and devices described herein allow a plurality of slave devices connected in parallel to perform various current sharing and balancing architectures. By enabling the slave devices to perform the current sharing architectures described herein, additional phase multipliers or current balancing circuits may not be required between the master and slave devices, resulting in a reduction in printed circuit board space. Furthermore, the devices described herein can be constructed using different components to perform different current sharing architectures, allowing the devices to be designed based on an application or other attributes (such as available board space on a printed circuit board). Additionally, the devices described herein can be integrated into slave devices of power converters with other types of integrated circuits without requiring excessive modifications to existing devices.

[0073] Figure 7 is a flowchart illustrating a current-sharing procedure 700 implemented in a slave device driven by a control signal (e.g., a PWM output) in a multi-phase system according to the present invention. The procedure may include one or more operations, actions, or functions, as illustrated by one or more of blocks 702, 704, 706, 708, 710, and / or 712. Although illustrated as discrete blocks, the various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, or executed in parallel, depending on the desired implementation.

[0074] Program 700 may begin at block 702. In block 702, a controller integrated into a first slave device may receive a PWM signal. The first device may include the controller and a power converter connected to the controller. Program 700 may continue from block 702 to block 704. In block 704, the controller may detect a sensed current in the first slave device. In one example, the sensed current in the first slave device may be a phase current associated with an output of the first slave device. Program 700 may continue from block 704 to block 706. In block 706, the controller may receive a voltage signal associated with a second slave device. The second device may include another power converter. Program 700 may continue from block 706 to block 708. In block 708, the controller may generate a correction current based on the sensed current and voltage signal. Program 700 may continue from block 708 to block 710. In block 704, the controller can use a corrected current-modulated PWM signal. Program 700 can continue from block 710 to block 712. In block 712, the controller can use the modulated PWM signal to control the power converter.

[0075] In a first embodiment, in response to the sensed current of the first slave device being less than the sensed current of the second slave device, the voltage signal may represent a difference between the sensed current of the first slave device and the sensed current of one of the second slave devices. The correction current may be a current difference between the sensed current and the current corresponding to the voltage signal (e.g., the sensed current that generates the voltage signal). If the sensed current is greater than or equal to the current corresponding to the voltage signal, the controller may output a zero-value current as the correction current and control the power converter using a PWM signal. Furthermore, in the first embodiment, the external current may be a difference between the sensed current of the first slave device and the highest sensed current of one of a plurality of slave devices connected in parallel via a common bus, wherein the plurality of slave devices may include the first slave device and the second slave device.

[0076] In a second embodiment, the voltage signal may be based on an average current of one of a plurality of sensed currents of a plurality of slave devices. The plurality of sensed currents may include a sensed current of a first slave device and a sensed current of a second slave device. The plurality of slave devices may include a first slave device and a second slave device. The plurality of slave devices may be connected in parallel via a common bus. The correction current may be a current difference between the sensed current and the average current.

[0077] In a third embodiment, the voltage signal may be based on a proportionally adjusted sensed current of one of the first slave devices. The correction current may be a current difference between the sensed current and the proportionally adjusted sensed current.

[0078] In a fourth embodiment, the voltage signal may be based on the sensed current of one of the second slave devices. The controller may be configured to determine an average current between the sensed current of the first slave device and the sensed current of the second slave device. The correction current may be a current difference between the sensed current of the first slave device and the average current.

[0079] In a fifth embodiment, the controller may divide the PWM signal into a first PWM signal and a second PWM signal. The first PWM signal and the second PWM signal may be out of phase. The controller may output the second PWM signal to a second slave device. Modulation of the PWM signal may include modulating the first PWM signal using a correction current.

[0080] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of feasible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions including one or more executable instructions for implementing one or more specified logical functions. In some alternative embodiments, the functions mentioned in the blocks may not occur in the order shown in the figures. For example, depending on the functionality involved, two blocks shown consecutively may actually be executed simultaneously, or such blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagram and / or flowchart illustration, and combinations of blocks in the block diagram and / or flowchart illustration, may be implemented by a dedicated hardware-based system that performs a specified function or action or implements a combination of dedicated hardware and computer instructions.

[0081] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms "a (a, an)" and "the" are intended to include the plural forms as well. It will be further understood that the terms "comprises and / or comprising," when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0082] All methods or steps plus functional elements, corresponding structures, materials, actions, and equivalents described in the following claims are intended to encompass any structure, material, or action used to perform a function in conjunction with other claimed elements as expressly claimed. The description of this invention has been made for illustrative and descriptive purposes, but is not intended to be exhaustive or limited to the invention as disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Examples have been chosen and described to best illustrate the principles and practical application of the invention, and to enable those skilled in the art to understand the invention with respect to various embodiments having modifications suitable for the particular purpose contemplated. [Simplified Explanation of the Diagram]

[0008] Figure 1 illustrates an example system according to the present invention, comprising a controller configured to support multiple power levels in a multi-phase system.

[0009] FIG2A illustrates a diagram of a device that can implement a current sharing architecture when the current sensing signal is output as a voltage sourced type according to the present invention.

[0010] Figure 2B illustrates a diagram of another device that can implement a current-shared architecture when the current sensing signal is output as a current-sourced type according to the present invention.

[0011] FIG3A illustrates a diagram of a device using an averaged current common architecture when the current sensing signal system is a voltage source type output according to the present invention.

[0012] FIG3B illustrates a diagram of another device that can be implemented using an averaged current common architecture when the current sensing signal is output as a current source type according to the present invention.

[0013] Figure 4 illustrates a diagram of a device that can be implemented using an averaging, proportionally adjusted current sharing architecture when the current sensing signal is output as a current source type according to the present invention.

[0014] Figure 5 illustrates a device according to the present invention that can implement a current common architecture for a two-phase system.

[0015] Figure 6 illustrates a device according to the present invention that can be implemented using a current common architecture of a pulse divider for interleaved operation.

[0016] Figure 7 is a flowchart illustrating a procedure for implementing current sharing in a slave device driven by a control signal in a multi-phase system according to the present invention.

Claims

1. A power stage device comprising: A controller integrated into a first slave device, the controller being configured to: detect a sensed current in the first slave device; receive a voltage signal associated with a second slave device connected to the first slave device; generate a correction current based on the sensed current of the first slave device and the voltage signal, wherein the correction current represents a current difference between the sensed current of the first slave device and at least one average current, the average current being the average current between the sensed current of the first slave device and the sensed current of the second slave device; and modulate a pulse width modulation (PWM) signal received by the first slave device using the correction current.

2. The power stage device of claim 1, wherein in response to the sensed current of the first slave device being less than a sensed current of the second slave device: the correction current represents a current difference between the sensed current of the first slave device and a current corresponding to the voltage signal.

3. As in request item 1, the power stage device, wherein: The voltage signal is based on the average current of one of a plurality of sensed currents of a plurality of slave devices; the plurality of sensed currents includes the sensed current of the first slave device and the sensed current of the second slave device; the plurality of slave devices includes two or more slave devices, the two or more slave devices including the first slave device and the second slave device; and in response to the voltage signal based on the average current of the plurality of sensed currents, the correction current further represents a current difference between the sensed current of the first slave device and the average current of the plurality of sensed currents.

4. As in request item 1, the power stage device, wherein: The voltage signal is based on the sensed current of one of the first slave devices by a proportional adjustment amount; and in response to the voltage signal based on the sensed current of the first slave device by a proportional adjustment amount, the correction current further represents a difference between the sensed current of the first slave device and the sensed current of the first slave device by a proportional adjustment amount.

5. As in request item 1, the power stage device, wherein: The voltage signal is based on the sensed current of the second slave device; and the controller is configured to determine the average current between the sensed current of the first slave device and the sensed current of the second slave device based on the voltage signal.

6. The power stage device of claim 1, wherein the controller is further configured to: divide the PWM signal into a first PWM signal and a second PWM signal, wherein the first PWM signal and the second PWM signal are out of phase; output the second PWM signal to the second slave device; and modulate the first PWM signal using the correction current.

7. The power stage device as claimed in claim 1, further comprising: A power converter is integrated into the first slave device, wherein the controller is configured to control the power converter using the modulated PWM signal.

8. A power stage system comprising: One main control device; A first subordinate device, which is connected to the master control device; A second slave device is connected to the master device and the first slave device, wherein: the first slave device is configured to: receive a first pulse width modulation (PWM) signal; detect a first sensed current; receive a first voltage signal associated with the second slave device; generate a first correction current based on the first sensed current and the first voltage signal; and modulate the first PWM signal using the first correction current; and the second slave device is configured to: receive a second PWM signal; detect a second sensed current; receive a second voltage signal associated with the first slave device; generate a second correction current based on the second sensed current and the second voltage signal; and modulate the second PWM signal using the second correction current.

9. The power stage system of claim 8, wherein the second PWM signal is the same PWM pulse as the first PWM signal, and in response to the sensed current of the first slave device being less than the sensed current of the second slave device: in response to the first sensed current being less than the second sensed current, the first correction current represents a first current difference between the first sensed current and the first external current; and in response to the first sensed current being less than the second sensed current, the second correction current is zero.

10. The power stage system as described in request item 8, wherein: The second PWM signal is the same PWM pulse as the first PWM signal; the first voltage signal and the second voltage signal are generated based on the average current of one of the plurality of sensed currents of the plurality of slave devices, and the first voltage signal and the second voltage signal are the same; the plurality of sensed currents include the first sensed current and the second sensed current; the plurality of slave devices includes two or more slave devices, and the two or more slave devices include the first slave device and the second slave device; the first correction current represents a first current difference between the first sensed current and the average current; and the second correction current represents a second current difference between the second sensed current and the average current.

11. As in request item 8, the power stage system, wherein: The second PWM signal is the same PWM pulse as the first PWM signal; the first voltage signal is based on the first sensed current of one of the first slave devices with a proportional adjustment amount, the proportional adjustment amount being based on a proportional adjustment factor; the second voltage signal is based on the second sensed current of one of the second slave devices with a proportional adjustment amount, the proportional adjustment amount being based on the proportional adjustment factor; the first correction current represents a first difference between the first sensed current and the first sensed current with the proportional adjustment amount; and the second correction current represents a current difference between the second sensed current and the second sensed current with the proportional adjustment amount.

12. As in the power stage system of request item 8, wherein: The second PWM signal is the same PWM pulse as the first PWM signal; the first voltage signal is generated based on the second sensed current; the first voltage signal is received by the first slave device from a first communication bus connected to one of the first slave device and the second slave device; the first slave device is configured to determine an average current between the first sensed current and the second sensed current based on the first voltage signal; the first correction current represents a first current difference between the first sensed current and the average current; the second voltage signal is generated based on the first sensed current; the second voltage signal is received by the second slave device from a second communication bus connected to one of the first slave device and the second slave device; the second slave device is configured to determine the average current between the first sensed current and the second sensed current based on the second voltage signal; and the second correction current represents a second current difference between the second sensed current and the average current.

13. As in request item 8, the power stage system, wherein: The first slave device is configured to: divide the first PWM signal into a second PWM signal and a third PWM signal, wherein the second PWM signal and the third PWM signal are out of phase; output the second PWM signal to the second slave device, wherein the modulation of the PWM signal includes modulation of one of the third PWM signals using the first correction current; the second slave device is configured to: receive the second PWM signal from the first slave device; and divide the second PWM signal into a fourth PWM signal and a fifth PWM signal, wherein the fourth PWM signal and the fifth PWM signal are out of phase, wherein the modulation of the second PWM signal includes modulation of one of the fourth PWM signals using the second correction current.

14. The power stage system of claim 8, wherein the master control device, the first slave device and the second slave device are part of a multi-phase power regulation system.

15. A method for controlling a device including a controller integrated in a first slave device, the method comprising: The controller detects a sensed current in one of the first slave devices; the controller receives a voltage signal associated with a second slave device connected to one of the first slave devices; the controller generates a correction current based on the sensed current of the first slave device and the voltage signal, wherein the correction current represents a current difference between the sensed current of the first slave device and at least one average current, the average current being the average current between the sensed current of the first slave device and the sensed current of the second slave device; the controller modulates a pulse width modulation (PWM) signal received by the first slave device using the correction current; and the controller controls a power converter using the modulated PWM signal.

16. The method of claim 15, wherein in response to the sensed current of the first slave device being less than the sensed current of the second slave device: the correction current further represents a current difference between the sensed current and a current corresponding to the voltage signal.

17. As in request item 15, wherein: The voltage signal is based on the average current of one of a plurality of sensed currents of a plurality of slave devices; the plurality of sensed currents includes the sensed current of the first slave device and the sensed current of the second slave device; the plurality of slave devices includes the first slave device and the second slave device; and in response to the voltage signal based on the average current of the plurality of sensed currents, the correction current further represents a current difference between the sensed current and the average current of the plurality of sensed currents.

18. As in request item 15, wherein: The voltage signal is based on the sensed current of one of the first slave devices by a proportional adjustment amount; and responds to the voltage signal based on the sensed current of the first slave device by a proportional adjustment amount, wherein the correction current further represents a current difference between the sensed current and the sensed current by the proportional adjustment amount.

19. As in request item 15, wherein: The voltage signal is based on the sensed current of the second slave device; and the method further includes, by means of the controller, determining the average current between the sensed current of the first slave device and the sensed current of the second slave device based on the voltage signal.

20. The method of claim 15, further comprising: The controller divides the PWM signal into a first PWM signal and a second PWM signal, wherein the first PWM signal and the second PWM signal are out of phase; and the controller outputs the second PWM signal to the second slave device; and the modulation of the PWM signal includes modulation of one of the first PWM signals using a correction current.

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