Gate driver for switching transistor of power supply circuit, power management integrated circuit, switched-mode power supply circuit, and method of supplying power

Abstract

Techniques and apparatus for driving the gate of a transistor in a switch-mode power supply (SMPS) circuit. In summary, an exemplary gate driver for a switching transistor in an SMPS circuit includes: a first power rail; a reference rail; an output node for coupling to a control input of the switching transistor; a floating power supply node; a pull-down transistor having a drain coupled to the output node of the gate driver and a source coupled to the reference rail; and a pull-down logic buffer having a first power input coupled to the floating power supply node, a second power input coupled to the reference rail, and an output coupled to the gate of the pull-down transistor. The floating power supply node is configured to selectively receive power from the first power rail and the output node of the gate driver.

Description

[Technical Field]

[0001] This patent application claims priority to U.S. Application No. 17 / 319,749, filed May 13, 2021, which has been assigned to the assignee of this application and whose entire contents are incorporated herein by reference.

[0002] In general, certain aspects of the content of this application relate to electronic circuits, and more specifically, certain aspects of the content of this application relate to driver architectures for switched-mode power supplies. [Previous Technology]

[0003] Ideally, a voltage regulator provides a constant direct current (DC) output voltage, regardless of variations in load current or input voltage. Voltage regulators can be classified as linear regulators or switching regulators. While linear regulators tend to be small and compact, many applications may benefit from the increased efficiency of switching regulators (also known as "switching converters"). For example, a linear regulator can be implemented using a low-dropout (LDO) regulator. Switching regulators can be implemented using a switch-mode power supply (SMPS) such as a buck converter, boost converter, buck-boost converter, or charge pump.

[0004] For example, a buck converter is a type of SMPS that typically includes: (1) a high-side switch coupled between a relatively high voltage rail and a switching node, (2) a low-side switch coupled between the switching node and a relatively low voltage rail, and (3) an inductor coupled between the switching node and a load (e.g., represented by a parallel capacitor element). The high-side and low-side switches are typically implemented using transistors (referred to as "switching transistors"), but the low-side switch can alternatively be implemented using diodes.

[0005] A charge pump is a type of SMPS that typically includes at least one switching element to control the connection of a supply voltage across a load via a capacitor. For example, in a voltage doubler, the capacitor in the charge pump circuit can initially be connected across the supply voltage, thereby charging the capacitor to the supply voltage. Subsequently, the charge pump circuit can be reconfigured to connect the capacitor in series with both the supply voltage and the load, thereby doubling the voltage across the load. This two-stage cycle repeats at the switching frequency used for the charge pump. The charge pump can be used to multiply or divide the voltage by an integer or fractional amount, depending on the circuit topology.

[0006] A power management integrated circuit (power management IC or PMIC) is used to manage the power requirements of a host system and may include and / or control one or more voltage regulators (e.g., buck converters or charge pumps). A PMIC can be used in battery-operated devices (such as mobile phones, tablets, laptops, wearable devices, etc.) to control the flow and direction of electrical power within the device. A PMIC can perform a wide variety of functions for the device, such as DC-DC conversion (e.g., using voltage regulators as described above), battery charging, power selection, voltage scaling, power sequencing, etc. [Summary of the Invention]

[0007] The systems, methods, and apparatuses of this invention each have several variations, with no single variation solely responsible for its desired properties. Without limiting the scope of this invention as expressed by the following claims, some features will now be briefly discussed. After considering this discussion, and especially after reading the section entitled "Detailed Description," those skilled in the art will understand how the features of this invention provide the advantages described herein.

[0008] Certain embodiments of this invention provide a gate driver for a switching transistor in a power supply circuit. In general, the gate driver includes: a first power rail; a reference rail; an output node for coupling to a control input of the switching transistor; a floating power supply node; a pull-down transistor having a drain coupled to the output node of the gate driver and a source coupled to the reference rail; and a pull-down logic buffer having a first power input coupled to the floating power supply node, a second power input coupled to the reference rail, and an output coupled to the gate of the pull-down transistor. The floating power supply node is configured to selectively receive power from the first power rail and the output node of the gate driver.

[0009] Certain forms of the content of this case provide a power management integrated circuit (PMIC), including the gate driver described herein.

[0010] Certain forms of the present invention provide a method for supplying power. In general, the method includes the steps of: receiving power from a first power rail of the gate driver at a floating power supply node to power a pull-down logic buffer of the gate driver; receiving power from a second power rail of the gate driver at the floating power supply node via an output node of the gate driver to power the pull-down logic buffer of the gate driver; and using the pull-down logic buffer to control a pull-down transistor coupled to the output node of the gate driver.

[0011] Certain forms of this invention provide a gate driver for a high-side transistor in a switch-mode power supply circuit. In general, the gate driver includes: a first power rail; a reference rail; an output node for coupling to the gate of the high-side transistor; a floating power supply node; a pull-down transistor having a drain coupled to the output node of the gate driver and a source coupled to the reference rail; a pull-down logic buffer having a first power input coupled to the floating power supply node, a second power input coupled to the reference rail, and an output coupled to the gate of the pull-down transistor; a first set of one or more diode elements coupled between the first power rail and the floating power supply node; a second set of one or more diode elements coupled between the output node of the gate driver and the floating power supply node; and a capacitor element coupled between the floating power supply node and the reference rail.

[0012] To achieve the foregoing and related objectives, one or more forms include the features fully described below and specifically pointed out in the claims. The following description and figures illustrate certain illustrative features of one or more forms in detail. However, these features indicate only a few of the various ways in which the principles of the various forms are employed.

Implementation Method

[0019] Certain aspects of this application provide techniques and apparatus for driving transistor gates in switch-mode power supply (SMPS) circuits. One exemplary apparatus is a gate driver with a floating power supply node configured to selectively receive power from at least two different sources.

[0020] The various forms of the present invention are described more fully below with reference to the accompanying drawings. However, the present invention may be embodied in many different forms and should not be construed as limited to any particular structure or function presented herein. Rather, these forms are provided so that the present invention will be comprehensive and complete, and fully convey the scope of the present invention to those skilled in the art. Based on the teachings herein, those skilled in the art should recognize that the scope of the present invention is intended to cover any form of the disclosed content herein, whether that form is implemented independently or in combination with any other form of the present invention. For example, an apparatus or a method may be implemented using any number of forms set forth herein. Furthermore, the scope of the present invention is intended to cover such an apparatus or method practiced using structures, functions, or structures and functions other than or different from the various forms of the present invention set forth herein. It should be understood that any form of the disclosed content herein may be embodied by one or more elements of the claim.

[0021] The term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any state described as “exemplary” herein is not necessarily to be construed as superior or advantageous over other states.

[0022] As used herein, the term "connected to" in various tenses of the verb "connect" can mean that element A is directly connected to element B, or that other elements can be connected between element A and B (i.e., element A and element B are indirectly connected). In the case of electronic components, the term "connected to" can also be used herein to mean that a conductor, trace, or other conductive material is used to electrically connect element A and B (and any elements electrically connected therebetween). Exemplary Device

[0023] It should be understood that various forms of the content of this application can be used in a wide variety of applications. Although the content of this application is not limited to this point, the circuits disclosed herein can be used in any of a wide variety of suitable devices, such as power supply, battery charging circuits, or power management circuits in communication systems, video transcoders, audio devices (such as music players and microphones), televisions, camera devices, and test equipment (such as oscilloscopes). By way of example only, communication systems intended to be included within the scope of this application include cellular radiotelephone communication systems, satellite communication systems, two-way radio communication systems, one-way pagers, two-way pagers, personal communication systems (PCS), personal digital assistants (PDAs), etc.

[0024] Figure 1 illustrates an exemplary device 100 in which various forms of the present invention may be implemented. Device 100 may be a battery-operated device, such as a cellular phone, PDA, handheld device, wireless device, laptop, tablet device, smartphone, Internet of Things (IoT) device, wearable device, etc.

[0025] Device 100 may include a processor 104 that controls the operation of device 100. Processor 104 may also be referred to as a central processing unit (CPU). Memory 106, which may include both read-only memory (ROM) and random access memory (RAM), provides instructions and data to processor 104. A portion of memory 106 may also include non-volatile random access memory (NVRAM). Processor 104 typically performs logical and arithmetic operations based on program instructions stored in memory 106.

[0026] In some embodiments, device 100 may also include housing 108, which may include transmitter 110 and receiver 112 to allow data transmission and reception between device 100 and a remote location. In some embodiments, transmitter 110 and receiver 112 may be combined into transceiver 114. One or more antennas 116 may be attached to or otherwise coupled to housing 108 and electrically coupled to transceiver 114. Device 100 may also include (not shown) multiple transmitters, multiple receivers, and / or multiple transceivers.

[0027] Device 100 may also include a signal detector 118, which may be used to attempt to detect and quantize the level of the signal received by transceiver 114. The signal detector 118 may detect signal parameters such as total energy, energy per symbol per carrier, and power spectral density. Device 100 may also include a digital signal processor (DSP) 120 for processing the signal.

[0028] Device 100 may also include a battery 122 for powering various components of device 100. Device 100 may also include a power management integrated circuit (power management IC or PMIC) 124 for managing power from the battery to various components of device 100. PMIC 124 may perform a wide variety of functions for the device, such as DC-DC conversion, battery charging, power selection, voltage scaling, power sequencing, etc. In some embodiments, PMIC 124 may include at least a portion of a power supply circuit, which may include a switch-mode power supply circuit 125. In some embodiments, PMIC 124 may include multiple power supply circuits or at least a portion thereof, and the multiple power supply circuits may share one or more voltage rails (e.g., VDD and / or VDDH as described below). The switch-mode power supply circuit 125 may be implemented by any of a variety of suitable switch-mode power supply circuit topologies, such as a buck converter, a boost converter, an inverting buck-boost converter, or a charge pump. In some embodiments, PMIC 124 may include a battery charging circuit (e.g., a master-slave battery charging circuit). For certain configurations, the power supply circuit may include a gate driver with a floating power node configured to selectively receive power from at least two different sources, as described herein.

[0029] Various components of device 100 can be coupled together via bus system 126, which may include power buses, control signal buses, and / or status signal buses in addition to data buses. Exemplary power circuit

[0030] Figure 2 is a block diagram of an exemplary power supply circuit 200 in which the contents of this invention may be practiced. The power supply circuit 200 may include control logic 210, one or more gate drivers 220, and a switching regulator 230. The control logic 210 may be implemented by, for example, a state machine and may output control signals to control the timing of elements in the gate driver 220. The gate driver 220 may output signals with a specified output signal swing to control the control input (e.g., the gate) of the switching element (e.g., a switching transistor, such as a power MOSFET) in the switching regulator 230. As described herein, one or more of the gate drivers 220 may have floating power supply nodes configured to selectively receive power from at least two different sources (e.g., a power rail for the gate driver and an output node of the gate driver). The switching regulator 230 may be implemented as any of a variety of suitable switching converter topologies, such as a buck converter, a boost converter, a buck-boost converter, a charge pump, etc. The switching regulator 230 may include a high-voltage side transistor and a low-voltage side transistor.

[0031] A high-voltage side n-type field-effect transistor (NFET) power stage may be more desirable than a high-voltage side p-type field-effect transistor (PFET) power stage because NFETs have a higher figure of merit compared to PFETs. For example, a buck converter with a high-voltage side NFET power stage typically has higher peak efficiency for the same drain-source on-resistance (Rds,on) compared to a high-voltage side PFET power stage. To provide overdrive to the gate-source voltage (VGS) of the high-voltage side NFET, thereby reducing Rds,on to improve efficiency, it may be desirable to provide a power supply with a voltage greater than the input voltage (e.g., the drain voltage for the NFET) to the gate driver used for the high-voltage side NFET. In this case, a "boot" capacitor can be used to provide a source of charge to drive the gate of the high-voltage side NFET using the gate driver. A pilot capacitor may be coupled between the power supply terminals of the high-side gate driver, one power supply terminal being coupled to a power rail having a voltage greater than the input voltage, and the other power supply terminal being coupled to a switching node of the switching regulator 230 (e.g., between the high-side and low-side transistors). The pilot capacitor may be an external component or an integrated component (e.g., external to or integrated into a PMIC or other integrated circuit (IC) having the gate driver 220 and the switching regulator 230). External capacitors are typically coupled to IC pins, so each such switching regulator IC may have IC pins for connecting to its respective external pilot capacitor. Although integrated capacitors do not require external access via IC pins, they may occupy a significant area within the IC die. An exemplary gate driver with a floating pilot power supply.

[0032] Certain embodiments of this invention provide means and techniques for driving the gate of a power transistor in a switching regulator using a significantly smaller pilot capacitor. This can be achieved using a gate driver architecture in which a pull-down path is located on a floating pilot power supply. This floating pilot power supply can be configured to receive power from at least two different sources and charge the pilot capacitor via at least two different charging paths. The gate driver architecture can also have a pull-up path to a high-voltage power supply (greater than the input voltage of the high-voltage side transistor), and this high-voltage power supply can be shared among multiple switching regulators.

[0033] Figure 3 is a circuit diagram of a power supply circuit 300 having a buck converter 301, a high-side gate driver 302, and a low-side gate driver 304, according to certain embodiments of the present invention. In this example, the switch-mode power supply (e.g., the switching regulator 230) is implemented as a buck converter. However, it will be understood that the switch-mode power supply can alternatively be implemented as any of a variety of other suitable switch converter topologies, such as a boost converter, a buck-boost converter, a three-position quasi-buck converter, or a charge pump.

[0034] As shown in FIG. 3, the buck converter 301 includes a high-side switching transistor M3, a low-side switching transistor M4, a series inductor L (e.g., implemented by one or more inductors), and a parallel capacitor Cout (e.g., implemented by one or more capacitors). The high-side transistor M3 may be implemented by an n-type transistor (e.g., an n-type field-effect transistor (NFET)), as shown. In this case, the transistor M3 may have a drain coupled to a first power rail 322 (labeled "VDD"), a source coupled to a switching node of the buck converter (labeled "VSW"), and a gate coupled to the output node 313 of the high-side gate driver 302. The low-side transistor M4 may also be implemented by an n-type transistor (e.g., an NFET), as shown. In this configuration, transistor M4 may have a drain coupled to the switching node, a source coupled to the reference potential node of the buck converter (e.g., ground 327), and a gate coupled to the output of the low-side gate driver 304. An inductor L may be coupled between the switching node and the output node of the buck converter (labeled "VOUT"), and a capacitor Cout may be coupled between the output node of the buck converter and the reference potential node.

[0035] The low-side gate driver 304 can receive an input signal (labeled "LS_in") and drive the gate of the switching transistor M4 based on LS_in. The input signal LS_in can represent a low-side pull-up input signal and a low-side pull-down input signal (not shown). The low-side gate driver 304 can have a first power input coupled to a first power rail 322 (VDD) and a second power input coupled to a reference potential node of the buck converter. Therefore, the low-side gate driver 304 can output a control signal with a voltage ranging from 0 V to VDD.

[0036] The high-voltage side gate driver 302 can receive a high-voltage side pull-up input signal (labeled "HS_in_pullup") and a high-voltage side pull-down input signal (labeled "HS_in_pulldown"), and drive the gate of the switching transistor M3 based on these high-voltage side input signals. The high-voltage side gate driver 302 may include a high-voltage side pull-up logic buffer 306, a high-voltage side pull-down logic buffer 308, a pull-up transistor M1, a pull-down transistor M2, a first set of one or more diode elements 310, a second set of one or more diode elements 312, and a capacitor element Cboot (e.g., implemented by one or more capacitors). The pull-up logic buffer 306 may have an input that receives the HS_in_pullup signal, a first power input 315 coupled to the second power rail 324 (labeled "VDDH"), a second power input 316 coupled to the first power rail 322 (VDD), and an output 317 coupled to the gate of the transistor M1. In this manner, the pull-up logic buffer 306 can output a control signal with a voltage ranging from VDD to VDDH. The transistor M1 can be a p-type transistor (e.g., a p-type field-effect transistor (PFET)), may have a source (and body) coupled to the second power rail 324, and may have a drain coupled to the output node 313 of the high-side gate driver 302. The second power rail 324 may have a higher voltage than the first power rail 322 (VDDH > VDD), allowing the high-side gate driver 302 to pull up the output node 313 to a voltage level greater than VDD, and reducing the drain-source on-resistance of the switching transistor M3, thereby reducing conduction losses through the transistor M3 and improving the efficiency of the buck converter.

[0037] The pull-down logic buffer 308 may have an input that receives the HS_in_pulldown signal, a first power input 319 coupled to a floating power supply node 311 (labeled "Vfloat"), a second power input 320 coupled to a reference rail 323 of the high-side gate driver 302, and an output 318 coupled to the gate of transistor M2. The reference rail 323 of the high-side gate driver 302 may be coupled to the switching node VSW of the buck converter. In this way, the pull-down logic buffer 308 is referenced to VSW (i.e., to the source of the switching transistor M3, rather than, for example, to ground), and may output a control signal with a voltage ranging from VSW to Vfloat, where VSW can swing from 0 V to VDD, depending on the duty cycle of the buck converter. Transistor M2 may be an n-type transistor (e.g., an NFET), may have a source (and body) coupled to the reference rail 323, and may have a drain coupled to the output node 313 of the high-side gate driver 302.

[0038] A first group of one or more diode elements 310 may be coupled between the first power rail 322 (VDD) and the floating power supply node 311. The first group of diode elements 310 may include one or more unidirectional elements (also referred to as current guiding elements). For example, the first group of diode elements 310 may be implemented by a diode or a diode-connected transistor. In this case, the diode (or diode-connected transistor) in the first group may have an anode coupled to the first power rail 322 and may have a cathode coupled to the floating power supply node 311. When the first group of diode elements 310 includes multiple diode elements, these elements may be connected in series.

[0039] A second group of one or more diode elements 312 may be coupled between the output node 313 of the high-side gate driver 302 and the floating power supply node 311. The second group of diode elements 312 may include one or more unidirectional elements. For example, the second group of diode elements 312 may be implemented by a diode or a diode-connected transistor. In this case, the diode (or diode-connected transistor) in the second group may have an anode coupled to the output node 313 of the high-side gate driver 302 and may have a cathode coupled to the floating power supply node 311. When the second group of diode elements 310 includes multiple diode elements, these elements may be connected in series. For some cases, the second group of diode elements 312 may include a buffer, such as a source follower. In this case, the source follower may include a transistor (e.g., an NFET) having a gate coupled to the output node 313 and a source coupled to the floating power supply node 311.

[0040] The capacitor element Cboot is coupled between the floating power supply node 311 and the reference rail 323. Compared to conventional gate drivers, the capacitor element Cboot can have a smaller capacitance (e.g., approximately 20 pF) and can occupy a smaller area. The first set of diode elements 310 and the second set of diode elements 312 provide two different charging paths via the capacitor element Cboot.

[0041] During operation, logic buffers 306 and 308 can receive control signals (e.g., HS_in_pullup and HS_in_pulldown) from the control logic, and output signals for driving the gates of transistors M1 and M2. In some states, the buffer output signals can have a higher voltage swing compared to the control signals received from the control logic (e.g., lower logic level signals). For example, the output signal from pull-up logic buffer 306 can swing between VDD and VDDH, where VDDH is greater than VDD, and the output signal from pull-down logic buffer 308 can swing between VSW and Vfloat. When HS_in_pulldown is asserted (and HS_in_pullup is deasserted) causing pull-down transistor M2 to be turned on (and pull-up transistor M1 to be turned off), the gate driver output node 313 will be pulled down to the voltage (VSW) of reference rail 323, causing high-voltage side switching transistor M3 to be turned off. In this configuration, the floating power node 311 can receive power from the first power rail 322 via the first set of diode elements 310, and therefore Vfloat can be close to VDD (e.g., one or more forward-biased diodes descend from VDD). The output node 313 is at VSW, so the second set of diode elements 312 is reverse-biased (in this scenario, VSW is less than VDD). Therefore, as the first charging path, the capacitor element Cboot can be charged via the first set of diode elements 310.

[0042] At other times, when HS_in_pulldown is de-asserted (and HS_in_pullup is asserted), causing pull-down transistor M2 to turn off (and pull-up transistor M1 to turn on), the output node 313 of the gate driver will be pulled up to VDDH, causing high-voltage side switching transistor M3 to turn on and VSW to rise to VDD. In this scenario, the floating power supply node 311 can receive power from the second power rail 324 via pull-up transistor M1, output node 313, and the second set of diode elements 312, and therefore Vfloat can approach VDDH (e.g., one or more forward-biased diodes fall from VDDH). Since Vfloat is approximately VDDH, which is greater than VDD, the first set of diode elements 310 is reverse-biased in this scenario. Therefore, as a second charging path, the capacitor element Cboot can be charged via pull-up transistor M1 and the second set of diode elements 312.

[0043] In this manner, based on the switching frequency and duty cycle of the buck converter 301 controlled by the control logic, the output signal from the high-side gate driver 302 on the output node 313 can be pulled down to VSW to turn off the switching transistor M3, and can be pulled up to VDDH (e.g., pulled up to the second power rail 324) to turn on the transistor M3. Similarly, another output signal from the low-side gate driver 304 can be used to control the operation of the switching transistor M4, wherein the gate can be pulled up to VDD (logic high level) to turn on the transistor M4, and can be pulled down to ground (logic low level) to turn off the transistor M4. The gate signal can operate in a break-before-make manner, such that the transistor M3 is turned off before the transistor M4 is turned on, and vice versa. As explained above, VOUT is controlled based on the duty cycles of the switching transistors M3 and M4.

[0044] In addition to the smaller area, the gate driver architecture described herein offers several advantages due to its smaller pilot capacitance and reduced pilot capacitor area. For example, the gate driver architecture supplies charge to the pilot capacitor during both the on and off phases of the high-voltage side switching transistor, rather than only when the high-voltage side switching transistor is off (when VSW=0 V). This removes concerns about discharge paths for large pilot capacitors in conventional gate driver architectures, and therefore, the switching regulator does not need to be limited to maximum duty cycles and can operate at 100% duty cycles. Furthermore, the gate driver architecture described herein has a pull-down path that returns the gate charge of the high-voltage side switching transistor to the regulator output instead of ground, resulting in higher efficiency. Additionally, sharing a higher voltage supply rail (VDDH) among multiple switching regulators eliminates large pilot capacitors (external or integrated) for pull-up paths in the regulator, thereby reducing overall system cost and area. Exemplary operation for power supply

[0045] Figure 4 is a flowchart of an exemplary operation 400 for supplying power according to certain aspects of the present invention. Operation 400 may be performed by a power supply circuit (e.g., power supply circuit 300) having a gate driver having a floating power node configured to selectively receive power from at least two different sources (such as the high-voltage side gate driver 302 of Figure 3).

[0046] Operation 400 may begin at block 402 as follows: A floating power supply node (e.g., floating power supply node 311) of the gate driver (e.g., high-voltage side gate driver 302) receives power (e.g., receives current) from the first power rail (e.g., first power rail 322 (VDD)) of the gate driver to power a pull-down logic buffer (e.g., pull-down logic buffer 308) of the gate driver. At block 404, the floating node may receive power (e.g., receives current) from the second power rail (e.g., second power rail 324 (VDDH)) of the gate driver via the output node (e.g., output node 313) of the gate driver to power the pull-down logic buffer of the gate driver. At block 406, the pull-down logic buffer may control the pull-down transistor (e.g., transistor M2) coupled to the output node of the gate driver.

[0047] Depending on certain configurations, operation 400 may also involve receiving power from a second power rail to power a pull-up logic buffer (e.g., pull-up logic buffer 306). The pull-up logic buffer may reference a first power rail, which may have a higher voltage than the first power rail. In this case, the pull-up logic buffer may control a pull-up transistor (e.g., transistor M1) coupled to the output node of the gate driver. The pull-up transistor may be coupled between the second power rail and the output node, and / or a pull-down transistor may be coupled between the output node and a reference rail of the gate driver (e.g., reference rail 323). For example, the pull-up transistor may have a drain coupled to the output node of the gate driver and a source coupled to the second power rail. The pull-down transistor may have a drain coupled to the output node of the gate driver and a source coupled to the reference rail. The reference rail may be coupled to a switching node (e.g., node VSW) of a switch-mode power supply (e.g., a buck converter, such as buck converter 301). Operation 400 may also include charging a capacitive element (e.g., capacitor Cboot) coupled between the floating power supply node and the reference rail via the output node of the gate driver from at least one of the first or second power rails. The capacitive element may be charged during the on and off phases of the switching transistor (e.g., transistor M3).

[0048] According to certain states, when the pull-down transistor is turned on and the pull-up transistor is turned off, the power at the floating power supply node is received from the first power rail (e.g., at block 402). For certain states, when the pull-up transistor is turned on and the pull-down transistor is turned off, the power at the floating power supply node is received from the second power rail (e.g., at block 404).

[0049] According to certain embodiments, receiving power from the first power rail at block 402 involves receiving power via a first set of one or more diode elements (e.g., a first set of one or more diode elements 310) coupled between the first power rail and the floating power supply node. The first set of one or more diode elements may include a diode or a diode-connected transistor having an anode coupled to the first power rail and a cathode coupled to the floating power supply node. For certain embodiments, receiving power from the second power rail at block 404 via the output node of the gate driver involves receiving power via a second set of one or more diode elements (e.g., a second set of one or more diode elements 312) coupled between the output node of the gate driver and the floating power supply node. The second set of one or more diode elements may include a diode or a diode-connected transistor having an anode coupled to the output node of the gate driver and a cathode coupled to the floating power supply node. Alternatively, the second group of one or more diode elements may include a source follower having a transistor having a gate coupled to an output node and a source coupled to a floating power supply node. Exemplary State

[0050] In addition to the above-mentioned individual forms, the specific combinations of these forms are also within the scope of this case. Some of these forms are described in detail below:

[0051] Sample 1: A gate driver for a switching transistor in a power supply circuit, the gate driver comprising: a first power rail; a reference rail; an output node for coupling to a control input of the switching transistor; a floating power supply node; a pull-down transistor having a drain coupled to the output node of the gate driver and a source coupled to the reference rail; and a pull-down logic buffer having a first power input coupled to the floating power supply node, a second power input coupled to the reference rail, and an output coupled to the gate of the pull-down transistor, wherein the floating power supply node is configured to selectively receive power from the first power rail and the output node of the gate driver.

[0052] State 2: The gate driver according to State 1 also includes: a first group of one or more diode elements coupled between the first power rail and the floating power supply node; a second group of one or more diode elements coupled between the output node of the gate driver and the floating power supply node; and a capacitor element coupled between the floating power supply node and the reference rail.

[0053] State 3: Gate driver according to State 2, wherein the first group of one or more diode elements includes a diode or a diode-connected transistor, the diode having an anode coupled to the first power rail and a cathode coupled to the floating power supply node.

[0054] State 4: A gate driver according to State 2 or State 3, wherein the second group of one or more diode elements includes a diode or a diode-connected transistor, the diode having an anode coupled to the output node of the gate driver and a cathode coupled to the floating power supply node.

[0055] State 5: Gate driver according to State 2 or State 3, wherein the second group of one or more diode elements includes a source follower having a transistor having a gate coupled to the output node and a source coupled to the floating power supply node.

[0056] State 6: The gate driver according to any of the aforementioned states also includes: a second power rail having a higher voltage than the first power rail; a pull-up transistor having a drain coupled to the output node of the gate driver and a source coupled to the second power rail; and a pull-up logic buffer having a first power input coupled to the second power rail, a second power input coupled to the first power rail, and an output coupled to the gate of the pull-up transistor.

[0057] State 7: Gate driver according to state 6, wherein the pull-down transistor includes an n-type transistor and wherein the pull-up transistor includes a p-type transistor.

[0058] State 8: Gate driver according to any of the aforementioned states, wherein the floating power supply node is configured to supply charge during the turn-on and turn-off phases of the switching transistor.

[0059] State 9: A power management integrated circuit (PMIC) including a gate driver according to any of the aforementioned states.

[0060] State 10: A switch-mode power supply circuit including a gate driver according to any of the aforementioned states, the switch-mode power supply circuit also including: a switching transistor having a drain coupled to the first power rail, a gate coupled to the output node of the gate driver, and a source coupled to the reference rail of the gate driver; another gate driver; and another switching transistor having a drain coupled to the source of the switching transistor, a source coupled to the reference potential node of the switch-mode power supply circuit, and a gate coupled to the output node of the other gate driver.

[0061] Sample 11: A gate driver for a high-voltage side transistor in a switch-mode power supply circuit, the gate driver comprising: a first power rail; a reference rail; an output node for coupling to the gate of the high-voltage side transistor; a floating power supply node; a pull-down transistor having a drain coupled to the output node of the gate driver and a source coupled to the reference rail; a pull-down logic buffer having a first power input coupled to the floating power supply node, a second power input coupled to the reference rail, and an output coupled to the gate of the pull-down transistor; a first set of one or more diode elements coupled between the first power rail and the floating power supply node; a second set of one or more diode elements coupled between the output node of the gate driver and the floating power supply node; and a capacitor element coupled between the floating power supply node and the reference rail.

[0062] Sample 12: A method of supplying power, comprising the steps of: receiving power from a first power rail of the gate driver at a floating power supply node of the gate driver to power a pull-down logic buffer of the gate driver; receiving power from a second power rail of the gate driver at the floating power supply node via an output node of the gate driver to power the pull-down logic buffer of the gate driver; and using the pull-down logic buffer to control a pull-down transistor coupled to the output node of the gate driver.

[0063] State 13: The method according to State 12 also includes the following steps: receiving power from the second power rail to power a pull-up logic buffer, the pull-up logic buffer being referenced to the first power rail; and using the pull-up logic buffer to control the pull-up transistor coupled to the output node of the gate driver.

[0064] State 14: According to the method of State 13, wherein: the pull-up transistor is coupled between the second power rail and the output node; the pull-down transistor is coupled between the output node and the reference rail of the gate driver; and the reference rail is coupled to the switching node of the switch mode power supply.

[0065] State 15: The method according to State 14 also includes the following steps: charging the capacitor element coupled between the floating power supply node and the reference rail from at least one of the first power rail or the second power rail via the output node of the gate driver.

[0066] State 16: According to the method of State 13, wherein: the power at the floating power supply node is received from the first power rail when the pull-down transistor is turned on and the pull-up transistor is turned off; and the power at the floating power supply node is received from the second power rail when the pull-up transistor is turned on and the pull-down transistor is turned off.

[0067] State 17: The method according to any one of States 12-16, wherein: receiving power from the first power rail includes: receiving power via a first set of one or more diode elements coupled between the first power rail and the floating power supply node; and receiving power from the second power rail via the output node of the gate driver includes: receiving power via a second set of one or more diode elements coupled between the output node of the gate driver and the floating power supply node.

[0068] The various operations of the methods described above can be performed by any suitable component capable of performing the corresponding function. Such components may include various hardware and / or software elements and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Typically, where the operations illustrated in the figures are present, those operations may have corresponding paired functional component elements with similar numbering.

[0069] As used herein, the term "decision" encompasses a wide variety of actions. For example, "decision" can include calculation, operation, processing, deduction, investigation, examination (e.g., examining in a table, database, or other data structure), ascertainment, and so on. Furthermore, "decision" can include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), and so on. In addition, "decision" can include parsing, selecting, choosing, building, and so on.

[0070] As used herein, the phrase “at least one of” in a list of items means any combination of those items, including a single member. For example, “at least one of a, b, or c” is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination having multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbb, cc, and ccc, or any other ordering of a, b, and c).

[0071] The methods disclosed herein include one or more steps or actions for implementing the described methods. Method steps and / or actions may be interchanged without departing from the scope of the claim. In other words, unless a specific order of steps or actions is specified, the order and / or use of a particular step and / or action may be modified without departing from the scope of the claim.

[0072] It should be understood that the requested items are not limited to the precise configuration and components described above. Various modifications, alterations and variations can be made to the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the requested items. [Simplified Explanation of the Diagram]

[0013] A more detailed description, as briefly summarized above, can be provided by referring to some of the embodiments illustrated in the accompanying drawings, so that the aforementioned features of the present invention can be understood in detail. However, it should be noted that the accompanying drawings only illustrate some typical embodiments of the present invention and are therefore not to be considered as limiting its scope, as the specification may allow for other equally valid embodiments.

[0014] Figure 1 is a block diagram of an exemplary device including a switch-mode power supply (SMPS) circuit of various forms in which the contents of this case can be practiced.

[0015] Figure 2 is a block diagram of various exemplary power supply circuits in which the contents of this case can be practiced.

[0016] Figure 3 is a circuit diagram of a buck converter and an exemplary high-voltage side gate driver for driving the gate of a high-voltage side switching transistor according to certain aspects of the present invention.

[0017] Figure 4 is a flowchart of an exemplary operation for supplying electricity according to certain aspects of the present case.

[0018] To facilitate understanding, the same element symbols have been used where possible to designate identical elements that are common to the drawings. Elements disclosed in one configuration may be beneficially used in other configurations without specific description. [Biomaterial Storage]

[0074] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A gate driver for a switching transistor in a power supply circuit, the gate driver comprising: First power rail; One reference rail; An output node used to couple to a control input of the switching transistor; A floating power supply node; a pull-down transistor having a drain coupled to the output node of the gate driver and a source coupled to the reference rail; And a pull-down logic buffer having a first power input coupled to the floating power node, a second power input coupled to the reference rail, and an output coupled to a gate of the pull-down transistor, wherein the floating power node is configured to selectively receive power from the first power rail and the output node of the gate driver.

2. The gate driver according to claim 1 also includes: A first group of one or more diode elements coupled between the first power rail and the floating power supply node; A second group of one or more diode elements coupled between the output node of the gate driver and the floating power supply node; and a capacitor element coupled between the floating power supply node and the reference rail.

3. The gate driver according to claim 2, wherein the first group of one or more diode elements includes a diode or a diode-connected transistor, the diode having an anode coupled to the first power rail and a cathode coupled to the floating power supply node.

4. The gate driver according to claim 2, wherein the second group of one or more diode elements includes a diode or a diode-connected transistor, the diode having an anode coupled to the output node of the gate driver and a cathode coupled to the floating power supply node.

5. The gate driver according to claim 2, wherein the second group of one or more diode elements includes a source follower having a transistor having a gate coupled to the output node and a source coupled to the floating power supply node.

6. The gate driver according to claim 1 also includes: A second power rail having a voltage higher than the first power rail; A pull-up transistor having a drain coupled to the output node of the gate driver and a source coupled to the second power rail; and a pull-up logic buffer having a first power input coupled to the second power rail, a second power input coupled to the first power rail, and an output coupled to a gate of the pull-up transistor.

7. The gate driver according to claim 6, wherein the pull-down transistor comprises an n-type transistor, and wherein the pull-up transistor comprises a p-type transistor.

8. The gate driver according to claim 1, wherein the floating power supply node is configured to supply charge during an on-phase and an off-phase of the switching transistor.

9. A power management integrated circuit (PMIC) including a gate driver according to claim 1.

10. A switch-mode power supply circuit, including a gate driver according to claim 1, the switch-mode power supply circuit also including: The switching transistor has a drain coupled to the first power rail, a gate coupled to the output node of the gate driver, and a source coupled to the reference rail of the gate driver; another gate driver; and another switching transistor has a drain coupled to the source of the switching transistor, a source coupled to a reference potential node of the switch-mode power supply circuit, and a gate coupled to the output node of the other gate driver.

11. A gate driver for a high-voltage side transistor in a switch-mode power supply circuit, the gate driver comprising: First power rail; One reference rail; An output node used to couple to a gate of the high-voltage side transistor; A floating power supply node; a pull-down transistor having a drain coupled to the output node of the gate driver and a source coupled to the reference rail; a pull-down logic buffer having a first power supply input coupled to the floating power supply node, a second power supply input coupled to the reference rail, and an output coupled to a gate of the pull-down transistor; A first group of one or more diode elements coupled between the first power rail and the floating power supply node; a second group of one or more diode elements coupled between the output node of the gate driver and the floating power supply node; and a capacitor element coupled between the floating power supply node and the reference rail.

12. A method of supplying power, comprising the steps of: receiving power from a first power rail of a gate driver at a floating power supply node to power a pull-down logic buffer of the gate driver; receiving power from a second power rail of the gate driver at the floating power supply node via an output node of the gate driver to power the pull-down logic buffer of the gate driver; and using the pull-down logic buffer to control a pull-down transistor coupled to the output node of the gate driver.

13. The method according to claim 12 also includes the steps of: receiving power from the second power rail to power a pull-up logic buffer, the pull-up logic buffer being referenced to the first power rail; and using the pull-up logic buffer to control a pull-up transistor coupled to the output node of the gate driver.

14. According to the method of request item 13, wherein: The pull-up transistor is coupled between the second power rail and the output node; The pull-down transistor is coupled between the output node and a reference rail of the gate driver; and the reference rail is coupled to a switching node of a switch-mode power supply.

15. The method according to claim 14 also includes the step of charging a capacitor element coupled between the floating power supply node and the reference rail from at least one of the first power rail or the second power rail via the output node of the gate driver.

16. According to the method of request item 13, wherein: The power at the floating power supply node is received from the first power rail when the pull-down transistor is turned on and the pull-up transistor is turned off; and the power at the floating power supply node is received from the second power rail when the pull-up transistor is turned on and the pull-down transistor is turned off.

17. According to the method of request item 12, wherein: The step of receiving power from the first power rail includes the following steps: receiving power via a first group of one or more diode elements coupled between the first power rail and the floating power supply node; The step of receiving power from the second power rail via the output node of the gate driver includes the following steps: receiving power via a second group of one or more diode elements coupled between the output node of the gate driver and the floating power supply node.

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