Process integration to reduce contact resistance in semiconductor device

Abstract

This document provides various methods for forming nanosheet field-effect transistor (FET) devices with reduced source / drain contact resistance. In some embodiments, a method of forming a FET device includes: etching a nanosheet stack of the nanosheet FET device to form a plurality of first source / drain regions and a plurality of second source / drain regions, the nanosheet stack including alternating layers of a plurality of nanosheet channel layers and a plurality of sacrificial nanosheet layers; depositing silicon layers at the ends of the nanosheet channel layers in the plurality of first source / drain regions through a selective siliconization process to control the length of the nanosheet channel layers between the first source / drain regions; and performing a metal-filling process to fill the plurality of first source / drain regions, wherein the metal filler extends from the lowermost nanosheet channel layer to the uppermost nanosheet channel layer to contribute to the reduced source / drain contact resistance.

Description

Technical Field

[0001] The embodiments disclosed in this case generally relate to semiconductor devices, and more specifically, to nanosheet field-effect transistor device structures. Prior Technology

[0002] Transistors are circuit components or elements typically formed on semiconductor devices. Depending on the circuit design, many transistors can be formed on semiconductor devices in addition to capacitors, inductors, resistors, diodes, conductors, or other components. Integrated circuits also include planar field-effect transistors (FETs), in which current flows through a semiconductor channel between the source and drain in response to a voltage applied to the control gate. As device size has shrunk, new device geometries, structures, and materials have presented challenges in maintaining switching speed without inducing failure.

[0003] Several new technologies have emerged that have allowed chip designers to continue shrinking gate lengths. One particularly impactful technological shift required redesigning the FET structure from a planar element to a three-dimensional element, where the semiconductor channel is replaced by fins extending from the substrate plane. In such an element (often called a FinFET), the control gate surrounds three sides of the fins to influence current from three surfaces instead of one. The improved control achieved with the three-dimensional design results in faster switching performance and reduced current leakage.

[0004] The concept of FinFET was extended by developing gate-all-around FETs (GAA FETs), where the gate completely surrounds the channel to maximize control over the current. In GAA FETs, the channel can take the form of cylindrical nanowires isolated from the substrate. Existing GAA FETs are horizontally oriented, causing the nanowires to extend parallel to the surface of the semiconductor substrate.

[0005] The FinFET concept has been further expanded through the development of nanosheet FET devices, which are similar to the concept of columnar nanowires, except that the device channel comprises one or more nanosheet layers arranged in a stacked configuration, where the width of each nanosheet layer is substantially greater than its thickness. A common gate structure is formed above and below each nanosheet layer, and the increased width, compared to nanowire structures, contributes to an increase in drive current (for a given footprint). However, as three-dimensional device dimensions continue to shrink, the contact resistance of the source / drain regions in nanosheet device structures may become excessively high due to the limited contact surface area between the source / drain regions and the corresponding metal contacts.

[0006] Therefore, the inventors provide embodiments herein of nanosheet FET devices and methods for forming such devices, which have reduced source / drain contact resistance. Summary of the Invention

[0007] This article provides various methods for forming nanosheet field-effect transistor (FET) devices with reduced source / drain contact resistance. In some embodiments, a method of forming a FET device includes: etching a nanosheet stack of the nanosheet FET device to form a plurality of first source / drain regions and a plurality of second source / drain regions, the nanosheet stack including alternating layers of a plurality of nanosheet channel layers and a plurality of sacrificial nanosheet layers; depositing silicon layers on a plurality of sidewalls of the plurality of nanosheet channel layers in the plurality of first source / drain regions through a selective siliconization process to control the channel length of the plurality of nanosheet channel layers between adjacent first source / drain regions; and performing a metal-filling process to fill the plurality of first source / drain regions, wherein the metal filler extends from the lowermost nanosheet channel layer of the plurality of nanosheet channel layers to the uppermost nanosheet channel layer of the plurality of nanosheet channel layers to contribute to the reduced source / drain contact resistance.

[0008] In some embodiments, a method of forming a nanosheet field-effect transistor (FET) device with reduced source / drain contact resistance includes: forming a nanosheet stack on a substrate, the nanosheet stack including alternating layers of a plurality of nanosheet channel layers and a plurality of sacrificial nanosheet layers; etching the nanosheet stack of the nanosheet FET device to form a plurality of first source / drain regions and a plurality of second source / drain regions; applying a hard mask on the plurality of second source / drain regions; depositing silicon layers in the plurality of first source / drain regions at a plurality of sidewalls of the nanosheet channel layers through a selective siliconization process to control the channel length of the nanosheet channel layers between the first source / drain regions; and performing a metal-filling process to fill the plurality of first source / drain regions, wherein the A metal filler extends from the bottommost nanosheet channel layer to the topmost nanosheet channel layer, thereby contributing to the reduction of source / drain contact resistance; a hard mask is applied over the metal filler in the plurality of first source / drain regions; a silicon layer is deposited in the plurality of second source / drain regions through a selective siliconization process to control the channel length of the nanosheet channel layers between adjacent second source / drain regions, the silicon layer being located at multiple sidewalls of the nanosheet channel layers exposed in the plurality of second source / drain regions; and a second metal filling process is performed to fill the plurality of second source / drain regions, wherein the second metal filler extends from the bottommost nanosheet channel layer to the topmost nanosheet channel layer, thereby contributing to the reduction of source / drain contact resistance.

[0009] In some embodiments, a nanosheet field-effect transistor (FET) device includes: a nanosheet stack including a plurality of nanosheet channel layers; and a source / drain region in contact with a plurality of end portions of the plurality of nanosheet channel layers, wherein the source / drain region is filled with a metal filler and a silicon layer, the metal filler extending below the uppermost nanosheet channel layer of the plurality of nanosheet channel layers, and the silicon layer disposed between the metal filler and a plurality of sidewalls of the plurality of nanosheet channel layers.

[0010] Other and further embodiments of the disclosures in this case are described below. Simple Explanation of the Diagram

[0011] The embodiments of the disclosure, which are briefly summarized above and discussed in more detail below, can be understood by referring to the illustrative embodiments of the disclosure depicted in the accompanying drawings. However, the accompanying drawings only illustrate typical embodiments of the disclosure and should therefore not be considered as limiting the scope, as other equivalent embodiments are permissible.

[0012] Figure 1 is a flowchart depicting a method for forming a nanosheet field-effect transistor (FET) device according to at least some embodiments of the disclosure herein.

[0013] Figure 2 depicts a schematic isometric view of a nanosheet FET device with multiple source / drain regions.

[0014] Figure 3 depicts a cross-sectional view of a portion of a nanosheet FET element according to at least some embodiments disclosed in this case.

[0015] Figure 4 depicts a cross-sectional view of a portion of a nanosheet FET element according to at least some embodiments disclosed in this case.

[0016] To aid understanding, the same element symbols are used to designate the same elements shared across multiple figures, where possible. These figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further description. Implementation

[0017] This document provides embodiments of a nanosheet FET device and a method for forming such a device, which has reduced source / drain contact resistance. The method provided herein increases the contact area between the source / drain regions of the nanosheet FET device and the respective metal contacts, thereby advantageously reducing the contact resistance between the source / drain regions and the respective metal contacts, and thus improving device performance. The method provided herein also advantageously facilitates the adjustment of channel length through controlled deposition techniques to optimize device performance.

[0018] Figure 1 depicts a flowchart of a method for forming a nanosheet field-effect transistor (FET) device with reduced source / drain contact resistance according to at least some embodiments of the disclosure herein. At 102, method 100 includes: forming a nanosheet stack on a substrate (e.g., substrate 218) comprising alternating layers of nanosheet channel layers (e.g., a plurality of nanosheet channel layers 206) and sacrificial nanosheet layers (e.g., a plurality of sacrificial nanosheet layers 212). The nanosheet stack of the nanosheet FET device can be etched to form trenches (e.g., trench 304) defining a plurality of first source / drain regions (e.g., a plurality of first source / drain regions 202) and a plurality of second source / drain regions (e.g., a plurality of second source / drain regions 204). The etching process can be anisotropic dry etching, wet etching, or any other suitable etching process. In some embodiments, the etching process vertically etches the exposed portions of the nanosheet stack down to the substrate. In some embodiments, the etching process vertically etches the exposed portions of the nanosheet stack and a portion of the substrate, or in other words, etches down to below the upper surface of the substrate.

[0019] At 104, method 100 optionally includes applying a hard mask (e.g., hard mask 238) over a plurality of second source / drain regions. In some embodiments, the hard mask is deposited over the plurality of first source / drain regions before any deposition or filling process (e.g., depositing a silicon layer in the plurality of first source / drain regions) is performed. In some embodiments, method 100 includes forming inner spacers (e.g., inner spacers 226) in the plurality of first source / drain regions adjacent to the plurality of nanosheet channel layers. In some embodiments, the spacers are formed of a dielectric material, such as silicon nitride (SiN) or any suitable dielectric material.

[0020] For example, FIG2 depicts a schematic isometric view of a nanosheet FET device (or device 200) according to at least some embodiments of the disclosure herein, the device having a plurality of source / drain regions. In some embodiments, the plurality of source / drain regions 201 may generally include a plurality of first source / drain regions 202 and a plurality of second source / drain regions 204. In some embodiments, the plurality of first source / drain regions 202 correspond to a p-channel metal-oxide-semiconductor (pMOS) region of device 200. In some embodiments, the plurality of second source / drain regions 204 correspond to an n-channel metal-oxide-semiconductor (nMOS) region of device 200. FIG1 depicts a plurality of second source / drain regions 204 filled with material and covered with a hard mask 238, and a plurality of first source / drain regions 202 in an unfilled intermediate step in preparation for subsequent deposition and filling processes. A plurality of first source / drain regions 202 and a plurality of second source / drain regions 204 may be separated by an insulating layer 230, which includes, for example, a low-k dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), or silicon carbonitride (SiOC). A gate region 242 may be disposed above the plurality of source / drain regions 201.

[0021] Component 200 generally includes a plurality of nanosheet channel layers 206, which alternate with a plurality of sacrificial nanosheet layers 212 deposited or disposed on a substrate 218 (e.g., in a stacked configuration or stacked layers). In some embodiments, the plurality of nanosheet channel layers 206 have a thickness of about 5 to about 15 nanometers per layer. In some embodiments, the plurality of sacrificial nanosheet layers 212 have a thickness of about 5 to about 15 nanometers per layer. In some embodiments, the substrate 218 may be a semiconductor substrate formed of silicon (Si), silicon germanium (SiGe), or any other suitable semiconductor substrate material. In some embodiments, the plurality of nanosheet channel layers 206 include exactly three stacked channel layers, namely a first channel layer 220, a second channel layer 222, and a third channel layer 224, which are separated by layers of the plurality of sacrificial nanosheet layers 212. However, component 200 may include more or fewer than three nanosheet channel layers. In some embodiments, a plurality of nanosheet channel layers 206 and a plurality of sacrificial nanosheet layers 212 are grown sequentially in an alternating manner through an epitaxial growth process.

[0022] In some embodiments, a plurality of nanosheet channel layers 206 are substantially composed of silicon (Si), and a plurality of sacrificial nanosheet layers 212 are substantially composed of silicon germanium (SiGe) with a desired Ge concentration. In some embodiments, the plurality of nanosheet channel layers 206 are substantially composed of silicon germanium (SiGe) with a desired Ge concentration, and the plurality of sacrificial nanosheet layers 212 are substantially composed of silicon (Si). In some embodiments, the desired Ge concentration is from about 15% to about 40% by volume. In some embodiments, the plurality of nanosheet channel layers 206 and the plurality of sacrificial nanosheet layers 212 comprise a single-crystal semiconductor material, such as single-crystal silicon. In some embodiments, the material of the plurality of nanosheet channel layers 206 may be selectively etched away to free the plurality of nanosheet channel layers 206 for subsequent metal filling. The plurality of first source / drain regions 202 may include inner spacers 226 adjacent to the plurality of sacrificial nanosheets 212.

[0023] Referring back to Figure 1, at 106, method 100 includes depositing a silicon layer (e.g., silicon layer 322) at the ends of a nanosheet channel layer in a plurality of first source / drain regions via a selective siliconization process to control the length of the nanosheet channel layer between the first source / drain regions. The silicon layer serves as a contact element for the first source / drain regions and as a material to reduce contact resistance. In some embodiments, the silicon layer includes at least one of the following: titanium, nickel, palladium, ruthenium, molybdenum, platinum, osmium, or iridium. In some embodiments, the silicon layer includes titanium silicon for the nMOS region and molybdenum or ruthenium for the pMOS region.

[0024] In some embodiments, prior to depositing silica layers in a plurality of first source / drain regions as shown in FIG3, method 100 includes performing a controlled epitaxial growth process to deposit silicon or silicon-germanium on exposed sidewalls (e.g., sidewall 350) of the nanosheet channel layer, and to partially fill only the plurality of second source / drain regions prior to depositing silica layers in the plurality of second source / drain regions. In some embodiments, the controlled epitaxial growth process advantageously forms gaps (e.g., gap 344) between opposing sidewalls of the nanosheet channel layer to prevent epitaxial merge in the plurality of first source / drain regions. Silicide layers are deposited on the epitaxial growth layer (e.g., epitaxial material 306). By controlling the thickness of the epitaxial material deposited on the exposed nanosheet channel layer and controlling the thickness of the silica layer, the channel length 318 of the element 200 extending between adjacent metal fillers (e.g., metal filler 310) can be advantageously controlled.

[0025] Figure 3 depicts a cross-sectional view of a portion of a nanosheet FET element 200 according to at least some embodiments disclosed herein. Each of a plurality of first source / drain regions 202 may be defined by a trench 304. In some embodiments, an inner spacer 226 may be formed in or adjacent to the trench 304 by a process that laterally removes material from the sidewalls of a plurality of sacrificial nanosheet layers 212, such that the sidewalls 334 of the plurality of sacrificial nanosheet layers 212 are recessed relative to the sidewalls 350 of a plurality of nanosheet channel layers 206 adjacent to the plurality of first source / drain regions 202. For example, the lateral etching may be performed by a wet etching process using an etch solution or dry plasma etching, which selectively etches the plurality of sacrificial nanosheet layers 212 of material from the plurality of nanosheet channel layers 206. The amount of lateral recess may be controlled by timed etch. In some embodiments, dielectric material may be selectively deposited in the lateral recesses to form inner spacers 226. In some embodiments, a conformal layer of dielectric material may be deposited in a plurality of first source / drain regions 202 (including the recesses) and then etched back to remove excess material. In some embodiments, the width of the recesses is substantially equal to the thickness of the inner spacers 226.

[0026] In some embodiments, a plurality of nanosheet channel layers 206 may isolate gate electrodes 348 disposed above the plurality of nanosheet channel layers 206 through individual upper spacers 320. In some embodiments, the upper spacers 320 are formed of the same material as the inner spacers 226. In some embodiments, a conformal layer of dielectric material may form both the inner spacers 226 and the upper spacers 320.

[0027] In some embodiments, the epitaxial material 306 is grown from and extends from the sidewalls 350 of a plurality of nanosheet channel layers 206 (e.g., first channel layer 220, second channel layer 222, and third channel layer 224). The epitaxial material 306 may also be grown from the lower surface 338 of the trench 304. In some embodiments, the epitaxial material 306 grows from the lower surface 338 to a position vertically below the uppermost nanosheet channel layer of the plurality of nanosheet channel layers 206. In some embodiments, the epitaxial material 306 grows from the lower surface 338 to a position vertically below the lowermost nanosheet channel layer of the plurality of nanosheet channel layers 206. In some embodiments, the epitaxial material 306 grown from the sidewalls 350 of the plurality of nanosheet channel layers 206 forms a bulb shape. In some embodiments, the epitaxial material 306 adjacent to one of the plurality of nanosheet channel layers 206 will not fuse with the epitaxial material 306 extending from any of the remaining channels of the plurality of nanosheet channel layers 206. In some embodiments, the epitaxial material 306 may comprise epitaxial silicon (Si) or silicon germanium (SiGe) doped with suitable dopants to form an nMOS or pMOS region.

[0028] In some embodiments, a silicate layer 322 is disposed on and conforms to the epitaxial material 306. A metal filler 310 is disposed in the remainder of the trench 304 not occupied by one or more of the epitaxial material 306 and the silicate layer 322. The contact interface 380 between the metal filler 310 and the epitaxial material 306 or the silicate layer 322 is larger than conventional interfaces, advantageously resulting in a lower contact resistance between the metal filler 310 and the epitaxial material 306 or the silicate layer 322.

[0029] In some embodiments, a gate spacer 312 may be disposed around the metal filler 310 in the gate region 242. The gate spacer 312 may be made of a dielectric material. In some embodiments, a second gate spacer 314 is disposed between the gate spacer 312 and the gate electrode 348 to facilitate conduction of the control element 200. In some embodiments, the gate spacer 312 is made of a different material than the second gate spacer 314. In some embodiments, the gate spacer 312 is made of a low-k material, and the second gate spacer 314 is made of a high-k material. In some embodiments, the second gate spacer 314 may be consumed during processing, thus creating more space for the gate electrode 348.

[0030] Figure 4 depicts a cross-sectional view of a portion of a nanosheet FET device according to at least some embodiments disclosed herein. In some embodiments, a silicon layer 408 is deposited or formed in a trench 304, directly situated on the lower surface 338 of the trench 304 and on the sidewalls 350 of the plurality of nanosheet channel layers 206, without the epitaxial material 306 discussed above with respect to Figure 3. In some embodiments, the thickness 410 of the silicon layer 408 is greater than the thickness of the silicon layer 322. In some embodiments, the thickness is about 1 to about 4 nanometers. In some embodiments, the thickness 410 optimizes device performance while minimizing short-channel effects. A metal filler 310 is disposed in the remaining portion of the trench 304 not occupied by the silicon layer 408. In some embodiments, the metal filler 310 extends beneath the plurality of nanosheet channel layers 206. The channel length 420 may include the length of each of the plurality of nanosheet channel layers 206 plus the thickness 410 of the silica layer 408 at both ends of each layer. The channel length 420 can be controlled by controlling the thickness 410 to adjust the device 200 for optimal performance. In some embodiments, the channel length of the device 200 is about 10 to about 15 nanometers. The contact interface 480 between the metal filler 310 and the silica layer 408 is larger than conventional interfaces, advantageously resulting in a lower contact resistance between the metal filler 310 and the silica layer 408. The device of FIG. 4 also advantageously eliminates the need for source / drain placement and activation steps, resulting in lower cost and lower thermal budget.

[0031] Returning to Figure 1, at 108, method 100 includes performing a metal fill process to fill a plurality of first source / drain regions, wherein a metal filler (e.g., metal filler 310) extends from the lowest nanosheet channel layer (e.g., third channel layer 224) over the highest nanosheet channel layer (e.g., first channel layer 220) to help reduce source / drain contact resistance. The metal filler results in less epitaxial material (e.g., epitaxial material 306) disposed in the source / drain regions, thereby reducing epitaxial strain. However, the advantage of reducing source / drain contact resistance through the metal fill process described herein outweighs the disadvantage of reducing epitaxial strain. In some embodiments, method 100 includes modulating the metal filler to enhance channel stress and compensate for any performance loss due to reduced epitaxial strain.

[0032] In some embodiments, method 100 includes applying a hard mask over metal fillers in a plurality of first source / drain regions. In some embodiments, method 100 includes performing similar process steps for a plurality of second source / drain regions after applying the hard mask over the metal fillers in the plurality of first source / drain regions. For example, in some embodiments, the method includes performing a controlled epitaxial growth process to deposit silicon or silicon-germanium on exposed sidewalls of nanosheet channel layers in the plurality of second source / drain regions, and partially filling only the plurality of second source / drain regions. In some embodiments, a silicate layer is deposited in the plurality of second source / drain regions, followed by metal filling. In some embodiments, a second metal filler extends from the lowermost nanosheet channel layer over the uppermost nanosheet channel layer to help reduce source / drain contact resistance. In some embodiments, internal spacers are formed in the plurality of second source / drain regions before the silicate layer is deposited in the plurality of second source / drain regions. In some embodiments, after the metal filling process, a suitable mid-line (MEOL) or end-line (BEOL) process may be performed on the component 200.

[0033] While the foregoing description is an embodiment of the disclosure herein, other and further embodiments of the disclosure may be designed without departing from the basic scope of this application. For ease of explanation, one or more layers, structures, and regions of types commonly used to form semiconductor elements or structures may not be explicitly shown in the accompanying drawings. Any such layers, structures, and / or regions not explicitly shown may exist in actual semiconductor element structures. Furthermore, the description provided herein, with respect to semiconductor processing techniques, is not intended to cover all processing procedures that may be necessary to form functional semiconductor integrated circuit elements.

[0034] 100: Method 102~108: Square 200: Components 201: Source / Drain Region 202: Source / Drain Region 204: Source / Drain Region 206: Nanosheet Channel Layer 212: Sacrificial Nanosheets 218:Substrate 220: Channel Layer 222: Channel Layer 224: Channel Layer 226: Inner spacer 230: Insulation layer 238: Hard Mask 242: Gate Region 304: Trench 306: Epitaxial Material 310: Metal filler 312: Gate spacer 314: Gate spacer 318: Channel Length 320: Upper spacer 322: Silicone layer 334: Sidewall 338: Lower surface 344: Gap 348: Gate electrode 350: Sidewall 380: Contact Interface 408: Silicon layer 410: Thickness 420: Channel Length 480: Contact Interface

[0035] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for forming a nanosheet field-effect transistor (FET) device, comprising: The nanosheet stack of the nanosheet FET element is etched to form a plurality of first source / drain regions and a plurality of second source / drain regions. The nanosheet stack includes alternating layers of a plurality of nanosheet channel layers and a plurality of sacrificial nanosheet layers. Spacers are formed adjacent to the plurality of sacrificial nanosheet layers, wherein, adjacent to the plurality of first source / drain regions, the spacers extend into the plurality of first source / drain regions and beyond the plurality of sidewalls of the plurality of nanosheet channel layers. A silicon layer is deposited on multiple sidewalls of the plurality of nanosheet channel layers in the plurality of first source / drain regions through a selective siliconization process to control the channel length of the plurality of nanosheet channel layers between adjacent first source / drain regions; and a metal filling process is performed to fill the plurality of first source / drain regions, wherein the metal filler extends from a lowermost nanosheet channel layer of the plurality of nanosheet channel layers to an uppermost nanosheet channel layer of the plurality of nanosheet channel layers.

2. The method as described in claim 1, further comprising: Prior to depositing the silica layer, a controlled epitaxial growth process is performed to deposit silicon or silicon-germanium on multiple exposed sidewalls of the plurality of nanosheet channel layers and to partially fill the plurality of first source / drain regions.

3. The method as described in claim 2, wherein the controlled epitaxial growth process prevents epitaxial merging in the plurality of first source / drain regions.

4. The method as described in claim 1, wherein the silicate layer is deposited or formed directly on a lower surface of the plurality of first source / drain regions and directly on the sidewalls of the plurality of nanosheet channel layers.

5. The method as described in any one of claims 1 to 4, wherein the plurality of first source / drain regions correspond to a plurality of pMOS regions of the nanosheet FET element, and the plurality of second source / drain regions correspond to a plurality of nMOS regions of the nanosheet FET element.

6. A method for forming a nanosheet field-effect transistor (FET) device, comprising: The nanosheet stack of the nanosheet FET device is etched to form a plurality of first source / drain regions and a plurality of second source / drain regions. The nanosheet stack includes alternating layers of a plurality of nanosheet channel layers and a plurality of sacrificial nanosheet layers. A hard mask is applied to the plurality of second source / drain regions. Then, a silicon layer is deposited in the plurality of first source / drain regions on the plurality of sidewalls of the plurality of nanosheet channel layers through a selective siliconization process to control a channel length of the plurality of nanosheet channel layers between adjacent first source / drain regions. A metal fill process is performed to fill the plurality of first source / drain regions, wherein the metal filler extends from a lowermost nanosheet channel layer of the plurality of nanosheet channel layers to an uppermost nanosheet channel layer of the plurality of nanosheet channel layers.

7. The method as described in any one of claims 1 to 4, wherein the silicate layer comprises at least one of the following: titanium, nickel, palladium, molybdenum, platinum, osmium, or iridium.

8. The method as described in any one of claims 1 to 4, further comprising: A silicon layer is deposited in the plurality of second source / drain regions through a selective siliconization process, the silicon layer being located on multiple sidewalls of the plurality of nanosheet channel layers disposed in the plurality of second source / drain regions; and a second metal filling process is performed to fill the plurality of second source / drain regions, wherein the second metal filler extends from the lowermost nanosheet channel layer to the uppermost nanosheet channel layer, thereby helping to reduce source / drain contact resistance.

9. The method as described in claim 8, further comprising: Before depositing the silica layer in the plurality of second source / drain regions, a controlled epitaxial growth process is performed to deposit silicon or silicon-germanium on multiple exposed sidewalls of the plurality of nanosheet channel layers disposed in the plurality of second source / drain regions and to partially fill the plurality of second source / drain regions.

10. A method for forming a nanosheet field-effect transistor (FET) device with reduced source / drain contact resistance, comprising: A nanosheet stack is formed on a substrate, the nanosheet stack including alternating layers of multiple nanosheet channel layers and multiple sacrificial nanosheet layers; the nanosheet stack of the nanosheet FET element is etched to form a plurality of first source / drain regions and a plurality of second source / drain regions; a hard mask is applied to the plurality of second source / drain regions; a silicon layer is deposited in the plurality of first source / drain regions at multiple sidewalls of the nanosheet channel layers through a selective siliconization process to control a channel length of the nanosheet channel layers between the first source / drain regions; a metal fill process is performed to fill the plurality of first source / drain regions, wherein the metal filler extends from a lowermost nanosheet channel layer to an uppermost nanosheet channel layer to help reduce the source / drain contact resistance; A hard mask is applied over the metal filler in the plurality of first source / drain regions; a silicon layer is deposited in the plurality of second source / drain regions through a selective siliconization process to control a channel length of the nanosheet channel layers between adjacent second source / drain regions, the silicon layer being located at multiple sidewalls of the nanosheet channel layers exposed in the plurality of second source / drain regions; and a second metal filling process is performed to fill the plurality of second source / drain regions, wherein the second metal filler extends from the lowermost nanosheet channel layer to the uppermost nanosheet channel layer, thereby contributing to the reduction of source / drain contact resistance.

11. The method as described in claim 10, further comprising: Before depositing the silica layer in the plurality of first source / drain regions, a controlled epitaxial growth process is performed to deposit silicon or silicon-germanium on multiple exposed sidewalls of the nanosheet channel layers and partially fill the plurality of first source / drain regions; and before depositing the silica layer in the plurality of second source / drain regions, a controlled epitaxial growth process is performed to deposit silicon or silicon-germanium on multiple exposed sidewalls of the nanosheet channel layers and partially fill the plurality of second source / drain regions.

12. The method as described in claim 10, further comprising: Before depositing the silica layer in the plurality of first source / drain regions, a spacer is formed between the sacrificial nanosheets and the plurality of first source / drain regions; and before depositing the silica layer in the plurality of second source / drain regions, a spacer is formed between the sacrificial nanosheets and the plurality of second source / drain regions.

13. The method as described in any one of claims 10 to 12, wherein the nanosheet channel layers are made of silicon and the sacrificial nanosheet layers are made of silicon-germanium.

14. A nanosheet field-effect transistor (FET) device, comprising: A nanosheet stack includes a plurality of nanosheet channel layers; a source / drain region in contact with a plurality of end portions of the plurality of nanosheet channel layers, wherein the source / drain region is filled with a metal filler and a silica layer, the metal filler extending below the uppermost nanosheet channel layer of one of the plurality of nanosheet channel layers, the silica layer disposed between the metal filler and a plurality of sidewalls of the plurality of nanosheet channel layers, and silicon or silicon-germanium disposed between the sidewalls of the plurality of nanosheet channel layers and the silica layer, and disposed on the lower surface of one of the source / drain regions.

15. The nanosheet FET device as described in claim 14, wherein the silicon layer is about 1 nanometer to about 4 nanometer thick.

16. The nanosheet FET device as claimed in claim 14, wherein the plurality of nanosheet channel layers comprises exactly three stacked layers.

17. The nanosheet FET device as claimed in claim 14, wherein one channel length of the nanosheet FET device is about 10 to about 15 nanometers.

18. A nanosheet FET device as claimed in any one of claims 14 to 17, wherein the silicon layer comprises at least one of the following: titanium, nickel, palladium, molybdenum, platinum, osmium, or iridium.

19. A nanosheet FET device as claimed in any one of claims 14 to 17, wherein the plurality of nanosheet channel layers are made of single-crystal silicon.

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