Camera components and electronic devices

Abstract

The objective of this invention is to expand the dynamic range of a photodiode. The imaging element of this invention includes: a photoelectric conversion unit that converts light into electrical charge; three or more storage units that temporarily store electrical charge; a transmission unit that transmits electrical charge from the photoelectric conversion unit to the storage units; and a conversion efficiency switching unit that controls the conduction state between the storage units; wherein at least two of the three or more storage units are capacitors, and the three or more storage units store the electrical charge overflowing from the photoelectric conversion unit. This technology can be applied, for example, to imaging elements for capturing images.

Description

[Technical Field]

[0001] This technology relates to a camera element and an electronic device, for example, to a camera element and electronic device that can expand the dynamic range and obtain higher quality images. [Previous Technology]

[0002] Generally speaking, imaging elements such as CMOS (Complementary Metal Oxide Semiconductor) image sensors or CCD (Charge Coupled Device) are widely used in digital still cameras or digital video cameras. To improve the characteristics of imaging elements, such as to expand the dynamic range, Patent Document 1 proposes to expand the dynamic range by having a plurality of storage capacitor elements that store the charge overflowing from the photodiode. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2006-245522 [Summary of the Invention]

[0004] [The problem that the invention aims to solve]

[0005] In order to store the charge overflowing from the photodiode in the storage capacitor element, it is necessary to set the overflow barrier of the transfer transistor that transmits the charge from the photodiode to a lower value. In this case, the Qs (saturation charge) of the photodiode may decrease. It is desirable to expand the dynamic range without reducing the saturation charge of the photodiode.

[0006] This technology was developed in view of the following circumstances and can expand the dynamic range. [Technical means to solve the problem]

[0007] One aspect of the imaging element of this technology includes: a photoelectric conversion unit that converts light into electric charge; three or more storage units that temporarily store electric charge; a transmission unit that transmits electric charge from the aforementioned photoelectric conversion unit to the aforementioned storage units; and a conversion efficiency switching unit that controls the conduction state between the aforementioned storage units; wherein at least two of the aforementioned three or more storage units are capacitor elements, and the aforementioned three or more storage units store the electric charge overflowing from the aforementioned photoelectric conversion unit.

[0008] One aspect of the present technology is an electronic device comprising an imaging element and a processing unit. The imaging element comprises: a photoelectric conversion unit that converts light into electric charge; three or more storage units that temporarily store electric charge; a transmission unit that transmits electric charge from the aforementioned photoelectric conversion unit to the aforementioned storage units; and a conversion efficiency switching unit that controls the conduction state between the aforementioned storage units; wherein at least two of the aforementioned three or more storage units are capacitor elements, and the aforementioned three or more storage units store the electric charge overflowing from the aforementioned photoelectric conversion unit; and the processing unit processes signals from the aforementioned imaging element.

[0009] In one embodiment of the imaging element of the present technology, there are: a photoelectric conversion unit that converts light into electric charge; three or more storage units that temporarily store electric charge; a transmission unit that transmits electric charge from the photoelectric conversion unit to the storage units; and a conversion efficiency switching unit that controls the conduction state between the storage units. At least two of the aforementioned three or more storage units are configured as capacitor elements, and the aforementioned three or more storage units store the electric charge overflowing from the photoelectric conversion unit.

[0010] In one aspect of the present technology, an electronic machine is configured to include the aforementioned imaging element.

[0011] Furthermore, an electronic device can be an independent device or an internal block that constitutes a device.

Implementation Method

[0013] Hereinafter, the form used to implement this technology (hereinafter referred to as the implementation form) will be described.

[0014] <Example of camera device configuration> Figure 1 shows an example of the configuration of one embodiment of a camera device to which this technology is applicable.

[0015] The camera device 1 in Figure 1 is configured to have a pixel array section 3 in which pixels 2 are arranged in a two-dimensional array, and a peripheral circuit section around it. The peripheral circuit section includes: a vertical drive circuit 4, a horizontal signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.

[0016] Pixel 2 is formed having a photodiode as a photoelectric conversion element and a plurality of pixel transistors. The plurality of pixel transistors are, for example, transmission transistors, selection transistors, reset transistors, amplification transistors, etc., and are composed of MOS transistors.

[0017] The control circuit 8 receives data such as the input clock and the command operation mode, and outputs data such as the internal information of the camera device 1. That is, the control circuit 8 generates a clock signal or control signal based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock, which serves as the reference for the operation of the vertical drive circuit 4, the horizontal signal processing circuit 5, and the horizontal drive circuit 6. The control circuit 8 outputs the generated clock signal or control signal to the vertical drive circuit 4, the horizontal signal processing circuit 5, and the horizontal drive circuit 6.

[0018] The vertical driving circuit 4 is, for example, composed of a shift register, which selects a specific pixel driving line 10 and supplies pulses to the selected pixel driving line 10 for driving the pixel 2, thereby driving the pixel 2 in column units. That is, the vertical driving circuit 4 sequentially selects each pixel 2 of the scanning pixel array 3 in column units along the vertical direction, and supplies the pixel signal based on the signal charge generated in the photoelectric conversion unit of each pixel 2 in accordance with the amount of light received to the row signal processing circuit 5 via the vertical signal line 9.

[0019] The row signal processing circuit 5 is configured for each row of pixels 2, and performs signal processing such as noise removal on each row of pixels for the signal output from pixels 2 of 1 column share. For example, the row signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) or DDS (double data sampling) for removing fixed pattern noise inherent in pixels, and AD conversion.

[0020] The horizontal drive circuit 6 includes, for example, a shift register, which sequentially selects each of the line signal processing circuits 5 by outputting horizontal scan pulses in sequence, and each of the line signal processing circuits 5 outputs a pixel signal to the horizontal signal line 11.

[0021] The output circuit 7 processes and outputs the signals sequentially supplied to each of the signal processing circuits 5 via the horizontal signal line 11. The output circuit 7 may be configured to perform simple buffering, or it may perform black level adjustment, line deviation correction, or various digital signal processing. The input / output terminals 13 exchange signals with the outside world.

[0022] The camera device 1 configured as described above is a CMOS image sensor, referred to as the line AD mode, configured for each pixel row by the line signal processing circuit 5 that performs CDS processing or DDS processing and AD conversion processing.

[0023] <Example of Pixel Circuit Configuration> The configuration of the unit pixel provided in the pixel array section 3 will be described. The unit pixel provided in the pixel array section 3 is configured as shown in FIG2, for example. Furthermore, in the description following FIG2, the parts corresponding to the situation in FIG1 will be given the same symbols, and their descriptions will be omitted as appropriate. FIG2 is a diagram showing an example of the circuit configuration of pixel 2.

[0024] Referring to FIG2, pixel 2 of unit pixel has: photoelectric conversion unit 51, transmission transistor 52, FD (Floating Diffusion) unit 53, first conversion efficiency switching transistor 54, MIM (Metal-Insulator-Metal) capacitor element 55, second conversion efficiency switching transistor 56, MIM capacitor element 57, reset transistor 58, amplification transistor 59, and selection transistor 60.

[0025] For pixel 2, as pixel driving lines 10, for example, multiple driving lines are wired for each pixel column. Moreover, driving signals TG, FDG, FCG, RST, and SEL are supplied from the vertical driving circuit 4 to each of the transmission transistor 52, the first conversion efficiency switching transistor 54, the second conversion efficiency switching transistor 56, the reset transistor 58, and the selection transistor 60 via multiple driving lines.

[0026] These drive signals are pulse signals that are valid when they are at a high level (e.g., power supply voltage VDD) and invalid when they are at a low level (e.g., negative potential). That is, when each drive signal from drive signal TG to drive signal SEL is set to a high level, the transistor supplied to it becomes in the ON state, and when each drive signal is at a low level, the transistor supplied to it becomes in the OFF state.

[0027] The photoelectric conversion unit 51 includes, for example, a photodiode with a PN junction. The photoelectric conversion unit 51 receives incident light and performs photoelectric conversion, and accumulates the charge obtained as a result.

[0028] The transmission transistor 52 is disposed between the photoelectric conversion unit 51 and the FD unit 53, and a drive signal TG is supplied to the gate electrode of the transmission transistor 52. When the drive signal TG is at a high level, the transmission transistor 52 is turned on, and the charge stored in the photoelectric conversion unit 51 is transferred to the FD unit 53 via the transmission transistor 52.

[0029] The FD section 53 is a floating diffusion region called the floating diffusion section, which functions as a storage section for temporarily accumulating the charge transmitted from the photoelectric conversion section 51 or the charge overflowing from the photoelectric conversion section 51.

[0030] A first conversion efficiency switching transistor 54 is disposed between the FD section 53 and the MIM capacitor element 55. A drive signal FDG is supplied to the gate electrode of the first conversion efficiency switching transistor 54. When the drive signal FDG is at a high level, the first conversion efficiency switching transistor 54 is turned on, and the charge from the FD section 53 is transferred to the MIM capacitor element 55 via the first conversion efficiency switching transistor 54. The MIM capacitor element 55 functions as a storage unit for temporarily storing the charge overflowing from the photoelectric conversion section 51.

[0031] By setting the first conversion efficiency switching transistor 54 to conduction, the area where charge is accumulated becomes the area combining the FD section 53 and the MIM capacitor element 55, and the conversion efficiency when the charge generated in the photoelectric conversion section 51 is converted into voltage can be switched. The first conversion efficiency switching transistor 54 functions as a conversion efficiency switching transistor for switching conversion efficiency.

[0032] A second conversion efficiency switching transistor 56 is disposed between MIM capacitor element 55 and MIM capacitor element 57. A drive signal FCG is supplied to the gate electrode of the second conversion efficiency switching transistor 56. When the drive signal FCG is high, the second conversion efficiency switching transistor 56 is turned on, and the charge from MIM capacitor element 55 is transferred to MIM capacitor element 57 via the second conversion efficiency switching transistor 56.

[0033] By turning on the second conversion efficiency switching transistor 56, the area where charge is accumulated becomes the area combining the FD section 53, the MIM capacitor element 55, and the MIM capacitor element 57, thereby switching the conversion efficiency when the charge generated in the photoelectric conversion section 51 is converted into voltage. The second conversion efficiency switching transistor 56 functions as a conversion efficiency switching transistor for switching conversion efficiency.

[0034] MIM capacitor element 55 and MIM capacitor element 57 can achieve high capacitance without sacrificing the area of ​​the Si (silicon) substrate surface on which the pixel transistor is disposed, and the capacitance is larger than that of FD part 53.

[0035] The reset transistor 58 is connected between the power supply VDD and the MIM capacitor element 57. A drive signal RST is supplied to the gate electrode of the reset transistor 58. When the drive signal RST is at a high level, the reset transistor 58 is turned on, and the potential of the MIM capacitor element 57 is reset to the level of the power supply voltage VDD.

[0036] The gate electrode of the amplifying transistor 59 is connected to the FD section 53, and the drain electrode is connected to the power supply VDD, forming the input section of the readout circuit that reads and holds the signal corresponding to the charge in the FD section 53, also known as the source follower circuit. That is, the amplifying transistor 59 is connected to the vertical signal line 9 via the select transistor 60 through its source electrode, and together with a constant current source (not shown) connected to one end of the vertical signal line 9, it forms a source follower circuit.

[0037] Selector transistor 60 is connected between the source of amplifier transistor 59 and vertical signal line 9, and a drive signal SEL is supplied to the gate electrode of selector transistor 60. When the drive signal SEL is at a high level, selector transistor 60 is turned on, and pixel 2 is in the selected state. In this way, the pixel signal output from amplifier transistor 59 is output to vertical signal line 9 via selector transistor 31.

[0038] Furthermore, the following refers to each drive signal as being in an active state, i.e., a high level, also as each drive signal being turned on, and each drive signal as being in an inactive state, i.e. a low level, also as each drive signal being turned off.

[0039] The pixel 2 shown in Figure 2 includes: FD part 53, MIM capacitor element 55, and MIM capacitor element 57. These capacitors are connected in series to form a configuration in which the conversion efficiency when the charge generated by the photoelectric conversion unit is converted into voltage is switched in three stages.

[0040] The high conversion efficiency (HCG) is composed of FD section 53. The medium conversion efficiency (MCG) is composed of (FD section 53 + MIM capacitor element 55). The low conversion efficiency (LCG) is composed of (FD section 53 + MIM capacitor element 55 + MIM capacitor element 57).

[0041] The charge stored in the photoelectric conversion unit 51 becomes conductive through the transmission transistor 52, and is received and output by the FD unit 53 (high conversion efficiency), (FD unit 53 + MIM capacitor element 55) (medium conversion efficiency), or (FD unit 53 + MIM capacitor element 55 + MIM capacitor element 57) (low conversion efficiency).

[0042] Under high illumination, the charge stored in the photoelectric conversion unit 51 overflows to the FD unit 53 side through the transmission transistor 52 and is stored in the FD unit 53, MIM capacitor element 55, and MIM capacitor element 57.

[0043] When the light received is low for a small signal, the conversion efficiency is set to high, with charge stored in the FD section 53; when the light received is high for a large signal, the conversion efficiency is set to low, with charge stored in (FD section 53 + MIM capacitor element 55 + MIM capacitor element 57). Here, a conversion efficiency between high and low is further set, and a conversion efficiency with charge stored in (FD section 53 + MIM capacitor element 55) is set.

[0044] The charge that overflows in the photoelectric conversion unit 51 and accumulates in the FD unit 53, MIM capacitor element 55, and MIM capacitor element 57, together with the charge accumulated in the photoelectric conversion unit 51, is received and output by (FD unit 53 + MIM capacitor element 55 + MIM capacitor element 57).

[0045] The readouts of high conversion efficiency, medium conversion efficiency, and low conversion efficiency are each subjected to AD conversion separately, and the choice of which readout signal to use is determined based on the amount of each readout signal. At the junction of the high conversion efficiency signal and the medium conversion efficiency signal, or at the junction of the medium conversion efficiency signal and the low conversion efficiency signal, two readout signals can be mixed. By using a mixed signal, image quality degradation at the junction is suppressed.

[0046] <Example of Pixel Cross-Sectional Composition> Figure 3 shows an example of the cross-sectional composition of pixel 2.

[0047] The N-type semiconductor region 105 constituting the photoelectric conversion unit 51 of pixel 2 receives incident light from the back side (upper surface in the figure) of the semiconductor substrate 100. The N-type semiconductor region 105 is configured to be embedded inside the semiconductor substrate 100, or configured to have almost no N-type semiconductor region 105 on the surface of the substrate.

[0048] Above the N-type semiconductor region 105 (photoelectric conversion unit 51), a CF (color filter) 102 and a crystal lens 101 are provided. In the photoelectric conversion unit 51, incident light that passes through each part in sequence is received on the light-receiving surface and photoelectric conversion is performed.

[0049] For example, the N-type semiconductor region 105 of the photoelectric conversion unit 51 is formed as a charge accumulation region for storing charge (electrons). In the photoelectric conversion unit 51, the N-type semiconductor region 105 is disposed inside the P-type semiconductor region 104 of the semiconductor substrate 100.

[0050] Inside the semiconductor substrate 100, a pixel separation section 106 is provided to electrically separate a plurality of pixels 2, and a photoelectric conversion section 51 is provided in the area defined by the pixel separation section 106. When observing the pixel 2, the pixel separation section 106 is formed in a grid shape, for example, between the plurality of pixels 2, and the photoelectric conversion section 51 is formed in the area defined by the pixel separation section 106.

[0051] The pixel separation section 106 may be configured as FFTI (Front Full Trench Isolation). When the pixel separation section 106 is formed by FFTI, FFTI is configured as a trench penetrating the semiconductor substrate 100 (FIG. 7). The pixels 2 are separated by an insulating material by FFTI, thus configuring each pixel 2 to be electrically separated. STI (Shallow Trench Isolation) is provided between each transistor. STI is configured to form a shallow trench in the component separation area and embed an insulating film therein.

[0052] The wiring layer 120 is disposed on the lower surface of the semiconductor substrate 100, which is opposite to the back side (upper surface) of each part on which the light-shielding film 103, CF 102, crystal lens 101, etc. are disposed.

[0053] The wiring layer 120 includes wiring 122 and an insulating layer 123. Within the insulating layer 123, wiring 122 is formed to electrically connect to various components. The wiring layer 120 is a so-called multilayer wiring layer, formed by alternating layers of the interlayer insulating film constituting the insulating layer 123 and wiring 122 multiple times. Here, wiring 122 is used for wiring to transistors such as the photoelectric conversion unit 51 that reads charge from the transistor 52, or for wiring of VSL 9, etc., which is deposited across the insulating layer 123.

[0054] The support substrate (not shown) may be provided on the side of the wiring layer 120 opposite to the side where the photoelectric conversion unit 51 is provided. For example, a substrate containing silicon semiconductor with a thickness of several hundred μm may be provided as the support substrate.

[0055] In the configuration shown in FIG3, an example is shown where a logic circuit substrate 130 on which logic circuits are formed is laminated in the wiring layer 120. The logic circuit substrate 130 includes wiring 131 and an insulating layer 133. Within the insulating layer 133, the wiring 131 is formed in such a way that it is electrically connected to each component. The logic circuit substrate 130 is also a so-called multilayer wiring layer, which is formed by alternatingly laminating the interlayer insulating film constituting the insulating layer 133 and the wiring 131 multiple times.

[0056] A light-shielding film 103 is disposed on the back side (upper surface in the figure) of the semiconductor substrate 100, within CF 102. The light-shielding film 103 is configured to block a portion of incident light from above the semiconductor substrate 100 toward below the semiconductor substrate 100. The light-shielding film 103 is formed of a light-shielding material. For example, the light-shielding film 103 is formed by sequentially depositing a titanium (Ti) film and a tungsten (W) film. Alternatively, the light-shielding film 103 may be formed, for example, by sequentially depositing a titanium nitride (TiN) film and a tungsten (W) film. Furthermore, the light-shielding film 103 may be coated with a nitride (N) or the like.

[0057] An SCF (Stabilized Charge Film) or a P-type semiconductor region (solid-state diffusion layer) may be formed on the side of the pixel separation portion 106 (FFTI). The stabilized charge film is formed using a high dielectric material with a negative fixed charge in a manner that suppresses the generation of dark current by forming a positive charge (hole) accumulation region at the interface with the semiconductor substrate 100. By forming the stabilized charge film with a negative fixed charge, an electric field can be applied to the interface with the semiconductor substrate 100 by the negative fixed charge, thereby forming a positive charge (hole) accumulation region.

[0058] The fixed charge film may be formed, for example, from a hafnium oxide film (HfO2 film). Alternatively, the fixed charge film may also be formed from at least one of oxides containing elements such as hafnium, zirconium, aluminum, tantalum, titanium, magnesium, yttrium, and lanthanum.

[0059] It can also be configured as follows: a layer of P-type semiconductor region conformally formed on the sidewall of FFTI as a solid phase diffusion layer for solid phase diffusion.

[0060] Furthermore, here, an example is given of a photodiode formed by an N-type semiconductor region 105 enclosed within a semiconductor substrate 100 and a P-type semiconductor region 104 formed around it, but the N-type and P-type can be reversed. When the N-type and P-type are reversed, in the above and below descriptions, the pixel 2 can be formed by converting the N-type to the P-type and the P-type to the N-type.

[0061] It can be configured to embed SiO2 inside the pixel separation section 106. By embedding SiO2 and the like inside the pixel separation section 106 (a trench formed as FFTI), it can be configured to more reliably separate adjacent pixels 2.

[0062] By providing such a pixel separation section 106, the pixels 2 are electrically separated, which prevents charge leaking from the photoelectric conversion section 51 (PD: Photo Diode) from leaking into adjacent pixels 2. Therefore, the overflow barrier on the side of the transmitting transistor 52 can be strengthened, and the Qs (saturation charge) of the photoelectric conversion section 51 can be increased.

[0063] In the cross-sectional configuration example of pixel 2 shown in FIG3, the transmission transistor 52 is formed on the right side of the figure. It is configured such that an N-type semiconductor region 105 formed within the semiconductor substrate 100 is extended and connected to the transmission transistor 52. In the central portion within the semiconductor substrate 100, an FD portion 53 formed from an N+ region is formed. The FD portion 53 is connected to the amplifying transistor 59 shown on the left side of the figure via a region wiring 121.

[0064] The area wiring 121 is formed of polysilicon or advanced contacts (MIS contacts). Advanced contacts are contacts using a high-dielectric-constant insulating film. When the area wiring 121 is configured as an advanced contact made of a high-dielectric-constant insulating film, in the example shown in FIG7, it is configured as a metal-based insulating film inserted between the FD section 53 and the gate electrode of the amplifying transistor 59. For example, the high-dielectric-constant insulating film is formed as a thin film with a thickness of approximately 2.0 nm to 3.0 nm by a metal oxide having a high dielectric constant, such as titanium dioxide (TiO2).

[0065] When the area wiring 121 is configured to use advanced contacts, the N-type density of the FD section 53 is set to a low density, thereby reducing the contact resistance. By setting the N-type density of the FD section 53 to a low density, the electric field strength at the PN junction with the semiconductor substrate 100 (P-type semiconductor region 104) is weakened, thereby suppressing the generation of dark current. In this way, the pixel 2 can avoid the mixing of dark current with charge signal, prevent FPN (Fixed Pattern Noise) caused by inconsistency in FD dark current leakage, and improve the S / N at the connection points of multiple conversion efficiencies accompanying FPN, thereby improving image quality.

[0066] Furthermore, here we show an example of the FD unit 53 and the amplifying transistor 59 being connected by the area wiring 121, but in addition to the contacts of the FD unit 53, it is also possible to configure it to use the area wiring 121 (advanced contacts).

[0067] In the wiring layer 120 of pixel 2 shown in FIG. 3, wiring 122 forms 6 layers. When the layers are sequentially set as layer 1, layer 2, layer 3, layer 4, layer 5, and layer 6 from the top side (semiconductor substrate 100 side) in the figure, a MIM capacitor element 55 is formed three-dimensionally between the wiring 122 of layer 4 and the wiring 122 of layer 5. The MIM capacitor element 55 is a capacitor formed three-dimensionally with trenches and a capacitor film formed on its sidewalls.

[0068] One of the electrodes of the MIM capacitor element 55 is connected to the wiring 122 of the 4th layer, and the other is connected to the wiring 122 of the 5th layer via the conductive part 124. The wiring 122 of the 6th layer is used as a terminal for connection with the logic circuit board 130.

[0069] The bottommost wiring 122 of the wiring layer 120 and the topmost wiring 13 of the logic circuit board 130 are connected by metal bonding. Here, the metal used for metal bonding can be Cu (copper), and there are also cases called copper-copper (Cu-Cu) bonding, etc. In the figure, the surface of the copper-copper (Cu-Cu) bonding is marked with the symbol CCC.

[0070] The logic circuit board 130 is also configured with a plurality of wirings 131 stacked on top of each other. Figure 3 shows a configuration of 5 layers. When the layers are arranged sequentially from the top side (side of wiring layer 120) as layer 1, layer 2, layer 3, layer 4, and layer 5, the wirings 131 of layer 1 are connected to the wirings 122 of the bottom layer of wiring layer 120 as described above. The wirings 131 of layer 1 and the wirings 131 of layer 2 are connected by conductive parts.

[0071] A MIM capacitor element 57 is formed three-dimensionally between the wiring 131 of the second layer and the wiring 131 of the third layer. The MIM capacitor element 57, like the MIM capacitor element 55, is a capacitor formed three-dimensionally with a trench and a capacitor film formed on its sidewall.

[0072] Thus, pixel 2 has capacitors of FD part 53, MIM capacitor element 55, and MIM capacitor element 57. MIM capacitor element 55 is formed in wiring layer 120 of semiconductor substrate 100, and MIM capacitor element 57 is formed in logic circuit substrate 130.

[0073] As shown in FIG3, pixel 2 is configured to be formed by stacking a semiconductor substrate 100 including a wiring layer 120 and a logic circuit substrate 130. Referring again to FIG2, the semiconductor substrate 100 is configured to include a photoelectric conversion unit 51, a transmission transistor 52, an FD unit 53, a first conversion efficiency switching transistor 54, a MIM capacitor element 55, a second conversion efficiency switching transistor 56, a reset transistor 58, an amplifying transistor 59, and a selection transistor 60. The logic circuit substrate 130 is configured to include a MIM capacitor element 57.

[0074] Pixel 2 has three capacitors: FD section 53, MIM capacitor element 55, and MIM capacitor element 57. Using these, three conversion efficiencies are achieved. By configuring the readout to be three times, the S / N step difference variation of the connection section can be suppressed.

[0075] <Pixel Configuration in the Second Embodiment> Figure 4 is a cross-sectional view showing an example of pixel 2b in the second embodiment, and Figure 5 is a circuit configuration example showing pixel 2b. In the following description, pixel 2 described with reference to Figures 2 and 3 will be referred to as pixel 2a in the first embodiment. In the following description, the same symbols will be used for the parts that are the same as those of pixel 2a in the first embodiment, and the descriptions will be omitted as appropriate.

[0076] The pixel 2b of the second embodiment differs from the pixel 2a of the first embodiment in that it is configured as a stack of three substrates, but is otherwise basically the same.

[0077] Referring to FIG4, pixel 2b is configured to consist of a first semiconductor substrate 150, a second semiconductor substrate 160, and a logic circuit substrate 130. The first semiconductor substrate 150, the second semiconductor substrate 160, and the logic circuit substrate 130 of pixel 2 are manufactured by different steps, by stacking in a wafer state and then monolithizing them. Alternatively, they can be manufactured by stacking after monolithization.

[0078] In pixel 2a shown in FIG3, the first semiconductor substrate 150 and the second semiconductor substrate 160 are equivalent to the semiconductor substrate 100 including the wiring layer 120, and have the same configuration as the semiconductor substrate 100 including the wiring layer 120. The first semiconductor substrate 150 is configured to include the photoelectric conversion unit 51.

[0079] The wiring 162 of the second semiconductor substrate 160, which corresponds to the wiring 122 formed on the wiring layer 120 (FIG. 3), is formed on the insulating layer 163. A transistor is also formed on the second semiconductor substrate 160. In the example shown in FIG. 4, a first conversion efficiency switching transistor 54 and an amplifying transistor 59 are formed and connected to the FD portion 53 formed in the first semiconductor substrate 150 via TCV (Through-CIS-Via).

[0080] The wiring 162 of the second semiconductor substrate 160 of pixel 2b shown in FIG4 forms 6 layers. When the layers are arranged sequentially from the upper side (the side of the first semiconductor substrate 150) as the first layer, the second layer, the third layer, the fourth layer, the fifth layer, and the sixth layer, the wiring of the first layer is connected to the TCV 161 and connected to the contacts of the first conversion efficiency switching transistor 54 and the amplifying transistor 59, respectively.

[0081] A MIM capacitor element 55 is formed three-dimensionally between the wiring 162 of the 4th layer and the wiring 162 of the 5th layer. One electrode of the MIM capacitor element 55 is connected to the wiring 162 of the 4th layer, and the other electrode is connected to the wiring 162 of the 5th layer via the conductive portion 124. The wiring 162 of the 5th layer and the wiring 162 of the 6th layer are connected by wiring formed in the vertical direction, and the wiring 162 of the 6th layer is used as a connection terminal for copper-copper (Cu-Cu) bonding with the logic circuit board 130.

[0082] The logic circuit board 130 is configured to be the same as the logic circuit board 130 shown in FIG3, and a MIM capacitor element 57 is formed in three dimensions between the wiring 131 of the second layer and the wiring 131 of the third layer.

[0083] Referring to the example circuit configuration of pixel 2b shown in FIG5, the circuit configuration is the same as that of pixel 2a shown in FIG2. The first semiconductor substrate 150 is configured to include a photoelectric conversion unit 51, a transmission transistor 52, and an FD unit 53.

[0084] The second semiconductor substrate 160 is configured to include a first conversion efficiency switching transistor 54, a MIM capacitor element 55, a second conversion efficiency switching transistor 56, a reset transistor 58, an amplifying transistor 59, and a selection transistor 60. The transmission transistor 52 included in the first semiconductor substrate 150 is connected to the first conversion efficiency switching transistor 54 and the amplifying transistor 59 included in the second semiconductor substrate 160 via a TCV.

[0085] The logic circuit board 130 is configured to include MIM capacitor elements 57. The logic circuit board 130 and the second semiconductor board 160 are connected by copper-copper (Cu-Cu) bonding.

[0086] In pixel 2, there are three capacitors: FD part 53, MIM capacitor element 55, and MIM capacitor element 57. Using these, three conversion efficiencies are achieved. By setting the configuration to read out three times, the S / N step difference variation of the connection part can be suppressed.

[0087] <Pixel Configuration in the Third Embodiment> Figure 6 shows an example of the circuit configuration of pixel 2c in the third embodiment, and Figure 7 shows an example of the cross-sectional configuration of pixel 2c. In the following description, the same symbols are given to the parts that are the same as those of pixel 2b in the second embodiment, and the descriptions are omitted as appropriate.

[0088] The point where the MIM capacitor element 55 and the MIM capacitor element 57 are formed in the second semiconductor substrate 160c in the third embodiment is different from the point where the pixel 2c in the second embodiment is different from the point where the pixel 2b in the second embodiment is formed. Other points are basically the same.

[0089] Referring to the example circuit configuration of pixel 2c shown in FIG6, the first semiconductor substrate 150 is configured to include a photoelectric conversion unit 51, a transmission transistor 52, and an FD unit 53.

[0090] The second semiconductor substrate 160 is configured to include a first conversion efficiency switching transistor 54, a MIM capacitor element 55, a second conversion efficiency switching transistor 56, a MIM capacitor element 57, a reset transistor 58, an amplifying transistor 59, and a selector transistor 60. The FD portion 53 included in the first semiconductor substrate 150 is connected to the first conversion efficiency switching transistor 54 and the amplifying transistor 59 included in the second semiconductor substrate 160 via a TCV.

[0091] Referring to the cross-sectional configuration example of pixel 2c shown in FIG7, MIM capacitor element 55 and MIM capacitor element 57 are disposed in the second semiconductor substrate 160c. MIM capacitor element 55 and MIM capacitor element 57 are formed between the wiring 162 of the fourth layer and the wiring 162 of the fifth layer of the second semiconductor substrate 160c.

[0092] A MIM capacitor element 55 is formed near the center of the second semiconductor substrate 160c in the figure. One of the electrodes of the MIM capacitor element 55 is connected to the wiring 162 of the fourth layer, and the other is connected to the wiring 162 of the fifth layer via the conductive portion 124. Similarly, a MIM capacitor element 57 is formed on the left side of the second semiconductor substrate 160c in the figure. One of the electrodes of the MIM capacitor element 57 is connected to the wiring 162 of the fourth layer, and the other is connected to the wiring 162 of the fifth layer via the conductive portion 124.

[0093] Thus, the second semiconductor substrate 160c can be configured to have a plurality of MIM capacitor elements, as shown in the examples of Figures 6 and 7, which are composed of two MIM capacitor elements 55 and two MIM capacitor elements 57. When the size of pixel 2 is large, even if a plurality of MIM capacitor elements are disposed in one semiconductor substrate, the capacitance of each MIM capacitor element can be ensured to form a MIM capacitor element. The configuration of providing a plurality of MIM capacitor elements in the second semiconductor substrate 160c is applicable to relatively large-sized pixels 2.

[0094] In Figures 6 and 7, an example is given in which two MIM capacitor elements 55 and MIM capacitor elements 57 are disposed on the second semiconductor substrate 160. However, it is also possible to configure it so that a plurality of MIM capacitor elements are disposed on the logic circuit substrate 130.

[0095] The third embodiment can be combined with the first embodiment to form a configuration in which a plurality of MIM capacitor elements are formed in the semiconductor substrate 100. Alternatively, the third embodiment can be combined with the second embodiment to form a configuration in which a plurality of MIM capacitor elements are provided in the second semiconductor substrate 160 and MIM capacitor elements are also provided in the logic circuit substrate 130.

[0096] In pixel 2, there are three capacitors: FD part 53, MIM capacitor element 55, and MIM capacitor element 57. Using these, three conversion efficiencies are achieved. By setting the configuration to read out three times, the S / N step difference of the connection part can be suppressed.

[0097] In the first to third embodiments, the capacitance of the MIM capacitor element 55 and the capacitance of the MIM capacitor element 57 may be the same capacitance or different capacitances.

[0098] <Regarding the operation of pixel 2> The operation of pixel 2 in the first to third embodiments will be explained with reference to FIG8. In FIG8, PD represents photoelectric conversion unit 51, FD represents FD unit 53, MIM1 represents MIM capacitor element 55, and MIM2 represents MIM capacitor element 57.

[0099] At time t1, a reset operation is performed for pixel 2. The reset operation, for example, is performed during shutter action, by turning on the drive signal TG supplied to the transmission transistor 52, the drive signal FDG supplied to the first conversion efficiency switching transistor 54, the drive signal FCG supplied to the second conversion efficiency switching transistor 56, and the drive signal RST supplied to the reset transistor 58. Each drive signal is turned off after being turned on for a specific period.

[0100] During the exposure period at time t2, drive signals TG and RST are off, while drive signals FDG and FCG are on. During the exposure period, charge accumulates in the photoelectric conversion unit 51. During the exposure period, the charge overflowing from the photoelectric conversion unit 51 via the transducer 52 is transferred to the FD unit 53, the MIM capacitor element 55, and the MIM capacitor element 57.

[0101] At time t3, the MCG (Medium Conversion Efficiency) reset period is set. During the MCG reset period, the drive signals FCG and FDG are turned on for a specific period. Afterward, by keeping the drive signal FDG on, the drive signal FCG is turned off and the drive signal SEL is turned on, thereby performing the MCG reset. In the case where the MCG (Medium Conversion Efficiency) uses the FD section 53 and the MIM capacitor element 55, the FD section 53 and the MIM capacitor element 55 are reset during the MCG reset period.

[0102] At time t4, the HCG (High Conversion Efficiency) reset period is set. The high conversion efficiency is constituted by the FD unit 53. During the HCG reset period, the drive signals TG, FDG, FCG, and RST are in a turned-off state. The FD unit 53 is reset by turning on the drive signal SEL.

[0103] When reading from the photoelectric conversion unit 51 (PD: photodiode) begins, the drive signal TG supplied to the transmission transistor 52 is turned on for a specific period. The reading from the photodiode is performed by CDS (correlated double sampling) drive. The CDS drive is as follows: after resetting the FD to a specific potential and reading out the specific potential as the reset potential, the signal charge stored in the PD is transferred to the FD, and the signal charge in the FD is read out as the signal level.

[0104] As described later, after reading out the photodiode using CDS drive, reading out the photodiode and MIM capacitor elements using DDS (double data sampling) drive is performed. DDS drive is performed as follows: the signal charge held or stored in FD is read out as a signal level, and then FD is reset to a specific potential and read out as a reset level.

[0105] Since the reading from the PD is performed by the CDS driver, as described above, the MCG reset period and the HCG reset period are set, and the reset signal for medium conversion efficiency and the reset signal for high conversion efficiency are obtained in each period.

[0106] At time t5, the HCG readout period is set. The transmission transistor 52 is turned on for a specific time before the start of the HCG readout period by turning on the drive signal TG, and charge is transferred from the photoelectric conversion unit 51 to the FD unit 53. After the drive signal TG is turned off, the selection transistor 60 is turned on by turning on the drive signal SEL. Because high conversion efficiency is achieved in the FD unit 53, the charge accumulated in the FD unit 53 is read out during the HCG readout period.

[0107] At time t6, the MCG readout period is set. At the end of the HCG readout period, the drive signal SEL is used to return to off, the drive signal FDG is turned on, and the first conversion efficiency switching transistor 54 is turned on. While the first conversion efficiency switching transistor 54 is on, the drive signal TG is used to turn on the transmission transistor 52. By turning on both the transmission transistor 52 and the first conversion efficiency switching transistor 54, charge flows through the FD section 53 and the MIM capacitor element 55.

[0108] After the drive signal TR returns to the off state, the select transistor 60 is set to the on state by turning on the drive signal SEL, and the charge stored in the FD section 53 and the MIM capacitor element 55 is read out.

[0109] At time t7, the LCG readout period is set. After the MCG readout period ends, the drive signal FCG and drive signal TG are set to the on state. Since the drive signal FDG remains on, the transmission transistor 52, the first conversion efficiency switching transistor 54, and the second conversion efficiency switching transistor 56 are turned on, and the charge is transferred to the FD section 53, the MIM capacitor element 55, and the MIM capacitor element 57.

[0110] Because the low conversion efficiency is caused by (FD section 53 + MIM capacitor element 55 + MIM capacitor element 57), the charge accumulated in (FD section 53 + MIM capacitor element 55 + MIM capacitor element 57) is read out during LCG readout.

[0111] At time t8, the LCG reset period is set. At the end of the LCG readout period, the drive signal SEL is turned off. After turning off the drive signal SEL, the reset transistor 58 is turned on by turning on the drive signal RST for a specific time, thereby resetting the FD section 53, the MIM capacitor element 55, and the MIM capacitor element 57.

[0112] At the end of the LCG reset period, the drive signal SEL returns to off. By performing such a series of actions, the signals during HCG (high conversion efficiency), MCG (medium conversion efficiency), and LCG (low conversion efficiency) can be read out respectively.

[0113] Based on the configuration and operation of pixel 2 as described above, Qs (saturation charge) can be increased by using MIM capacitor element 57 for overflow driving of capacitor element. Since the pixels are separated by through channels (pixel separation section 106) through semiconductor substrate 100, smearing to adjacent pixels can be prevented, and the potential under the transmission transistor can be strengthened. In this way, the Qs of photodiode (photoelectric conversion section 51) can be increased, and the S / N difference of high illumination connection section can be suppressed.

[0114] By configuring the system to read out three times using three different conversion efficiencies, the variation in S / N step difference at the connection section can be suppressed.

[0115] <Pixel Configuration in the Fourth Embodiment> Figure 9 shows an example of the circuit configuration of pixel 2d in the fourth embodiment, and Figure 10 shows an example of the cross-sectional configuration of pixel 2d. In the following description, the same symbols are given to the parts that are the same as those of pixel 2b in the second embodiment, and the descriptions are omitted as appropriate.

[0116] The fourth embodiment of pixel 2d is configured such that a wiring capacitor 201 is further added to pixel 2b in the second embodiment.

[0117] Referring to the example of the circuit configuration of pixel 2d shown in FIG9, the first semiconductor substrate 150 is configured to include a photoelectric conversion unit 51, a transmission transistor 52, and an FD unit 53.

[0118] The second semiconductor substrate 160 is configured to include a first conversion efficiency switching transistor 54, a MIM capacitor element 55, a second conversion efficiency switching transistor 56, a reset transistor 58, an amplifying transistor 59, a selection transistor 60, a wiring capacitor 201, and a third conversion efficiency switching transistor 202.

[0119] The logic circuit board 130 is configured to include MIM capacitor elements 57.

[0120] The wiring capacitor 201 is disposed between the first conversion efficiency switching transistor 54 and the third conversion efficiency switching transistor 202. The pixel 2d is configured as a charge storage unit that stores the charge from the photoelectric conversion unit 51, and has four parts: the FD unit 53, the wiring capacitor 201, the MIM capacitor element 55, and the MIM capacitor element 57.

[0121] Referring to the cross-sectional configuration example of pixel 2d shown in FIG10, a MIM capacitor element 55 and a wiring capacitor 201 are disposed within the second semiconductor substrate 160d. The MIM capacitor element 55 is formed between the wiring 162 of the fourth layer and the wiring 162 of the fifth layer of the second semiconductor substrate 160d. The wiring capacitor 201 is disposed between the wiring 162 of the first layer and the wiring 162 of the second layer.

[0122] Figure 11 is a partially enlarged view of the wiring capacitor 201. The wiring capacitor 201 is provided with wiring 161-2 formed in a specific layer of the wiring 161 of the second semiconductor substrate 160d, which is composed of multiple layers. Wiring 161-2 forming the wiring capacitor 201 is connected to wiring 162-1. Wiring 162-1 is connected to the N+ diffusion layer formed on the layer on which the first conversion efficiency switching transistor 54 and the third conversion efficiency switching transistor 202 are formed.

[0123] The wiring capacitor 201 is formed by using a portion of the wiring 161, which is composed of multiple layers, on the second semiconductor substrate 160d. The pixel 2d further includes such a wiring capacitor 201 as an accumulation section.

[0124] In pixel 2d, there are four capacitors: FD part 53, MIM capacitor element 55, MIM capacitor element 57, and wiring capacitor 201. Using these, four conversion efficiencies are achieved. By setting the configuration to read out four times, the S / N step difference variation of the connection part can be suppressed.

[0125] In Figures 9 and 10, the case in which the wiring capacitor 201 is disposed on the second semiconductor substrate 160d is given as an example, but it can also be disposed on the logic circuit substrate 130.

[0126] Alternatively, the fourth embodiment can be combined with the first embodiment to form a configuration in which a wiring capacitor 201 is formed within the semiconductor substrate 100. Alternatively, the fourth embodiment can be combined with the third embodiment to form a configuration in which a plurality of MIM capacitor elements and wiring capacitors 201 are provided within the second semiconductor substrate 160.

[0127] <Pixel Configuration in the Fifth Embodiment> Figure 12 shows an example of the circuit configuration of pixel 2e in the fifth embodiment, and Figure 13 shows an example of the cross-sectional configuration of pixel 2e. In the following description, the same symbols are given to the parts that are the same as those of pixel 2b in the second embodiment, and the descriptions are omitted as appropriate.

[0128] The pixel 2e of the fifth embodiment differs from the pixel 2 of the other embodiments in that it is composed of a plurality of pixels sharing the FD section 53 to the selection transistor 60. Here, the case in which four pixels 2e share the FD section 53 to the selection transistor 60 will be used as an example for explanation.

[0129] Referring to the circuit configuration example of pixel 2e shown in FIG12, photoelectric conversion unit 51-1 and transmission transistor 52-1, photoelectric conversion unit 51-2 and transmission transistor 52-2, photoelectric conversion unit 51-3 and transmission transistor 52-3, and photoelectric conversion unit 51-4 and transmission transistor 52-4 are formed in the first semiconductor substrate 150e. A (common) FD unit 53 to a selection transistor 60 are connected to these four photoelectric conversion units 51-1 to 51-4.

[0130] The second semiconductor substrate 160 is configured to include a first conversion efficiency switching transistor 54, a MIM capacitor element 55, a second conversion efficiency switching transistor 56, a reset transistor 58, an amplifying transistor 59, and a selection transistor 60. The logic circuit substrate 130 is configured to include a MIM capacitor element 57.

[0131] The FD section 53 to the select transistor 60 is configured to be shared by four photoelectric conversion sections 51 (pixels 2e). Figure 13 shows a cross-sectional configuration example of two pixels 2e arranged horizontally among the four pixels 2e. FD sections 53 are formed on the lower part of the first semiconductor substrate 150e of pixels 2e-1 and 2e-2, respectively. The FD section 53 is connected to the first conversion efficiency switching transistor 54 and the amplifying transistor 59 formed in the second semiconductor substrate 160 via a TCV 161 formed in the second semiconductor substrate 160.

[0132] Near the center of the lower part of the first semiconductor substrate 150e in pixel 2e-1, a gate of a transfer transistor 52-1 that reads out the charge from the N-type semiconductor region 105 (photoelectric conversion unit 51-1) is formed. Similarly, near the center of the lower part of the first semiconductor substrate 150e in pixel 2e-2, a gate of a transfer transistor 52-2 that reads out the charge from the N-type semiconductor region 105 (photoelectric conversion unit 51-1) is formed.

[0133] The photoelectric conversion unit 51 or the transmission transistor 52 formed in the first semiconductor substrate 150e is formed in each pixel 2e, and the first conversion efficiency switching transistor 54 to the selection transistor 60 (excluding the MIM capacitor element 57) formed in the second semiconductor substrate 160 and the MIM capacitor element 57 formed in the logic circuit substrate 130 are shared by the four pixels 2e.

[0134] Similar to pixel 2 in the first embodiment, the following configuration can also be applied: forming a first semiconductor substrate 150e and a second semiconductor substrate 160 as shown in FIG13 in a semiconductor substrate 100.

[0135] The second to fourth embodiments can also be applied to the configuration of the second semiconductor substrate 160 and the logic circuit substrate 130. In other words, the fifth embodiment can also be implemented by combining the second to fourth embodiments. The examples shown in Figures 12 and 13 are examples of combining the second and fifth embodiments.

[0136] The third and fifth embodiments can also be combined to form a configuration in which a plurality of MIM capacitor elements are formed on the second semiconductor substrate 160 or the logic circuit substrate 130. The fourth and fifth embodiments can also be combined to provide wiring capacitors 201 on the second semiconductor substrate 160 or the logic circuit substrate 130. The third to fifth embodiments can also be combined to form a configuration in which a plurality of MIM capacitor elements or wiring capacitors 201 are provided on the second semiconductor substrate 160 or the logic circuit substrate 130, and these plurality of MIM capacitor elements or wiring capacitors 201 are shared by a plurality of pixels 2.

[0137] In pixel 2e, there are three capacitors: FD part 53, MIM capacitor element 55, and MIM capacitor element 57. Using these, three conversion efficiencies are achieved. By setting the configuration to read out three times, the S / N step difference variation of the connection part can be suppressed.

[0138] In pixel 2e, since it is configured to consist of a plurality of pixels 2e sharing a common FD part 53 to a select transistor 60, the pixel can be miniaturized.

[0139] <Pixel Configuration in the Sixth Embodiment> Figure 14 is a cross-sectional view of pixel 2f in the sixth embodiment, and Figure 15 is a circuit configuration example of pixel 2f. In the following description, the same symbols are used for the parts that are the same as those for pixel 2b in the second embodiment, and the descriptions are omitted as appropriate.

[0140] The pixel 2f of the sixth embodiment differs from the pixel 2 of the other embodiments in that it is configured to have a plurality of photoelectric conversion units 51 within one pixel. Here, the case in which two photoelectric conversion units 51 are provided as an example will be described. When the area surrounded by the pixel separation unit 106 is defined as one pixel 2f, one pixel 2f has two light-receiving parts.

[0141] In pixel 2f shown in FIG16, by forming a P-type semiconductor region 301 in the central part of the N-type semiconductor region 105, it is divided into two regions, N-type semiconductor region 105-1 and N-type semiconductor region 105-2. N-type semiconductor region 105-1 and N-type semiconductor region 105-2 respectively form PD (photoelectric conversion unit 51).

[0142] A transmission transistor 52-1 is disposed in N-type semiconductor region 105-1 (photoelectric conversion unit 51-1), and a transmission transistor 52-2 is disposed in N-type semiconductor region 105-2 (photoelectric conversion unit 51-2). An FD portion 53 is formed between the transmission transistors 52-1 and 52-2. The FD portion 53 is connected to a first conversion efficiency switching transistor 54 and an amplifying transistor 59 formed in the second semiconductor substrate 160 via a TCV 161 formed in the first semiconductor substrate 160.

[0143] The second semiconductor substrate 160 and the logic circuit substrate 130 can be configured in the same way as the second semiconductor substrate 160 and the logic circuit substrate 130 shown in FIG4.

[0144] Referring to the circuit configuration example of pixel 2f shown in FIG16, a photoelectric conversion unit 51-1 and a transmission transistor 52-1, a photoelectric conversion unit 51-2 and a transmission transistor 52-2, and an FD unit 53 are formed in the first semiconductor substrate 150. Each pixel 2f includes a photoelectric conversion unit 51-1 and a photoelectric conversion unit 51-2, and an FD unit 53 is connected to the two photoelectric conversion units 51-1 and 51-2.

[0145] The second semiconductor substrate 160 is configured to include a first conversion efficiency switching transistor 54, a MIM capacitor element 55, a second conversion efficiency switching transistor 56, a reset transistor 58, an amplifying transistor 59, and a selection transistor 60. The logic circuit substrate 130 is configured to include a MIM capacitor element 57.

[0146] The FD section 53 to the select transistor 60 is configured to be shared by the two photoelectric conversion sections 51 contained in one pixel.

[0147] Like the pixel 2 in the first embodiment, it can also be applied to the semiconductor substrate 100 to form the configuration of the first semiconductor substrate 150f and the second semiconductor substrate 160 shown in FIG14.

[0148] The second to fourth embodiments can also be applied to the configuration of the second semiconductor substrate 160 and the logic circuit substrate 130. In other words, the sixth embodiment can also be implemented by combining the second to fourth embodiments. The examples shown in Figures 14 and 15 are examples of combining the second and sixth embodiments.

[0149] The third and sixth embodiments can also be combined to form a configuration in which a plurality of MIM capacitor elements are formed on the second semiconductor substrate 160 or the logic circuit substrate 130. The fourth and sixth embodiments can also be combined to provide wiring capacitors 201 on the second semiconductor substrate 160 or the logic circuit substrate 130. The third to sixth embodiments can also be combined to form a configuration in which a plurality of MIM capacitor elements or wiring capacitors 201 are provided on the second semiconductor substrate 160 or the logic circuit substrate 130, and these plurality of MIM capacitor elements or wiring capacitors 201 are shared by a plurality of pixels 2.

[0150] In pixel 2f, there are three capacitors: FD part 53, MIM capacitor element 55, and MIM capacitor element 57. Using these, three conversion efficiencies are achieved. By setting the configuration to read out three times, the S / N step difference of the connection part can be suppressed.

[0151] Pixel 2f can be used, for example, for pixels used in phase difference detection.

[0152] <Regarding the manufacture of pixels> Referring to FIG16, the manufacture of pixel 2 will be explained. FIG16 will be used as an example to illustrate the manufacture of pixel 2b shown in FIG4.

[0153] In step S11, each part of the first semiconductor substrate 150, such as the photoelectric conversion section 51, the transmission transistor 52, and the FD section 53, is formed on the first semiconductor substrate 150.

[0154] In step S12, a transistor is formed within the second semiconductor substrate 160. For example, a first conversion efficiency switching transistor 54 or an amplifying transistor 59 is formed.

[0155] In step S13, wiring 122 or MIM capacitor element 55 is further formed on the second semiconductor substrate 160. When a plurality of MIM capacitor elements are formed on the second semiconductor substrate 160, in step S13, the plurality of MIM capacitor elements are formed within the second semiconductor substrate 160. When wiring capacitor 201 is formed on the second semiconductor substrate 160, in step S13, wiring capacitor 201 is formed within the second semiconductor substrate 160.

[0156] On the other hand, in steps S21 and S22, processing of the logic circuit substrate 130 is performed on the first semiconductor substrate 150 or the second semiconductor substrate 160. In step S21, for example, a first conversion efficiency switching transistor 54 or wiring 131 is formed on the logic circuit substrate 130.

[0157] In step S22, a MIM capacitor element 57 is formed within the logic circuit substrate 130. When a plurality of MIM capacitor elements are formed within the logic circuit substrate 130, in step S22, a plurality of MIM capacitor elements are formed within the logic circuit substrate 130. When a wiring capacitor is formed within the logic circuit substrate 130, in step S22, a wiring capacitor is formed within the logic circuit substrate 130. Furthermore, when no MIM capacitor element or wiring capacitor is formed within the logic circuit substrate 130, the step of forming the MIM capacitor element or wiring capacitor can be skipped in step S22.

[0158] In step S14, a logic circuit substrate 130 manufactured in steps S21 and S22 is deposited on the first semiconductor substrate 150 and the second semiconductor substrate 160 manufactured in steps S11 to S13. The logic circuit substrate 130 is attached to the second semiconductor substrate 160. In step S15, the pixel 2 shown in FIG3 is manufactured by forming a crystal lens 101, a CF 102, and a light-shielding film 103 on the first semiconductor substrate 150.

[0159] The same manufacturing steps can be used to manufacture the pixel 2 in other implementation forms.

[0160] According to this technology, by constructing a pixel with a plurality of MIM capacitor elements, the dynamic range can be greatly expanded, the conversion efficiency can be changed in stages, and the step difference between S / N when switching conversion efficiency can be reduced.

[0161] <Application Example to Electronic Machines> This technology is not limited to its application to imaging elements. That is, this technology is applicable to all electronic machines that use imaging elements in the image capturing unit (photoelectric conversion unit), such as digital still cameras or video cameras, portable terminal devices with imaging functions, and photocopiers that use imaging elements in the image reading unit. The imaging element can be formed as a single chip or as a module that integrates the imaging unit with the signal processing unit or optical system to have imaging functions.

[0162] FIG17 is a block diagram showing an example of the configuration of a camera device as an electronic machine to which the present invention is applied.

[0163] The imaging element 1000 in Figure 17 includes: an optical section 1001 comprising a lens group, etc.; an imaging element (image-capturing device) 1002 configured with the imaging device 1 of Figure 1; and a camera signal processing circuit, i.e., a DSP (Digital Signal Processor) circuit 1003. Furthermore, the imaging element 1000 also includes: a frame memory 1004, a display section 1005, a recording section 1006, an operation section 1007, and a power supply section 1008. The DSP circuit 1003, frame memory 1004, display section 1005, recording section 1006, operation section 1007, and power supply section 1008 are interconnected via bus cables 1009.

[0164] The optical unit 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of the imaging element 1002. The imaging element 1002 converts the amount of incident light imaged on the imaging surface by the optical unit 1001 into an electrical signal in pixel units and outputs it as a pixel signal. The imaging device 1 of FIG1 can be used as the imaging element 1002.

[0165] The display unit 1005 is composed of a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays the animation or still images captured by the camera element 1002. The recording unit 1006 records the animation or still images captured by the camera element 1002 onto a recording medium such as a hard disk or semiconductor memory.

[0166] Under the operation of the user, the operation unit 1007 issues operation commands for the various functions of the imaging element 1000. The power supply unit 1008 appropriately supplies various power supplies for the operation of the DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006 and operation unit 1007 to these supply objects.

[0167] <Application Example to Endoscopic Surgical Systems> The technology disclosed herein (the technology) can be applied to various products. For example, the technology disclosed herein can be applied to endoscopic surgical systems.

[0168] Figure 18 is a diagram showing an example of the general configuration of an endoscopic surgical system to which the technology disclosed herein (the technology) is applicable.

[0169] Figure 18 illustrates the situation where the surgeon (doctor) 11131 uses the endoscopic surgical system 11000 to perform surgery on the patient 11132 on the bed 11133. As shown, the endoscopic surgical system 11000 includes: an endoscope 11100, other surgical instruments 11110 such as an insufflator 11111 or energy treatment device 11112, a support arm device 11120 for supporting the endoscope 1110, and a trolley 11200 equipped with various devices for endoscopic surgery.

[0170] Endoscope 1110 includes: a tube 11101, which is inserted into the body cavity of patient 11132 for a specific length from its tip; and a camera head 11102, which is connected to the base of 1. In the illustrated example, the illustrated endoscope 11100 is configured as a so-called rigid endoscope with a rigid tube 11101, but endoscope 11100 can also be configured as a so-called flexible endoscope with a flexible tube.

[0171] An opening for embedding an objective lens is provided at the front end of the endoscope tube 11101. A light source device 11203 is connected to the endoscope 11100. The light generated by the light source device 11203 is guided to the front end of the endoscope tube by a light guide that extends into the interior of the endoscope tube 11101, and then illuminates the object to be observed inside the body cavity of the patient 11132 through the objective lens. Furthermore, the endoscope 11100 can be a direct viewing endoscope, or an oblique viewing endoscope or a side viewing endoscope.

[0172] An optical system and an imaging element are provided inside the camera head 11102. The reflected light (observation light) from the observed object is focused onto the imaging element by the optical system. The imaging element performs photoelectric conversion on the observation light to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observed image. This image signal is sent as RAW data to the camera control unit (CCU) 11201.

[0173] The CCU 11201 is composed of a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), etc., and comprehensively controls the operation of the endoscope 1110 and the display device 11202. Furthermore, the CCU 11201 receives image signals from the camera head 11102 and performs various image processing on the image signals, such as developing processing (de-mosaic processing), for displaying images based on the image signals.

[0174] The display device 11202 displays an image based on the image signal processed by the CCU 11201, under the control of the CCU 11201.

[0175] The light source device 11203 is composed of a light source such as an LED (light emitting diode) and provides illumination light to the endoscope 11100 when taking pictures of the surgical site.

[0176] Input device 11204 is the input interface for the endoscopic surgery system 11000. Users can input various information or instructions to the endoscopic surgery system 11000 through input device 11204. For example, users can input instructions to change the imaging conditions of the endoscope 11100 (type of illumination light, magnification, and focal length, etc.).

[0177] The treatment device control device 11205 controls the drive of the energy treatment device 11112 used for cauterization, tissue incision, or vascular occlusion. The pneumoperitoneum device 11206, for the purpose of ensuring the field of vision of the endoscope 11100 and ensuring the operator's working space, inflates the body cavity of the patient 11132 by introducing gas into the cavity via the pneumoperitoneum tube 11111. The recorder 11207 is a device that can record various information related to the surgery. The printer 11208 is a device that can print various information related to the surgery in various forms such as text, images, or charts.

[0178] Furthermore, the light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site may include, for example, an LED, a laser light source, or a white light source composed of a combination of these. When a white light source is composed of a combination of RGB laser light sources, the output intensity and timing of each color (wavelength) can be controlled with high precision, so the white balance of the photographed image can be adjusted in the light source device 11203. In this case, by illuminating the object of observation with laser light from each of the RGB laser light sources in a time-division manner, and controlling the driving of the imaging element of the camera head 11102 in sync with the illumination timing, images corresponding to each of the RGB light sources can also be captured in a time-division manner. According to this method, a color image can be obtained even if a color filter is not provided on the imaging element.

[0179] Furthermore, the light source device 11203 can control the drive by changing the intensity of the output light at specific intervals. By controlling the drive of the imaging element of the camera head 11102 in sync with the timing of the change in light intensity, images are acquired in time-division multiplexing, and the images are combined to produce so-called high dynamic range images without underexposure or overexposure.

[0180] Furthermore, the light source device 11203 can be configured to supply light within a specific wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption by body tissues, a narrower band of light is irradiated compared to the irradiation light used in normal observation (i.e., white light), thus performing so-called narrow-band imaging of specific tissues such as blood vessels on the mucosal surface under high contrast. Alternatively, in special light observation, fluorescence observation can be performed using fluorescence generated by irradiating excitation light to obtain an image. In fluorescence observation, one can irradiate body tissue with excitation light to observe the fluorescence from that body tissue (autofluorescence observation), or locally inject a reagent such as indocyanine green (ICG) into body tissue and irradiate the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image, etc. The light source device 11203 can be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0181] Figure 19 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 18.

[0182] The camera head 11102 includes: a lens unit 11401, an image capturing unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes: a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 can be communicatively connected to each other via a transmission cable 11400.

[0183] The lens unit 11401 is an optical system disposed at the connection portion with the lens barrel 11101. The observation light captured from the front end of the lens barrel 11101 is guided to the camera head 11102 and incident on the lens unit 11401. The lens unit 11401 is composed of a plurality of lenses including a zoom lens and a focusing lens.

[0184] The imaging element constituting the imaging unit 11402 can be a single unit (so-called single-plate type) or multiple units (so-called multi-plate type). When the imaging unit 11402 is composed of multiple units, for example, a color image can be obtained by generating image signals corresponding to each of the RGB values ​​using each imaging element and combining them. Alternatively, the imaging unit 11402 can be configured with a pair of imaging elements for acquiring image signals for the right eye and left eye respectively, corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue at the surgical site. Furthermore, when the imaging unit 11402 is composed of multiple units, a plurality of lens units 11401 can also be provided in a system corresponding to each imaging element.

[0185] Furthermore, the camera unit 11402 may not necessarily be located in the camera head 11102. For example, the camera unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0186] The drive unit 11403 is composed of an actuator, which, under the control of the camera head control unit 11405, moves the zoom lens and the focus lens of the lens unit 11401 a specific distance along the optical axis. In this way, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0187] The communication unit 11404 is composed of a communication device for sending and receiving various information between the communication unit and the CCU 11201. The communication unit 11404 transmits the image signal obtained from the camera unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0188] Furthermore, the communication unit 11404 receives control signals from the CCU 11201 for controlling the drive of the camera head 11102 and supplies them to the camera head control unit 11405. These control signals include, for example, information related to shooting conditions such as information specifying the frame rate of the captured image, information specifying the exposure value during shooting, and / or information specifying the magnification and focus of the captured image.

[0189] Furthermore, the aforementioned image capture conditions, such as frame rate or exposure value, magnification, and focus, can be appropriately specified by the user, or can be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions are installed in the endoscope 11100.

[0190] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0191] The communication unit 11411 is composed of a communication device for transmitting and receiving various information between the camera head 11102 and the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0192] Furthermore, the communication unit 11411 sends control signals to the camera head 11102 to control the driving of the camera head 11102. The image signal or control signal can be transmitted via electrical communication or optical communication, etc.

[0193] The image processing unit 11412 performs various image processing on the RAW data, i.e., the image signal, sent by the camera head 11102.

[0194] The control unit 11413 performs various controls related to the endoscope 11100's imaging of the surgical site, etc., and the display of the image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates control signals for controlling the drive of the camera head 11102.

[0195] Furthermore, the control unit 11413 displays a camera image showing the surgical site, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 can use various image recognition technologies to identify various objects in the camera image. For example, the control unit 11413 can identify surgical instruments such as forceps, specific biological parts, bleeding, and mist during the use of the energy treatment device 11112 by detecting the shape or color of the edges of objects contained in the camera image. When displaying the camera image on the display device 11202, the control unit 11413 can use the recognition results to overlay various surgical support information onto the image of the surgical site. By overlaying the surgical support information and providing prompts to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery accurately.

[0196] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 can be an electrical signal cable corresponding to electrical signal communication, an optical fiber corresponding to optical communication, or a composite cable of the like.

[0197] Here, in the illustrated example, the transmission cable 11400 can be used for wired communication, but communication between the camera head 11102 and the CCU 11201 can also be carried out wirelessly.

[0198] In this specification, the term "system" means a device as a whole consisting of a plurality of devices.

[0199] Furthermore, the effects described in this specification are ultimately illustrative and not limited to any particular effect, and may also have other effects.

[0200] Furthermore, the embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the essence of the present invention.

[0201] Furthermore, the present technology may also adopt the following configuration. (1) An imaging element comprising: a photoelectric conversion unit that converts light into charge; three or more storage units that temporarily store charge; a transmission unit that transmits charge from the aforementioned photoelectric conversion unit to the aforementioned storage units; and a conversion efficiency switching unit that controls the conduction state between the aforementioned storage units; wherein at least two of the aforementioned three or more storage units are capacitor elements, and the aforementioned three or more storage units store the charge overflowing from the aforementioned photoelectric conversion unit. (2) The imaging element of (1) above, wherein the aforementioned capacitor element is a MIM (Metal-Insulator-Metal) capacitor element. (3) The imaging element of (1) or (2) above, wherein it comprises a wiring capacitor as the aforementioned storage unit. (4) The imaging element of any one of (1) to (3) above, further comprising a through channel for separating pixels. (5) An imaging element as described in any one of (1) to (4) above, wherein the aforementioned photoelectric conversion unit is disposed within a first semiconductor substrate, the aforementioned capacitor element and the aforementioned conversion efficiency switching unit are disposed within a second semiconductor substrate, and the aforementioned first semiconductor substrate and the aforementioned second semiconductor substrate are stacked. (6) An imaging element as described in (5) above, wherein a plurality of the aforementioned capacitor elements are disposed on the aforementioned second semiconductor substrate. (7) An imaging element as described in (5) above, wherein a logic circuit substrate having logic circuits formed is stacked on the aforementioned second semiconductor substrate, and the aforementioned capacitor element is disposed within the aforementioned logic circuit substrate. (8) An imaging element as described in any one of (1) to (7) above, wherein the aforementioned capacitor element and the aforementioned conversion efficiency switching unit are shared by a plurality of the aforementioned photoelectric conversion units. (9) An imaging element as described in any one of (1) to (7) above, wherein two of the aforementioned photoelectric conversion units are provided within one pixel, and the aforementioned capacitor element and the aforementioned conversion efficiency switching unit are shared by the two aforementioned photoelectric conversion units. (10) An imaging element as described in any one of (2) to (9) above, wherein the aforementioned three or more storage units are FD (Floating Diffusion) and two of the aforementioned MIM capacitor elements, and the charge from the aforementioned photoelectric conversion unit is read out in each of high conversion efficiency, medium conversion efficiency, and low conversion efficiency by controlling the aforementioned conversion efficiency switching unit. (11) An electronic machine comprising an imaging element and a processing unit, the imaging element comprising: a photoelectric conversion unit that converts light into charge; three or more storage units that temporarily store charge; a transmission unit that transmits charge from the aforementioned photoelectric conversion unit to the aforementioned storage units; and a conversion efficiency switching unit that controls the conduction state between the aforementioned storage units; wherein at least two of the aforementioned three or more storage units are capacitor elements, the aforementioned three or more storage units store the charge overflowing from the aforementioned photoelectric conversion unit, and the processing unit processes the signal from the aforementioned imaging element. [Simplified Explanation of the Diagram]

[0012] Figure 1 is a diagram showing an embodiment of the imaging device to which this technology is applied. Figure 2 is a diagram showing an example of the circuit configuration of a pixel. Figure 3 is a diagram showing an example of the cross-sectional configuration of a pixel. Figure 4 is a diagram showing an example of the cross-sectional configuration of a pixel in a second embodiment. Figure 5 is a diagram showing an example of the circuit configuration of a pixel in a second embodiment. Figure 6 is a diagram showing an example of the circuit configuration of a pixel in a third embodiment. Figure 7 is a diagram showing an example of the cross-sectional configuration of a pixel in a third embodiment. Figure 8 is a diagram illustrating the operation of a pixel. Figure 9 is a diagram showing an example of the circuit configuration of a pixel in a fourth embodiment. Figure 10 is a diagram showing an example of the cross-sectional configuration of a pixel in a fourth embodiment. Figure 11 is a diagram illustrating the configuration of a wiring capacitor. Figure 12 is a diagram showing an example of the circuit configuration of a pixel in a fifth embodiment. Figure 13 is a diagram showing an example of the cross-sectional configuration of a pixel in a fifth embodiment. Figure 14 is a diagram showing an example of the cross-sectional configuration of a pixel in a sixth embodiment. Figure 15 is a diagram showing an example of the circuit configuration of a pixel in the sixth embodiment. Figure 16 is a diagram illustrating the manufacture of a pixel. Figure 17 is a diagram showing an example of an electronic device. Figure 18 is a diagram showing an example of the schematic configuration of an endoscopic surgical system. Figure 19 is a block diagram showing an example of the functional configuration of a camera head and CCU.

Claims

1. An imaging element comprising: a photoelectric conversion unit that converts light into electric charge; three or more storage units that temporarily store electric charge; a transmission unit that transmits electric charge from the photoelectric conversion unit to the storage units; a conversion efficiency switching unit that controls the conduction state between the storage units; and a through channel that separates pixels; wherein at least two of the three or more storage units are capacitor elements, the three or more storage units include FD (Floating Diffusion), and the three or more storage units store electric charge overflowing from the photoelectric conversion unit.

2. The imaging element of claim 1, wherein the aforementioned capacitor element is a MIM (Metal-Insulator-Metal) capacitor element.

3. The imaging element of claim 1, wherein at least one of the aforementioned capacitor elements is a MIM capacitor element.

4. The imaging element of claim 1, wherein the aforementioned capacitor element is formed in a predetermined layer, a predetermined next layer, and between such layers.

5. The imaging element of claim 1, wherein the aforementioned capacitor element has a repeating structure.

6. The imaging element of claim 1 has a wiring capacitor as the aforementioned storage unit.

7. The imaging element of claim 1, wherein the aforementioned photoelectric conversion unit is disposed in a first semiconductor substrate, the aforementioned capacitor element and the aforementioned conversion efficiency switching unit are disposed in a second semiconductor substrate, and the aforementioned first semiconductor substrate and the aforementioned second semiconductor substrate are laminated.

8. The imaging element of claim 7, wherein a plurality of the aforementioned capacitor elements are disposed on the aforementioned second semiconductor substrate.

9. The imaging element of claim 7, wherein a logic circuit substrate having logic circuits is laminated on the aforementioned second semiconductor substrate, and the aforementioned capacitor element is disposed within the aforementioned logic circuit substrate.

10. The imaging element of claim 1, wherein the aforementioned capacitor element and the aforementioned conversion efficiency switching unit are shared by a plurality of the aforementioned photoelectric conversion units.

11. The imaging element of claim 1, wherein two of the aforementioned photoelectric conversion units are provided in one pixel, and the aforementioned capacitor element and the aforementioned conversion efficiency switching unit are shared by the two aforementioned photoelectric conversion units.

12. The imaging element of claim 2, wherein the aforementioned three or more storage units are the aforementioned FD (Floating Diffusion) and two aforementioned MIM capacitor elements, and by controlling the aforementioned conversion efficiency switching unit, the charge readout from the aforementioned photoelectric conversion unit is performed in each of the high conversion efficiency, medium conversion efficiency and low conversion efficiency.

13. An electronic device comprising an imaging element and a processing unit, the imaging element comprising: a photoelectric conversion unit that converts light into electrical charge; three or more storage units that temporarily store electrical charge; a transmission unit that transmits electrical charge from the photoelectric conversion unit to the storage units; a conversion efficiency switching unit that controls the conduction state between the storage units; and a through channel that separates pixels; wherein at least two of the three or more storage units are capacitor elements, the three or more storage units include FD (Floating Diffusion), the three or more storage units store electrical charge overflowing from the photoelectric conversion unit, and the processing unit processes signals from the imaging element.

Images