Hardware accelerated database sorting in solid state storage drives

Abstract

This invention relates to a system and related method for a storage device. In this system and method, a sorting command is received from a host. In response to receiving the sorting command, the storage device is configured to perform sorting by allocating at least one storage location based on at least a) the amount of data to be sorted and b) the available storage space in the storage device's memory. In this system and method, a sorted subset of data is generated using an scalable sorting algorithm, and the sorted serialized subset of data is stored based on at least one storage location indicating the data to be stored and sorted. A page identifier (ID) for the sorted subset of data is provided to the host.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a platform for sorting data in a solid-state storage drive (SSD). [Previous Technology]

[0002] The computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices, i.e., data storage devices. The data storage device serves as either the main memory or secondary memory device of the portable electronic device.

[0003] Because memory devices have no moving parts, memory systems using memory devices offer excellent stability, durability, high data access speeds, and low power consumption. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces such as Universal Flash Memory (UFS), and solid-state drives (SSDs).

[0004] As described in U.S. Patent No. 9,727,308 (the entire contents of which are incorporated herein by reference), the performance of batch data processing becomes an issue when millions of records need to be processed within a memory block over a set time period. Furthermore, when random read operations occur during database processing, each read operation takes longer, which can impact performance.

[0005] For filtering and sorting, database storage engines rely heavily on sorting algorithms and techniques. One of the functions of the central database, namely, indexing the records of the data set, is based on sorting operations. In order to perform sorting, filtering, or indexing operations, the database storage engine typically a) reads the raw database records from the underlying storage medium and b) processes each record individually to determine its relationship to other records.

[0006] For input / output (I / O) performance optimization, database records are typically organized using a special data structure mapped to SSD pages. Alignment of database table record fields with a single SSD page allows access to all record fields located within that page, eliminating the need to read multiple NAND pages to reconstruct a single database record. [Summary of the Invention]

[0007] In one aspect of the invention, a method for operating a storage device is provided. The method receives a sorting command from a host. In response to receiving the sorting command, the method configures the storage device for optimal sorting by allocating at least one storage location based on at least a) the amount of data to be sorted and b) the available storage space in the memory of the storage device. The method utilizes an upgradable sorting algorithm to generate a sorted subset of data and stores the sorted subset of data based on at least one storage location indicating the data to be stored and sorted. The method provides the host with a page identifier (ID) for the sorted subset of data.

[0008] In another aspect of the invention, a system for accelerating the sorting of data from a storage device is provided. The system includes: a host interface for communication between a host and the storage device; memory in the storage device for storing data; and a reconfigurable SSD hardware accelerator processor in the storage device, communicating with the memory and the host interface. The reconfigurable SSD hardware accelerator processor is configured to: a) configure the storage device for optimal sorting by allocating at least one storage location for storing data to be sorted; b) generate a sorted subset of data retrieved from memory using an scalable sorting algorithm; c) store the sorted subset of data based on at least one storage location indicating the data to be stored and sorted; and d) provide a page identifier (ID) of the sorted subset of data to the host.

[0009] In another aspect of the present invention, a method for operating a storage device is provided. In this method, a host can reconfigure the sorting algorithm of an SSD hardware accelerator processor. The method responds to receiving a sorting algorithm update command by updating the sorting algorithm to be used for data sorting using a sorting / arranging algorithm provided as write data in the command. In this method, database records can be stored according to a database storage engine page format specified by the host in the sorting algorithm update command. In this method, the database storage engine page format can be configured for the data sorting accelerator before starting the sorting / arranging operation.

[0010] Other aspects of the invention will become apparent from the following description.

Implementation Method

[0012] Various embodiments of the invention are described in more detail below with reference to the drawings. However, the invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to fully convey the scope of the invention to those skilled in the art to which it pertains. Furthermore, references herein to “embodiment,” “another embodiment,” etc., are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. The term “embodiment” as used herein does not necessarily refer to all embodiments. Throughout the disclosure, the same element symbols refer to the same parts in the drawings and embodiments of the invention.

[0013] This invention can be embodied in a variety of ways, including as: a process; an apparatus; a system; a computer program product implemented on a computer-readable storage medium; and / or a processor, such as a processor adapted to execute instructions stored on and / or provided thereto in memory coupled to a processor. In this specification, these embodiments or any other form in which the invention may take place can be referred to as technology. Generally, the order of operations of the disclosed processes can be modified within the scope of this invention. Unless otherwise stated, components such as processors or memory described as suitable for performing a task can be implemented as general-purpose means or circuit components configured or otherwise programmed to perform the task at a given time, or as specific means or circuit components manufactured to perform the task. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores adapted to process data (e.g., computer program instructions).

[0014] The methods, processes, and / or operations described herein can be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or elements other than those described herein. Because the algorithms underlying the methods (or the operation of a computer, processor, controller, or other signal processing device) are described herein, the code or instructions for implementing the methods can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0015] If implemented at least in part in software, the controller, processor, device, module, unit, multiplexer, generator, logic, interface, decoder, driver, generator and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller or other signal processing device.

[0016] The following provides a detailed description of embodiments of the present invention, along with drawings illustrating aspects of the invention. The invention has been described in conjunction with these embodiments, but is not limited to any particular embodiment. The invention includes many alternatives, modifications, and equivalents. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes only; the invention may be practiced according to the scope of the claims without requiring some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention.

[0017] Hardware and Firmware

[0018] FIG1 is a block diagram illustrating a system 2 according to an embodiment of the present invention. Referring to FIG1, the system 2 may include a host device 5, a memory system 10, and an embedded reconfigurable SSD data sorting accelerator 15.

[0019] This invention is based on the understanding that, in order to transfer data from modern high-performance SSDs to CPUs in a timely manner, the performance of sorting algorithms can often be limited by insufficient computing resources and RAM in the CPU. For example, database storage engines typically run on general-purpose CPUs that may not be optimized for processing large amounts of data. Furthermore, the computing resources of database storage systems are shared between user and system tasks.

[0020] As an example, in order to retrieve a single dataset record, at least a single database system page is read from the underlying storage. Next, the database system reconstructs the record from the original page data. Database record reconstruction is typically performed on a general-purpose CPU in host device 5, which is not optimized for this type of operation.

[0021] When the dataset for which sorting operations are performed (e.g., database pages) cannot be fully contained within the database storage engine device memory (e.g., memory 508), external sorting techniques are typically applied to the dataset. External sorting typically utilizes periodic data exchange between the computing device's main memory (RAM) and underlying storage memory, both of which reside within the CPU of the host device 5. Modern SSDs offer high I / O bandwidth and relatively low random read / write latency, making them the preferred choice for database systems utilizing external sorting algorithms. Modern high-performance SSDs ensure timely data delivery to the CPU running the sorting algorithm. In this respect, performance limitations when running external sorting algorithms may arise from the lack of computing resources and RAM within the CPU, as described above.

[0022] Furthermore, during external sorting, processed data can be continuously transferred between the main memory of the computing device and the SSD storage device. This continuous data transfer increases power consumption and increases the utilization of the communication interface channel.

[0023] Therefore, in one embodiment of the present invention, an embedded reconfigurable SSD hardware accelerator is provided, which is programmed to perform sorting of built-in SSD database records. In one embodiment of the present invention, the embedded reconfigurable SSD hardware accelerator offloads resources from the host RAM and CPU, thereby reducing power consumption and host interface utilization, thereby speeding up the entire data retrieval process.

[0024] Referring back to FIG1, the memory system 10 can receive requests from the host device 5 and operate in response to the received requests. For example, the memory system 10 can store data to be accessed by the host device 5. The host device 5 can be implemented using any of various types of electronic devices.

[0025] In various embodiments, for example, the host device 5 may be an electronic device, such as a desktop computer, workstation, 3D television, smart television, digital audio recorder, digital audio player, digital image recorder, digital image player, and / or digital video recorder and / or digital video player. In various embodiments, for example, the host device 5 may be a portable electronic device, such as a mobile phone, smartphone, e-book reader, MP3 player, portable multimedia player (PMP), and / or portable game console.

[0026] The memory system 10 can be implemented using any of a variety of storage devices such as solid-state drives (SSDs) and memory cards. In various embodiments, for example, the memory system 10 can be one of a variety of components in electronic devices such as: computers, ultra-mobile personal computers (UMPCs), workstations, netbooks, personal digital assistants (PDAs), portable computers, network tablets, wireless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable gaming devices, navigation devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital image recorders, digital image players, digital video recorders, digital video players, storage devices for data centers, devices capable of receiving and transmitting information in a wireless environment, radio frequency identification (RFID) devices, and one of a variety of electronic devices in home networks, one of a variety of electronic devices in computer networks, one of a variety of electronic devices in telematics networks, or one of a variety of components in computing systems.

[0027] The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory controller 100 can control all operations of the semiconductor memory device 200.

[0028] The semiconductor memory device 200 can perform one or more erase, program, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive commands CMD, addresses ADDR, and data DATA through input / output lines. The semiconductor memory device 200 can receive power PWR through power lines and control signals CTRL through control lines. Depending on the design and configuration of the memory system 10, the control signal CTRL may include, for example, a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, a read enable signal, and other operation signals.

[0029] The memory controller 100 and the semiconductor memory device 200 can be a single semiconductor device such as the solid-state drive (SSD) described above. The SSD may include a storage device for storing data. When the memory system 10 is used in an SSD, the operating speed of the host device (e.g., host device 5 of FIG. 1) connected to the memory system 10 can be improved.

[0030] The memory controller 100 and the semiconductor memory device 200 may also be a single semiconductor device such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 may be a PC card, a compact flash memory (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a miniature multimedia card (RS-MMC), a micro-version of the MMC (micro MMC), a secure digital card (SD card), a mini secure digital card (mini SD card), a micro secure digital card (micro SD card), a high-capacity secure digital card (SDHC), and a universal flash memory (UFS).

[0031] FIG2 is a block diagram illustrating a memory system according to another embodiment of the present invention. For example, the memory system of FIG2 can depict the memory system 10 shown in FIG1.

[0032] Referring to FIG2, the memory system 10 may include a controller 100 and a memory device 200. The memory system 10 may operate in response to requests from a host device (e.g., requests from host device 5 of FIG1), particularly storing data to be accessed by the host device.

[0033] The memory device 200 can store data to be accessed by the host device. For example, the memory device 200 can be a volatile memory device such as dynamic random access memory (DRAM) and / or static random access memory (SRAM), or a non-volatile memory device such as read-only memory (ROM), masked ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM) and / or resistive RAM (RRAM).

[0034] The controller 100 can control the storage of data in the memory device 200. For example, the controller 100 can control the memory device 200 in response to a request from the host device. The controller 100 can provide data read from the memory device 200 to the host device, and can store data provided from the host device into the memory device 200.

[0035] The controller 100 may include a storage device 110, a control component 120, an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150 connected via a bus 160. For example, the control component 120 may be implemented as a processor such as a central processing unit (CPU). For simplicity, the controller 100 may be considered as a host interface layer (HIL).

[0036] Storage device 110 can be used as working memory for memory system 10 and controller 100, and storage device 110 can store data for driving memory system 10 and controller 100. When controller 100 controls the operation of memory device 200, storage device 110 can store data for controller 100 and memory device 200 for operations such as read operation, write operation, programming operation and erase operation.

[0037] The storage device 110 may be volatile memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, the storage device 110 can store data used by the host device for read and write operations in the memory device 200. In order to store data, the storage device 110 may include program memory, data memory, write buffer, read buffer, mapping buffer, etc.

[0038] The control component 120 can control the general operation of the memory system 10 and control the write or read operations of the memory device 200 in response to write or read requests from the host device. For simplicity, the control component 120 (which can drive firmware or other program instructions) can be referred to as the Flash Translation Layer (FTL) and controls the operation of the memory system 10. For example, the FTL can perform operations such as logic-to-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block disposal. L2P mapping is referred to as logical block addressing (LBA).

[0039] The ECC component 130 can detect and correct errors in the data read from the memory device 200 during a read operation. In one embodiment, when the number of error bits is greater than or equal to a threshold number of correctable error bits, the ECC component 130 may not correct the error bits, but may instead output an error correction failure signal indicating that the correction of the error bits has failed.

[0040] In various embodiments, for example, ECC component 130 may perform error correction operations based on coding modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). However, error correction is not limited to these techniques. Therefore, ECC component 130 may include any and all circuitry, systems, or devices suitable for error correction operations.

[0041] For example, host interface 140 may communicate with host devices through one or more of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0042] The memory interface 150 can provide an interface between the controller 100 and the memory device 200, allowing the controller 100 to control the memory device 200 in response to requests from the host device. The memory interface 150 can generate control signals for the memory device 200 and process data under the control of the control component 120. In one embodiment, where the memory device 200 is flash memory, such as NAND flash memory, the memory interface 150 can generate control signals for the memory and process data under the control of the control component 120.

[0043] For example, the memory device 200 shown in FIG2 may include a memory cell array 210, a control circuit 220, a voltage generation circuit 230, a row decoder 240, a page buffer array 250 in the form of a page buffer array, a column decoder 260, and input and output (input / output) circuitry 270 (or SEs of these components). The memory cell array 210 may include multiple memory blocks 211 capable of storing data. The voltage generation circuitry 230, the row decoder 240, the page buffer array 250, the column decoder 260, and the input / output circuitry 270 may form peripheral circuitry of the memory cell array 210. The peripheral circuitry may perform programming, reading, or erasing operations on the memory cell array 210. The control circuitry 220 may control the peripheral circuitry.

[0044] The voltage generation circuit 230 can generate operating voltages at various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages at various levels, such as erase voltage and pass voltage.

[0045] The row decoder 240 can communicate electrically with the voltage generation circuit 230 and a plurality of memory blocks 211. The row decoder 240 can select at least one memory block among the plurality of memory blocks 211 in response to the row address generated by the control circuit 220, and transmit the operating voltage supplied from the voltage generation circuit 230 to the selected memory block.

[0046] The page buffer array 250 can be connected to the memory cell array 210 via bit line BL (shown in FIG3). The page buffer array 250 can precharge the bit line BL with a positive voltage during programming and read operations, transfer data to and receive data from the selected memory block, or temporarily store the transferred data in response to the page buffer control signal generated by the control circuit 220.

[0047] The column decoder 260 can transmit data to and receive data from the page buffer array 250, or it can transmit data to and receive data from the input / output circuit 270.

[0048] Input / output circuit 270 can transmit commands and addresses received from an external device (e.g., memory controller 100 of FIG. 1) to control circuit 220, transmit data from the external device to column decoder 260, or output data from column decoder 260 to an external device via input / output circuit 270. Control circuit 220 can control peripheral circuits in response to commands and addresses.

[0049] FIG3 is a circuit diagram showing a memory block of a semiconductor memory device according to another embodiment of the present invention. For example, the memory block of FIG3 may be any one of the memory blocks 211 of the memory cell array 210 shown in FIG2.

[0050] Referring to Figure 3, memory block 211 may include multiple character lines WL0 to WLn-1, drain select line DSL, and source select line SSL connected to line decoder 240. These lines may be arranged in parallel and have multiple character lines between DSL and SSL.

[0051] Memory block 211 may further include multiple cell strings 221 respectively connected to bit lines BL0 to BLm-1. Each column of cell strings may include one or more drain select transistors (DSTs) and one or more source select transistors (SSTs). In the illustrated embodiment, each cell string has one DST and one SST. In the cell string, multiple memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the select transistors DST and SST. Each of the memory cells may be formed as a multi-layer cell. For example, each of the memory cells may be formed as a single-layer cell (SLC) storing 1 bit of data. Each of the memory cells may be formed as a multi-layer cell (MLC) storing 2 bits of data. Each of the memory cells may be formed as a three-layer cell (TLC) storing 3 bits of data. Each of the memory cells may be formed as a four-layer cell (QLC) storing 4 bits of data.

[0052] The source of the SST in each cell string can be connected to the common source line CSL, and the drain of each DST can be connected to the corresponding bit line. The gate of the SST in the cell string can be connected to SSL, and the gate of the DST in the cell string can be connected to DSL. The gates of memory cells in different cell strings can be connected to their respective word lines. That is, the gate of memory cell MC0 is connected to the corresponding word line WL0, the gate of memory cell MC1 is connected to the corresponding word line WL1, and so on. A group of memory cells connected to a specific word line can be called a physical page. Therefore, the number of physical pages in memory block 211 can correspond to the number of word lines.

[0053] The page buffer array 250 may include a plurality of page buffers 251 connected to bit lines BL0 to BLm-1. The page buffers 251 may operate in response to page buffer control signals. For example, the page buffers 251 may temporarily store data received through bit lines BL0 to BLm-1 or sense the voltage or current of the bit lines during a read or verification operation.

[0054] In various embodiments of the present invention, memory block 211 may be a NAND flash memory cell. However, memory block 211 is not limited to this cell type, but may include NOR flash memory cells. Memory cell array 210 may be implemented as a hybrid flash memory combining two or more types of memory cells, or as a one-NAND flash memory with the controller embedded inside the memory chip.

[0055] Figure 4 is a diagram showing the state or programming voltage (PV) level distribution of different types of cells in a memory device according to an embodiment of the present invention.

[0056] Referring to Figure 4, each memory cell can be implemented using a specific type of cell, such as a single-level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a three-level cell (TLC) storing 3 bits of data, or a four-level cell (QLC) storing 4 bits of data. Typically, all memory cells in a particular memory device are of the same type, but this is not required.

[0057] An SLC can include two states, P0 and P1. P0 can represent an erase state, and P1 can represent a programming state. Since an SLC can be set to one of two different states, each SLC can be programmed or store 1 bit according to the set encoding method. An MLC can include four states, P0, P1, P2, and P3. Among these states, P0 can represent an erase state, and P1 to P3 can represent programming states. Since an MLC can be set to one of four different states, each MLC can be programmed or store 2 bits according to the set encoding method. A TLC can include eight states, P0 to P7. Among these states, P0 can represent an erase state, and P1 to P7 can represent programming states. Since a TLC can be set to one of eight different states, each TLC can be programmed or store 3 bits according to the set encoding method. A QLC can include sixteen states, P0 to P15. Among these states, P0 can represent an erase state, and P1 to P15 can represent programming states. Since a QLC can be set to one of sixteen different states, each QLC can be programmed or stored with 4 bits according to the set encoding method.

[0058] Referring back to Figures 2 and 3, the memory device 200 may include a plurality of memory cells (e.g., NAND flash memory cells). The memory cells are arranged in an array of rows and columns, as shown in Figure 3. Cells in each row are connected to word lines (e.g., WL0), and cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, when a word line is asserted, data to be written ("1" or "0") is provided at the bit line. During a read operation, the word line is asserted again, and the threshold voltage of each cell can then be obtained from the bit line. Multiple pages may share memory cells belonging to (i.e., connected to) the same word line. When the memory cells are implemented using MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cells are implemented using TLC, the multiple pages include an MSB page, a center significant bit (CSB) page, and an LSB page. When memory cells are implemented using QLC, multiple pages include MSB pages, Central Most Significant Bit (CMSB) pages, Central Least Significant Bit (CLSB) pages, and LSB pages. For example, memory cells can be programmed using an encoding scheme (e.g., Gray encoding) to increase the capacity of a memory system 10 such as an SSD.

[0059] In one embodiment of the present invention, a system for accelerating a storage device is provided. Here, as shown in Figures 1 and 2, an SSD data sorting accelerator 15 is embedded in a memory system 10. The SSD data sorting accelerator 15 may communicate with a control component 120 or with a control circuit 220. In one embodiment, the SSD data sorting accelerator 15 may be integrated into the control component 120 and / or the control circuit 220.

[0060] Typically, a database index is a data structure that maintains an index data structure at the cost of additional write and storage space to improve the speed of data retrieval operations on database tables. Indexing all database columns is not always feasible or necessary. When the retrieved database query result set should be sorted by a single column, the database storage engine can sort the result set before returning the sorted data to the query initiator (e.g., the host). The first step in the data sorting process is to store the intermediate query results in a temporal table. In the second step, the database storage engine sorts the temporal table records using the query "order by" parameter. The database query "order by" parameter specifies the database table columns that should be used to sort the result set before returning it to the user. The database storage engine returns the sorted data set, ordered by the column specified by the "order by" parameter, to the query initiator.

[0061] Typically, database systems use external sorting algorithms to sort query results that are not stored in main memory. External sorting is an interactive process involving reading a subset of database table entries from the SSD into local cache memory, sorting the subset, and writing the sorted data to the storage medium. The external sorting algorithm is complete when all sorted subsets of data are merged into a single sorted set representing the final query results returned to the user.

[0062] The database storage engine processes pages by loading them from NAND into memory. Page processing is a computationally intensive task that is typically performed by a general-purpose CPU.

[0063] Figure 5 is a block diagram illustrating a specific accelerated sorting system according to an embodiment of the present invention.

[0064] Referring to FIG5, in one embodiment of the present invention, the SSD controller 510 receives a sorting command from the host 505 to perform hardware-accelerated sorting of database records stored in NAND pages according to the database storage engine page format. In one embodiment, data retrieved from NAND can be sorted according to columns specified in the sorting command. Before starting the sorting / arranging operation, the host 505 configures the SSD data sorting accelerator 15 using the database engine storage page format layout and other database-specific configurations.

[0065] After issuing the SSD sorting command, the database storage engine 507 in the host 505 can delegate the sorting operation to the SSD data sorting accelerator 15, and then the database storage engine 507 can continue to perform other operations. When the sorting operation is completed, the SSD data sorting accelerator 15 notifies the database storage engine 507 that the data set has been sorted and can be retrieved.

[0066] In one embodiment of the present invention, the SSD controller 510 includes a single SSD data sorting accelerator 15. In another embodiment of the present invention, the SSD controller 510 may include a large number of independent data sorting units (SSD data sorting accelerators 15), which allows for parallel processing, making it more efficient than a general-purpose central processing unit (CPU), especially for algorithms that process large blocks of data in parallel.

[0067] As shown in FIG5, the SSD data sorting accelerator 15 may include: a) one or more data sorting accelerator processors 515 configured to sort de-serialized data; b) one or more database page serialization / deserialization (DBPSDU) processors 517 (each including a DBPSDU internal cache memory 517a) configured to retrieve database pages from the memory device of the storage device and deserialize the retrieved database pages into a data structure containing attributes defining the sorting order and metadata; c) one or more database sorting manager (DSM) processors 519 configured to sort the retrieved database pages based on the deserialized database table columns using an upgradeable sorting algorithm; d) one or more sorting algorithm memory (SAM) 530 for storing upgradeable sorting algorithms used by DSA and DMRA; and e) one or more data merging accelerator (DMRA) processors 521 configured to merge sorted subsets of data together to form page identifiers of sorted subsets of data.

[0068] The SSD Host Interface Protocol Layer (HIL) 523 is extended to support sorting logic configuration, sorting algorithm updates, and support for custom SSD sorting commands (SSDSC). In one embodiment of the invention, the SSD sorting logic is configured through the SSD Host Interface to adapt to vendor-specific commands. For example, the input data distribution may affect the performance of the sorting algorithm. Prior knowledge about the input data distribution (e.g., vendor-specific knowledge) and the corresponding sorting algorithm associated with the vendor-specific input data distribution can significantly speed up data sorting. In one embodiment of the invention, this ability to update the sorting algorithm enables improved sorting performance gains by employing a sorting algorithm optimized for the input data.

[0069] After the initial SSD configuration is complete, a table sorting task can be submitted to retrieve the data to be sorted from the NAND. For example, after an SSD sorting command request is issued, the SSD controller's DSM can reserve dedicated computing resources and begin SSD data sorting. The SSD data sorting accelerator 15 can intelligently select between internal SSD sorting methods: internal memory data sorting, external NAND memory sorting, or a weighted combination of the above methods. The selection of the sorting method can be adjusted by the capacity of the available controller volatile memory for temporary storage of the sorted data. For example, the capacity of the controller volatile memory available for internal sorting depends on the memory occupied by other currently running SSD controller tasks. When the data to be sorted is fully contained in the available controller volatile memory, a memory sorting algorithm can be applied. This means that all data is sorted at once. Because sorting is performed internally (in the internal memory) while all data can be stored in volatile memory, the sorting algorithm is much faster than external sorting. Sorting large datasets that cannot be fully contained in the available controller volatile memory may require storing only a portion of the data in the controller volatile memory for sorting. After sorting the data in memory, the sorted data is persisted to NAND, and subsequent data blocks can be loaded into memory for sorting. These described steps are repeated until all datasets are partially or fully sorted. The amount of memory available for storing data for sorting may vary over time, and at some point, the controller memory may have enough memory to hold all unsorted data.

[0070] In one embodiment of the invention, SSD internal logic (e.g., in the Database Sorting Manager 519) evaluates the amount of data to be sorted and the capacity of the available SSD controller volatile memory for the sorting task. Based on the available memory, the DSM 519 can select the optimal sorting method for the current sorting task. When using a correctly used sorting algorithm configured by the host, the optimal sorting method can complete the dataset sorting faster, given the available SSD sorting accelerator computing resources and SSD controller memory utilization. The selection of the optimal sorting method has been described in detail above.

[0071] In another embodiment, the present invention provides a horizontally scalable solution for throughput gain by connecting mirrored hardware-accelerated database sorting SSD accelerators (in parallel) to the database storage engine system. Grouping the hardware-accelerated database sorting SSD accelerators into the storage cluster allows end users to improve the sorting performance of the database storage engine by redirecting sorting tasks to different SSDs. In any case, the completion of the sorting task can be indicated by transmitting the SSD sorting command completion status to the host 505.

[0072] As shown in Figure 5, there exists an SSD memory device with a built-in SSD data sorting accelerator 15. As shown in Figure 5, the built-in SSD data sorting accelerator 15 may include a data sorting accelerator (DSA) 515, a sorting algorithm memory (SAM) 530, an SSD database page serialization / deserialization unit (DBPSDU) 517, a database sorting manager (DSM) 519, and a data merging accelerator (DMRA) 521 integrated into the data path between HIL 523 and FTL 525. The sorting algorithm can be embedded as microcode in the sorting algorithm memory (SAM) 530 and run by the data sorting accelerator (DSA) 515.

[0073] The Central Memory Manager (CMM) 529 is one of the SSD controller components that coordinates access to shared memory space. The DSM 519 coordinates sorting tasks and determines the sorting method used. The DSA 515 performs sorting on deserialized database pages. The DBPSDU 517 deserializes database storage engine pages, on which the DSA sorting algorithm sorts them. Additionally, the DBPSDU 517 supports serializing data into a database storage engine page storage format.

[0074] Figure 6 describes a virtual-to-physical database table storage mapping scheme. The database system stores records in files divided into fixed-size units called pages, shown in Figure 6 as page 0, page 1, ..., page n. Database system pages are aligned in NAND pages, and a single database page can consist of one or more NAND pages. In the case shown in Figure 6, the database page is completely contained within the physical NAND page, i.e., the size of the database virtual page is equal to the size of the NAND page. In Figure 6, database page m 700 is mapped to NAND page ε 700a through virtual-to-physical database page mapping table 701, and the size of page m 700 is equal to the size of NAND page ε 700a. In one embodiment of the invention, pages are organized in a way that minimizes the storage overhead (operation and storage space) for each stored data record.

[0075] Two examples of this page organization are the N-ary storage model (NSM) and the cross-partition attribute (PAX). U.S. Patent No. 9,798,674 (the entire contents of which are incorporated herein by reference) describes an N-ary tree for mapping virtual memory space. In the '674 patent, an N-ary tree (where N is a power of 2 (e.g., 2, 4, 8, 16, etc.) comprises multiple levels, each corresponding to a different page table size. The '674 N-ary tree can be used as an N-ary storage model in this invention. U.S. Patent Application Publication No. 2015 / 0347426 (the entire contents of which are incorporated herein by reference) describes PAX data storage, where each page represents a set of rows and within a block, the first column is stored first, and the corresponding data points are stored as fields. '426 PAX data storage can be used in this invention. DBPSDU 517 parses the NAND page layout according to the page format, deserializes the record fields, and extracts the fields that define the sort order. Figure 7 is a description of the auxiliary metadata accompanying the database record fields. As shown in Figure 7, the deserialized database record fields are accompanied by auxiliary metadata that uniquely identifies the location of the database record within the database storage page.

[0076] More specifically, auxiliary metadata uniquely identifies database records within a database storage page. To identify a database record within a database storage page, it is only necessary to know the record offset within the page and its corresponding page ID. Figure 7 depicts the database table columns for sorting dataset records, and the auxiliary metadata pointing to complete dataset records within the NAND page. The database table columns defining the sort order are a subset of all database table columns. For sorting table records, it is sufficient to deserialize the columns (attributes / fields) defining the dataset order and sort the deserialized column fields, which are accompanied by auxiliary pointers to complete table records. The process of reducing a table to the columns defining the dataset sort order and the auxiliary metadata pointing to the record locations within the NAND page is referred to herein as table reduction. Finally, by traversing the reduced table in sort order, the table sort order can be reconstructed from the auxiliary metadata of the reduced sort table. In Figure 7, columns 0, 1, ..., ε are the columns defining the sort order. Columns 0, 1, ..., ε are subsets of the database table columns. Each deserialized record is accompanied by metadata containing offsets within the page, i.e., the offsets of records within the page (e.g., a database storage system page layout such as NSM or PAX as described above). The NAND page ID (the location of record n) is a metadata identifier that uniquely identifies the NAND page across all NAND pages.

[0077] In one embodiment of the present invention, the sorted database table is reduced to columns, through which dataset sorting is performed using auxiliary metadata containing pointers to determine the record positions within the NAND page. This method reduces NAND wear leveling by minimizing NAND programming loops during the external sorting process applied to the entire table of records. In one embodiment of the present invention, the sorted data is kept in the same location throughout the sorting process, and it is a pointer to the database record being sorted. Furthermore, since not all sorted database table record attributes are sorted in memory, but only selected attributes (e.g., attributes defining the sort order) are sorted, more records can be accommodated in SSD memory (SRAM or DRAM) for internal memory sorting, thereby reducing the overall sorting time by not having to store all sorted record fields in the NAND 527.

[0078] In one embodiment of the present invention, the SSD host interface protocol layer is extended to support SSD sorting logic configuration, sorting algorithm updates, and data sorting commands through the host interface protocol. The SSD host protocol extension can be implemented by adding vendor-specific SSD sorting commands, and the SSD sorting logic configuration commands can be set to the already supported command set required for SSD operation. The SSD sorting command set can extend the SSD host protocol functionality to provide complete control over the applied sorting algorithm, database page storage format configuration, sorting task priority, SSD sorting logic configuration, and / or SSD sorting task submission. These commands can write to and read from the configuration DSM and DBPSDU address spaces.

[0079] Figure 12 is a description of the DBPSDU memory address mapping. The DBPSDU memory mapping includes a database page storage format configuration address space 1200, which is used for configuring the database page storage format, such as page header layout, database page size, supported database data type descriptions, maximum number of records per page, and other database page layout configurations for DBPSDU page serialization / deserialization. The DBPSDU status address space 1201 may contain serialization / deserialization logic operation status information about the number of currently active serialization / deserialization threads, statistics about the memory consumption of serialization / deserialization threads, the number of pages processed, and correctable / uncorrectable error states.

[0080] Figure 13 is a depiction of the DSM memory mapping. The sorting algorithm microcode address space 1300 can be used as storage memory for sorting the algorithm microcode, used by the DSA logic and for the SAM 530 for deserializing data sorting. The sorting algorithm update provides the possibility to improve sorting speed by applying an appropriate (more suitable) algorithm to sort data. For example, the DSM status page address space 1301 can contain status information about the SSD sorting accelerator operation: such as the number of NAND pages to be processed, the number of pages to be sorted, the number of pages to be merged, and the number of pages to be merged. The DSM control address space 1302 can store the configuration of the maximum capacity of SRAM and DRAM reserved for sorting and merging operations and the allocation of reserved SRAM / DRAM memory between the DSA and DMRA. The DSM database page storage format configuration space 1200 can be configured for the SSD sorting logic according to the required database page layout. The page storage layout can be unified throughout the database storage system; therefore, the configuration spaces of the DSM and DBPSDU can be configured only once for the page layout. In embodiments of the present invention, after the initial DSM and DBPSDU configuration is completed, the database sorting task can be submitted without additional DSM and DBPSDU configuration overhead.

[0081] The database table sorting task can be submitted to the SSD data sorting accelerator 15 through the aforementioned vendor-specific sorting command, hereinafter referred to as the SSD sorting command (SSDSC). The SSDSC includes the following input parameters: a) the columns to be sorted in the dataset, b) a set of page IDs to be sorted, and c) the target host memory address of the page ID records to be written to the database. After completing the sorting command, the SSD controller's DSM notifies the host by sending a corresponding completion status command.

[0082] Figures 9A and 9B are flowcharts according to another embodiment of the present invention, which together depict an example of the SSD sorting command execution flow. The execution flow is described below with reference to Figures 5, 8, 9A, 9B, 12, and 13: 1. As shown in Figures 9A and 9B, HIL 523 identifies the internal SSD sorting command and adds it to the waiting execution queue 601, and then begins executing the command. 2. HIL retrieves the SSD sorting command from the waiting execution queue 601. 3. HIL notifies DSM 519 of the incoming SSD sorting command. 4. DSM 519 retrieves the NAND page ID to be sorted from HIL 523. Based on the submitted sorting command parameters, DSM configuration, and available computing and memory resources, DSM 519 determines the optimal sorting method for the sorting operation. 5. DSM 519 uses, for example, the DBPSDU memory mapping in Figure 12 and the DSM memory mapping in Figure 13 to reserve memory, DBPSDU, DMRA, and DSA computing resources (or processors 515, 517, 521) for the upcoming sorting task. The amount of memory and computing resources allocated to hold the raw NAND pages is related to the number of independently run parallel sorting threads and the total dataset sorting time. 6. After resource reservation, DSM 519 notifies FTL 525 to begin fetching database pages from NAND 527. 7. Parallel processing “a” and “b” (corresponding to Figures 9A and 9B, respectively) can be utilized as follows: a. Although described in additional detail in Figure 9A, DSA 515 is also notified about which NAND pages should be sorted when pages begin to arrive at controller memory (SRAM or DRAM). i. DSA 515 instructs DBPSDU 517 to read the required raw database pages and deserialize them, storing them in the DBPSDU internal cache 517a. Records are deserialized into a data structure containing attributes defining the sort order and metadata, as shown in Figures 7 and 8. ii. The deserialized records are initially sorted by DSA 515 in the DBPSDU internal cache 517a. iii. After the initial sorting is complete, the sorted database records are serialized and moved from the internal cache 517a to SSD volatile memory, such as SRAM / DRAM. The sorted data obtained from this step will subsequently be used in the merging step of the sorting algorithm. iv. As shown in branch 602 of Figure 9A, the steps in process "a" (data sorting) are repeated until all pages are sorted. b. Although described in additional details in Figure 9B. DMRA 521 merges the sorted subset of data into temporary volatile memory. i. DSM 519 provides a buffer ID ready to be merged into DMRA 521.ii. DMRA 521 reads data for merging. When the merged data cannot fit into the memory space allocated for the sorting task in the SSD memory (e.g., SRAM / DRAM), the merged output is redirected to DBPSDU 517 for serialization and further stored in NAND 527. After page serialization is complete, DBPSDU 517 notifies DSM 519 and subsequently FIL 525. (1) DSM 519 requests FIL 523 to persist the serialized sorted data accompanying the auxiliary metadata to NAND. iii. As shown in branch 603 of FIG9A, the following situation may occur: the data merging step is run on the sorted data set loaded from NAND 527, and the sorted data set is only partially contained in the memory allocated for the sorting task. In this case, data is gradually transferred from NAND 527 to SSD volatile memory SRAM / DRAM. In one embodiment, only the amount of data contained in the memory allocated for the merging operation is transferred. 8. Repeat steps “a” and “b” above until unsorted data (or unmerged data) is available. 9. As shown in Figures 9A and 9B, after the merging step is complete, the sorting auxiliary metadata is read from the NAND. Using the sorting auxiliary metadata, the sorting order of the data sent to the internal SSD for sorting is reproduced. 10. At 605, HIL 523 returns the NAND page IDs of the sorted data to the host. The page IDs are returned in the correct order to preserve the sorted data order. 11. As shown in Figures 9A and 9B, at 605, after the sorting command is complete and the SSD controller 510 has processed all pages, HIL 523 sends a command completion notification and command completion status to the SSD sorting command initiator (e.g., database storage engine 507).

[0083] As described above, the hardware-accelerated database sorting SSD supports updating the sorting algorithm via vendor-specific commands and sorting algorithm update commands. SSD end-users may have different criteria when selecting a sorting algorithm. For example, prioritizing one algorithm over another may be influenced by algorithm simplicity, runtime, memory consumption, parallel processing capabilities, stability, and assumptions about the input data. Applying an appropriately selected algorithm to the input data used for sorting can significantly improve sorting time.

[0084] Therefore, as described above, the present invention can offload host RAM and CPU resources, reduce power consumption and host interface utilization, and speed up the entire data retrieval process.

[0085] The following provides an example of a system utilizing hardware-accelerated database sorting. In this example, system components and attributes include: - A database search-accelerated SSD with NVMe and a PCIe interface. High-speed NVM (NVMe) is a logical device interface protocol for accessing non-volatile storage media typically attached via high-speed PCI (PCIe) buses. - On the host side, the database storage system is connected to an SSD controller (e.g., CMM 529 in SSD controller 510) via NVMe with a PCIe interface. A database storage engine (e.g., database storage engine 507 in host 505) can issue NVMe commands to SSD controller 510. - The SSD supports vendor-specific commands: setting / getting configuration attributes for DBPASDU 517, DSM 519, DMRA 521, and DSA 515. - The SSD supports vendor-specific commands: updating the DSA microcode to update the DSA sorting algorithm stored in the SAM 530. - The SSD supports vendor-specific commands: SSD sorting commands. - The database storage system knows the database files mapped to the underlying SSD pages.

[0086] Before issuing the first SSD sort command, the database system configures DBPASDU 517 and DSM 519 as the database page layout format to be used. The database system in this example uses the PAX page format. Figure 10 is a depiction of an example of the PAX page format. Table 1004 in Figure 10 shows the employer ID, name, and service period information mapped to the PAX page in this example.

[0087] In this PAX format layout example: - Fixed-length attribute values ​​are stored in the "F Minimum" page. At the end of each F Minimum page, there is a present bit vector, where each record has one entry representing the nullable value of a nullable attribute. A nullable attribute can contain NULL values ​​(no value). A present bit set to "0" indicates that the attribute contains a null value. A present bit set to "1" indicates that the attribute contains a value according to its type. - Variable-length attribute values ​​are stored in the "V Minimum" page. The V Minimum page is divided into slots by pointers pointing to the end of each value. In Figure 10, the V Minimum page 1002 is divided into two variable-length attributes by offset pointers 1000 and 1001. The first attribute, containing the string value "Mike", starts at the beginning of the V Minimum page 1002, is offset zero by 1005 from the beginning of the V Minimum page 1002, and ends at offset 1000a, i.e., offset pointer 1000 points to offset 1000a. In other words, the first attribute is divided by offset addresses 1005 and 1000a. The second attribute contains the string value "Isabella", which starts at offset 1000a from the smallest page 1002 of V and ends at offset 1001a, meaning the offset pointer 1001 points to offset 1001a. The second attribute is also divided by offset addresses 1000a and 1001a. Null values ​​are represented by null pointers.

[0088] Each newly allocated page contains a page header 1006, and the number of minimum pages equals the relevance. The page header contains the number of attributes, the attribute size (for fixed-length attributes), the offset to the beginning of the minimum page, the current number of records on the page, and the total available space. In this example, there are two F minimum pages, one for the employee ID attribute and one for the length of the employment attribute. The name attribute ("Mike" or "Isabella") is a variable-length string, so it is stored in a V minimum page. There is an offset at the end of each V minimum page from the end of the variable-length value. In Figure 10, the table 1004 depicted will be mapped to NAND page 1006.

[0089] As previously described, DBPASDU 517 and DSM 519 are configured to deserialize PAX pages. After DBPASDU 517 and DSM 519 are initialized, the database sorting hardware-accelerated SSD of this invention receives and performs sorting tasks. As an example, suppose the database storage system processes requests to / from a large social network database. In this example, a cluster of hardware-accelerated database sorting SSDs serves as the storage device for the database storage engine, i.e., the physical device that receives and retains electronic data. The database in this example contains information about the popularity of social network posts ranging from 1 to 10, as well as the posting date. The database storage engine in this example will frequently handle queries that can aggregate user posts at a given date interval and geographic location, and can sort filtered posts by popularity. For such queries, the database storage system in this example benefits from delegating the sorting operation to the hardware-accelerated sorting SSD, rather than processing the operation in the CPU of the social network database storage engine. In this example, the query result set may contain approximately 700 million entries that satisfy the query search criteria. In the next step of the query process, the result set will be sorted using the hardware-accelerated database sorting SSD of this invention.

[0090] Furthermore, in this example, the following steps can be performed during the exemplary sorting: - Due to the popularity of user-posted data, sorting by field results in values ​​varying within a range [1...10]. Therefore, if a non-comparison-based sorting algorithm is applied, the sorting time will be significantly improved. Therefore, the database storage engine (e.g., database engine 507 in host 525) issues an NVMe vendor-specific command to update the sorting algorithm microcode in SAM 530 and update the SAM sorting algorithm microcode via bucket sorting algorithm microcode. - In the next step, the database storage engine issues an SSD sorting command with all necessary parameters. The SSD sorting logic is provided to the NAND page ID via the command parameters, which includes the data to be sorted, sorted by column index, defined sort order, and other auxiliary configurations. - In the next step, the SSD data sorting accelerator 15 operates as described in the SSD sorting command execution flow discussed above. - After the sorting command is executed, the database storage engine 507 in the host is given a NAND page ID as the sorting query result set, so that the data can be returned to the database query initiator.

[0091] FIG11 is a diagram illustrating a sorting operation according to another embodiment of the present invention. As depicted in FIG11, the method receives a sorting command from a host at 1101. At 1103, in response to receiving the sorting command, the method configures a storage device for optimal sorting by determining at least one storage location for storing the data to be sorted. At 1105, the method generates a sorted subset of data using an scalable sorting algorithm and stores the sorted subset of data based on at least one storage location indicating the data to be sorted. At 1107, the method provides the host with a page identifier (ID) of the sorted subset of data.

[0092] Through this method, at least one storage location can be determined based on at least a) the amount of data to be sorted and b) the available storage space in the memory of the storage device. The method can further retrieve database pages from the memory of the storage device, deserialize the retrieved database pages into a data structure containing attributes defining the sorting order and metadata, sort the deserialized database pages based on the attributes defining the sorting order, save a subset of serialized data not contained in the controller memory to a NAND flash memory, and merge the sorted subsets of data together to form a page identifier for the sorted subsets of data. In response to receiving a sorting algorithm update command, the method can update the scalable sorting algorithm to be used for data sorting using a sorting / arrangement algorithm provided as write data for the sorting algorithm update command. The method can further store the retrieved database pages in a temporary storage device, sort the deserialized database pages, serialize the sorted database pages, and store the serialized entries of the sorted database pages in the temporary storage device. This method can further configure multiple storage devices to achieve optimal sorting and direct different sorting tasks to different storage devices. The method can further read database records including metadata from the storage devices, process each database record including metadata individually to determine the record relationships between them, and arrange the sorted data subsets. The method can further reserve memory for generating the sorted data subset and for storing the sorted data subsets from previous steps. The method can update the sorting algorithm used to sort the deserialized database pages.

[0093] This method can operate on a storage device having a solid-state drive memory buffer, a NAND memory of the storage device, and a memory controller of the storage device, and can reserve memory in at least one of the solid-state drive memory buffer, the NAND memory, or the controller memory. When the solid-state drive memory buffer does not have available space for all the data to be sorted, the method can store some of the data to be sorted in the NAND memory, and the method can merge data from the solid-state drive memory buffer into the NAND memory.

[0094] In one embodiment of the present invention, as shown in the figure above, a system for accelerating the sorting of data from a storage device has: a) a host interface for communication between a host and a storage device; b) memory in the storage device for storing data; and c) a reconfigurable SSD hardware accelerator, including a processor in the storage device, communicating with the memory and the host interface, and configured to: a) configure the storage device for optimal sorting by allocating at least one storage location for storing data to be sorted; b) generate a sorted subset of data retrieved from the memory using an upgradeable sorting algorithm; c) store the sorted subset of data based on at least one storage location indicating the data to be stored and sorted; and d) provide a page identifier (ID) of the sorted subset of data to the host.

[0095] In a data acceleration sorting system, a reconfigurable SSD hardware accelerator can be configured to allocate at least one storage location based at least a) the amount of data to be sorted and b) the available storage space in the memory of the storage device. In a data acceleration sorting system, the reconfigurable SSD hardware accelerator includes one or more of the following: a) a database page serialization processor configured to retrieve database pages from the memory of the storage device and deserialize the retrieved database pages into a data structure containing attributes defining the sorting order and metadata; b) a database sorting manager processor configured to sort the deserialized database pages based on the attributes defining the sorting order; c) a data sorting accelerator processor; and d) a data merging accelerator processor configured to merge sorted subsets of data together to form a page identifier for the sorted subset of data.

[0096] In the data acceleration sorting system, the data sorting accelerator processor and the data merging accelerator processor are configured to perform data sorting using an upgradeable sorting algorithm configured in the algorithm sorting memory.

[0097] In the data acceleration sorting system, a reconfigurable SSD hardware accelerator can be configured to store retrieved database pages in a temporary storage device, sort the deserialized database pages, serialize the sorted database pages, and store the serialized entries of the sorted database pages in the temporary storage device. The reconfigurable SSD hardware accelerator can be configured to direct different sorting tasks to multiple different storage devices. Furthermore, the reconfigurable SSD hardware accelerator can be configured to: read database records including metadata from the storage device, process each database record including metadata individually to determine the record relationships between them, and arrange the sorted subset of data.

[0098] In a data acceleration sorting system, a reconfigurable SSD hardware accelerator can be configured to reserve memory for generating a subset of data for sorting and for storing the subset of data for sorting. In a data acceleration sorting system, the storage device can be a solid-state drive memory buffer, a NAND memory, and a controller memory of the storage device, and the reconfigurable SSD hardware accelerator can be configured to reserve memory in at least one of the solid-state drive memory buffer, NAND memory, or controller memory.

[0099] In a data acceleration sorting system, a reconfigurable SSD hardware accelerator can be configured to transfer some of the data to NAND memory when the solid-state drive memory buffer does not have available space for all the data to be sorted. Furthermore, the reconfigurable SSD hardware accelerator can be configured to merge data from the solid-state drive memory buffer into the NAND memory.

[0100] Although the foregoing embodiments have been shown and described in detail for clarity and understanding, the invention is not limited to the details provided. As will be understood by those skilled in the art based on the foregoing disclosure, many alternative ways of implementing the invention exist. Therefore, the disclosed embodiments are exemplary and not restrictive. The invention is intended to cover all modifications and alternatives to the disclosed embodiments. Furthermore, the disclosed embodiments can be combined to form other embodiments.

[0101] In fact, embodiments and functional operations of the subject matter described in this patent document can be implemented in various systems, digital electronic circuits including the structures disclosed in this specification and their equivalents or combinations thereof, or in computer software, firmware, or hardware. Embodiments of the subject matter described in this specification can be implemented as one or more computer program products (i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer-readable medium) to be run by or to control the operation of a data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a material composition that influences machine-readable propagation signals, or combinations thereof. The terms "data processing unit" or "data processing device" encompass all devices, apparatuses, and machines for processing data (e.g., including programmable processors, computers, or multiple processors or computers). In addition to hardware, the device may also include code that creates an operating environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, or combinations thereof.

[0102] A computer program (also known as a program, software, software application, script, or code) can be written in any programming language (including compiled or interpreted languages) and can be deployed in any form, including as a standalone program suitable for use in a computing environment, or as a module, component, subroutine, or other unit. A computer program does not necessarily correspond to a file in a file system. A program can be stored as part of a file that stores other programs or data (e.g., one or more scripts stored in a markup language document), a single file dedicated to the program in question, or multiple coordination files (e.g., a file that stores part of one or more modules, subroutines, or code). A computer program can be deployed to run on a single computer or on multiple computers located at one site or distributed across multiple sites and interconnected via a communications network.

[0103] The processes and logic flows described in this specification can be executed by one or more programmable processors that run one or more computer programs to perform functions by manipulating input data and generating data. The processes and logic flows can also be executed by special-purpose logic circuits (e.g., FPGAs (Field Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits)), and the devices can also be implemented as special-purpose logic circuits.

[0104] Processors suitable for running computer programs include, for example, both general-purpose microprocessors and special-purpose microprocessors, as well as any one or more processors of any kind of digital computer. Typically, a processor receives instructions and data from read-only memory or random access memory, or both. The basic components of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices (e.g., magneto-optical, magneto-optical, or optical disc) for storing data, or operatively coupled to receive data from or transfer data to one or more mass storage devices (e.g., magneto-optical, magneto-optical, or optical disc). However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices). The processor and memory may be supplemented by or incorporated into special-purpose logic circuitry.

[0105] Although this patent document contains numerous details, these details should not be construed as limiting the scope of any invention or any invention that may be claimed, but rather as a description of specific features that may be present in a particular embodiment of a particular invention. Certain features described in the context of individual embodiments in this patent document may also be implemented in combinations of individual embodiments. Conversely, various features described in the context of individual embodiments may also be implemented individually in multiple embodiments, or in any applicable sub-combinations. Furthermore, although the foregoing may describe features as functioning in certain combinations, in some cases one or more features of a combination may be excluded from the combination, and the combination may relate to sub-combinations or variations thereof.

[0106] Similarly, although the operations are depicted in a specific order in the figures, this should not be construed as requiring the operations to be performed in the specific order shown or in a sequential order to achieve the desired effect, or requiring all the operations shown to be performed. Furthermore, the separation of the various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

[0107] This patent document describes only a few embodiments and examples, and other embodiments, improvements and variations can be derived based on the content described and shown in this patent document. [Simplified Explanation of the Diagram]

[0011] Figure 1 is a block diagram illustrating a sorting system according to an embodiment of the present invention. Figure 2 is a block diagram illustrating a memory system according to another embodiment of the present invention. Figure 3 is a circuit diagram illustrating a memory block of a memory device according to yet another embodiment of the present invention. Figure 4 is a diagram illustrating the state distribution of different types of units of a memory device according to an embodiment of the present invention. Figure 5 is a block diagram illustrating a specific accelerated sorting system according to an embodiment of the present invention. Figure 6 is a description of a virtual-to-physical database table storage mapping scheme. Figure 7 is a description of auxiliary metadata accompanying database record fields. Figure 8 is a description of database table compression (reduction) into a dataset formed by a storage sorting table and columns of auxiliary metadata. Figures 9A and 9B are flowcharts according to yet another embodiment of the present invention. Figure 10 is a description of partition attributes across (PAX) pages. Figure 11 is a diagram illustrating a sorting operation according to another embodiment of the present invention. Figure 12 is a diagram illustrating a DBPSDU memory mapping according to yet another embodiment of the present invention. Figure 13 is a diagram illustrating a DSM memory mapping according to yet another embodiment of the present invention.

Claims

1. A method of operating a solid-state drive (SSD) storage device, comprising: Receive sorting commands from the host; In response to receiving the sorting command, the system configures the SSD storage device for optimal sorting based on the capacity of the available SSD controller volatile memory for sorting, and in response to receiving the sorting command, determines at least one storage location within the SSD storage device to store the data to be sorted; generates a sorted subset of data using an optional scalable sorting algorithm in the SSD storage device, and stores the sorted subset of data based on the at least one storage location within the SSD storage device indicating where the data to be sorted is to be stored; and provides the host with a page identifier for the sorted subset of data, i.e., the page ID of the sorted subset of data.

2. The method of claim 1, wherein determining the at least one storage location is based at least on a) the amount of data to be sorted and b) the available storage space in the memory of the SSD storage device.

3. The method as described in claim 1, wherein utilizing the optional scalable sorting algorithm comprises: Retrieves database pages from the memory of the SSD storage device; deserializes the retrieved database pages into a data structure containing attributes defining the sorting order and metadata; sorts the deserialized database pages based on the attributes defining the sorting order using the optional scalable sorting algorithm; and merges the sorted data subsets together to form a page identifier for the sorted data subset.

4. The method as described in claim 3, further comprising: In response to receiving a sorting algorithm update command, the optional upgradable sorting algorithm to be used for sorting the data is updated using the sorting algorithm provided as the write data of the sorting algorithm update command.

5. The method as described in claim 3, further comprising: The retrieved database pages are stored in a temporary storage device, and the deserialized database pages are sorted, the sorted database pages are serialized, and the serialized entries of the sorted database pages are stored in the temporary storage device.

6. The method as described in claim 1, wherein configuring the SSD storage device includes: Configure multiple SSD storage devices to achieve optimal sorting; and route different sorting tasks to different SSD storage devices.

7. The method as described in claim 1, wherein generating the sorted subset of data comprises: Read database records, including metadata, from the SSD storage device; Each database record, including the metadata, is processed individually to determine the relationship between the records; And the sorted subset of data is arranged.

8. The method as described in claim 1, further comprising: The memory used to generate the sorted subset of data and to store the sorted subset of data is reserved.

9. The method of claim 1, wherein the SSD storage device includes a solid-state drive memory buffer, NAND memory, and a memory controller, and the reserved memory includes reserving the memory in at least one of the solid-state drive memory buffer, the NAND memory, and the memory controller.

10. The method of claim 9, further comprising: When the solid-state drive memory buffer does not have available space for all the data to be sorted, some of the data is transferred to the NAND memory.

11. The method as described in claim 10, further comprising: Data from the solid-state drive memory buffer is merged into the NAND memory.

12. A system for accelerating the sorting of data from a solid-state drive (SSD) storage device, the system comprising: Host interface for communication between the host and the SSD storage device; The SSD storage device contains memory for storing data; And a reconfigurable built-in SSD hardware accelerator, including a processor in the SSD storage device, communicating with the memory and the host interface, and a) configuring the SSD storage device for optimal sorting based on the capacity of the available SSD controller volatile memory for sorting, b) allocating at least one storage location within the SSD storage device to store the data to be sorted, c) generating a sorted subset of data retrieved from the memory using an optional scalable sorting algorithm, d) storing the sorted subset of data based on the at least one storage location within the SSD storage device indicating where the data to be sorted is stored, and e) providing the host with a page identifier for the sorted subset of data, i.e., the page ID of the sorted subset of data.

13. The system as claimed in claim 12, wherein the reconfigurable built-in SSD hardware accelerator allocates the at least one storage location based at least on a) the amount of data to be sorted and b) the available storage space in the memory of the SSD storage device.

14. The system of claim 12, wherein the reconfigurable built-in SSD hardware accelerator comprises one or more of the following: a) a library page serialization processor that retrieves library pages from the memory device of the SSD storage device and deserializes the retrieved library pages into a data structure containing attributes defining a sorting order and metadata; b) a library sorting manager processor that sorts the deserialized library pages based on the attributes defining the sorting order using the optional scalable sorting algorithm; c) a data sorting accelerator processor; and d) a data merging accelerator processor that merges the sorted subsets of data together to form a page identifier for the sorted subsets of data.

15. The system of claim 12, wherein the reconfigurable built-in SSD hardware accelerator stores the retrieved database pages in a temporary storage device, sorts the deserialized database pages, serializes the sorted database pages, and stores the serialized entries of the sorted database pages in the temporary storage device.

16. The system as described in claim 12, wherein the reconfigurable built-in SSD hardware accelerator directs different sorting tasks to different multiple SSD storage devices.

17. The system of claim 12, wherein the reconfigurable built-in SSD hardware accelerator: reads database records including metadata from the SSD storage device; processes each database record including the metadata individually to determine record relationships between them; and sorts the sorted subset of data.

18. The system of claim 12, wherein the reconfigurable built-in SSD hardware accelerator reserves memory for generating the sorted subset of data and storing the sorted subset of data.

19. The system of claim 12, wherein the SSD storage device includes a solid-state drive memory buffer, NAND memory, and a memory controller, and wherein the reconfigurable built-in SSD hardware accelerator reserves memory in at least one of the solid-state drive memory buffer, the NAND memory, and the memory controller.

20. The system of claim 19, wherein the reconfigurable built-in SSD hardware accelerator transfers some of the data to the NAND memory when the solid-state drive memory buffer does not have available space for all of the data to be sorted.

21. The system as claimed in claim 20, wherein the reconfigurable built-in SSD hardware accelerator merges data from the solid-state drive memory buffer into the NAND memory.

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