Circuit and timer for memory

Abstract

Various examples may include a device comprising: a memory for storing incoming or outgoing data; a timer for generating a timing signal in response to a user-configurable time interval; and a circuit for moving the incoming or outgoing data from the memory, at least partially in response to the timing signal generated by the timer. Various examples may include a method comprising: receiving a data packet at a network interface; writing data of the data packet into a memory; receiving a timing signal; and providing the data from the memory at a device interface in response to the timing signal. Various examples may include a method comprising: receiving data at a device interface; writing the data into a memory; receiving a timing signal; and providing a data packet containing the data at a network interface in response to the timing signal. Related apparatuses, systems, and methods are also disclosed.

Description

[Technical Field]

[0001] [Priority Claim] This application claims the priority date of U.S. Patent Application Serial No. 17 / 812,379, filed July 13, 2022, entitled "Circuit and Timer for Memory" and International Patent Application No. PCT / US2022 / 073692, filed July 13, 2022, entitled "Circuit and Timer for Memory". Both patent applications claim the priority date of U.S. Provisional Patent Application No. 63 / 203,475, filed July 23, 2021, entitled "Isochronous Operations in a Network", the disclosure of which is incorporated herein by reference in its entirety.

[0002] This specification generally relates to a circuit and timer for memory. More specifically, and without limitation, certain examples relate to a circuit and timer for managing the movement of data into or out of memory. [Previous Technology]

[0003] To transmit data over an Ethernet network, it may be necessary to insert data into an Ethernet packet that includes a header and a frame check sequence. To insert data into an Ethernet packet, the data may be stored in a buffer after generation (or reception) and may be read from the buffer into the packet during generation or transmission. Additionally, to receive data over an Ethernet network, it may be necessary to retrieve data from an Ethernet packet and store the data in a buffer before providing it at an interface. [Summary of the Invention]

[0004] Various examples may include a device comprising: a memory for storing incoming or outgoing data; a timer for generating a timing signal in response to a user-configurable time interval; and a circuit for moving the incoming or outgoing data from the memory, at least partially in response to the timing signal generated by the timer. Various examples may include a method comprising: receiving a data packet at a network interface; writing data of the data packet into a memory; receiving a timing signal; and providing the data from the memory at a device interface in response to the timing signal. Various examples may include a method comprising: receiving data at a device interface; writing the data into a memory; receiving a timing signal; and providing a data packet containing the data at a network interface in response to the timing signal. Related devices, systems, and methods are also disclosed.

Implementation Method

[0006] In the following detailed description, reference is made to the accompanying drawings, which form part of this disclosure and illustrate specific examples of how this disclosure can be practiced. These examples are described in sufficient detail to enable those skilled in the art to practice this disclosure. However, other examples may be used, and structural, material, and procedural changes may be made without departing from the scope of this disclosure.

[0007] The diagrams presented herein are not actual views of any particular method, system, apparatus, or structure, but are merely idealized illustrations used to describe examples of this disclosure. The diagrams presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in various diagrams may retain the same or similar numbering; however, similarity in numbering does not imply that the structures or components must be identical in size, composition, configuration, or any other property.

[0008] The following description may include examples to help those skilled in the art to practice the disclosed examples. The use of the terms “illustrative,” “by example,” and “for example” means that the description is explanatory, and although the scope of this disclosure is intended to cover examples and legal equivalents, the use of these terms is not intended to limit the scope of one example of this disclosure to the specified components, steps, features, functions, or the like.

[0009] It will be readily understood that the components of the examples generally described herein and illustrated in the diagrams can be configured and designed in a wide variety of different configurations. Therefore, the following descriptions of various examples are not intended to limit the scope of this disclosure, but merely to illustrate various examples. Although various forms of examples may be presented in the diagrams, the diagrams are not necessarily drawn to scale unless specifically indicated.

[0010] Furthermore, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure, unless otherwise specified herein. Components, circuits, and functions may be illustrated in block diagram form so as not to obscure this disclosure with unnecessary details. Conversely, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure, unless otherwise specified herein. In addition, block definitions and logical divisions between various blocks are examples of a specific embodiment. Those skilled in the art will readily understand that this disclosure can be implemented using many other division solutions. In most cases, details concerning timing considerations and such are omitted where they are unnecessary for obtaining a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0011] Those skilled in the art will understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, and symbols throughout this specification can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. For clarity of presentation and illustration, certain diagrams may illustrate several signals as a single signal. Those skilled in the art will understand that a signal can represent a signal bus, wherein the bus can have multiple bit widths, and this disclosure can be applied to any number of data signals comprising a single data signal. Those skilled in the art will understand that this disclosure covers quantum information and communication of qubits used to represent quantum information.

[0012] The various illustrative logic blocks, modules, and circuits described in connection with the examples disclosed herein can be implemented or executed using a general-purpose processor, special-purpose processor, digital signal processor (DSP), integrated circuit (IC), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof designed to perform the functions described herein. A general-purpose processor (also referred to herein as a host processor or simply host) may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of arithmetic devices (such as a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration). A general-purpose computer containing a processor is considered a special-purpose computer when executing arithmetic instructions (e.g., non-limitingly, software code) related to the examples disclosed herein.

[0013] Examples can be described with respect to programs illustrated as flowcharts, flow diagrams, structure diagrams, or block diagrams. Although a flowchart may describe actions as a sequential procedure, many of these actions may be performed in another sequence, in parallel, or substantially simultaneously. Furthermore, the order of actions may be rearranged. Without limitation, a program may correspond to a method, thread, function, program step, subroutine, or subroutine. Moreover, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, a function may be stored or transmitted as one or more instructions or program code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, and communication media includes any media that facilitates the transfer of a computer program from one place to another.

[0014] Automation / control systems (e.g., non-limiting, industrial automation control systems) are used to control the operation of, for example, programs or machines, and are typically adaptable to different control applications through the configuration and interconnection of multiple control system components (e.g., non-limiting, control modules, input / output (I / O) modules, and I / O devices). Some control systems may include a processor that runs or executes a control program to interact with an I / O system (e.g., non-limiting, typically one or more I / O modules or devices) to receive system information in the form of analog or digital input from sensors and to provide output (analog or digital) to one or more actuators (e.g., non-limiting, motors or motor drives). Control systems may interconnect with management information systems and other systems in a manufacturing facility and are operatively connected to any number of communication networks to facilitate various management functions (e.g., non-limiting, inventory control, accounting, and manufacturing control) in addition to program / machine control functionality.

[0015] The desire to integrate business and control network architectures to interconnect control systems and general-purpose systems, along with the evolution and development of Ethernet (e.g., in a switching mode with full-duplex capability, without limitation), has allowed Ethernet (e.g., Ethernet / Internet Protocol (IP) networks that allow field devices to connect directly to an Ethernet network) to be widely used in various applications (e.g., industrial applications, without limitation). As a non-limiting example, some industrial automation control systems use Ethernet to provide communication between various components and controllers. Some Ethernet networks are capable of transmitting data at approximately 100 megabits per second (“Mb / s”). Other Ethernet networks are capable of transmitting data at approximately 1 billion bits per second (“Gb / s”).

[0016] To transmit data over a network (e.g., non-limitingly, an Ethernet network), it may be necessary to packetize the data (e.g., non-limitingly, in an Ethernet packet). A packet (e.g., non-limitingly, an Ethernet packet) may sequentially include a header (e.g., non-limitingly, including a preamble, a start frame delimiter, a destination address, a source address, and a VLAN tag), a payload (e.g., non-limitingly, containing data), and a frame check sequence (e.g., non-limitingly, a cyclic redundancy check ("CRC")). Data may be stored in a buffer between the time the data is generated and the time the data is transmitted in the packet. Storing data in a buffer may be a step in data packetization. Some instances may manage the timing of writing data to the buffer and / or reading data from the buffer and providing data at the network peer interface (in the packet).

[0017] To process data received via a network (e.g., without limitation, an Ethernet network), it may be necessary to retrieve data from a packet (e.g., without limitation, an Ethernet packet). The data may be stored in a buffer (e.g., without limitation, stored in a memory accessible by the receiving device or provided at an interface communicatively coupled to the receiving device) between the time the data is received in the packet and the time the data is provided to the receiving device. Storing the data in the buffer is a step in retrieving data from the packet. Some examples may relate to managing the timing of writing data from the packet to the buffer and / or reading data from the buffer and providing the data at the device-facing interface.

[0018] A conventional device in a network (e.g., a controller, sensor, and / or actuator) may need to handshake between a writer and a reader to ensure that data is not read from the buffer while data is being written to it.

[0019] Various instances can manage the timing of reading from and / or writing to a buffer, allowing data to be read from the buffer shortly after writing to it is completed. Such instances ensure that data is not read from the buffer while data is being written to it. Furthermore, such instances allow reading from the buffer earlier than conventional devices, as they allow reading immediately after writing to the buffer is complete. Allowing earlier data reading improves communication latency for devices operating in a network.

[0020] Figure 1 is a functional block diagram illustrating one or more embodiments of system 100. Communication within system 100 can be improved according to one or more embodiments. For example, communication latency within system 100 can be reduced according to one or more embodiments.

[0021] System 100 may be an industrial automation control system. System 100 may include a controller 102, a sensor 116, a motor driver 118, and a motor control device 120. The motor control device 120 may have an observation position 122 and a desired position 124. System 100 may include a network switch 106, a network 108, and a network switch 110. System 100 may include a device 104, a device 112, and a device 114.

[0022] Controller 102 can cause a motor-controlled device 120 to move from an observed position 122 toward a desired position 124. As a non-limiting example, controller 102 can receive sensing data indicating a measurement from sensor 116. The sensing data from sensor 116 can indicate the observed position 122 of the motor-controlled device 120. Controller 102 can provide control data to motor driver 118 to control the operation of motor driver 118. The control data can respond to the observed position 122. The control data can cause motor driver 118 to operate so that motor-controlled device 120 moves toward the desired position 124.

[0023] Controller 102 may be or may include any suitable logic or processor for controlling operations performed in system 100. In some instances, controller 102 may be or may include a programmable logic controller (PLC) or a processor.

[0024] Sensor 116 can sense (or measure) one or more properties (alternatively referred to herein as "performing a measurement"). Sensor 116 can generate sensing data based on the sensed properties. Sensor 116 can transmit the sensing data to controller 102 (e.g., non-limitingly, via network 108). Non-limiting examples of suitable sensors include: sound sensors, chemical sensors, electrical sensors, magnetic sensors, radiation sensors, fluid sensors, position sensors, displacement sensors, velocity sensors, optical sensors, pressure sensors, force sensors, weight sensors, thermal sensors, and combinations thereof. Non-limitingly, sensor 116 can be an example of any of the listed suitable sensors.

[0025] Motor driver 118 is an example of an actuator. An actuator (e.g., motor driver 118, non-limiting) can directly or indirectly move, electrically connect to, or control a mechanism or system in response to control data. The actuator (including motor driver 118) may include, where appropriate, a sensor, such as sensor 116, for measuring movement (e.g., non-limiting, for a control loop). Non-limiting examples of suitable actuators include: hydraulic actuators, pneumatic actuators, electric actuators, thermal actuators, magnetic actuators, motors, or mechanical actuators. Non-limitingly, motor driver 118 may be an example of any of the suitable actuators listed. The actuator can move or cause movement based on control data. For example, the control data may include instructions regarding how much to move, how fast to move, how much force to apply, or how much current to apply, and the actuator can move or cause movement in response to the control data.

[0026] The motor-controlled device 120 can be moved or controlled by a motor driver 118. The motor-controlled device 120 may be able to move from a first position to a second position (e.g., "desired position 124", without limitation). The observed position 122 of the motor-controlled device 120 can be sensed by a sensor 116 (e.g., observed or updated, without limitation). The controller 102 can track the observed position 122 of the motor-controlled device 120 until the observed position 122 is the same as the desired position 124. The description herein relates to causing the motor driver 118 to operate so that the motor-controlled device 120 moves toward the desired position 124, and is in any way non-limiting and merely an example.

[0027] Network 108 may be or may include a communication network through which controller 102 can send control data to motor driver 118 and receive sensing data from sensor 116. Network 108 may include one or more switches, bridges, and network cables, and the like. Network 108 may operate according to Ethernet protocols; in other words, without limitation, network 108 may be an Ethernet network.

[0028] Network switch 106 and network switch 110 may be or may include any suitable switch for communication in network 108. Network switch 106 and network switch 110 may be considered as part of network 108.

[0029] According to one or more examples, devices 104, 112 and 114 may (collectively or individually) enable the improvement of communication latency in system 100.

[0030] One example of sending sensing data from device 112 is as a non-limiting example. Device 112 may receive sensing data from sensor 116 and encapsulate the sensing data, such that the sensing data is contained in a packet of a suitable format for transmission over network 108. Device 112 may then provide the encapsulated sensing data to network switch 110.

[0031] In some non-limiting embodiments, device 112 may be external to sensor 116 and may receive sensing data at a device-to-device interface and subsequently provide packets to network switch 110 at a network-to-device interface. In other non-limiting embodiments, device 112 may be part of sensor 116 and may receive sensing data when sensor 116 senses sensing data and subsequently provide packets to network switch 110 at a network-to-device interface.

[0032] In either case, device 112 may store sensing data in a buffer for a period of time between the time when sensor 116 generates sensing data (or the time when sensing data is received at the device-to-device interface) and the time when the sensing data is provided to network switch 110 in a packet at the network-to-device interface of device 112. Storing sensing data in the buffer may be a step in the process of packetizing sensing data. Device 112 may manage the timing when reading sensing data from the buffer, such that data is read from the buffer (e.g., for packetization) shortly after the sensing data is written to the buffer (e.g., immediately after the sensing data is written to the buffer). This may improve the communication latency of device 112, for example, with respect to the transmission of sensing data from sensor 116.

[0033] In one example of receiving sensing data at device 104, device 104 may receive a packet containing sensing data (which may originate from sensor 116) from network switch 106. Device 104 may extract the sensing data from the packet such that the sensing data is in a format suitable for controller 102. Device 104 may then provide the sensing data to controller 102.

[0034] In some non-limiting embodiments, device 104 may be separate from controller 102 and may receive packetized sensing data at a network peer interface and subsequently provide the sensing data to controller 102 at a device peer interface. In other non-limiting embodiments, device 104 may be part of the same system or device as controller 102 and may receive packetized sensing data at a network peer interface and subsequently provide the sensing data to a memory (e.g., non-limitingly, a register) of controller 102.

[0035] In either case, device 104 may store sensing data in a buffer for a period between the time the packet is received and the time the sensing data is provided to controller 102 (at a device-to-device interface or memory of controller 102). Storing the sensing data in the buffer may be a step in the process of retrieving sensing data from the packet. Device 104 may manage the timing of reading sensing data from the buffer and providing the sensing data to controller 102 (e.g., non-limitingly, at a network-to-device interface of controller 102) such that data is read from the buffer shortly after it is written (e.g., immediately after it is written). This may, for example, improve the communication latency of the controller with respect to receiving sensing data.

[0036] One example of sending control data from device 104: Alternatively or concurrently, device 104 may receive control data from controller 102 and provide the control data to motor driver 118 (via network 108). Device 104 may packetize the control data such that the control data is contained in a packet of a suitable format for transmission over network 108.

[0037] In some non-limiting embodiments, device 104 may be external to controller 102 and may receive control data at a device-to-device interface and subsequently provide packets to network switch 106 at a network-to-device interface. In other non-limiting embodiments, device 104 may be part of the same system or apparatus as controller 102 and may receive control data when controller 102 generates control data and subsequently provide packets to network switch 106 at a network-to-device interface.

[0038] In either case, device 104 may store control data in a buffer for a period of time between the time when controller 102 generates control data (or the time when control data is received at the device peer interface) and the time when control data is provided to network switch 106 in a packet at the network peer interface. Storing control data in the buffer may be a step in the process of packetizing control data. Device 104 may manage the timing when reading control data from the buffer so that data is read from the buffer shortly after it is written to the buffer (e.g., immediately after it is written to the buffer). This may, for example, improve the communication latency of controller 102 with respect to the transmission of control data.

[0039] As another non-limiting example, receiving control data at device 114, device 114 may receive a packet containing control data (which may originate from controller 102) from network switch 110. Device 114 may extract the control data from the packet such that the control data is in a format suitable for motor driver 118. Device 114 may then provide the control data to motor driver 118.

[0040] In some non-limiting embodiments, device 114 may be external to motor driver 118 and may receive packetized control data at a network peer interface and subsequently provide the control data to motor driver 118 at a device peer interface. In other non-limiting embodiments, device 114 may be part of motor driver 118 and may receive packetized control data at a network peer interface and subsequently provide the control data to a memory (e.g., non-limitingly, a register) accessible by motor driver 118.

[0041] In either case, device 114 may store control data in a buffer for a period of time between the time the control data is received and the time the control data is provided to motor driver 118 (at the device-facing interface or memory of motor driver 118). Storing the control data in the buffer may be a step in the process of retrieving control data from a self-package. Device 114 may manage the timing when reading control data from the buffer, such that data is read from the buffer shortly after the control data is written to the buffer (e.g., immediately after the control data is written to the buffer). This may, for example, improve the communication delay of motor driver 118 with respect to receiving control data.

[0042] In Figure 1, devices 112 and 114 are illustrated and described separately. In other instances, devices 112 and 114 may be combined into a single device capable of performing the operations described for both devices 112 and 114. Furthermore, devices 112, 114, or a combined device 112 / 114 (not illustrated in Figure 1) may further improve communication latency for additional sensors, actuators, or controllers (not illustrated in Figure 1) within system 100.

[0043] In Figure 1, a sensor 116 and a motor driver 118 are illustrated for illustrative purposes. In other instances, system 100 may include any number of sensors, actuators, or controllers. Such example systems (containing multiple sensors, actuators, or controllers) may include additional devices that operate substantially the same as or identically to any of devices 104, 112, or 114. Alternatively or additionally, device 104 may improve all communication of multiple sensors, actuators, or controllers.

[0044] Figure 2 is a functional block diagram illustrating one or more embodiments of device 200. Device 200 may, for example, improve the delay of component 236 with respect to transmitting data 206 and / or receiving data 212.

[0045] Device 200 may include a memory 202, a timer 214 (which may be alternatively referred to herein as "network-side timer 214") (which may generate a timing signal 216 (which may be alternatively referred to herein as "network-side timing signal 216") and the timer 214 may store a user-configurable time interval 218 (which may be alternatively referred to herein as "network-side user-configurable time interval 218")), and a timer 226 (which may be alternatively referred to herein as "device-side timer 226") The timer 226 can generate a timing signal 228 (which may be referred to herein as "device-side timing signal 228") and can store a user-configurable time interval 230 (which may be referred to herein as "device-side user-configurable time interval 230"), a circuit 220 (which may be referred to herein as "network-side circuit 220"), a circuit 232 (which may be referred to herein as "device-side circuit 232"), a network interface 222, and a device interface 234. The device 200 can store preset data 238 and / or write time 242. Depending on the operation of the device 200, a delay time 240 may exist between the timing signal 216 and the timing signal 228.

[0046] Device 200 may communicate with network switch 204 and / or component 236, for example, by: receiving data 206 from component 236, providing data packet 208 (containing data 206) to network switch 204, receiving data packet 210 from network switch 204, and providing data 212 (which may be included in data packet 208) to component 236. Network switch 204 or component 236 may or may not be part of device 200. Therefore, both network switch 204 and component 236 are selected in device 200. The selection of network switch 204 and component 236 in device 200 is illustrated in Figure 2 by using dashed lines to illustrate network switch 204 and component 236.

[0047] Device 200 is an example of any one of device 104, device 112, and device 114 in FIG. 1. As a non-limiting example, device 200 may be an example of device 112, in which case component 236 may be an example of sensor 116 in FIG. 1 and network switch 204 may be an example of network switch 110 in FIG. 1. As another non-limiting example, device 200 may be an example of device 104, in which case component 236 may be an example of controller 102 in FIG. 1 and network switch 204 may be an example of network switch 106 in FIG. 1. As another non-limiting example, device 200 may be an example of device 114, in which case component 236 may be an example of motor driver 118 in FIG. 1 and network switch 204 may be an example of network switch 110.

[0048] Either or both of circuits 220 and 232 may be or may include any suitable circuitry or logic for moving data into or out of memory 202 in response to timing signal 216 or timing signal 228. As a non-limiting example, either or both of circuits 220 and 232 may be or may include an ASIC or an FPGA.

[0049] Memory 202 may be or may include any suitable means for storing data. Random access memory (RAM) is a non-limiting example of a suitable memory. In this disclosure, both the terms "memory" and "buffer" may refer to a suitable means for storing data.

[0050] An example of managing the timing of receiving data and generating data packets relates to an example of providing operation of device 200 by receiving data 206 at device interface 234 and providing data packets 208 at network interface 222. As a non-limiting example, device 200 may receive data 206 (which may be sensing data, such as sensing data received from a sensor, or control data received from a controller). In some non-limiting examples, data 206 may be received at device interface 234, as illustrated in FIG2. In other non-limiting examples, when device 200 includes component 236, device 200 may receive data 206 when it is generated or store it in a memory of component 236 accessible by device 200.

[0051] Circuit 232 can write data 206 to memory 202 (e.g., non-limitingly, circuit 232 can "move" data 206 to memory 202). Memory 202 can be a buffer. As part of encapsulating data 206 into data packet 208, circuit 232 can write data 206 to memory 202. Circuit 232 can manage the timing of writing data 206 to memory 202. As a non-limiting example, circuit 232 can write data 206 to memory 202 in response to timing signal 228. Timer 226 can generate timing signal 228 based on a user-configurable time interval 230. For example, timer 226 can repeatedly generate timing signal 228 after consecutive expiration of user-configurable time intervals 230.

[0052] In some non-limiting instances (e.g., non-limitingly, where data 206 is sensing data from a sensor to be provided to a controller in data packet 208 via a network, or where data 206 is control data from a controller to be provided to an actuator via a network), the user-configurable time interval 230 may be periodic operation based on component 236. For example, the user-configurable time interval 230 may be based on a periodicity of operation of component 236.

[0053] For example, component 236 may be a sensor or controller that can provide data 206 at regular intervals. The user-configurable time interval 230 may be based on this regular periodicity. In such an example, circuit 232 may write data 206 into memory 202 according to the regular periodicity of component 236. As a non-limiting example, component 236 may operate at 10 ms intervals. Based on a timing signal 228 generated by timer 226 according to the user-configurable time interval 230, circuit 232 may write data 206 into memory 202 every 10 ms. The timing signal 228 is not required to be synchronized with the operation of component 236; for example, there may be a phase difference between the timing of component 236 and the timing signal 228.

[0054] Alternatively, in some non-limiting embodiments, circuit 232 may write data 206 to memory 202 upon receiving data 206 from component 236 (e.g., not based on a timing signal). Such non-limiting embodiments may or may not include timer 226 and / or timing signal 228.

[0055] Continuing an example of operation of device 200, circuitry 220 can read data 206 from memory 202 and provide data 206 in data packets 208 at network peer interface 222 (e.g., non-limitingly, circuitry 220 can "move" data 206 from memory 202 to network peer interface 222). Circuitry 220 can manage the timing of reading data 206 from memory 202 to provide data packets 208 at network peer interface 222. As a non-limiting example, circuitry 220 can read data 206 from memory 202 in response to timing signal 216. Timer 214 can generate timing signal 216 based on a user-configurable time interval 218. For example, timer 214 can repeatedly generate timing signal 216 after the continuous expiration of user-configurable time interval 218.

[0056] In certain non-limiting instances (e.g., non-limitingly, where data 206 is sensing data from a sensor to be provided to a controller via a network in data packet 208, or where data 206 is control data from a controller to be provided to an actuator via a network), the user-configurable time interval 218 may be periodic according to a rule of component 236. In such instances, circuitry 220 may periodically read data 206 according to a rule of component 236 and provide data packet 208 at network interface 222.

[0057] The user-configurable time interval 218 may have the same duration as the user-configurable time interval 230. In other words, the user-configurable time interval 218 may be the same as the user-configurable time interval 230.

[0058] However, the timing signal 216 may be generated after a delay time 240 following the generation of the timing signal 228. As a non-limiting example, the circuit 232 may write data 206 into the memory 202 every 10 ms (according to the timing signal 228), and the circuit 220 may read data 206 from the memory 202 every 10 ms (according to the timing signal 216), but the time for the circuit 220 to read data 206 from the memory 202 may be after the time for the circuit 232 to write data 206 into the memory 202, which may be delayed by the delay time 240.

[0059] Timer 214 can operate independently of timer 226. For example, timer 214 and timer 226 can be synchronized but can operate independently. For example, timer 214 can generate a timing signal 216 based on a user-configurable time interval 218 even when a timing signal 228 is not received.

[0060] Alternatively, for example, in the case where circuit 232 receives data 206 but does not write data 206 to memory 202 according to timing signal 228, timer 214 may generate timing signal 216 according to an expected reception time of data 206. For example, timer 214 may start counting from a time when data 206 is expected to arrive at device interface 234 plus a delay time 240, and generate timing signal 216 every 10 ms.

[0061] In some non-limiting embodiments, the delay time 240 may be based on the duration for which the circuit 232 spends writing data 206 to memory 202, i.e., based on the write time 242. In some non-limiting embodiments, the delay time 240 may additionally include a buffer time, i.e., to allow for an additional time to avoid potentially simultaneous reading from and writing to memory 202. In other words, the delay time 240 may additionally include a buffer time, i.e., to allow for an additional time to avoid potentially prior reading of data 206 from memory 202 before the writing of data 206 to memory 202 is completed.

[0062] A timing signal 216 is generated after a delay 240 following the start of data 206 being written to memory 202 by circuit 232 (and circuit 220 reads from memory 202), such that data 206 is read from memory 202 shortly after it is written (e.g., immediately after it is written). Therefore, timer 214 (e.g., timer 214 generates timing signal 216 after a delay 240 following the start of data 206 being written to memory 202 by circuit 232) can result in a short delay. In some non-limiting embodiments, for example, by reading from memory 202 immediately after it is written, the delay between writing to memory 202 and reading from memory 202 can be as short as possible. The short latency provided by device 200 allows device 200 or component 236 to be integrated into an Ethernet network capable of transmitting data at a high rate (e.g., 100 Mb / s or 1 Gb / s, without limitation). It should be understood that, in response to timing signal 216, circuitry 220 can read data 206 from memory 202, prepare a data packet 208 based on the read data 206, and send data 206 as part of the data packet 208.

[0063] An example of managing the timing of receiving and providing data packets relates to an example of providing operation of device 200 by receiving data packet 210 at network peer interface 222 and providing data 212 at device peer interface 234. As a non-limiting example, device 200 may receive data packet 210 (which may contain, for example, packetized sensing data received from a sensor, or packetized control data received from a controller). In some non-limiting examples, data packet 210 may be received at a network peer interface 222, as illustrated in FIG2.

[0064] Non-limitingly, for example as part of retrieving data 212 from data packet 210, circuit 220 may write data 212 from data packet 210 into memory 202. Circuit 220 may manage the timing of writing data 212 into memory 202. As a non-limiting example, circuit 220 may write data 212 into memory 202 in response to timing signal 216. Timer 214 may generate timing signal 216 based on a user-configurable time interval 218. For example, timer 214 may repeatedly generate timing signal 216 after a series of user-configurable time intervals 218 have elapsed.

[0065] In certain non-limiting instances (non-limitingly including instances where data packet 210 contains control data from a controller to be provided as data 212 to an actuator, or instances where data packet contains sensing data from a sensor to be provided as data 212 to a controller), the user-configurable time interval 218 may be a periodic operation based on the device transmitting data packet 210. For example, the user-configurable time interval 218 may be periodic based on a rule of operation of the device transmitting data packet 210.

[0066] For example, the device for sending data packets 210 may be a sensor or controller that can periodically provide synchronous operation of data packets 210 according to a rule. The user-configurable time interval 218 may be based on this periodicity. As a non-limiting example, data packets 210 may be received from the network switch 204 periodically every 10 ms according to a rule of the device for sending data packets 210. Based on the timer 214 generating a timing signal 216 according to the user-configurable time interval 218, the circuit 220 may write data 212 into the memory 202 every 10 ms.

[0067] Alternatively, in some non-limiting instances, circuit 220 may write data 212 into memory 202 upon receiving data packet 210 from network switch 204 (e.g., not based on a timing signal).

[0068] Continuing an example of operation of device 200, circuit 232 can read data 212 from memory 202 and provide data 212 at the device interface 234. Circuit 232 can manage the timing of reading data 212 from memory 202. As a non-limiting example, circuit 232 can read data 212 from memory 202 in response to a timing signal 228. Timer 226 can generate timing signal 228 based on a user-configurable time interval 230. For example, timer 226 can repeatedly generate timing signal 228 after the continuous expiration of user-configurable time intervals 230.

[0069] In certain non-limiting instances (including instances where data packet 210 contains control data from a controller to be provided as data 212 to component 236, and instances where data packet contains sensing data from a sensor to be provided as data 212 to a controller), the user-configurable time interval 230 can be periodic according to the rules of the transmitter of data packet 210. In such instances, circuit 232 can periodically read data 212 from memory 202 and provide data 212 to component 236 according to the rules of the transmitter of data packet 210.

[0070] For example, the transmitter of data packet 210 may be a sensor or controller that can provide isochronous operation of data packet 210 according to a regular periodicity. The user-configurable time interval 230 may be based on this regular periodicity. In such an example, circuit 232 may read data 212 from memory 202 according to the regular periodicity of the transmitter of data packet 210. As a non-limiting example, the transmitter of data packet 210 may operate isochronously at 10 ms intervals. According to the timer 226 generating a timing signal 228 based on the user-configurable time interval 230, circuit 232 may read data 212 from memory 202 every 10 ms. The timing signal 228 may not be synchronized with the operation of the transmitter of data packet 210; for example, there may be a phase difference between the timing of the transmitter of data packet 210 and the timing signal 228.

[0071] In some non-limiting embodiments, circuit 232 may provide preset data 238 as data 212 to component 236 in response to receiving timing signal 228 and not finding new data in memory 202. Preset data 238 may include predefined data 244. As a non-limiting embodiment, predefined data 244 may include empty data, data that does not indicate a read, or data that does not instruct an actuator to perform an operation. Alternatively or concurrently, preset data 238 may be associated with previously provided data 246 (e.g., "last good" data). As a non-limiting embodiment, preset data 238 may be an instance of previously provided data 206 or an average of one or more samples of previously provided data.

[0072] The user-configurable time interval 230 may have the same duration as the user-configurable time interval 218. In other words, the user-configurable time interval 230 may be the same as the user-configurable time interval 218.

[0073] However, the timing signal 228 may be generated after a delay time 240 following the generation of the timing signal 216. As a non-limiting example, the circuit 220 may write data 212 into the memory 202 every 10 ms (according to the timing signal 216), and the circuit 232 may read data 212 from the memory 202 every 10 ms (according to the timing signal 228), but the time for the circuit 232 to read data 212 from the memory 202 may be after the time for the circuit 220 to write data 212 into the memory 202, which may be delayed by the delay time 240.

[0074] Timer 226 can operate independently of timer 214. For example, timer 226 and timer 214 can be synchronized but can operate independently. For example, timer 226 can generate a timing signal 228 based on a user-configurable time interval 230 even when timing signal 216 is not received.

[0075] Alternatively, for example, where circuit 220 writes data 212 to memory 202 upon receiving data packet 210 (e.g., not based on a timing signal), timer 226 may generate a timing signal 228 based on an expected reception time of data packet 210. For example, timer 226 may start counting from the expected time when data packet 210 has arrived at network peer interface 222 plus a delay time 240, generating a timing signal 228 every 10 ms. Such non-limiting embodiments may or may not include timer 214 and / or timing signal 216.

[0076] In some non-limiting embodiments, the delay time 240 may be based on the duration for which the circuit 220 spends writing data 212 to memory 202, i.e., based on the write time 242. In some non-limiting embodiments, the delay time 240 may additionally include a buffer time, i.e., a time allowance to avoid potentially simultaneous reading from and writing to memory 202. In other words, the delay time 240 may additionally include a buffer time, i.e., a time allowance to avoid potentially prior reading of data 212 from memory 202 before the writing of data 212 to memory 202 is completed.

[0077] A timing signal 228 is generated after a delay 240 following the start of data 212 being written to memory 202 by circuit 220 (and causing circuit 232 to read from memory 202), such that data 212 is read from memory 202 shortly after it is written (e.g., immediately after it is written). Therefore, timer 226 (e.g., timer 226 generates timing signal 228 after a delay 240 following the start of data 212 being written to memory 202 by circuit 220) can result in a short delay. In some non-limiting embodiments, for example, by reading from memory 202 immediately after it is written, the delay between writing to memory 202 and reading from memory 202 can be as short as possible. The low latency provided by device 200 allows device 200 or component 236 to be integrated into an Ethernet network capable of transmitting data at a high rate (e.g., 100 Mb / s or 1 Gb / s, without limitation).

[0078] Figure 3 is a functional block diagram illustrating one or more embodiments of device 300. Among other things, device 300 may also manage the timing of reading data from memory 302 to improve the delay of a device (not illustrated in Figure 3) (e.g., non-limitingly, in an industrial automation control system).

[0079] Device 300 may include a memory 302 for storing data 306 received from or transmitted to a network switch 304. Device 300 may include a timer 310 for generating a timing signal 312 in response to a user-configurable time interval 314. Device 300 may include a circuit 316 for moving data to or from memory 302 in at least partially in response to the timing signal 312 generated by timer 310 (e.g., moving data 306 to or from memory 302, or moving data 308 from memory 302, without limitation).

[0080] Device 300 may be an example of device 200 of FIG2 illustrated and described as a subset of the components of device 200. As a non-limiting example, memory 302 may be an example of memory 202 of FIG2. Network switch 304 may be an example of network switch 204 of FIG2. Data 306 may be an example of data packet 210 of FIG2. Data 308 may be an example of data packet 208 of FIG2. Timer 310 may be an example of timer 214 or timer 226 of FIG2. Timing signal 312 may be an example of timing signal 216 or timing signal 228 of FIG2. User-configurable time interval 314 may be an example of user-configurable time interval 218 or user-configurable time interval 230 of FIG2. Circuit 316 may be an example of circuit 220 or circuit 232 of FIG2. Similar to network switch 204 in Figure 2, network switch 304 is optional in device 300. The optionality of network switch 304 in device 300 is illustrated in Figure 3 by using dashed lines to illustrate network switch 304.

[0081] As one example of the considered operation, device 300 may receive data 308 from a component (not illustrated in FIG. 3). Without limitation, data 308 may be sensed data from a sensor or control data from a controller. Data 308 may be written to memory 302 by a circuit (not illustrated in FIG. 3). Timer 310 may generate a timing signal 312 after a delay following an expected reception time of data 308 at device 300. In response to timing signal 312, circuitry 316 may move data 308 from memory 302 to a data packet (containing data 308) and may provide the data packet (containing data 308) to a network switch.

[0082] As an alternative example of the considered operation, device 300 may receive a data packet (containing data 306) from network switch 304. Without limitation, data 306 may be sensed data from a sensor or control data from a controller. Data 306 may be written to memory by a circuit (not illustrated in FIG3). Timer 310 may generate a timing signal 312 after a delay following an expected reception time of the data packet (containing data 306) at device 300. In response to timing signal 312, circuitry 316 may move data 306 from memory 302 to an interface or memory accessible by a component (not illustrated in FIG3).

[0083] Figure 4 is a functional block diagram illustrating one or more embodiments of device 400. Among other things, device 400 can also manage the timing of writing data to or reading data from memory 402 to improve the latency of communication between network switch 404 and any or all of controller 418, motor driver 420 and sensor 422.

[0084] Device 400 may include a network switch 404 for enabling communication in the industrial automation control system 432. Device 400 may include a memory 402 for storing data 406 received from or transmitted to the network switch 404. Device 400 may include a timer 410 for generating a timing signal 412 in response to a user-configurable time interval 414. Device 400 may include circuitry 416 for moving data 406 to or from memory 402 in at least part of response to the timing signal 412 generated by timer 410.

[0085] Device 400 may additionally include a circuit 430 for at least partially responding to an additional timing signal (not illustrated in FIG. 4) generated by an additional timer (not illustrated in FIG. 4) to move data 408 (e.g., data received from one or more components, not limited to) to memory 402 and provide data 406 to one or more components (e.g., at a device-to-device interface (not illustrated in FIG. 4, not limited to)). Circuit 430 is selected in device 400. The selection of circuit 430 in device 400 is illustrated in FIG. 4 by using dashed lines to illustrate circuit 430.

[0086] Device 400 may be an example of device 200 of FIG2 illustrated and described as a subset of the components of device 200. As a non-limiting example, memory 402 may be an example of memory 202 of FIG2. Network switch 404 may be an example of network switch 204 of FIG2. Data 406 may be an example of data packet 210 of FIG2. Data 408 may be an example of data packet 208 of FIG2. Timer 410 may be an example of timer 214 of FIG2. Timing signal 412 may be an example of timing signal 216 of FIG2. User-configurable time interval 414 may be an example of user-configurable time interval 218 of FIG2. Circuit 416 may be an example of circuit 220 of FIG2. Circuit 430 may be an example of circuit 232 of FIG2. In addition, controller 418 may be an example of controller 102 of FIG1. Motor driver 420 may be an example of motor driver 118 in FIG1. ​​Sensor 422 may be an example of sensor 116 in FIG1. ​​Motor control device 424 may be an example of motor control device 120 in FIG1.

[0087] In some non-limiting embodiments, the industrial automation control system 432 may include components including a controller 418, a motor driver 420, and a sensor 422, all of which are communicable via one or more instances of device 400 and network switch 404 to execute a program for tracking an observed position 426 of a motor control device 424 to a desired position 428 of the motor control device 424. The industrial automation control system 432, controller 418, motor driver 420, sensor 422, motor control device 424, observed position 426, and desired position 428 are all optional. The selectivity of the industrial automation control system 432, controller 418, motor driver 420, sensor 422, motor control device 424, observed position 426, and desired position 428 relative to the device 400 is illustrated in Figure 4 by using dashed lines to illustrate each of the industrial automation control system 432, controller 418, motor driver 420, sensor 422, motor control device 424, observed position 426, and desired position 428.

[0088] As a non-limiting example, one or both of the motor driver 420 and the sensor 422 may be directly communicatively coupled to the device 400 (which may include a network switch 404). The controller 418 may be communicatively coupled to the network switch 404 via one or more additional network switches (not illustrated in FIG. 4). This example of communication coupling is illustrated by the communication coupling between the device 112 or the device 114 of FIG. 1 and the controller 102, the sensor 116, and the motor driver 118 of FIG. 1.

[0089] As a non-limiting example, sensor 422 may generate sensing data (e.g., data 408, non-limiting) (which may indicate the observed position 426 of motor-controlled device 424). Sensor 422 may provide the sensing data to device 400 (e.g., at a device-to-device interface (not illustrated in FIG. 4, non-limiting)). Device 400 (using circuitry 430, an additional timer, circuitry 416, or timer 410) may manage the timing of writing sensing data to memory 402 or reading sensing data from memory 402 for provision to network switch 404 in a packet. The packetized sensing data may be provided to controller 418 via a network. Controller 418 may generate control data based on the sensing data to, for example, non-limitingly, cause motor driver 420 to move motor-controlled device 424 to desired position 428.

[0090] Controller 418 may provide control data (e.g., data 406, non-limitingly) to device 400 via a network. Device 400 (using circuitry 416, timer 410, circuitry 430, and additional timers) may manage the timing of writing control data to memory 402 or reading control data from memory 402 for provision to motor driver 420. Motor driver 420 may operate according to the control data, such operation causing motor control device 424 to move toward desired position 428.

[0091] As another non-limiting example, the controller 418 may be directly communicatively coupled to the device 400 (including the network switch 404). The motor driver 420 and the sensor 422 may be communicatively coupled to the network switch 404 via one or more additional network switches (not illustrated in FIG. 4). This example of communication coupling is illustrated by the communication coupling between the device 104 of FIG. 1, the controller 102 of FIG. 1, the sensor 116 of FIG. 1, and the motor driver 118 of FIG. 1.

[0092] Controller 418 may provide control data (e.g., data 408, non-limitingly) to device 400. Device 400 (using circuitry 430, an additional timer, circuitry 416, or timer 410) may manage the timing of writing control data to memory 402 or reading control data from memory 402 for packetization and provision to network switch 404. The packetized control data may then be transmitted via a network (not illustrated in FIG. 4) to motor driver 420. Motor driver 420 may operate according to the control data, such operation causing motor control device 424 to move toward desired position 428.

[0093] Continuing this example, sensor 422 may generate sensing data (e.g., data 406, not limited to) (which may indicate the observed position 426 of motor-controlled device 424). Sensor 422 may provide the sensing data (e.g., packetized, not limited to) to network switch 404 via a network. Device 400 (using circuitry 416, timer 410, circuitry 430, and / or additional timers) may manage the timing of writing sensing data to memory 402 or reading sensing data from memory 402 for provision to controller 418. Controller 418 may generate additional control data based on the sensing data to, for example, cause motor driver 420 to move motor-controlled device 424 to desired position 428.

[0094] Figure 5 is a functional block diagram illustrating one or more embodiments of system 500. Among other things, system 500 can also manage the timing of writing data to or reading data from memory 502 to improve the latency of communication between network switch 504 and any or all of controller 518, motor driver 520 and sensor 522.

[0095] System 500 may be an industrial automation control system. System 500 may include one or more components 530. Component 530 includes a controller 518, a motor driver 520, and a sensor 522. Component 530 may communicate with other components in Component 530 or with other components of System 500 via a network switch 504. System 500 may include a memory 502 configured to store data 506 transmitted from the network switch 504 to one or more of the components 530 or data 508 transmitted from one or more of the components 530 to the network switch 504. System 500 may include a timer 510 for generating a timing signal 512 in response to a user-configurable time interval 514. System 500 may include a circuit 516 for moving data 506 to memory 502 or moving data 508 from memory 502 in at least part response to a timing signal 512 generated by timer 510.

[0096] System 500 may additionally include a circuit 532 for at least partially responding to an additional timing signal (not illustrated in FIG. 5) generated by an additional timer (not illustrated in FIG. 5) to move data 508 (e.g., data received from one or more of the components 530, not limited to) to memory 502 and to provide data 506 to one or more of the components 530 (e.g., at a device-facing interface (not illustrated in FIG. 5, not limited to)). Circuit 532 is selected in system 500. The selection of circuit 532 in system 500 is illustrated in FIG. 5 by using dashed lines to illustrate circuit 532.

[0097] System 500 may include a subset of the components of device 200 illustrated and described as an example of device 200 in Figure 2. As a non-limiting example, memory 502 may be an example of memory 202 in Figure 2. Network switch 504 may be an example of network switch 204 in Figure 2. Data 506 may be an example of data packet 210 in Figure 2. Data 508 may be an example of data packet 208 in Figure 2. Timer 510 may be an example of timer 214 in Figure 2. Timing signal 512 may be an example of timing signal 216 in Figure 2. User-configurable time interval 514 may be an example of user-configurable time interval 218 in Figure 2. Circuit 516 may be an example of circuit 220 in Figure 2. Circuit 532 may be an example of circuit 232 in Figure 2. In addition, controller 518 may be an example of controller 102 in Figure 1. Motor driver 520 may be an example of motor driver 118 in FIG1. ​​Sensor 522 may be an example of sensor 116 in FIG1. ​​Motor control device 524 may be an example of motor control device 120 in FIG1.

[0098] In some non-limiting embodiments, component 530 may include two or more of controller 518, motor driver 520, and sensor 522, all of which can communicate via one or more instances of a device (e.g., device 200 of FIG. 2) and network switch 504 to perform a program for tracking an observed position 526 of a motor control device 524 to a desired position 528 of the motor control device 524. Components 530 (e.g., non-limitingly, controller 518, motor driver 520, and sensor 522), motor control device 524, observed position 526, and desired position 528 are all (but except one) selected in system 500. The selection of all (but one of) components 530 (e.g., controller 518, motor driver 520, and sensor 522, without limitation), motor control device 524, observed position 526, and desired position 528 is illustrated in FIG5 by using dashed lines to illustrate each of components 530, controller 518, motor driver 520, sensor 522, motor control device 524, observed position 526, and desired position 528.

[0099] Similar to network switch 204 in Figure 2 and network switch 304 in Figure 3, network switch 504 may be selected in system 500. The selectivity of network switch 504 in system 500 is illustrated in Figure 5 by using dashed lines to illustrate network switch 504.

[0100] Figure 6 is a functional block diagram illustrating a device 600 according to one or more embodiments. Device 600 may include a memory 602 for storing data 606 entering device 600 or data 608 exiting device 600 (e.g., to / from a network switch (not illustrated in Figure 6)). Device 600 may include a timer 610 for generating a timing signal 612 in response to a user-configurable time interval 614. Device 600 may include a circuit 616 for at least partially responding to the timing signal 612 generated by timer 610 to move incoming data 606 to memory 602 or to move outgoing data 608 from memory 602.

[0101] Figure 7 is a flowchart of method 700 according to one or more examples. In some examples, at least a portion of method 700 may be performed by means or systems such as: system 100 of Figure 1, device 104 of Figure 1, device 112 of Figure 1, device 114 of Figure 1, device 200 of Figure 2, device 300 of Figure 3, device 400 of Figure 4, system 500 of Figure 5, device 600 of Figure 6, or another means or system. Although illustrated as discrete blocks, depending on the implementation, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated.

[0102] In operation 702, data can be received at a device-facing interface. Data 206 in FIG2 may be an example of data received at operation 702. Device-facing interface 234 in FIG2 may be an example of a device-facing interface used to receive data at operation 702. Without limitation, the data may be, or may include, sensing data generated by a sensor, for example; alternatively, the data may be, or may include, control data generated by a controller, for example.

[0103] In operation 706, data can be written to a memory. Data 206 in Figure 2 can be an example of data written to memory at operation 706. Memory 202 in Figure 2 can be an example of memory to which data is written at operation 706. Data can be written to memory by a circuit (e.g., circuit 232 in Figure 2).

[0104] In operation 708, a timing signal may be received. The timing signal 216 of FIG2 may be an example of a timing signal received at operation 708. The timing signal may have been generated by a timer (e.g., non-limitingly, timer 214 of FIG2) based on a user-configurable time interval (e.g., non-limitingly, user-configurable time interval 218 of FIG2). The user-configurable time interval may be periodically related to a regular period of a device (e.g., controller or sensor) at the device-to-interface.

[0105] A timing signal may be received after a delay following an expected reception time of data at the device's opposing interface. This delay may be related to a write time of memory. As a non-limiting example, the delay may be based on a duration for which a circuit may write data to memory. Some examples may include generating a timing signal after a delay following an expected reception time of the data packet at the device's opposing interface.

[0106] In operation 710, in response to a timing signal, a data packet containing data can be provided at a network peer interface. One or more of the data packets 208 in FIG. 2 may be an example of a data packet provided at the network peer interface in operation 710. The network peer interface 222 in FIG. 2 may be an example of a network peer interface used to provide data packets in operation 710. Without limitation, the data packet may contain, for example, sensing data generated by a sensor and provided to a controller via a network, or the data packet may contain, for example, control data generated by a controller and used for actuator control via the network.

[0107] Figure 8 is a flowchart of another method 800 according to one or more examples. In some examples, at least a portion of method 800 may be performed by means or systems such as: system 100 of Figure 1, device 104 of Figure 1, device 112 of Figure 1, device 114 of Figure 1, device 200 of Figure 2, device 300 of Figure 3, device 400 of Figure 4, system 500 of Figure 5, device 600 of Figure 6, or another means or system. Although illustrated as discrete blocks, depending on the implementation, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated.

[0108] At operation 802, a data packet may be received at a network peer interface. One or more of the data packets 210 in FIG. 2 may be an example of a data packet received at operation 802. The network peer interface 222 in FIG. 2 may be an example of a network peer interface used at operation 802 to receive the data packet. The data packet may have been transmitted across a network (e.g., non-limitingly, network 108 in FIG. 1) to a network switch (e.g., non-limitingly, network switch 204 in FIG. 2) communicatively coupled to the network peer interface. Non-limitingly, the data packet may contain, for example, sensing data generated by a sensor; alternatively, the data packet may contain, for example, control data generated by a controller and used to control an actuator.

[0109] At operation 806, data in a data packet can be written into a memory. Data 212 in Figure 2 can be an example of data written into memory at operation 806. Memory 202 in Figure 2 can be an example of memory into which data is written at operation 806. Data can be written into memory by a circuit (e.g., circuit 220 in Figure 2).

[0110] At operation 808, a timing signal may be received. The timing signal 228 of FIG2 may be an example of a timing signal received at operation 808. The timing signal may have been generated by a timer (e.g., non-limitingly, timer 226 of FIG2) based on a user-configurable time interval (e.g., non-limitingly, user-configurable time interval 230 of FIG2). The user-configurable time interval may be periodically associated with a regularity of a device (e.g., a sensor or controller) that transmits data packets.

[0111] A timing signal may be received after a delay following the expected reception time of one of the data packets. This delay may be related to the write time of one of the memory. As a non-limiting example, the delay may be based on the duration for which a circuit may be used to write data to one of the memory. Some instances may include generating a timing signal after a delay following the expected reception time of the data packet at the network peer interface.

[0112] At operation 810, in response to a timing signal, data can be provided from memory at a device-facing interface. Data 212 in FIG2 may be an example of data provided at the device-facing interface at operation 810. Device-facing interface 234 in FIG2 may be an example of a device-facing interface used to provide data at operation 810. Without limitation, the data may be or may include, for example, sensing data generated by a sensor and provided at the device-facing interface to a controller, or the data may be or may include, for example, control data generated by a controller and provided at the device-facing interface to an actuator.

[0113] Modifications, additions, or omissions may be made to method 700 and / or method 800 without departing from the scope of this disclosure. For example, the operations of method 700 and / or method 800 may be performed in different orders. Furthermore, the operations and actions outlined are provided merely as examples, and some of these operations and actions may be optional, combined into fewer operations and actions, or extended to additional operations and actions without diminishing the essence of the disclosed examples.

[0114] FIG9 is a block diagram of an apparatus 900 that can be used in one or more embodiments to implement the various functions, operations, actions, procedures or methods disclosed herein. Without limitation, apparatus 900 includes one or more processors 902 (sometimes referred to herein as "processor 902") operatively coupled to one or more devices (such as data storage devices (sometimes referred to herein as "storage device 904")). Storage device 904 includes machine-executable code 906 stored thereon (e.g., without limitation, stored on a computer-readable memory), and processor 902 includes a logic circuit system 908. Machine-executable code 906 includes information describing functional elements that can be implemented (e.g., without limitation, executed by) the logic circuit system 908. Logic circuit system 908 implements (e.g., without limitation, executes) the functional elements described by machine-executable code 906. When executing the functional elements described by machine executable code 906, device 900 should be considered as special-purpose hardware capable of executing the functional elements disclosed herein. In one or more instances, processor 902 may execute the functional elements described by machine executable code 906 sequentially, simultaneously (e.g., non-limitingly, on one or more different hardware platforms), or in one or more parallel program flows.

[0115] When implemented by the logic circuit system 908 of the processor 902, the machine-executable code 906 can adapt the processor 902 to perform the operations of the examples disclosed herein. For example, the machine-executable code 906 can adapt the processor 902 to perform at least a portion or all of the method 700 of FIG. 7 or the method 800 of FIG. 8. As another example, the machine-executable code 906 can adapt the processor 902 to perform at least a portion or all of the operations discussed with respect to the system 100 of FIG. 1, the device 104 of FIG. 1, the device 112 of FIG. 1, the device 114 of FIG. 1, the device 200 of FIG. 2, the device 300 of FIG. 3, the device 400 of FIG. 4, the system 500 of FIG. 5, or the device 600 of FIG. 6.

[0116] Processor 902 may comprise a general-purpose processor, special-purpose processor, central processing unit (CPU), microcontroller, programmable logic controller (PLC), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, other programmable device, or any combination thereof, designed to perform the functions disclosed herein. A general-purpose computer containing a processor is considered a special-purpose computer when it executes instance-specific arithmetic instructions (e.g., software code, without limitation). It should be noted that a general-purpose processor (also referred to herein as a host processor or simply host) may be a microprocessor, but alternatively, processor 902 may comprise any conventional processor, controller, microcontroller, or state machine. Processor 902 may also be implemented as a combination of computing devices (such as a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration).

[0117] In one or more embodiments, storage device 904 includes volatile data storage devices (e.g., non-limitingly, random access memory (RAM)) and non-volatile data storage devices (e.g., non-limitingly, flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM)). In one or more embodiments, processor 902 and storage device 904 may be integrated into a single device (e.g., non-limitingly, a semiconductor device product, system-on-a-chip (SOC)). In one or more embodiments, processor 902 and storage device 904 may be implemented as separate devices.

[0118] In one or more embodiments, the machine-executable code 906 may contain computer-readable instructions (e.g., non-limitingly, software code, firmware code). By a non-limiting embodiment, the computer-readable instructions may be stored in storage device 904, directly accessed by processor 902, and executed by processor 902 using at least logic circuit system 908. Alternatively, by a non-limiting embodiment, the computer-readable instructions may be stored on storage device 904, transferred to a memory device (not shown) for execution, and executed by processor 902 using at least logic circuit system 908. Therefore, in one or more embodiments, the logic circuit system 908 includes an electrically configurable logic circuit system.

[0119] In one or more instances, machine-executable code 906 may describe the hardware (e.g., a circuit system, without limitation) that will be implemented in logic circuit system 908 to perform functional elements. This hardware may be described at any of a variety of abstraction levels, from low-order transistor layouts to high-order description languages. At high abstraction levels, without limitation, a hardware description language (HDL) such as the Institute of Electrical and Electronics Engineers (IEEE) Standard Hardware Description Language (HDL) may be used. By way of non-limiting examples, Verilog™, SystemVerilog™, or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL™) may be used.

[0120] The HDL description can be converted into a description at any of a number of other levels of abstraction as needed. As a non-limiting example, a high-level description can be converted into a logic-level description, such as Register Transfer Language (RTL), gate-level (GL) description, layout-level description, or masking-level description. As a non-limiting example, micro-operations performed by the hardware logic circuitry of the logic circuitry system 908 (e.g., gates, flip-flops, registers, etc., without limitation) can be described in RTL and then converted into a GL description by a synthesis tool. The GL description can then be converted into a layout-level description corresponding to a physical layout of an integrated circuit of a programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof by a placement and routing tool. Thus, in one or more instances, the machine-executable code 906 may contain HDL, RTL, GL descriptions, masking-level descriptions, other hardware descriptions, or any combination thereof.

[0121] In an instance where the machine-executable code 906 includes a hardware description (at any level of abstraction), a system (not shown, but including storage device 904) may implement the hardware description described by the machine-executable code 906. By a non-limiting example, the processor 902 may include a programmable logic device (e.g., non-limitingly, an FPGA or PLC), and the logic circuit system 908 may be electrically controlled to implement a circuit system corresponding to the hardware description in the logic circuit system 908. Additionally, by a non-limiting example, the logic circuit system 908 may include hardwired logic manufactured by a manufacturing system (not shown, but including storage device 904) according to the hardware description of the machine-executable code 906.

[0122] Regardless of whether the machine executable code 906 contains computer-readable instructions or a hardware description, the logic circuit system 908 executes the functional elements described by the machine executable code 906 when implementing the functional elements of the machine executable code 906. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description can execute.

[0123] As used herein, the term "substantially" in reference to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition is satisfied with small variations (such as within acceptable manufacturing tolerances), as would be understood by one skilled in the art. For example, substantially satisfying a parameter may mean satisfying at least about 90%, at least about 95%, or even at least about 99%.

[0124] As used in this disclosure, the terms "module" or "component" may refer to a specific hardware implementation of an action or software object or software convention that is executable and can be stored on or executed by general-purpose hardware (e.g., computer-readable media, processing device, without limitation) of a computing system. In one or more instances, the different components, modules, engines, and services described in this disclosure may be implemented as objects or programs that execute on a computing system (e.g., without limitation, as standalone threads). While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on or executed by general-purpose hardware), specific hardware implementations or combinations of software with specific hardware implementations are also possible and contemplated.

[0125] As used in this disclosure, the term "combination" referring to a plurality of elements may include any combination of all elements or any of the various different subcombinations of some of the elements. For example, the phrase "A, B, C, D or a combination thereof" may refer to any one of A, B, C or D; a combination of each of A, B, C and D; and any subcombination of A, B, C or D, such as A, B and C; A, B and D; A, C and D; B, C and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0126] The terms used in this disclosure and, in particular, in the appended claims (e.g., the subject of the appended claims) are generally intended to be "open-ended" terms (e.g., without limitation, the term "including" should be interpreted as "including but not limited to", the term "having" should be interpreted as "having at least", and the term "include" should be interpreted as "including but not limited to"). As used herein, "each" means "some or all". As used herein, "each" means "all".

[0127] Furthermore, if it is intended that an introduced technical solution description has a specific number, this intention will be explicitly stated in the claims, and without such a statement, this intention does not exist. For example, to aid understanding, the appended claims may contain the use of the introductory phrases "at least one" and "one or more" for the introduced technical solution description. However, the use of such phrases should not be construed as implying that introducing a technical solution description by means of the indefinite article "a (a or an)" would limit any particular technical solution containing such introduced technical solution description to having only one instance of such description, even when the same technical solution contains the introductory phrase "one or more" or "at least one" and an indefinite article (such as "a (a or an)") (for example, "a (a or an)" should be interpreted as meaning "at least one" or "one or more"); the same applies to the use of definite articles for the introduced technical solution description.

[0128] Furthermore, even if it is explicitly stated that an introduced technical solution describes a specific number, those skilled in the art will recognize that such a statement should be interpreted as meaning at least the number described (e.g., in the absence of other modifiers, the explicit statement "two statements" means at least two statements or two or more statements). In addition, in instances where conventions such as "non-restrictive, at least one of A, B, and C" or "non-restrictive, one or more of A, B, and C" are used, generally speaking, non-restrictively, this construction is intended to include only A, only B, only C, both A and B, both A and C, both B and C, or both A, B, and C.

[0129] Furthermore, in the description, the claims, or the drawings, any transitional word or phrase indicating two or more alternative terms should be understood to include the possibility of including one, any, or both of such terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0130] Additional non-limiting examples of this disclosure may include:

[0131] Example 1: A device comprising: a memory for storing incoming or outgoing data; a timer for generating a timing signal in response to a user-configurable time interval; and a circuit for moving the incoming or outgoing data from the memory in at least part in response to the timing signal generated by the timer.

[0132] Example 2: The device of Example 1, wherein the incoming data is received at a network peer interface, and wherein the circuit is used to move the incoming data from the memory to a device peer interface.

[0133] Example 3: The device of any of Examples 1 and 2, wherein the circuit is used to provide preset data in response to receiving the timing signal and not finding new data in the memory, wherein the preset data includes one or more of predefined data and previously received data.

[0134] Example 4: A device as in any of Examples 1 to 3, wherein the circuit includes a device-side circuit, and wherein the device includes: a network-side circuit for moving the incoming data from the network-opposite interface to the memory.

[0135] Example 5: A device as in any of Examples 1 to 4, wherein the timer is used to generate the timing signal at a delay time after an expected reception time of the incoming data at the network peer interface, the delay time being related to a write time for writing the data to the memory.

[0136] Example 6: The device of any of Examples 1 to 5, wherein the device faces the interface communicatively coupled to a controller of an industrial automation control system, the controller communicating with a sensor and a motor driver via a network switch to move the observed position of a motor control device toward the desired position of the motor control device.

[0137] Example 7: A device as in any of Examples 1 to 6, wherein the device's opposing interface is communicatively coupled to one or more of a sensor and a motor driver, both of which communicate with a controller of an industrial automation control system via a network switch to move the observed position of a motor-controlled device to the desired position of the motor-controlled device.

[0138] Example 8: A device as in any of Examples 1 to 7, wherein the outgoing data is received at a device-facing interface, wherein the circuitry is used to move the outgoing data from the memory to a network-facing interface.

[0139] Example 9: A device as in any of Examples 1 to 8, wherein the timer includes a network-side timer, wherein the timing signal includes a network-side timing signal, wherein the user-configurable time interval includes a network-side user-configurable time interval, wherein the circuit includes a network-side circuit, and wherein the device includes: a device-side timer for generating a device-side timing signal; and a device-side circuit for at least partially responding to the device-side timing signal by moving the outgoing data from the device-facing interface to the memory.

[0140] Example 10: A device as in any of Examples 1 to 9, wherein the network-side timer is used to generate the network-side timing signal after a delay time following the generation of the device-side timing signal by the device-side timer, the delay time being related to a write time for writing the data to the memory.

[0141] Example 11: A device as in any of Examples 1 to 10, wherein the circuit includes a network-side circuit, and wherein the device includes: a device-side circuit for moving the outgoing data from the device-facing interface to the memory.

[0142] Example 12: A device as in any of Examples 1 to 11, wherein the timer is used to generate the timing signal at a delay time after an expected reception time of the outgoing data at the device's opposite interface, the delay time being related to a write time for writing the data to the memory.

[0143] Example 13: An apparatus comprising: a network switch for communication in an industrial automation control system; a memory for storing data input to or output to the network switch; a timer for generating a timing signal in response to a user-configurable time interval; and a circuit for moving the data to or from the memory in at least part of response to the timing signal generated by the timer.

[0144] Example 14: The device as in Example 13, wherein the industrial automation control system includes a controller, a motor driver and a sensor that communicate via the network switch to move an observed position of a motor-controlled device toward a desired position of the motor-controlled device.

[0145] Example 15: A system comprising: a component of an industrial automation control system, the component including one or more of a controller, a motor driver and a sensor, the component communicating with other components of the industrial automation control system via a network switch; a memory configured to store data transmitted from the network switch to the component or data transmitted from the component to the network switch; a timer for generating a timing signal in response to a user-configurable time interval; and a circuit for moving the data to or from the memory in at least a portion of response to the timing signal generated by the timer.

[0146] Example 16: The system of Example 15, wherein the other components of the industrial automation control system include two or more of a controller, a motor driver and a sensor, which communicate via the network switch to move the observed position of one of the motor control devices toward the desired position of one of the motor control devices.

[0147] Example 17: A method comprising: receiving a data packet at a network peer interface; writing data of the data packet into a memory; receiving a timing signal; and in response to the timing signal, providing the data from the memory at a device peer interface.

[0148] Example 18: The method of Example 17 includes generating the timing signal after a delay time following an expected reception time of the data packet at the network peer interface, the delay time being related to a write time for writing the data to the memory.

[0149] Example 19: A method comprising: receiving data at a device-to-device interface; writing the data into a memory; receiving a timing signal; and responding to the timing signal by providing a data packet containing the data at a network-to-device interface.

[0150] Example 20: The method of Example 19 includes generating the timing signal after a delay time following an expected reception time of the data at the device's opposing interface, the delay time being related to a write time for writing the data into the memory.

[0151] Although this disclosure has been described with reference to specific illustrated examples, those skilled in the art will recognize and understand that the invention is not limited thereto. Rather, many additions, deletions, and modifications can be made to the illustrated and described examples without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one example can be combined with features from another example while still being covered within the scope of the invention as contemplated by the inventors. [Simplified Explanation of the Diagram]

[0005] Although this disclosure concludes with a specifically pointed-out and explicit claim to particular examples of the patent application, the various features and advantages of the examples within the scope of this disclosure can be more readily determined from the following description when read in conjunction with the accompanying drawings, in which: Figure 1 is a functional block diagram illustrating one or more examples of a system. Figure 2 is a functional block diagram illustrating one or more examples of a device. Figure 3 is a functional block diagram illustrating one or more examples of a device. Figure 4 is a functional block diagram illustrating one or more examples of a device. Figure 5 is a functional block diagram illustrating one or more examples of a system. Figure 6 is a functional block diagram illustrating one or more examples of a device. Figure 7 is a flowchart illustrating one or more examples of a method. Figure 8 is a flowchart illustrating another method according to one or more examples. Figure 9 is a block diagram illustrating one or more examples of an apparatus that can be used to implement various functions, operations, actions, procedures, or methods.

Claims

1. A device for managing data, comprising: A memory module used to store incoming or outgoing data; A timer for generating a timing signal in direct response to the expiration of a user-configurable time interval; and a circuit for moving the incoming or outgoing data from the memory in at least part of response to the timing signal generated by the timer.

2. The equipment as requested in item 1, wherein, The incoming data is received at a network interface, and the circuitry is used to move the incoming data from the memory to a device interface.

3. The equipment as requested in item 2, wherein, The circuit is used to provide preset data in response to receiving the timing signal and not finding new data in the memory, wherein the preset data includes one or more of pre-defined data and previously received data.

4. The equipment as requested in item 2, wherein, The circuit includes a device-side circuit, wherein the device includes a network-side circuit for moving the incoming data from the network-opposite interface to the memory.

5. The equipment as requested in item 4, wherein, The timer is used to generate the timing signal at a delay time after one of the expected reception times of the incoming data at the network peer interface, the delay time being related to one of the write times for writing the incoming data into the memory.

6. The equipment as requested in item 4, wherein, The device's interface is communicatively coupled to a controller of an industrial automation control system, which communicates with a sensor and a motor driver via a network switch to move the observed position of a motor-controlled device toward the desired position of the motor-controlled device.

7. The equipment as requested in item 4, wherein, The device's interface is communicatively coupled to one or more of a sensor and a motor driver, both of which communicate with a controller of an industrial automation control system via a network switch to move the observed position of a motor-controlled device to the desired position of the motor-controlled device.

8. The device as requested in item 1, wherein, The outgoing data is received at a device-facing interface, wherein the circuitry is used to move the outgoing data from the memory to a network-facing interface.

9. The equipment as requested in item 8, wherein, The timer includes a network-side timer, wherein the timing signal includes a network-side timing signal, wherein the user-configurable time interval includes a network-side user-configurable time interval, wherein the circuitry includes a network-side circuitry, and wherein the device includes: a device-side timer for generating a device-side timing signal; and a device-side circuitry for at least partially responding to the device-side timing signal by moving the outgoing data from the device-facing interface to the memory.

10. The equipment as requested in item 9, wherein, The network-side timer is used to generate the network-side timing signal after a delay time following the generation of the device-side timing signal by the device-side timer. This delay time is related to the write time for writing the outgoing data into one of the memory.

11. The equipment as requested in item 8, wherein, The circuit includes a network-side circuit, and the device includes: a device-side circuit for moving the outgoing data from the device-facing interface to the memory.

12. The equipment as requested in item 11, wherein, The timer is used to generate the timing signal at a delay time after one of the expected reception times of the outgoing data at the device's opposing interface, the delay time being related to one of the write times for writing the outgoing data into the memory.

13. A device for managing data, comprising: A network switch used to enable communication within an industrial automation control system; A memory for storing data transmitted to or from the network switch; a timer for generating a timing signal in direct response to the expiration of a user-configurable time interval; and a circuit for moving the data to or from the memory in at least a partial response to the timing signal generated by the timer.

14. The equipment as requested in item 13, wherein, The industrial automation control system includes a controller, a motor driver, and a sensor that communicate via the network switch to move an observed position of a motor-controlled device toward a desired position of the motor-controlled device.

15. A system for managing data, comprising: A component of an industrial automation control system, the component including one or more of a controller, a motor driver, and a sensor, the component communicating with other components of the industrial automation control system via a network switch; a memory configured to store data transmitted from the network switch to the component or data transmitted from the component to the network switch; a timer for generating a timing signal directly in response to the expiration of a user-configurable time interval; and a circuit for at least partially responding to the timing signal generated by the timer to move the data to or remove the data from the memory.

16. The system as described in request item 15, wherein, The other components of the industrial automation control system include two or more of a controller, a motor driver, and a sensor, which communicate via the network switch to move the observed position of one of the motor control devices toward the desired position of one of the motor control devices.

17. A method for managing data, comprising: Receive a data packet at a network peer-to-peer interface; Write the data from the data packet into a memory. Receives a timing signal generated directly in response to the expiration of a user-configurable time interval; and in response to the timing signal, provides the data from the memory at a device-facing interface.

18. The method of claim 17, comprising generating the timing signal after a delay time following an expected reception time of the data packet at the network peer interface, the delay time being related to a write time for writing the data to the memory.

19. A method for managing data, comprising: Receive data at an interface opposite to the device; Write the data to a memory; Receive a timing signal generated directly in response to the expiration of a user-configurable time interval; and in response to the timing signal, provide a data packet containing the data at a network peer interface.

20. The method of claim 19, comprising generating the timing signal after a delay time following an expected reception time of the data at the device-facing interface, the delay time being related to a write time for writing the data to the memory.

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