Sub-sampling phase locked loop and integrated circuit

Abstract

This invention provides a subsampling phase-locked loop (PLL) comprising a slope generation and sampling circuit, a first transconductance circuit and a second transconductance circuit, a constant transconductance bias circuit, a loop filter, and a voltage-controlled oscillator (VCO). The slope generation and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first and second transconductance circuits generate a first output control voltage and a second output control voltage based on the sampling voltage, the reference voltage, and a control current. The constant transconductance bias circuit includes a switched capacitor resistor. The constant transconductance bias circuit is configured to generate a control current. The loop filter is connected to the outputs of the first and second transconductance circuits. The VCO generates an output clock signal based on the first and second output control voltages.

Description

Technical Field

[0001] Example embodiments generally relate to semiconductor integrated circuits, and more particularly, to sub-sampling phase locked loops (PLLs) having a compensated loop bandwidth and / or integrated circuits including sub-sampling phase locked loops. [Cross-reference to related applications]

[0002] This application claims the priority of Korean Patent Application No. 10-2021-0139933 filed on October 20, 2021 and Korean Patent Application No. 10-2021-0177631 filed on December 13, 2021 with the Korean Intellectual Property Office, and the content of each of the applications is incorporated herein by reference in its entirety.

Background Art

[0003] In some cases, despite improving the speed and data transfer rate of peripheral devices such as memories, communication devices, or graphic devices, the operating speed of the peripheral devices has fallen behind the operating speed of the processor. In addition, there is usually a speed difference between a new microprocessor and its peripheral devices. Therefore, there has been a need or desire for some high-performance digital systems to significantly improve the speed of peripheral devices.

[0004] For example, in an input and output method of transferring data by synchronizing a clock signal for data transfer between a memory device and a memory controller, the load on the bus increases and the transfer frequency becomes faster.

Summary of the Invention

[0005] At least one example embodiment of the present disclosure provides a sub-sampling phase locked loop (PLL) having a loop bandwidth compensated for the effects of process voltage temperature (PVT) variations.

[0006] At least one example embodiment of the present disclosure provides an integrated circuit including a sub-sampling phase locked loop.

[0007] According to some example embodiments, a sub-sampling phase-locked loop (PLL) includes a slope generation and sampling circuit, a first transconductance circuit, a second transconductance circuit, a constant transconductance bias circuit, a loop filter, and a voltage controlled oscillator (VCO). The slope generation and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first transconductance circuit generates a first output control voltage based on the sampling voltage, a reference voltage, and a control current. The second transconductance circuit generates a second output control voltage based on the sampling voltage, the reference voltage, and the control current. The constant transconductance bias circuit includes a switched capacitor resistor (SCR). The constant transconductance bias circuit is configured to generate the control current. The loop filter is connected to an output terminal of the first transconductance circuit and an output terminal of the second transconductance circuit. The VCO generates an output clock signal based on the first output control voltage and the second output control voltage.

[0008] According to some example embodiments, an integrated circuit includes a sub-sampling phase-locked loop (PLL) and internal circuitry. The sub-sampling PLL generates an output clock signal based on a reference clock signal. The internal circuitry operates based on the output clock signal. The sub-sampling PLL includes a slope generation and sampling circuit, a first transconductance circuit, a second transconductance circuit, a constant transconductance bias circuit, a loop filter, and a voltage controlled oscillator (VCO). The slope generation and sampling circuit generates a sampling voltage based on the reference clock signal and the output clock signal. The first transconductance circuit generates a first output control voltage based on the sampling voltage, a reference voltage, and a control current. The second transconductance circuit generates a second output control voltage based on the sampling voltage, the reference voltage, and the control current. The constant transconductance bias circuit includes a switched capacitor resistor (SCR). The constant transconductance bias circuit is configured to generate the control current. The loop filter is connected to an output terminal of the first transconductance circuit and an output terminal of the second transconductance circuit. The VCO generates an output clock signal based on the first output control voltage and the second output control voltage.

[0009] According to some example embodiments, a sub-sampling phase-locked loop (PLL) includes a slope generation and sampling circuit, a constant transconductance bias circuit, a first transconductance circuit, a second transconductance circuit, a loop filter, and a voltage-controlled oscillator (VCO). The slope generation and sampling circuit includes a first resistor and a first capacitor. The slope generation and sampling circuit is configured to generate a sampling voltage based on a reference clock signal and an output clock signal. The slope of the sampling voltage is inversely proportional to the resistance of the first resistor and the capacitance of the first capacitor. The constant transconductance bias circuit includes a switched capacitor resistor (SCR) including a second capacitor. The constant transconductance bias circuit is configured to generate a control current. The current level of the control current is proportional to the capacitance of the second capacitor. The first transconductance circuit generates a first output control voltage based on the sampling voltage, a reference voltage, and the control current. The voltage level of the first output control voltage is proportional to the resistance of a second resistor and the capacitance of the second capacitor. The second transconductance circuit generates a second output control voltage based on the sampling voltage, a reference voltage, and the control current. The loop filter includes a second resistor. The loop filter is connected to the output of the first transconductance circuit and the output of the second transconductance circuit. The voltage-controlled oscillator generates an output clock signal based on the first output control voltage and the second output control voltage. The proportional path of the sub-sampling PLL is formed by the first transconductance circuit, and the integral path of the sub-sampling PLL is formed by the second transconductance circuit. The loop bandwidth of the sub-sampling PLL is independent of the resistance of the first resistor, the capacitance of the first capacitor, the resistance of the second resistor, and the capacitance of the second capacitor. The loop bandwidth of the sub-sampling PLL is proportional to the gain of the proportional path.

[0010] In a sub-sampling PLL and an integrated circuit according to some example embodiments, the constant transconductance bias circuit may include a switched capacitor resistor, the first transconductance circuit and the second transconductance circuit may be respectively disposed on the proportional path and the integral path, and the loop filter may include a resistor connected to the output of the first transconductance circuit. The influence of the distribution of the resistors and capacitors included in the slope generation and sampling circuit on the loop bandwidth can be offset by the capacitor included in the switched capacitor resistor and the resistor included in the loop filter. Accordingly, the sub-sampling PLL may have a loop bandwidth that compensates for the effects of process, voltage, and temperature (PVT) variations (e.g., a loop bandwidth that is relatively insensitive to PVT variations), and may have improved and / or enhanced performance.

Embodiments

[0012] The various example embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are shown. However, the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In this application, like reference numerals refer to like elements.

[0013] FIG. 1 is a block diagram showing a sub-sampling phase-locked loop according to some example embodiments.

[0014] Referring to FIG. 1, a sub-sampling phase-locked loop (PLL) 100 includes a slope generation and sampling circuit 200, a first transconductance (Gm) circuit 300, a second transconductance circuit 400, a constant transconductance bias circuit 500, a loop filter 600, and a voltage-controlled oscillator (VCO) 700.

[0015] The slope generation and sampling circuit 200 generates a sampling voltage VSAMP based on a reference clock signal CLK_REF and an output clock signal CLK_VCO. The reference clock signal CLK_REF and the output clock signal CLK_VCO may respectively correspond to the input and output of the sub-sampling phase-locked loop 100. For example, the reference clock signal CLK_REF may be generated by a crystal oscillator using a crystal material and may have a fixed frequency. Thus, the frequency of the reference clock signal CLK_REF can be used as a reference frequency (e.g., a target frequency) for the frequency of the output clock signal CLK_VCO.

[0016] The sampling voltage VSAMP may correspond to a phase error between the reference clock signal CLK_REF and the output clock signal CLK_VCO. The slope generation and sampling circuit 200 may generate the sampling voltage VSAMP representing the phase error based on a sampling operation. The slope generation and sampling circuit 200 may be referred to as a sampling-based phase detector (PD) or a sampling-based phase frequency detector (PFD).

[0017] In some example embodiments, as will be described with reference to FIGS. 3A, 3B, and 3C, the sampling voltage VSAMP may have a first voltage level that is a relatively low voltage level or a second voltage level that is a relatively high voltage level. For example, when the phase of the reference clock signal CLK_REF leads the phase of the output clock signal CLK_VCO, e.g., when the phase of the output clock signal CLK_VCO lags behind the phase of the reference clock signal CLK_REF, a sampling voltage VSAMP having the first voltage level may be generated. When the phase of the reference clock signal CLK_REF lags behind the phase of the output clock signal CLK_VCO, e.g., when the phase of the output clock signal CLK_VCO leads the phase of the reference clock signal CLK_REF, a sampling voltage VSAMP having the second voltage level may be generated.

[0018] The detailed configuration and operation of the slope generation and sampling circuit 200 will be described with reference to FIGS. 2, 3A, 3B, 3C, and 3D.

[0019] The constant transconductance bias circuit 500 generates a control current ICTRL and provides the control current ICTRL to the first transconductance circuit 300 and the second transconductance circuit 400. The control current ICTRL can be used to operate or drive the first transconductance circuit 300 and the second transconductance circuit 400.

[0020] The constant transconductance bias circuit 500 includes a switched capacitor resistor (SCR) 520. For example, as will be described with reference to FIG. 4, the switched capacitor resistor 520 may include at least one capacitor and at least one switch.

[0021] The switched capacitor resistor is a type of switched capacitor (SC) and is the simplest switched capacitor. A switched capacitor is an electronic circuit element for implementing a filter and acts by moving charges into and out of the capacitor when the switch is opened and closed. Generally, non-overlapping signals are used to control the switches such that not all switches are closed simultaneously. The filter implemented by these elements is called a "switched capacitor filter" and depends only on the ratio between capacitances. This makes it more suitable for use within an integrated circuit where it is not economical to construct precisely specified resistors and capacitors.

[0022] The detailed configuration and operation of the constant transconductance bias circuit 500 will be described with reference to FIGS. 4, 5A, 5B, and 5C.

[0023] The first transconductance circuit 300 generates a first output control voltage VCTRL1 based on a sampled voltage VSAMP, a reference voltage VREF, and the control current ICTRL. The second transconductance circuit 400 generates a second output control voltage VCTRL2 based on the sampled voltage VSAMP, the reference voltage VREF, and the control current ICTRL. For example, the proportional path of the sub-sampling phase-locked loop 100 can be formed by the first transconductance circuit 300, and the integral path of the sub-sampling phase-locked loop 100 can be formed by the second transconductance circuit 400.

[0024] The loop filter 600 is connected to the output of the first transconductance circuit 300 and the output of the second transconductance circuit 400. The loop filter 600 may include a resistor RLF and a capacitor CLF. The resistor RLF may be connected between the output of the first transconductance circuit 300 and the ground voltage VSS. The capacitor CLF may be connected between the output of the second transconductance circuit 400 and the ground voltage VSS. The loop filter 600 may have a structure in which the resistor RLF and the capacitor CLF are electrically and / or physically separated from each other. In some example embodiments, the loop filter 600 can eliminate jitter by removing faults and by preventing voltage overshoot.

[0025] The constant transconductance bias circuit 500, the first transconductance circuit 300, and the second transconductance circuit 400 can form a charge pump. For example, the charge pump can obtain a current (e.g., the control current ICTRL) output from the power supply to the output terminal based on the sampled voltage VSAMP, or can sink the current from the output terminal to ground. For example, the loop filter 600 can increase the voltage (e.g., the first output control voltage VCTRL1 and the second output control voltage VCTRL2) based on the source current, or can decrease the voltage based on the sinking current.

[0026] The detailed configuration and operation of the first transconductance circuit 300 and the second transconductance circuit 400 will be described with reference to FIGS. 6, 7A, and 7B.

[0027] The voltage-controlled oscillator 700 generates an output clock signal CLK_VCO based on the first output control voltage VCTRL1 and the second output control voltage VCTRL2. For example, the voltage-controlled oscillator 700 can include a ring oscillator, an RC oscillator, a crystal oscillator, or a temperature compensated crystal oscillator (TCXO), but the example embodiments are not limited thereto.

[0028] In some example embodiments, the output frequency FVCO of the output clock signal CLK_VCO can be FVCO = Kp*VCTRL1 + Ki*VCTRL2, where Kp represents the gain of the proportional path and Ki represents the gain of the integral path.

[0029] A phase-locked loop can perform a function of generating an output clock signal by multiplying the input frequency of an input clock signal by a desired (or alternatively, pre-determined) number, and the output clock signal has an output frequency different from the input frequency of the input clock signal. In this case, phase noise can appear at the output frequency by appropriately filtering the phase noise on the input frequency, and the phase noise at the output frequency and the performance of the phase-locked loop affected by the phase noise can be determined and / or changed depending on the structure of the phase-locked loop. For example, one of the factors that greatly affects the phase noise at the output frequency can be the loop bandwidth (BW), and the loop bandwidth can be determined based on a parameter associated with or related to the transfer function of the blocks included in the phase-locked loop.

[0030] The sub-sampling phase-locked loop is a type of phase-locked loop. The sub-sampling phase-locked loop can operate by sampling the output clock signal using an input clock signal (or a reference clock signal). When the ratio of the output frequency of the output clock signal to the input frequency of the input clock signal is an integer, the sub-sampling phase-locked loop can operate without using a frequency divider, and thus the sub-sampling phase-locked loop may be widely used.

[0031] Generally, the sub-sampling phase-locked loop may include a slope generator and a sampler, and the slope generator and the sampler may include a resistor and a capacitor. In this case, the loop bandwidth of the sub-sampling phase-locked loop can be expressed as a function of the resistance of the resistor and the capacitance of the capacitor in the slope generator and the sampler. Since the resistor and the capacitor are passive components, the resistance of the resistor and the capacitance of the capacitor can have a relatively large distribution when manufactured in a semiconductor process. Therefore, there may be a problem that the loop bandwidth of the sub-sampling phase-locked loop has a relatively large distribution.

[0032] In the sub-sampling phase-locked loop 100 according to some example embodiments, the constant transconductance bias circuit 500 may include a switched-capacitor resistor 520, the first transconductance circuit 300 and the second transconductance circuit 400 may be respectively disposed on the proportional path and the integral path, and the loop filter 600 may include a resistor RLF connected to the output terminal of the first transconductance circuit 300. The influence of the distribution of the resistors and capacitors included in the slope generation and sampling circuit 200 on the loop bandwidth can be offset by the capacitor included in the switched-capacitor resistor 520 and the resistor RLF included in the loop filter 600. Therefore, the sub-sampling phase-locked loop 100 can have a loop bandwidth that compensates for the effects of process, voltage, and temperature (PVT) variations (e.g., a loop bandwidth that is relatively insensitive to PVT variations), and can have improved and / or enhanced performance.

[0033] FIG. 2 is a circuit diagram showing an example of a slope generation and sampling circuit included in a sub-sampling phase-locked loop according to some example embodiments.

[0034] Referring to FIG. 2, the slope generation and sampling circuit 202 may include a first circuit 210 and a second circuit 220.

[0035] The first circuit 210 may be connected between the power supply voltage VDD and the ground voltage VSS and may operate based on the output clock signal CLK_VCO. The first circuit 210 may include a transistor TS1, a transistor TS2, and a resistor RS.

[0036] The transistor TS1, the resistor RS, and the transistor TS2 may be connected in series between the power supply voltage VDD and the ground voltage VSS. For example, the transistor TS1 may be connected between the power supply voltage VDD and the node NS1, the resistor RS may be connected between the node NS1 and the node NS2, and the transistor TS2 may be connected between the node NS2 and the ground voltage VSS. The gate electrodes of the transistor TS1 and the second transistor TS2 may receive the output clock signal CLK_VCO.

[0037] In some exemplary embodiments, the transistor TS1 may be a p-type metal oxide semiconductor (PMOS) transistor, and the transistor TS2 may be an n-type metal oxide semiconductor (NMOS) transistor. However, the exemplary embodiments are not limited thereto.

[0038] The second circuit 220 may be connected to the first circuit 210 and the ground voltage VSS, may operate based on the reference clock signal CLK_REF, and may output the sampled voltage VSAMP. The second circuit 220 may include the switches SWS1 and SWS2, and the capacitors CS1 and CS2, and may further include an inverter INV.

[0039] The inverter INV may generate the inverted reference clock signal / CLK_REF, which inverts the reference clock signal CLK_REF. In some exemplary embodiments, the inverter INV may be disposed outside the second circuit 220 or outside the slope generation and sampling circuit 202.

[0040] The switch SWS1 may be connected between the resistor RS and the node NS3, and may be connected between the node NS2 connected to the resistor RS and the node NS3. The switch SWS2 may be connected between the node NS3 and the node NS4. The sampled voltage VSAMP may be output via the node NS4. The capacitor CS1 may be connected between the node NS3 and the ground voltage VSS. The capacitor CS2 may be connected between the node NS4 and the ground voltage VSS.

[0041] The switch SWS1 can be turned on and off based on the reference clock signal CLK_REF. The switch SWS2 can be turned on and off based on the inverted reference clock signal / CLK_REF. For example, when the reference clock signal CLK_REF has a first logic level (e.g., a logic high level), the switch SWS1 can be turned on and off, and when the reference clock signal CLK_REF has a second logic level (e.g., a logic low level), the switch SWS1 can be turned off and on. For example, when the inverted reference clock signal / CLK_REF has a first logic level, the switch SWS2 can be turned on and off, and when the inverted reference clock signal / CLK_REF has a second logic level, the switch SWS2 can be turned off and on. In other words, the switch SWS1 and the switch SWS2 can be turned on and off complementarily.

[0042] In some exemplary embodiments, each of the switch SWS1 and the switch SWS2 may include at least one transistor.

[0043] FIG. 3A, FIG. 3B, FIG. 3C, and FIG. 3D are diagrams for describing the operation of the slope generation and sampling circuit of FIG. 2.

[0044] Referring to FIG. 3A, the output clock signal CLK_VCO generated and output from the secondary sampling phase-locked loop 100 may be a sine wave having an amplitude and a direct current (DC) voltage VDC, and may be sampled by the slope generation and sampling circuit 202 based on the reference clock signal CLK_REF. When the output clock signal CLK_VCO is phase-aligned with the reference clock signal CLK_REF and there is no phase error between the output clock signal CLK_VCO and the reference clock signal CLK_REF, the voltage level of the sampling voltage VSAMP may have a constant level substantially equal to the DC voltage VDC of the output clock signal CLK_VCO. For example, the voltage level of the DC voltage VDC may be substantially equal to the voltage level of the reference voltage VREF applied to the first transconductance circuit 300 and the second transconductance circuit 400.

[0045] Referring to FIG. 3B, when the phase of the output clock signal CLK_VCO is guided by the phase of the reference clock signal CLK_REF, for example, when the phase of the output clock signal CLK_VCO lags behind the phase of the reference clock signal CLK_REF, a first phase error PE1 may exist between the output clock signal CLK_VCO and the reference clock signal CLK_REF, and the sampling voltage VSAMP may have a first voltage level lower than the voltage level of the DC voltage VDC. For example, a first voltage difference VD1 between the voltage level of the sampling voltage VSAMP and the voltage level of the DC voltage VDC may correspond to the first phase error PE1 between the output clock signal CLK_VCO and the reference clock signal CLK_REF. When the voltage level of the sampling voltage VSAMP is lower than the voltage level of the DC voltage VDC, the phase of the output clock signal CLK_VCO may be adjusted or modified in a first direction based on the sampling voltage VSAMP.

[0046] Referring to FIG. 3C, when the phase of the reference clock signal CLK_REF lags behind the phase of the output clock signal CLK_VCO, for example, when the phase of the output clock signal CLK_VCO guides the phase of the reference clock signal CLK_REF, a second phase error PE2 may exist between the output clock signal CLK_VCO and the reference clock signal CLK_REF, and the sampling voltage VSAMP may have a second voltage level higher than the voltage level of the DC voltage VDC. For example, a second voltage difference VD2 between the voltage level of the sampling voltage VSAMP and the voltage level of the DC voltage VDC may correspond to the second phase error PE2 between the output clock signal CLK_VCO and the reference clock signal CLK_REF. When the voltage level of the sampling voltage VSAMP is higher than the voltage level of the DC voltage VDC, the phase of the output clock signal CLK_VCO may be adjusted or modified in a second direction opposite to the first direction based on the sampling voltage VSAMP.

[0047] Referring to FIG. 3D, VNS2 denotes the voltage at node NS2 in FIG. 2, SLP denotes the slope of the sampling voltage VSAMP, and SLP = Y / X. The slope SLP of the sampling voltage VSAMP may be a small-signal voltage generated based on the voltage VNS2 at node NS2. The slope SLP of the sampling voltage VSAMP may be inversely proportional to the resistance of the resistor RS included in the slope generation and sampling circuit 202 of FIG. 2, and may be inversely proportional to the capacitances of the capacitor CS1 and the capacitor CS2 included in the slope generation and sampling circuit 202 of FIG. 2. In other words, the slope SLP of the sampling voltage VSAMP may be represented by Equation 1. [Equation 1]

[0048] In Equation 1, R1 denotes the resistance of resistor RS, and C1 denotes the capacitance of capacitors CS1 and CS2. For example, C1 can be determined based on at least one of capacitors CS1 and CS2. For example, C1 can correspond to the capacitance of one of capacitors CS1 and CS2 (e.g., the capacitance of capacitor CS1), or can correspond to the capacitance of both capacitors CS1 and CS2 (e.g., the average capacitance of capacitors CS1 and CS2).

[0049] Although the configuration and operation of the slope generation and sampling circuit 202 are described with reference to FIGS. 2, 3A, 3B, 3C, and 3D, the exemplary embodiments are not limited thereto, and the configuration and operation of the slope generation and sampling circuit 200 can be determined in different ways according to some exemplary embodiments.

[0050] FIG. 4 is a circuit diagram showing an example of a constant transconductance bias circuit included in a sub-sampling phase-locked loop according to some exemplary embodiments.

[0051] Referring to FIG. 4, the constant transconductance bias circuit 502 can include a first circuit 510, a switched capacitor resistor 522, and a second circuit 530.

[0052] The first circuit 510 can be connected between the power supply voltage VDD and the ground voltage VSS. The first circuit 510 can include transistors TB1, TB2, TB3, and TB4.

[0053] Transistors TB1 and TB2 can be connected in series between the power supply voltage VDD and the ground voltage VSS. For example, transistor TB1 can be connected between the power supply voltage VDD and node NB1, and transistor TB2 can be connected between node NB1 and the ground voltage VSS. Transistors TB3 and TB4 can be connected in series between the power supply voltage VDD and node NB3. For example, transistor TB3 can be connected between the power supply voltage VDD and node NB2, and transistor TB4 can be connected between node NB2 and node NB3. The gate electrodes of transistor TB1 and transistor TB3 can be connected to each other and can be connected to node NB2. The gate electrodes of transistor TB2 and transistor TB4 can be connected to each other and can be connected to node NB1.

[0054] In some exemplary embodiments, transistors TB1 and TB3 can be PMOS transistors, and transistors TB2 and TB4 can be NMOS transistors. However, the exemplary embodiments are not limited thereto.

[0055] The switched capacitor resistor 522 can be connected between the first circuit 510 and the ground voltage VSS, and can also be connected between the node NB3 connected to the first circuit 510 and the ground voltage VSS. The switched capacitor resistor 522 can operate based on the first phase signal PH1 and the second phase signal PH2. The switched capacitor resistor 522 can include a switch SWB1, a switch SWB2, and a capacitor CGm.

[0056] The switch SWB1 can be connected between the node NB3 and the node NB4. The capacitor CGm can be connected between the node NB4 and the ground voltage VSS. The switch SWB2 can be connected in parallel with the capacitor CGm between the node NB4 and the ground voltage VSS.

[0057] The switch SWB1 can be turned on and off based on the first phase signal PH1. The switch SWB2 can be turned on and off based on the second phase signal PH2. For example, when the first phase signal PH1 has a first logic level (e.g., logic high level), the switch SWB1 can be turned on and closed, and when the first phase signal PH1 has a second logic level (e.g., logic low level), the switch SWB1 can be turned off and opened. For example, when the second phase signal PH2 has a first logic level, the switch SWB2 can be turned on and closed, and when the second phase signal PH2 has a second logic level, the switch SWB2 can be turned off and opened.

[0058] In some example embodiments, each of the switch SWB1 and the switch SWB2 can include at least one transistor.

[0059] The second circuit 530 can be connected to the power supply voltage VDD and the first circuit 510, and can output a control current ICTRL. The second circuit 530 can include a transistor TB5.

[0060] The transistor TB5 can be connected between the power supply voltage VDD and the node NB5. The control current ICTRL can be output via the node NB5. The gate electrode of the transistor TB5 can be connected to the gate electrode of the transistor TB1 and the gate electrode of the transistor TB3.

[0061] In some example embodiments, the transistor TB5 can be a PMOS transistor. However, the example embodiments are not limited thereto.

[0062] Different from the constant transconductance bias circuit included in the conventional sub-sampling phase-locked loop, the constant transconductance bias circuit 502 included in the sub-sampling phase-locked loop 100 according to some example embodiments can further include a switched capacitor resistor 522.

[0063] Figures 5A, 5B, and 5C are diagrams for describing the operation of the constant transconductance bias circuit of FIG. 4.

[0064] Referring to FIG. 5A, an example of the first phase signal PH1 and the second phase signal PH2 applied to the switched capacitor resistor 522 in FIG. 4 is shown.

[0065] The effective (or active) duration TA1 of the first phase signal PH1 and the effective duration TA2 of the second phase signal PH2 may not overlap, and thus the switches SWB1 and SWB2 may not be turned on simultaneously or in parallel (e.g., may not be turned off simultaneously or in parallel).

[0066] The switched capacitor resistor 522 is the simplest switched capacitor. The switched capacitor resistor 522 may include a capacitor CGm and two switches SWB1 and SWB2 that alternately connect the capacitor CGm to the input and output of the switched capacitor resistor 522 at a given frequency (e.g., based on the phase signal PH1 and the phase signal PH2). In each switching cycle, a charge q may be transferred from the input to the output according to the switching frequency f. In a typical capacitor, q = C * V, where C denotes the capacitance of the capacitor and V denotes the voltage across the capacitor. Based on the characteristics described above, the operation of the switched capacitor resistor 522 will be described as follows.

[0067] In the switched capacitor resistor 522, when one of the switches SWB1 and SWB2 (e.g., SWB1) is closed and the other of the switches SWB1 and SWB2 (e.g., SWB2) is open, the charge input and stored in the capacitor CGm can be q1 = Cgm * V1, where V1 represents the input voltage of the switched capacitor resistor 522. When one of the switches SWB1 and SWB2 (e.g., SWB1) is open and the other of the switches SWB1 and SWB2 (e.g., SWB2) is closed, some of the charge stored in the capacitor CGm (e.g., q1) can be transferred out of the capacitor CGm, and then the remaining charge in the capacitor CGm can be q2 = Cgm * V2, where V2 is the output voltage of the switched capacitor resistor 522. Therefore, the charge transferred from the capacitor CGm to the output can be q3 = q1 - q2 = Cgm * (V1 - V2). Since the charge q3 is transferred at a rate of the switching frequency f, the transfer rate of the charge per unit time can be ISCR = q * f = Cgm * (V1 - V2) * f. (The continuous transfer of charge from one node to another is equivalent to current, so "I" (the symbol for current) is used). The voltage from the input to the output across the switched capacitor resistor 522 can be VSCR = V1 - V2, so the equivalent resistance (e.g., the voltage-current relationship) can be RSCR = VSCR / ISCR = 1 / (Cgm * f). Therefore, the switched capacitor resistor 522 can operate as a resistor, and the resistance of the resistor depends on the capacitance of the capacitor CGm and the switching frequency f.

[0068] The switched capacitor resistor 522 can be used as a replacement for a simple resistor in an integrated circuit because it is easier to manufacture reliably with a wide range of values. The switched capacitor resistor 522 can also have the following advantage: its value can be adjusted by changing the switching frequency f (e.g., it is a programmable resistor).

[0069] Referring to FIG. 5B, the relationship between the current level of the control current ICTRL generated by the constant transconductance bias circuit 502 of FIG. 4 and the capacitance of the capacitor CGm included in the switched capacitor resistor 522 of FIG. 4 is shown. As shown in FIG. 5B, the current level of the control current ICTRL can be proportional to the capacitance of the capacitor CGm. In other words, the current level of the control current ICTRL can increase as the capacitance of the capacitor CGm increases, and the current level of the control current ICTRL can decrease as the capacitance of the capacitor CGm decreases.

[0070] Referring to FIG. 5C, changes in the current level of the control current ICTRL generated by the constant transconductance bias circuit 502 of FIG. 4 over time are shown. As shown in FIG. 5C, the current level of the control current ICTRL can be constant at all times regardless of time. In other words, the constant transconductance bias circuit 502 can operate as a constant current source.

[0071] Although the configuration and operation of the constant transconductance bias circuit 502 are described with reference to FIGS. 4, 5A, 5B, and 5C, the example embodiments are not limited thereto, and the configuration and operation of the constant transconductance bias circuit 502 can be determined in different ways according to some example embodiments.

[0072] FIG. 6 is a diagram showing an example of a first transconductance circuit, a second transconductance circuit, and a loop filter included in a sub-sampling phase-locked loop according to some example embodiments.

[0073] Referring to FIG. 6, the first transconductance circuit (GmP) 302 can correspond to the first transconductance circuit 300 in FIG. 1, and the second transconductance circuit (GmI) 402 can correspond to the second transconductance circuit 400 in FIG. 1. The resistor RLF and the capacitor CLF can correspond to the resistor RLF and the capacitor CLF included in the loop filter 600 in FIG. 1, respectively.

[0074] The first transconductance circuit 302 can include a first input terminal (e.g., a positive (+) input terminal) for receiving the sampled voltage VSAMP, and a second input terminal (e.g., a negative (-) input terminal) for receiving the reference voltage VREF. The first transconductance circuit 302 can operate based on the control current ICTRL and can generate a first output control voltage VCTRL1. The resistor RLF can be connected between the output terminal of the first transconductance circuit 302 (which outputs the first output control voltage VCTRL1) and the ground voltage VSS. The proportional path of the sub-sampling phase-locked loop 100 can be formed by the first transconductance circuit 302 and the resistor RLF.

[0075] The second transconductance circuit 402 can include a first input terminal (e.g., a positive (+) input terminal) for receiving the reference voltage VREF, and a second input terminal (e.g., a negative (-) input terminal) for receiving the sampled voltage VSAMP. The second transconductance circuit 402 can operate based on the control current ICTRL and can generate a second output control voltage VCTRL2. The capacitor CLF can be connected between the output terminal of the second transconductance circuit 402 (which outputs the second output control voltage VCTRL2) and the ground voltage VSS. The integral path of the sub-sampling phase-locked loop 100 can be formed by the second transconductance circuit 402 and the capacitor CLF.

[0076] The configurations of the first transconductance circuit 302 and the second transconductance circuit 402 can be determined in different ways according to some example embodiments, and the example embodiments may not be limited to transconductance circuits having a specific structure. In some example embodiments, the first transconductance circuit 302 and the second transconductance circuit 402 may have the same structure. In other example embodiments, the first transconductance circuit 302 and the second transconductance circuit 402 may have different structures.

[0077] In a conventional sub-sampling phase-locked loop, the loop filter includes a resistor and a capacitor that are electrically and / or directly connected to each other. In contrast, in the sub-sampling phase-locked loop 100 according to some example embodiments, the loop filter 600 may have a dual-loop structure, and the resistor RLF and the capacitor CLF in the loop filter 600 may not be electrically and / or directly connected to each other but may be electrically and / or physically separated from each other. Additionally, a conventional sub-sampling phase-locked loop includes only one transconductance circuit. However, the sub-sampling phase-locked loop 100 according to some example embodiments may include two transconductance circuits 302 and 402 that are separated from each other, and each transconductance circuit can be used to drive a respective one of the individual components (e.g., the resistor RLF and the capacitor CLF) of the loop filter 600. For example, the first transconductance circuit 302 can be used to drive the resistor RLF, and the second transconductance circuit 402 can be used to drive the capacitor CLF.

[0078] FIGS. 7A and 7B are diagrams for describing the operations of the first transconductance circuit and the loop filter of FIG. 6.

[0079] Referring to FIG. 7A, the relationship between the voltage level of the first output control voltage VCTRL1 generated by the first transconductance circuit 302 of FIG. 6 and the resistance of the resistor RLF included in the loop filter 600 of FIG. 6 is shown. As shown in FIG. 7A, the voltage level of the first output control voltage VCTRL1 can be proportional to the resistance of the resistor RLF. In other words, the voltage level of the first output control voltage VCTRL1 can increase as the resistance of the resistor RLF increases, and the voltage level of the first output control voltage VCTRL1 can decrease as the resistance of the resistor RLF decreases.

[0080] Referring to FIG. 7B, the relationship between the voltage level of the first output control voltage VCTRL1 generated by the first transconductance circuit 302 of FIG. 6 and the capacitance of the capacitor CGm included in the switched-capacitor resistor 522 in FIG. 4 is shown. As described with reference to FIG. 5B, the voltage level of the control current ICTRL for driving the first transconductance circuit 302 can be proportional to the capacitance of the capacitor CGm. Therefore, as shown in FIG. 7B, the voltage level of the first output control voltage VCTRL1 can be proportional to the capacitance of the capacitor CGm. In other words, the voltage level of the first output control voltage VCTRL1 can increase as the capacitance of the capacitor CGm increases, and the voltage level of the first output control voltage VCTRL1 can decrease as the capacitance of the capacitor CGm decreases.

[0081] For example, there may be three cases where the capacitor CGm has a first capacitance CGm1, a second capacitance CGm2, and a third capacitance CGm3, and it can be assumed that the resistance of the register RLF is equal to each other in all three cases. When the capacitor CGm has the first capacitance CGm1, the voltage level of the first output control voltage VCTRL1 can be lower than the voltage level of the first output control voltage VCTRL1 when the capacitor CGm has the second capacitance CGm2, and the first capacitance CGm1 can be smaller than the second capacitance CGm2. In addition, when the capacitor CGm has the second capacitance CGm2, the voltage level of the first output control voltage VCTRL1 can be lower than the voltage level of the first output control voltage VCTRL1 when the capacitor CGm has the third capacitance CGm3, and the second capacitance CGm2 can be smaller than the third capacitance CGm3. In other words, CGm1 < CGm2 < CGm3, and thus VCTRL1(CGm1) < VCTRL1(CGm2) < VCTRL1(CGm3).

[0082] As described with reference to FIGS. 7A and 7B, the voltage level of the first output control voltage VCTRL1 can be proportional to the resistance of the resistor RLF included in the loop filter 600 of FIG. 6, and can be proportional to the capacitance of the capacitor CGm included in the switched-capacitor resistor 522 in the constant transconductance bias circuit 502 of FIG. 4. In other words, the voltage level of the first output control voltage VCTRL1 can be represented by Equation 2. [Equation 2]

[0083] In Equation 2, R2 denotes the resistance of the resistor RLF, and C2 denotes the capacitance of the capacitor CGm.

[0084] When a conventional sub-sampling phase-locked loop only includes a slope generation and sampling circuit (e.g., the slope generation and sampling circuit 202 in FIG. 2), for example, when the conventional sub-sampling phase-locked loop does not include the switched capacitor resistor 520 and only includes one transconductance circuit, the loop bandwidth LBWc can satisfy Equation 3. [Equation 3]

[0085] In Equation 3, R1 denotes the resistance of a resistor (e.g., the resistor RS in FIG. 2), and C1 denotes the capacitance of capacitors (e.g., the capacitors CS1 and CS2 in FIG. 2), as described with reference to Equation 1. Kp denotes the gain of the proportional path including the transconductance circuit.

[0086] As described above, when the sub-sampling phase-locked loop only includes the slope generation and sampling circuit 202, the loop bandwidth LBWc of the sub-sampling phase-locked loop can be expressed as a function of the resistance of the resistor RS and the capacitances of the capacitors CS1 and CS2. The resistor RS and the capacitors CS1 and CS2 can be passive components and can have a relatively large distribution (e.g., about 20%) when manufactured in a semiconductor process, and thus the loop bandwidth LBWc of the sub-sampling phase-locked loop can have a relatively large distribution corresponding to the product of the resistance of the resistor RS and the capacitances of the capacitors CS1 and CS2.

[0087] In contrast, when the sub-sampling phase-locked loop 100 according to some exemplary embodiments includes the switched capacitor resistor 522, two transconductance circuits 302 and 402, and the loop filter 600, for example, when the loop filter 600 is implemented in a dual-loop structure, two transconductance circuits 300 and 400 separated from each other drive individual components (e.g., the resistor RLF and the capacitor CLF) in the loop filter 600, and the constant transconductance bias circuit 500 includes the switched capacitor resistor 520, the loop bandwidth LBWp can satisfy Equation 4 and Equation 5. [Equation 4][Equation 5]

[0088] In Equation 4 and Equation 5, R1 denotes the resistance of the resistor RS, and C1 denotes the capacitances of the capacitors CS1 and CS2, as described with reference to Equation 1. R2 denotes the resistance of the resistor RLF, and C2 denotes the capacitance of the capacitor CGm, as described with reference to Equation 2. Kp denotes the gain of the proportional path including the first transconductance circuit 302.

[0089] As described above, the loop bandwidth LBWp of the sub-sampling phase-locked loop 100 according to some example embodiments may be proportional only to the gain Kp of the proportional path. For example, as represented in Equation 4, the influence of the distribution of the resistor RS, the capacitors CS1, and the capacitor CS2 included in the slope generation and sampling circuit 202 on the loop bandwidth LBWp may be offset by the capacitor CGm included in the switched-capacitor resistor 522 and the resistor RLF included in the loop filter 600. Therefore, the influence of external factors such as PVT on the loop bandwidth can be reduced, and thus the sub-sampling phase-locked loop 100 may have a loop bandwidth that compensates for the influence of PVT variations (e.g., a loop bandwidth that is relatively insensitive to PVT variations) and may have improved and / or enhanced performance.

[0090] FIG. 8 is a graph for describing the performance of a sub-sampling phase-locked loop according to some example embodiments.

[0091] Referring to FIG. 8, CASE1 represents a conventional sub-sampling phase-locked loop that includes only a slope generation and sampling circuit, and CASE2 represents the sub-sampling phase-locked loop 100 according to some example embodiments that includes the switched-capacitor resistor 522, two transconductance circuits 302 and 402, and the loop filter 600. Thirty-three samples are prepared for each case, and the loop bandwidth of each sample is normalized to one and plotted. The loop bandwidth of the conventional sub-sampling phase-locked loop may have a distribution of about 0.94 to 1.12 (e.g., a distribution of about 18%), and the loop bandwidth of the sub-sampling phase-locked loop 100 according to some example embodiments may have a distribution of about 0.98 to 1.04 (e.g., a distribution of about 6%). Therefore, it can be seen that the loop bandwidth of the sub-sampling phase-locked loop 100 according to some example embodiments is significantly improved.

[0092] FIG. 9 is a block diagram showing a sampling phase-locked loop according to some example embodiments.

[0093] Referring to FIG. 9, the sampling phase-locked loop 800 includes a slope generation and sampling circuit 200, a first transconductance circuit 300, a second transconductance circuit 400, a constant transconductance bias circuit 500, a loop filter 600, a voltage-controlled oscillator 700, and a frequency divider 900.

[0094] The sampling phase-locked loop 800 of FIG. 9 may be substantially the same as the sub-sampling phase-locked loop 100 of FIG. 1, except that the sampling phase-locked loop 800 further includes a frequency divider 900 and thus partially changes the operation of the sampling phase-locked loop 800.

[0095] The frequency divider 900 can generate a divided clock signal CLK_DIV by dividing the output clock signal CLK_VCO. For example, the frequency of the divided clock signal CLK_DIV can be lower than the frequency of the output clock signal CLK_VCO.

[0096] In some example embodiments, the frequency divider 900 can be an integer frequency divider. For example, the division ratio of the frequency divider 900, e.g., the value obtained by dividing the frequency of the output clock signal CLK_VCO by the frequency of the divided clock signal CLK_DIV, can be an integer. In other example embodiments, the frequency divider 900 can be a fractional frequency divider. For example, the division ratio of the frequency divider 900, e.g., the value obtained by dividing the frequency of the output clock signal CLK_VCO by the frequency of the divided clock signal CLK_DIV, can be a real number.

[0097] The slope generation and sampling circuit 200 can generate a sampling voltage VSAMP based on a reference clock signal CLK_REF and the divided clock signal CLK_DIV. In this case, the sampling voltage VSAMP can correspond to the phase error between the reference clock signal CLK_REF and the divided clock signal CLK_DIV.

[0098] The first transconductance circuit 300, the second transconductance circuit 400, the constant transconductance bias circuit 500, the loop filter 600, and the voltage-controlled oscillator 700 in FIG. 9 can be substantially the same as the first transconductance circuit 300, the second transconductance circuit 400, the constant transconductance bias circuit 500, the loop filter 600, and the voltage-controlled oscillator 700 in FIG. 1, respectively, and can be implemented as described with reference to FIGS. 2 to 8.

[0099] In the sampling phase-locked loop 800 according to some example embodiments, the constant transconductance bias circuit 500 can include a switched capacitor resistor 520, the first transconductance circuit 300 and the second transconductance circuit 400 can be respectively disposed on the proportional path and the integral path, and the loop filter 600 can include a resistor RLF connected to the output terminal of the first transconductance circuit 300. The influence of the distribution of the resistors and capacitors included in the slope generation and sampling circuit 200 on the loop bandwidth can be offset by the capacitors included in the switched capacitor resistor 520 and the resistor RLF included in the loop filter 600. Therefore, the sampling phase-locked loop 800 can have a loop bandwidth that compensates for the influence of PVT variations (e.g., a loop bandwidth that is relatively insensitive to PVT variations), and can have improved and / or enhanced performance.

[0100] In some example embodiments, at least some components of the sub-sampling phase-locked loop 100 and the sampling phase-locked loop 800 may be implemented as hardware. For example, at least some components of the sub-sampling phase-locked loop 100 and the sampling phase-locked loop 800 may be included in a computer-based electronic system. In other example embodiments, at least some components of the sub-sampling phase-locked loop 100 and the sampling phase-locked loop 800 may be implemented as instruction codes or program routines (e.g., software programs). For example, the instruction codes or program routines may be executed by a computer-based electronic system and may be stored in any storage device located inside or outside the computer-based electronic system.

[0101] FIG. 10 is a flowchart showing a method of generating a clock signal according to some example embodiments.

[0102] Referring to FIGS. 1 and 10, the method of generating a clock signal according to some example embodiments is performed by the sub-sampling phase-locked loop 100 according to some example embodiments. As described with reference to FIG. 1, the sub-sampling phase-locked loop 100 may perform a sampling-based phase detection operation. Additionally, in the sub-sampling phase-locked loop 100, the constant transconductance bias circuit 500 may include a switched capacitor resistor 520, the first transconductance circuit 300 and the second transconductance circuit 400 may be disposed on the proportional path and the integral path respectively, and the loop filter 600 may include a resistor RLF connected to the output terminal of the first transconductance circuit 300. The method of generating a clock signal may be described as a method of operating the sub-sampling phase-locked loop.

[0103] In the method of generating a clock signal according to some example embodiments, a sampled voltage VSAMP is generated based on a reference clock signal CLK_REF and an output clock signal CLK_VCO (step S100). For example, step S100 may be performed by the slope generation and sampling circuit 200 and may be performed as described with reference to FIGS. 2, 3A, 3B, 3C, and 3D.

[0104] A control current ICTRL is generated using a constant transconductance bias circuit 500 including a switched capacitor resistor (SCR) 520 (step S200). For example, step S200 may be performed as described with reference to FIGS. 4, 5A, 5B, and 5C.

[0105] A first output control voltage VCTRL1 is generated using a first transconductance circuit (GmP) 300 and a resistor RLF included in the loop filter 600 (step S300). For example, the first output control voltage VCTRL1 may be generated based on the sampled voltage VSAMP, a reference voltage VREF, and the control current ICTRL. For example, step S300 may be performed as described with reference to FIGS. 6, 7A, and 7B.

[0106] The second output control voltage VCTRL2 is generated (step S400) using a second transconductance circuit (GmI) 400 and a capacitor CLF included in the loop filter 600. For example, the second output control voltage VCTRL2 may be generated based on a sampled voltage VSAMP, a reference voltage VREF, and a control current ICTRL. Step S300 and step S400 may be performed substantially simultaneously or in parallel.

[0107] The output clock signal CLK_VCO is generated (step S500) based on the first output control voltage VCTRL1 and the second output control voltage VCTRL2. For example, step S500 may be performed by a voltage controlled oscillator 700.

[0108] As those skilled in the art will understand, the inventive concept may be embodied as a system, a method, a computer program product, and / or a computer program product embodied in one or more computer-readable media having computer-readable program code embodied thereon. The computer-readable program code may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device. The computer-readable media may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. For example, the computer-readable media may be a non-transitory computer-readable media.

[0109] FIG. 11 is a block diagram showing an integrated circuit according to some example embodiments.

[0110] Referring to FIG. 11, the integrated circuit 2000 includes a phase locked loop (SPLL) 2100 and an internal circuit 2200.

[0111] The phase-locked loop 2100 may include a sub-sampling phase-locked loop according to some example embodiments (e.g., the sub-sampling phase-locked loop 100 of FIG. 1) and / or a sampling phase-locked loop according to some example embodiments (e.g., the sampling phase-locked loop 800 of FIG. 9). The phase-locked loop 2100 may perform sampling-based phase detection operations. Additionally, in the phase-locked loop 2100, the loop filter 600 may be implemented in a dual-loop structure, two separate transconductance circuits 300 and 400 may drive individual components (e.g., resistor RLF and capacitor CLF) in the loop filter 600, and the constant transconductance bias circuit 500 may include a switched-capacitor resistor 520. Thus, the effects of the distribution of resistors and capacitors on the loop bandwidth may be canceled, and thus the phase-locked loop 2100 may have a loop bandwidth that compensates for the effects of PVT variations (e.g., a loop bandwidth that is relatively insensitive to PVT variations) and may have improved and / or enhanced performance. The phase-locked loop 2100 may include SCR 520, GmP 302, and resistor RLF.

[0112] The internal circuit 2200 may operate (or may be driven) based on the output clock signal generated from the phase-locked loop 2100 or may perform specific operations.

[0113] FIG. 12 is a block diagram illustrating a digital processing system according to some example embodiments.

[0114] Referring to FIG. 12, the digital processing system 3000 includes a master device 3100 and multiple slave devices 3200, 3300, 3400, 3500, 3600, 3700, 3800, and 3900.

[0115] In some example embodiments, the digital processing system 3000 can be any electronic system, such as a personal computer (PC), mobile phone, smartphone, tablet computer, laptop, personal digital assistant (PDA), enterprise digital assistant (EDA), portable multimedia player (PMP), digital video camera, portable game console, music player, camcorder, video player, navigation device, wearable device, Internet of Things (IoT) device, Internet of Everything (IoE) device, e-book reader, virtual reality (VR) device, augmented reality (AR) device, robotic device, drone, etc.

[0116] The master device 3100 can be a controller circuit or a processor that can actively control multiple slave devices 3200, 3300, 3400, 3500, 3600, 3700, 3800, and 3900. For example, the master device 3100 can be implemented as a baseband modem processor chip, a chip that can act as both a modem and an application processor (AP), an AP, or a mobile AP, but the example embodiments are not limited thereto.

[0117] Each of slave devices 3200, 3300, 3400, 3500, 3600, 3700, 3800, and 3900 may be one of various circuits or devices that can be operated passively based on the control of the master device 3100. For example, slave devices 3200, 3300, 3400, 3500, 3600, 3700, 3800, and 3900 may include a radio frequency integrated circuit (RFIC) 3200, a power management integrated circuit (PMIC) 3300, a power module 3400, a secondary RFIC 3500, a sensor 3600, a fingerprint recognition chip 3700, a touch screen controller 1800, and a display driver integrated circuit or a digital display interface (DDI) 3900.

[0118] RFIC 3200 may include at least one connectivity chip. For example, the connectivity chip may include a chip 3210 for mobile (cellular) communication, a chip 3220 for wireless local area network (WLAN) (e.g., WiFi), a chip 3230 for Bluetooth communication, a chip 3240 for global navigation satellite system (GNSS) communication, a chip 3250 for processing frequency modulation (FM) audio / video, and a chip 3260 for near field communication (NFC), but the example embodiments are not limited thereto.

[0119] The RFIC 3200 may further include at least one phase-locked loop 3270. The phase-locked loop 3270 may include a sub-sampling phase-locked loop (SPLL) according to some example embodiments (e.g., the sub-sampling phase-locked loop 100 of FIG. 1) and / or a sampling phase-locked loop according to some example embodiments (e.g., the sampling phase-locked loop 800 of FIG. 9). The phase-locked loop 3270 may perform sampling-based phase detection operations. Additionally, in the phase-locked loop 3270, the loop filter 600 may be implemented in a dual-loop structure, two separate transconductance circuits 300 and 400 may drive individual components (e.g., resistor RLF and capacitor CLF) in the loop filter 600, and the constant transconductance bias circuit 500 may include a switched-capacitor resistor 520. Thus, the influence of the distribution of resistors and capacitors on the loop bandwidth can be canceled, and thus the sampling phase-locked loop 3270 may have a loop bandwidth that compensates for the influence of PVT variations (e.g., a loop bandwidth that is relatively insensitive to PVT variations) and may have improved and / or enhanced performance. The phase-locked loop 3270 may include SCR 520, GmP 302, and resistor RLF.

[0120] In some example embodiments, the phase-locked loop 3270 may be formed to correspond to each connectivity chip.

[0121] The inventive concept can be applied to various electronic devices and systems including sub-sampling phase-locked loops. For example, the inventive concept can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0122] The foregoing shows example embodiments and is not to be construed as a limitation thereof. Although some example embodiments have been described, those of ordinary skill in the art will readily understand that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the example embodiments. Accordingly, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims. Therefore, it should be understood that the foregoing shows various example embodiments but is not to be construed as limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Brief Description of the Drawings

[0011] The following detailed description, taken in conjunction with the accompanying drawings, will more clearly understand the illustrative non-limiting example embodiments. FIG. 1 is a block diagram showing a sub-sampling phase-locked loop according to some example embodiments. FIG. 2 is a circuit diagram showing an example of a slope generation and sampling circuit included in the sub-sampling phase-locked loop according to some example embodiments. FIGS. 3A, 3B, 3C, and 3D are diagrams for describing the operation of the slope generation and sampling circuit of FIG. 2. FIG. 4 is a circuit diagram showing an example of a constant transconductance bias circuit included in the sub-sampling phase-locked loop according to some example embodiments. FIGS. 5A, 5B, and 5C are diagrams for describing the operation of the constant transconductance bias circuit of FIG. 4. FIG. 6 is a diagram showing an example of a first transconductance circuit, a second transconductance circuit, and a loop filter included in the sub-sampling phase-locked loop according to some example embodiments. FIGS. 7A and 7B are diagrams for describing the operation of the first transconductance circuit and the loop filter of FIG. 6. FIG. 8 is a diagram for describing the performance of the sub-sampling phase-locked loop according to some example embodiments. FIG. 9 is a block diagram showing a sampling phase-locked loop according to some example embodiments. FIG. 10 is a flowchart showing a method for generating a clock signal according to some example embodiments. FIG. 11 is a block diagram showing an integrated circuit according to some example embodiments. FIG. 12 is a block diagram showing a digital processing system according to some example embodiments.

Claims

1. A subsampling phase-locked loop (PLL), comprising: The slope generation and sampling circuit is configured to generate a sampling voltage based on the reference clock signal and the output clock signal; A first transconductance circuit is configured to generate a first output control voltage based on the sampled voltage, the reference voltage, and the control current; a second transconductance circuit is configured to generate a second output control voltage based on the sampled voltage, the reference voltage, and the control current; a constant transconductance bias circuit includes a switched capacitor resistor (SCR), the constant transconductance bias circuit being configured to generate the control current; and a loop filter is connected to the output terminals of the first transconductance circuit and the second transconductance circuit. and a voltage-controlled oscillator (VCO) configured to generate the output clock signal based on the first output control voltage and the second output control voltage, wherein the constant transconductance bias circuit further comprises: a first circuit connected between the power supply voltage and the ground voltage; and a second circuit connected to the power supply voltage and the first circuit and configured to output the control current, wherein the switched capacitor resistor is connected between the first circuit and the ground voltage, and the switched capacitor resistor is configured to operate based on the first phase signal and the second phase signal.

2. The subsampling phase-locked loop as claimed in claim 1, wherein the switched capacitor resistor comprises: a first switch connected between a first node and a second node, the first switch being configured to turn on and off based on a first phase signal, the first node being connected to the first circuit; a first capacitor connected between the second node and the ground voltage; and a second switch connected in parallel with the first capacitor between the second node and the ground voltage, the second switch being configured to turn on and off based on the second phase signal.

3. The subsampling phase-locked loop as described in claim 2, wherein the current level of the control current generated by the constant transconductance bias circuit is proportional to the capacitance of the first capacitor.

4. The subsampling phase-locked loop as described in claim 2, wherein the effective duration of the first phase signal and the effective duration of the second phase signal do not overlap.

5. The subsampling phase-locked loop as claimed in claim 2, wherein the first circuit comprises: a first transistor and a second transistor connected in series between the power supply voltage and the ground voltage; and a third transistor and a fourth transistor connected in series between the power supply voltage and the first node, wherein the gate electrodes of the first transistor and the third transistor are connected to each other, and the gate electrodes of the second transistor and the fourth transistor are connected to each other.

6. The subsampling phase-locked loop as claimed in claim 5, wherein the second circuit includes a fifth transistor connected between the power supply voltage and a third node, the third node outputting the control current, and the gate electrode of the fifth transistor being connected to the gate electrode of the first transistor and the gate electrode of the third transistor.

7. The subsampling phase-locked loop as claimed in claim 2, wherein the loop filter comprises: a first resistor connected between the output terminal of the first transconductance circuit and the ground voltage; and a second capacitor connected between the output terminal of the second transconductance circuit and the ground voltage.

8. The subsampling phase-locked loop as claimed in claim 7, wherein the voltage level of the first output control voltage generated by the first transconductance circuit is proportional to the resistance of the first resistor and proportional to the capacitance of the first capacitor.

9. The subsampling phase-locked loop as claimed in claim 1, wherein the proportional path of the subsampling phase-locked loop is formed by the first transconducting path, and the integral path of the subsampling phase-locked loop is formed by the second transconducting path.

10. The subsampling phase-locked loop as claimed in claim 9, wherein the loop bandwidth of the subsampling phase-locked loop is proportional to the gain of the proportional path.

11. The subsampling phase-locked loop as claimed in claim 9, wherein the first transconductance circuit includes a first input terminal and a second input terminal, the first input terminal receiving the sampled voltage and the second input terminal receiving the reference voltage, and the second transconductance circuit includes a third input terminal and a fourth input terminal, the third input terminal receiving the reference voltage and the fourth input terminal receiving the sampled voltage.

12. The subsampling phase-locked loop as claimed in claim 9, wherein the first transconductance path and the second transconductance path have the same structure.

13. The subsampling phase-locked loop as claimed in claim 9, wherein the first transconductance circuit and the second transconductance circuit have different structures.

14. The subsampling phase-locked loop as claimed in claim 1, wherein the slope generation and sampling circuitry comprises: a first circuit connected between a power supply voltage and a ground voltage, the first circuit being configured to operate based on the output clock signal; and a second circuit connected to the first circuit and the ground voltage, the second circuit being configured to operate based on the reference clock signal and configured to output the sampled voltage.

15. The subsampling phase-locked loop as claimed in claim 14, wherein the first circuit comprises: a first transistor, a first resistor, and a second transistor connected in series between the power supply voltage and the ground voltage, and the gate electrode of the first transistor and the gate electrode of the second transistor are configured to receive the output clock signal.

16. The subsampling phase-locked loop as claimed in claim 15, wherein the second circuitry comprises: a first switch connected between the first resistor and the first node, the first switch being configured to be turned on and off based on the reference clock signal; a second switch connected between the first node and the second node, the second switch being configured to be turned on and off based on a reverse reference clock signal, wherein the reference clock signal is inverted, and the second node outputs the sampled voltage; a first capacitor connected between the first node and the ground voltage; and a second capacitor connected between the second node and the ground voltage.

17. The subsampling phase-locked loop as claimed in claim 16, wherein the second circuit is configured such that the slope of the sampling voltage is inversely proportional to the resistance of the first resistor, and the slope of the sampling voltage is inversely proportional to the capacitance of the first capacitor and the second capacitor.

18. An integrated circuit, comprising: The subsampled phase-locked loop (PLL) is configured to generate an output clock signal based on a reference clock signal; The circuitry includes internal circuitry configured to operate based on the output clock signal. The subsampling phase-locked loop includes a slope generation and sampling circuit configured to generate a sampling voltage based on the reference clock signal and the output clock signal. A first transconductance circuit is configured to generate a first output control voltage based on the sampling voltage, the reference voltage, and a control current. A second transconductance circuit is configured to generate a second output control voltage based on the sampling voltage, the reference voltage, and the control current. A constant transconductance bias circuit includes a switched capacitor resistor (SCR) configured to generate the control current. A loop filter is connected to the output terminals of the first and second transconductance circuits. A voltage-controlled oscillator (VCO) is configured to generate the output clock signal based on the first and second output control voltages. The constant transconductance bias circuit further includes: A first circuit is connected between a power supply voltage and a ground voltage; and a second circuit is connected to the power supply voltage and the first circuit and configured to output the control current, wherein the switched capacitor resistor is connected between the first circuit and the ground voltage and the switched capacitor resistor is configured to operate based on a first phase signal and a second phase signal.

19. A subsampling phase-locked loop (PLL), comprising: A slope generation and sampling circuit, comprising a first resistor and a first capacitor, is configured to generate a sampling voltage based on a reference clock signal and an output clock signal, the slope of which is inversely proportional to the resistance of the first resistor and the capacitance of the first capacitor; a constant transconductance bias circuit, comprising a switched capacitor resistor (SCR) including a second capacitor, is configured to generate a control current, the current level of which is proportional to the capacitance of the second capacitor; a first transconductance circuit, configured to generate a first output control voltage based on the sampling voltage, the reference voltage, and the control current, the voltage level of which is proportional to the resistance of the second resistor and the capacitance of the second capacitor; and a second transconductance circuit, configured to generate a second output control voltage based on the sampling voltage, the reference voltage, and the control current. A loop filter, including a second resistor, is connected to the output terminals of the first and second transconductance circuits; and a voltage-controlled oscillator (VCO) configured to generate the output clock signal based on the first and second output control voltages, wherein the proportional path of the subsampled phase-locked loop is formed by the first transconductance circuit, the integral path of the subsampled phase-locked loop is formed by the second transconductance circuit, the loop bandwidth of the subsampled phase-locked loop is independent of the resistance of the first resistor, the capacitance of the first capacitor, the resistance of the second resistor, and the capacitance of the second capacitor, and the loop bandwidth of the subsampled phase-locked loop is proportional to the gain of the proportional path, wherein the constant transconductance bias circuit further includes: a first circuit connected between a power supply voltage and a ground voltage; and a second circuit connected to the power supply voltage and the first circuit and configured to output the control current, wherein a switched capacitor resistor is connected between the first circuit and the ground voltage, and the switched capacitor resistor is configured to operate based on a first phase signal and a second phase signal.

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