Gate end cap and boundary placement in transistor structures for n-metal oxide semiconductor (n-mos) performance tuning

Abstract

The transistor structure includes a channel region having a first sidewall. The gate electrode includes: a first layer having a first portion adjacent to the first sidewall and a second portion adjacent to a boundary sidewall of the gate electrode. The gate electrode includes a second layer between the first and second portions of the first layer. The first layer has a first composition associated with a first work function material and a first lateral thickness originating from the first sidewall. The second layer has a second composition associated with a second work function material. Depending on the second lateral thickness of the second layer, the second layer can more or less modulate the threshold voltage (VT) of the transistor structure. In some embodiments, the ratio of the second lateral thickness to the first lateral thickness is less than three.

Description

Technical Field

[0001] The present invention relates to a transistor structure, and in particular to a transistor structure for an N-type metal oxide semiconductor. Prior Art

[0002] Typically, N-type metal oxide semiconductor (MOS) and P-MOS devices within a complementary metal oxide semiconductor (CMOS) nanowire or nanoribbon architecture can operate at different threshold voltages. However, fine-tuning the threshold voltage within a single MOS is often necessary. Therefore, a method is needed to reliably adjust the threshold voltage within a single MOS CMOS device for SOC applications. Summary of the Invention

[0003] In view of the objectives of the present invention, the present invention provides a device structure comprising: a channel region including a first sidewall; a source region and a drain region coupling opposite ends of the channel region; a gate electrode located between the source region and the drain region, the gate electrode comprising: a first layer including a first portion adjacent to the first sidewall and a second portion adjacent to a boundary sidewall spaced apart from the first sidewall; a second layer directly adjacent to the first layer and occupying a space between the first and second portions of the first layer; wherein: the first layer has a first composition associated with a first work function; the first portion of the first layer has a first lateral thickness from the first sidewall; the second layer has a second composition associated with a second work function and a second lateral thickness; and a ratio of the second lateral thickness to the first lateral thickness is less than three. The present invention enables adjustment of the threshold voltage. Simple diagram description

[0004] The material described herein is illustrated in the accompanying drawings by way of example, and not by way of limitation. For simplicity and clarity of illustration, elements illustrated in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Furthermore, for clarity of discussion, various physical features may be shown in their simplified, "ideal" forms and geometries, with the understanding that actual implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be drawn, while ignoring the finite roughness, rounded corners, and imperfect corner intersections characteristic of structures formed by nanofabrication techniques. Furthermore, where considered appropriate, reference numerals in the drawings have been repeated to indicate corresponding or analogous elements.

[0005] FIG1A is a cross-sectional view of an NMOS nanowire transistor including a dual-layer gate electrode according to an embodiment of the present disclosure. FIG1B is a plan view taken along line AA' of the structure in FIG1A , illustrating various components of the NMOS nanowire transistor. FIG1C is a cross-sectional view of an NMOS transistor having one or more features of NMOS transistor 100A depicted in FIG1A .

[0006] FIG. 2A is a cross-sectional view of an NMOS nanoribbon device structure including a double-layer gate electrode adjacent to a PMOS nanoribbon device structure according to an embodiment of the present disclosure.

[0007] [FIG. 2B] is a plan view through line AA' of the structure in FIG. 2A, illustrating various components of the NMOS and PMOS nanoparticle transistors.

[0008] [FIG. 2C] is a plan view of an SRAM circuit structure according to some embodiments.

[0009] [FIGS. 2D and 2E] are cross-sectional views of transistor structures in the SRAM circuit structure shown in FIG. 2C according to some embodiments.

[0010] FIG3 shows a method for manufacturing the CMOS nanowire transistor shown in FIG2A according to an embodiment of the present disclosure.

[0011] FIG4A is a cross-sectional view of a material layer stack for fabricating a nanocharged crystal device according to an embodiment of the present disclosure, wherein the material layer stack includes a plurality of bilayers, each of which includes a sacrificial layer on single crystal silicon.

[0012] [ FIG. 4B ] is a cross-sectional view of a block formed by stacking patterned material layers.

[0013] [FIG. 4C] is an isometric view after forming a dummy gate structure on the first portion of the block.

[0014] [FIG. 4D] is an isometric view of the structure in FIG. 4C after forming a dielectric spacer adjacent to the dummy gate structure.

[0015] [ FIG. 4E ] shows the structure of FIG. 4D after the process of removing the hard mask, the dummy gate structure, and the sacrificial layer exposed after removing the dummy gate structure to form the nanoribbon channel.

[0016] [ FIG. 5A ] is a cross-sectional view taken along line AA′ of the structure in FIG. 4E .

[0017] FIG. 5B is a cross-sectional view of the structure of FIG. 5A after forming a gate dielectric layer on the nanoribbon channel and the substrate.

[0018] FIG. 5C is a cross-sectional view of the structure in FIG. 5B after a mask forming process.

[0019] [FIG. 5D] is a cross-sectional view of the structure in FIG. 5C after forming a WF layer to set a baseline NMOS VT.

[0020] [FIG. 5E] is a cross-sectional view of the structure in FIG. 5D after a process of depositing a sacrificial material on the NMOS WF layer, followed by a planarization process.

[0021] [FIG. 5F] is a cross-sectional view of the structure in FIG. 5E after the process of removing the mask and sacrificial material and depositing the second WF layer.

[0022] [FIG. 6A] is a cross-sectional view of the structure in FIG. 5E after the process of removing the sacrificial material from the NMOS region and depositing a third WF layer on the NMOS WF layer.

[0023] [FIG. 6B] is a cross-sectional view of the structure in FIG. 6A after the process of removing the mask from the PMOS region, depositing a PMOS WF layer, followed by a planarization process to fabricate a CMOS transistor.

[0024] [FIG. 7A] illustrates a cross-sectional view of a memory cell including a transistor structure according to some embodiments.

[0025] [ FIG. 7B ] is a cross-sectional view of the memory cell shown in FIG. 7A , according to some embodiments.

[0026] [Figures 7C and 7D] are cross-sectional views of a memory device material stack according to some embodiments.

[0027] [ FIG8 ] illustrates a computing device according to an embodiment of the present disclosure.

[0028] [Figure 9] illustrates the structure of an integrated circuit (IC). Implementation Method

[0029] The materials described herein are illustrated by way of example, not limitation, in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Furthermore, for clarity of discussion, various physical features may be shown in their simplified, "ideal" forms and geometries, with the understanding that actual implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be drawn, while ignoring the finite roughness, rounded corners, and imperfect corner intersections characteristic of structures formed by nanofabrication techniques. Furthermore, where considered appropriate, reference numerals in the figures are repeated to indicate corresponding or analogous elements.

[0030] The following describes the layout of NMOS boundary walls in single MOS and CMOS architectures. In the following description, numerous specific details, such as structural schemes and detailed manufacturing methods, are set forth to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features, such as transistor operation and switch operation associated with capacitors, are described in less detail to avoid unnecessarily obscuring the embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0031] In some cases, in the following description, well-known methods and devices are shown in block diagram form rather than in detail to avoid obscuring the present disclosure. References throughout this specification to "one embodiment" or "an embodiment" or "some embodiments" mean that a particular feature, structure, function, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment wherever the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0032] As used in the description and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0033] The terms "coupled" and "connected," as well as their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect physical, electrical, or magnetic contact (with other intervening elements between them), and / or that two or more elements co-operate or interact with each other (e.g., in a causal relationship).

[0034] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material relative to another component or material, where such physical relationship is significant. For example, in the context of materials, a material or materials disposed above or below another material may be in direct contact or may have one or more intervening materials. Furthermore, a material disposed between two materials may be in direct contact with both layers or may have one or more intervening layers. Conversely, a first material "above" a second material is in direct contact with the second material / materials. Similar distinctions will be made in the context of components of a component. As used throughout this specification and claims, a list of items linked by the terms "at least one" or "one or more" may refer to any combination of the listed terms.

[0035] The term "adjacent" is used herein generally to refer to the location of one thing in close proximity (eg, next to or near one or more things between them) or adjacent to another thing (eg, next to it).

[0036] The term "signal" may refer to at least one of a current signal, a voltage signal, a magnetic signal, or a data / clock signal. The meanings of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0037] The term "device" can generally refer to a device, depending on the context in which it is used. For example, a device can refer to a stack of layers or structures, a single structure or layer, a connection of various structures with active and / or passive components, and so on. Typically, a device is a three-dimensional structure with a plane (xyz) Cartesian coordinate system in the xy direction and a height along the z direction. The plane of the device can also be the plane of the equipment that includes the device.

[0038] As used throughout this specification and claims, a list of items linked by the terms "at least one" or "one or more" may mean any combination of the listed items.

[0039] Unless otherwise indicated in the explicit context in which they are used, the terms "substantially equal," "approximately equal," and "approximately equal" mean that only an incidental variation exists between the two items so described. In the art, such variations typically do not exceed + / - 10% of a predetermined target value.

[0040] Terms such as "left," "right," "front," "back," "top," "bottom," "over," and "under" throughout the description and claims, if any, are used for descriptive purposes and are not necessarily intended to describe permanent relative positions. For example, as used herein, the terms "above," "below," "front," "back," "top," "bottom," "above," "below," and "upper" refer to the relative position of one component, structure, or material relative to another referenced component, structure, or material within a device, where such physical relationship is significant. These terms are used herein for descriptive purposes only and primarily in the context of the device's z-axis, and therefore may be relative to the device's orientation. Thus, if the device is oriented upside down relative to the context of the figures provided herein, a first material "above" or "below" a second material may also be "below" the second material within the context of the figures provided herein. In the context of materials, a material disposed above or below another material may be in direct contact with or may have one or more intervening materials. Additionally, a material disposed between two materials may be in direct contact with both layers or may have one or more intervening layers. In contrast, a first material that is "on" a second material is in direct contact with the second material. A similar distinction will be made in the context of component-of-components.

[0041] The term "between" can be used in the context of the z-axis, x-axis, or y-axis of a device. A material between two other materials can be in contact with one or both of those materials, or it can be separated from the other two materials by one or more intermediate materials. Thus, a material "between" two other materials can be in contact with either of the other two materials, or it can be coupled to the other two materials through an intermediate material. A device located between two other devices can be directly connected to one or both of those devices, or it can be separated from the other two devices by one or more intermediate devices.

[0042] Threshold voltage (VT) tuning in CMOS devices is highly desirable because integrated circuits require devices with a wide range of VTs to accommodate diverse applications. For example, IC designers implement low-VT transistors when device performance is critical (e.g., in critical circuit paths). High-VT transistors can achieve performance that is less critical. Compared to low-VT transistors, high-VT transistors can be slower but use less power because leakage current can be lower. For example, low-VT transistors can switch orders of magnitude faster, but this comes at the cost of higher leakage. Of all CMOS device types, VT tuning is more ideal in nanowire or nanoribbon devices, which offer optimal electrostatic gate control for very short channels (less than 20nm gate length).

[0043] VT tuning in CMOS nanowire devices can be achieved through a number of different techniques, with independent variation of the gate dielectric type and thickness, as well as channel length, in N- and PMOS transistors being the most important. However, because gate dielectrics can be deposited separately for N- and PMOS transistors, the resulting VT cannot be fine-tuned between different NMOS devices and between different PMOS devices. Furthermore, such implementations require complex processing requirements (multiple masks, etc.), which are difficult to precisely tune within the tight (sub-30nm spacing) nanowire or nanoribbon geometries that require precise electrostatic control around the gate. Furthermore, even with relatively uncomplicated processing operations, the resulting VT shift is typically greater than 45mV. Other approaches involve applying a voltage bias between different parts of the transistor (e.g., between the body and drain) to produce a VT shift.

[0044] The inventors have devised a solution for tuning the Vt in an NMOS transistor that is applicable to a dual-layer electrode system. For example, the gate electrode includes a first conductive layer having a first work function directly adjacent to the gate dielectric layer, and a second conductive layer having a different work function adjacent to the first conductive layer.

[0045] The threshold voltage of an NMOS (NVT) is primarily determined by the NMOS work function (N-type WF) material directly adjacent to the gate dielectric layer on the nanowire sidewalls. However, the P-WF material on top of the N-type WF has also been found to cause a VT shift due to the shine-through effect. The amount of light transmitted depends on the type of P-WF material and the ratio between the P-WF and N-type WF materials.

[0046] The relative thickness of each layer can be adjusted through deposition, but two different layers of the same thickness cannot typically be varied between different devices within a given wafer. The inventors have devised two solutions to address the two different types of devices. One solution, implemented on devices adjacent to the gate cap, adjusts the space available for N-type and P-WF gate material deposition by shifting the gate cap wall relative to the nanowire channel's sidewalls. Due to the deposition process used and the geometry of the wall and channel sidewalls, a portion of N-type WF material is deposited adjacent to the gate cap wall in addition to the channel sidewalls. By positioning the gate cap wall at a specific distance relative to the nanowire channel, the amount of P-WF material deposited between the N-type WF material adjacent to the channel sidewall and the N-type WF material deposited adjacent to the wall can be adjusted. By controlling the distance between the gate cap wall and the device edge, NMOS VT can be fine-tuned for specific cell requirements, which may be advantageous for CMOS devices.

[0047] Another solution involves shifting the CMOS work function material boundary between adjacent NMOS and PMOS nanowire transistors to achieve VT shifting. Since the distance between two nanowires in a CMOS device is fixed (determined by patterning), the total lateral thickness of the N and P work function metal is also fixed. However, by shifting the N-type P work function material boundary, the spacing adjacent to the sidewalls of the nanowire channel corresponding to the NMOS nanowire transistor can be adjusted. Shifting the N-type P boundary can be accomplished by implementing a mask that modifies the well boundary.

[0048] Figure 1A is a cross-sectional view of a device structure 100A (here, an NMOS transistor 100A) including multiple channel regions 102 (e.g., fin, nanoribbon, or nanowire channel regions). Each channel region includes a corresponding sidewall 102A and a corresponding sidewall 102B opposite sidewall 102A. Sidewall 102A can be substantially vertical or have a curved surface as shown. As shown, channel regions 102 are arranged in a vertical stack and can be aligned above base region 101. In exemplary embodiments, channel regions 102 include single crystal silicon, SiGe, or Ge.

[0049] Channel region 102 extends in a longitudinal direction, as shown in the plan view of FIG1B (along line AA'). In the illustrative embodiment, NMOS transistor 100A further includes a source region 104 coupled to a first longitudinal end of channel region 102 and a drain region 106 coupled to a second longitudinal end of channel region 102. A gate electrode 108 is located between source region 104 and drain region 106.

[0050] Referring again to FIG. 1A , gate electrode 108 comprises multiple layers. As shown, gate electrode 108 includes an NMOS-WF layer 110 and an adjacent secondary-WF layer 112 to implement electrostatic gate control. NMOS-WF layer 110 comprises an NMOS work function material, such as, but not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, tantalum nitride, titanium nitride, and other nitrides. WF layer 112 comprises a material with a different work function than NMOS-WF layer 110. WF layer 112 is directly adjacent to WF layer 110. WF layer 112 comprises a material having a different work function than that of WF layer 110. In some exemplary embodiments, WF layer 112 has a work function suitable for a P-MOS device. In some embodiments, the WF layer 112 includes a material such as, but not limited to, ruthenium, palladium, platinum, cobalt, or nickel, or tungsten, molybdenum, ruthenium, and related nitrides or carbides of tungsten, ruthenium, or molybdenum.

[0051] In the illustrated embodiment, gate electrode 108 includes a specific arrangement of WF layers 110 and 112 to provide a desired V in transistor 100A. WF layer 110 includes a WF layer portion 110A adjacent to each corresponding sidewall 102A of channel region 102 and a WF layer portion 110B at gate end wall boundary 113 of transistor 100A. WF layer portion 110A also abuts from one sidewall 102A to the next sidewall 102A. As shown, WF layer portion 110A has a lateral thickness T L1 (or lateral width), measured from gate dielectric layer 114 located on sidewall 102A and directly between WF layer 110 and channel region 102.

[0052] As shown, WF layer 112 is located between portion 110A and portion 110B. WF layer 112 can be substantially conformal to WF layer portions 110A and 110B. WF layer 112 has a lateral thickness TL2, which results in an effective VT shift in NMOS transistor 100A during operation. TL2 is a function of the thickness TL1 of WF layer portion 110A, the thickness TL3 of WF layer portion 110B, and the spacing SNW between gate dielectric layer 114 and boundary 113 on sidewall 102A. However, wall boundary 113 is designed to be located at a variable distance SCW, depending on the specific TL2 desired. For example, the upper limit of distance SCW can be determined by spacing constraints between gate-to-gate spacing between adjacent transistors. In one embodiment, SCW is at least 6 nm. In other embodiments, SCW is between 6 nm and 30 nm. In one embodiment, the minimum TL1 is 2 nm to set the NMOS work function in NMOS transistor 100A.

[0053] According to some embodiments, the ratio of TL2:TL1 is less than or equal to 3, a range the inventors have found to provide significant VT shift. In some embodiments, S NW is between 6 nm and 26 nm. In some exemplary embodiments, the TL2:TL1 ratio ranges from slightly greater than zero (e.g., 0.1) to 2.5. This TL2:TL1 ratio range of slightly greater than zero to 2.5 translates to a VT shift range of approximately 30 mV.

[0054] In various embodiments, WF layer portion 110A is substantially conformal to sidewall 102A, but may have peaks and valleys relative to a tangent line 115 drawn from the outermost point on the surface of sidewall 102A. As shown, WF layer 110 also fills the space between each consecutive channel region 102.

[0055] In the illustrated embodiment, the vertical spacing SV between the uppermost surface 102C of the lowermost channel region 102 and the lowermost surface 102D of the channel region 102 directly above the lowermost channel region 102 is at most twice the lateral thickness TL1. In some such embodiments, there is no WF layer TL2 between the individual channel regions 102. SV is determined by the thickness of the sacrificial layer used to fabricate the nanowires. In most embodiments, the spacing is less than 5 nm to minimize capacitance. WF layer portion 110A also abuts WF layer portion 110B. In the illustrated embodiment, WF layer 110 also includes portion 110C below WF layer 112.

[0056] In the illustrated embodiment, the WF layer 112 is substantially conformal to the WF layer portion 110A, and therefore, TL2 has a minimum and maximum value. Variations in the minimum and maximum values ​​of TL2 may not significantly alter the range of the threshold voltage swing. In some embodiments, TL2 may vary with height based on the relative shape and width WNR of each channel region 102. For example, if WNR decreases from the lowest channel region 102 to the highest channel region 102, TL2 may increase with height. In some embodiments, in stacked channel regions, WNR may decrease by 10% with height from the lowest channel region 102 to the highest channel region 102. Depending on the embodiment, WNR may be between 2 nm and 20 nm.

[0057] A dielectric spacer 120 adjacent to the gate dielectric layer 114 is also shown in FIG. 1A . In various embodiments, the gate dielectric layer 114 includes one or more high-k dielectric materials and may include materials such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used for the gate dielectric layer 114 include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, the gate dielectric layer 114 may be subjected to an annealing process during the fabrication of the transistor 100A to improve the quality of the gate dielectric layer 114. In some embodiments, the gate dielectric layer 114 has a thickness between approximately 1 and 2 nanometers. In some embodiments, the gate dielectric layer 114 has a thickness of at least 1 nm.

[0058] As described above, a single boundary line associated with the gate cap is shown in FIG1A . In the illustrated embodiment, WF layer portion 110B is adjacent to dielectric 116 at wall boundary 113 . As further shown in FIG1B , source and drain regions 104 and 106 may include epitaxial source and drain semiconductor materials 118A and 118B doped with impurities.

[0059] FIG1C is a cross-sectional view of an NMOS transistor structure 100B, which may have one or more features of the NMOS transistor 100A depicted in FIG1A . NMOS structure 100B further includes boundaries 119 on opposing boundaries 113, with channel regions 102 therebetween. In the illustrative embodiment, WF layer 110 includes WF layer portions 110D on gate dielectric layer 114, which are located on sidewalls 102B of each channel region 102. WF layer portion 110E is located on boundary 119 adjacent to dielectric 120. As shown, dielectric 120 is spaced apart from gate dielectric layer 114 on each sidewall 102B by a distance SCW2. SCW2 may or may not be equal to SCW. In one embodiment, the difference between SCW and SCW2 may be less than 10% of the greater of the two. This difference may affect the lateral thickness of WF layer portion 112A and thus affect VT. Thus, a larger SCW2 can result in a larger VT shift from the nominal VT associated with the WF layer 110. In an illustrative embodiment, the WF layer portion 112A has a lateral thickness TL2A that is greater than TL2. In some embodiments, the VT of the device can be set by the average of TL2 and TL2A.

[0060] Specific applications of dielectric and metal boundaries are further described in the context of Figures 2A and 2B , such as at the interface between N and PWF material regions within a CMOS gate structure. In this exemplary embodiment, NMOS VT is advantageously tuned for NMOS transistor 100A, a component of CMOS device 200. In CMOS device 200, NMOS transistor 100A is directly adjacent to gate electrode 201 of PMOS transistor 202, as shown in Figure 2A . NMOS transistor 100A has one or more characteristics of NMOS transistor 100A described in conjunction with Figures 1A-1B . PMOS transistor 202 may also have one or more features of NMOS transistor 100A.

[0061] PMOS transistor 202 includes multiple channel regions 204 (e.g., fin, nanoribbon, or nanowire channel regions 204), each of which includes a respective sidewall 204A and a respective sidewall 204B opposite sidewall 204A. As shown, sidewall 204A may be substantially vertical or curved. Also shown, channel regions 204 are arranged in a vertical stack. In an exemplary embodiment, PMOS transistor 202 includes the same number of independent channel regions 204 as the plurality of independent channel regions 102. However, channel region 204 may have a lateral width W NRP that is wider or narrower than W NR. The width of channel region 204 may affect the drive current of PMOS transistor 202. In an exemplary embodiment, channel regions 204 and 102 comprise single crystal silicon, SiGe, or Ge.

[0062] Channel region 204 extends longitudinally along the y-axis shown in FIG2B . In the illustrative embodiment, PMOS transistor 202 further includes a source region 206 coupled to a first longitudinal end of channel region 204, and a drain region 208 coupled to a second longitudinal end of channel region 204. Gate electrode 201 is located between source region 206 and drain region 208. The gate lengths LG of gate electrodes 108 and 201 can be substantially the same, as shown, or different. As indicated by dashed lines 212A and 212B, source and drain regions 206 and 208, respectively, can comprise doped epitaxially grown source and drain structures.

[0063] As further shown in FIG2A , sidewall 102A is laterally spaced from sidewall 204A by a distance S NP , which can be defined by the design. However, the location of boundary 113 may not be so fixed and can be used to adjust NMOS VT. In the illustrative embodiment, S NP is equal to the combined sum of TL1, TL2, TL3, the lateral thickness TL4 of gate electrode 201, and the thicknesses of gate dielectric layers 210 and 114. TL4 is measured from gate dielectric layer 210 on sidewall 204A. For a given S NP and minimum thicknesses of TL1 and TL4, WF material wall boundary 113 can be moved in the x-direction to achieve a desired ratio TL2:TL1 to adjust NMOS VT. In exemplary embodiments, the desired ratio TL2:TL1 is less than 3, and in some embodiments, is preferably between 0.1 and 2.5. In embodiments requiring a larger NMOS VT, boundary 113 is closer to gate dielectric layer 210 adjacent to sidewall 204A than in structures requiring a smaller NMOS VT. SNP and TL4 should be large enough to facilitate the full range of NMOS VT values ​​required for a particular circuit.

[0064] In certain exemplary embodiments, the gate dielectric layer 210 comprises a material that is the same as or substantially the same as the material of the gate dielectric layer 114. In some such embodiments, the gate dielectric layer 210 has a thickness that is the same as or substantially the same as the thickness of the gate dielectric layer 114. In other embodiments, the gate dielectric layer 210 is different from the gate dielectric layer 114. The gate dielectric layer 210 may, for example, comprise two or more layers, one of which is a high-K material and the other of which comprises SiO2.

[0065] In some exemplary embodiments, the gate electrode 201 is a WF material for the PMOS transistor 202 and has the same chemical composition as the WF layer 112. However, the gate electrode 201 and the WF layer 112 may have different compositions and / or include different materials.

[0066] Figure 2C is a plan view of a 6-transistor (6T) SRAM cell, illustrating NMOS VT tuning achieved through (a) a gate-end cap layout and (b) an N-type P-well boundary layout. Various NMOS and PMOS transistors are shown. Figure 2D is a cross-sectional view of NMOS transistor 220 in Figure 2C . NMOS transistor 220 has some or all of the features of NMOS transistor 100B (described in conjunction with Figure 1C ). Figure 2E is a cross-sectional view of NMOS transistor 100B in Figure 2C .

[0067] NMOS transistor 100A has some or all of the features of NMOS transistor 100A, as described with reference to FIG1A . As shown in FIG2C , end cap dielectric 116 facilitates a shorter spacing S CW between gate end cap 116 and gate dielectric layer 114 on sidewall 102B of channel region 102, compared to spacing S CW3 between gate end cap 116 and gate dielectric layer 114 on sidewall 102A of channel region 102 in NMOS transistor 220. For a given WF material composition, a smaller spacing S CW provides a lower NMOS VT, while a larger spacing S CW3 provides a higher NMOS VT. Also as shown, CMOS boundary 113 is moved away from NMOS transistor 220 (indicated by arrow 222) to increase spacing S CW4 and improve NMOS VT. In one embodiment, a single threshold voltage tuning mask can be implemented to improve NMOS VT in transistor 220 while simultaneously reducing NMOS VT in transistor 100A. Thus, FIG. 2C is an example where a single VT mask can set the distance between the wall and the device edge, fine-tuning the NMOS VT to provide a pass gate with a tighter gate cap and lower NMOS VT, while the pull-down transistor has a larger gate cap with the CMOS boundary 113 moved away from the transistor to increase the NMOS VT.

[0068] FIG3 illustrates a method 300 for fabricating a transistor such as those described above, according to some embodiments of the present disclosure. Method 300 begins at operation 310, where a workpiece comprising a first plurality of nanowires adjacent to a second plurality of nanowires embedded in a dielectric is received. An opening in the dielectric extends orthogonally through a portion of the first and second pluralities of nanowires. Method 300 continues at operation 320, where a gate dielectric layer is deposited on the first and second sidewalls of the first and second pluralities of nanowires. Method 300 continues at operation 330, where a portion of the first plurality of nanowires within the opening is masked. Method 300 continues at operation 340, where a first electrode layer is deposited on the gate dielectric layer on the exposed sidewalls and on the sidewalls of the mask. Method 300 continues at operation 350, where a second electrode layer is deposited on the first electrode layer. The second electrode layer fills any space between the first electrode layer on the mask sidewalls and the exposed sidewalls of the channel region. Method 300 continues at operation 360, where the mask is removed. The method 300 concludes at operation 370 where a third electrode layer is deposited on the gate dielectric layer on the corresponding first sidewalls.

[0069] Figure 4A is a cross-sectional view of a material layer stack 400 suitable for fabricating a transistor device, according to some embodiments. As shown, material layer stack 400, comprising multiple bilayers, is positioned on substrate 405. In the illustrated embodiment, material layer stack 400 includes bilayer 401A and bilayer 401B on bilayer 401A. In the exemplary embodiment, bilayer 401A includes a sacrificial layer 402A and a channel layer 404A, which comprise single crystal silicon. Bilayer 401B includes a sacrificial layer 402B and a channel layer 404B, which comprise single crystal silicon. In the illustrated embodiment, bilayer 401B is covered by sacrificial layer 402C.

[0070] In one embodiment, sacrificial layers 402A, 402B, and 402C include silicon and germanium, such as Si1-xGeX, where X is between 0.3 and 0.35. In one embodiment, the sacrificial layers are doped to increase wet etch removal rates relative to silicon. In an exemplary embodiment, sacrificial layer 402A may be epitaxially grown on substrate 405 to conform to the crystal orientation of substrate 405. In one embodiment, substrate 405 includes silicon, wherein the silicon substrate has a top surface with a (001) crystal plane.

[0071] Layer 404A is formed on layer 402A, wherein layer 404A comprises the material of channel region 102. In one embodiment, the silicon is (001) silicon. In one embodiment, the process of growing the material in bilayer 401A is repeated until a desired number of silicon channel layers are formed within Si / SiGe superlattice stack 400.

[0072] The thickness of material layer stack 400 can be limited by the aspect ratio of the fin structure, for example, after patterning material layer stack 400. Given the total thickness of material layer stack 400, the individual thicknesses of sacrificial layers 402A, 402B, and 402C can be limited by the required minimum thickness of layers 404A and 404B. However, the thickness of sacrificial layers 402A, 402B, and 402C determines the spacing between channels to be formed in downstream processes. In one embodiment, sacrificial layer 402A is grown to a thickness between 10 nm and 15 nm. Depending on the embodiment, silicon layer 404A has a thickness between 5 nm and 15 nm.

[0073] In one embodiment, the material layer stack 400 is a Si / SiGe superlattice, wherein the superlattice material stack 400 is formed by a reduced pressure CVD process. It should be understood that the deposition process minimizes strain relaxation in the Si 1-xGe x, thereby enabling longitudinal strain in the subsequently formed transistor channel.

[0074] In the illustrative embodiment, bilayer 401B is formed on silicon layer 404A of bilayer 401A. Layer 402B in bilayer 401B is epitaxially formed on silicon layer 404A. The thickness of layer 402B may or may not be equal to the thickness of layer 402A. In an exemplary embodiment, silicon layers 404A and 404B are substantially identical, i.e., they both comprise the same material and have the same or substantially the same thickness, as shown in FIG4A. Material layer stack 400 also includes layer 402C formed on bilayer 401. While two bilayers 401A and 401B are shown, the number of bilayers can range from 2 to 10. FIG4B is a cross-sectional view of a block 406 formed through patterning material layer stack 400 (as shown in FIG4A). In one embodiment, prior to patterning, a mask is formed on topmost layer 402C that defines the shape and dimensions of block 406. In the illustrated embodiment, one block is shown, but in exemplary embodiments, multiple blocks are patterned simultaneously to form multiple nanoribbon channels. In one embodiment, a plasma etching process may be used to pattern and form block 406. The plasma etching defines the channel and etches a portion of substrate 405. The etching process stops after etching a desired amount of silicon. In exemplary embodiments, sidewalls 406A and 406B may be substantially vertical as shown. It should be understood that when sidewall profile 406A is substantially vertical, the lateral width of each subsequently formed channel layer can have substantially the same lateral dimension (defined by the space between sidewalls 406A and 406B).

[0075] After forming block 406, dielectric 408 is formed over block 406 and on its sidewalls. Dielectric 408 is then polished until the top surface of dielectric 408 is substantially coplanar with the top surface of the dielectric. In one embodiment, a chemical mechanical polishing (CMP) process is used to planarize the dielectric. As shown, dielectric 408 can then be recessed to a level at or below the uppermost surface 405A of substrate 405. In one embodiment, a wet etch process is used to recess dielectric 408.

[0076] FIG4C is an isometric view of a pseudo-gate structure 410 after the first portion of block 406 has been formed. In one embodiment, a pseudo-gate dielectric layer, such as silicon oxide or Al₂O₃, is blanket deposited over block 406 and over dielectric 408, and a sacrificial material is deposited over the pseudo-gate dielectric. In one embodiment, the pseudo-gate material includes a mask over the sacrificial material. For example, the mask, sacrificial material, and pseudo-gate material can be patterned into the pseudo-gate structure 410 using a plasma. In one exemplary embodiment, the plasma etch process is selective to the uppermost surface 408A of dielectric 408. In one embodiment, the pseudo-gate structure 410 has sidewalls 410A and 410B that are substantially perpendicular to the uppermost dielectric surface 408A. The pseudo-gate structure 410 has a lateral width, LG. LG defines the width of the transistor gate to be formed.

[0077] FIG4D is an isometric illustration of the structure in FIG4C after the formation of dielectric spacers 414 adjacent to dummy gate structure 410. In one embodiment, a dielectric spacer layer is blanket deposited over block 406, over dummy gate structure 410, and over sidewalls 410A and 410B. The deposition process used may include PECVD (plasma enhanced chemical vapor deposition), physical vapor deposition (PVD), or chemical vapor deposition (CVD). In one embodiment, the dielectric spacer layer comprises silicon and nitrogen and / or carbon.

[0078] In one embodiment, the dielectric spacer layer is planarized. The planarization process can expose the uppermost surface of the dummy gate structure 410. As shown, a mask 412 is formed over the dummy gate structure 410 and over a portion of the dielectric spacer layer. The dielectric spacer layer is etched to form dielectric spacers 414. A plasma etch can be used to pattern the dielectric spacers 414. An overetch of the dielectric spacer layer is performed to remove the dielectric spacer layer from the sidewall portions of the block 406 not covered by the mask.

[0079] In the illustrated embodiment, dielectric spacers 414 are formed on portions of the sidewalls of block 406 that are directly adjacent to dummy gate structure 410. As shown, both dummy gate structure 410 and dielectric spacers 414 cover portions of the sidewalls of block 406.

[0080] The dielectric spacer 414 can be formed to a thickness determined by downstream processing, electrical performance requirements (e.g., modulation of external resistance), or a combination thereof. In one embodiment, the dielectric spacer 414 has a lateral width between 5 nm and 10 nm.

[0081] FIG4E illustrates the structure of FIG4D after a process has been performed to remove the hard mask 412, the dummy gate structure 410, and the sacrificial layer exposed after removing the dummy gate structure 410 to form the channel region 102. In one embodiment, a dielectric 426 is deposited on the structure of FIG4D and planarized. A planarization process removes the hard mask 412. In one embodiment, where the dummy gate structure 410 comprises a dummy gate material such as polysilicon, silicon germanium, or germanium, a combination of plasma etching and wet chemical etching may be used to remove the dummy gate structure 410. Removing the dummy gate structure 410 does not affect the silicon layers 404A and 404B because a dummy gate dielectric is present beneath the dummy gate material (as described in conjunction with FIG4C ). As shown, removal of the dummy gate structure 410 forms an opening 427.

[0082] In one embodiment, sacrificial layers 402A, 402B, and 402C are removed using a wet chemical process ( FIG. 4B ). The wet etch chemistry selectively etches 402A, 402B, and 402C with respect to the dummy gate dielectric layer, dielectric spacer 418, and dielectric 426 on silicon layers 404A and 404B. After removing sacrificial layers 402A, 402B, and 402C, silicon layers 404A and 404B become suspended channel region 102. Dielectric spacer 418 remains adjacent to dielectric 426.

[0083] FIG5A is a cross-sectional view taken along line AA' through the structure in FIG4E . An additional pair of channel regions 204 is added to the cross-sectional view to illustrate the CMOS transistor structure pair. Channel regions 204 and 102 are separated by a distance SNP. SNP is set by design rules and represents the distance between the nearest sidewalls 102A and 204A of channel regions 204 and 102, respectively. In the illustrated embodiment, dielectric 408 is recessed below the uppermost surface 405A of substrate 405.

[0084] FIG5B is a cross-sectional view of the structure in FIG5A after forming a gate dielectric layer 500 on the channel regions 204 and 102 and the substrate 405. In one embodiment, the gate dielectric layer 500 is deposited using an ALD process. The ALD process facilitates coating the gate dielectric layer 500 on surfaces that are not within a vertical line of sight. As shown, the gate dielectric layer 500 can be blanket deposited on all exposed surfaces or protected from deposition on certain surfaces, such as the dielectric 408, through surface treatment. In the illustrative embodiment, the gate dielectric layer 500 is deposited to the same thickness on each of the channel regions 204 and 102 and, as shown, is substantially conformal to the outermost surface of the corresponding channel region 204 and 102.

[0085] 5C is a cross-sectional view of the structure in FIG 5B after a process of forming a mask 506 over a portion of the structure 504. The mask 506 exposes the NMOS region 508A and protects the PMOS region 508B.

[0086] In an illustrative embodiment, mask 506 can be formed by depositing a flowable material that is easily patterned. Examples of mask materials include compounds of silicon and one or more of oxygen, nitrogen, or carbon. After deposition, the mask material is patterned to form mask 506 having sidewalls 506A. The positioning of sidewalls 506A relative to the sidewall surface 102A of each channel region 102 and the planned thickness of the NMOS work function material can help achieve a desired NMOS VT. In one embodiment, mask 506 has a predetermined lateral width WM that is aligned with PN well boundary 508. Boundary 508 is defined in the substrate prior to patterning stack 400 ( FIG. 4A ). In various embodiments, sidewalls 506A of mask 506 are positioned along a point in the x-direction that provides a specific thickness ratio between the dual work function layers to be deposited adjacent to channel region 102. In the illustrative embodiment, mask sidewall 506A is positioned a distance T L4 from the gate dielectric layer 500 adjacent to sidewall 204A, resulting in an offset of the mask in the negative x-direction. Since S NP is fixed, the negative offset in mask 506 increases the spacing between sidewall 506A and the gate dielectric layer 500 on sidewall 102A. This offset provides more lateral space for work function material deposition and can promote an increase in NMOS VT. The amount of lateral offset of mask 506 in either the positive or negative direction can advantageously improve NMOS VT from a baseline level determined by implementing a single N-type work function electrode.

[0087] FIG5D is a cross-sectional view of the structure in FIG5C after forming a WF layer 110 to set the baseline NMOS VT. In one embodiment, the WF layer 110 is deposited using an ALD process. The WF layer 110 is substantially conformally formed on the portions of the gate dielectric layer 500 located on the corresponding sidewalls 102A and 102B. The ALD process can also advantageously fill the vertical spacing between each consecutive channel region 102. In an exemplary embodiment, the WF layer 110 is deposited on the gate dielectric layer 500 to a thickness of TL1. In an exemplary embodiment, the WF layer 110 is also conformally deposited on the sidewalls 506A and the top surface 506B of the mask 506 to a thickness of TL1. In some embodiments, the portion of the WF layer 110 on the sidewall 506A has a thickness different from TL1. The spacing between the WF layer 110 on the sidewall 506A and the gate dielectric layer 500 on the sidewall 102A is designed to produce a certain ratio between the second work function layer to be deposited. In the illustrative embodiment, the WF layer 110 is also deposited on the dielectric 408 .

[0088] FIG5E is a cross-sectional view of the structure in FIG5D after depositing a sacrificial material 510 on the WF layer 110 and performing a planarization process. In one embodiment, the sacrificial material comprises the same or substantially the same material as the mask 506. In some embodiments, the sacrificial material comprises polysilicon, which facilitates removal via wet chemical methods and plasma etching processes. A planarization process is performed to remove the sacrificial material from above the WF layer 110 above the mask 506. The planarization process continues until the WF layer 110 above the mask is removed and the uppermost surface 506B is exposed. In one embodiment, a chemical mechanical polishing (CMP) process is used for planarization.

[0089] FIG5F is a cross-sectional view of the structure of FIG5E after removal of mask 506, sacrificial material 510, and deposition of WF layer 512. Mask 506 and sacrificial material 510 can be removed simultaneously, selectively to, for example, WF layer 110 and gate dielectric layer 114, by wet chemical etching or plasma etching. In other embodiments, mask 506 and sacrificial material 510 are each removed sequentially by separate processes.

[0090] WF layer 512 is deposited in both PMOS region 508B and NMOS region 508A and planarized to remain only in PMOS region 508A. In the illustrative embodiment, the single material of WF layer 512 sets the work function of the PMOS gate "transparent" WF layer 110 to modulate the NMOS V by an amount dependent on T L4 and / or SCW4. After deposition, the excess WF layer 512 is planarized and removed to form CMOS transistor 200.

[0091] In other embodiments, removing the sacrificial layers in the NMOS region 508A and the PMOS region 508B separately may facilitate the deposition of two materials with different work functions in the corresponding regions.

[0092] 6A is a cross-sectional view of the structure in FIG5E after the process of removing sacrificial material 510 from NMOS region 508A and depositing WF layer 112 on WF layer 110. WF layer 112 may then be planarized to provide a substantially planar uppermost surface of WF layer 112.

[0093] 6B is a cross-sectional view of the structure in FIG. 6A after a process of removing mask 506 from PMOS region 508B, depositing WF layer 512, and then a planarization process to fabricate CMOS transistor 520. In an embodiment, WF layer 512 comprises a material different from that of WF layer 112.

[0094] The device structure and fabrication method can be applied to various integrated circuits. FIG7A illustrates a cross-sectional view of a memory cell 700, which includes a transistor 100A, such as described elsewhere herein, and a memory structure 701 coupled to a contact of transistor 100A. In the illustrated embodiment, memory structure 701 is coupled to the drain contact of transistor 100A. In other embodiments, memory cell 700 further includes multiple memory structures, such as memory structures 701 coupled to transistors 202 and 100A, respectively.

[0095] FIG7B is a cross-sectional view of a memory structure 701 taken along line AA' in the structure of FIG7A according to an embodiment of the present disclosure. As shown, memory structure 701 includes a non-volatile memory element 702 between a drain contact 703 and an interconnect 704. In other embodiments, one or more layers of interconnect exist between drain contact 703 and volatile memory element 702. In the illustrated embodiment, drain contact 703 contacts epitaxial drain structure 212B.

[0096] Non-volatile memory element 702 may include a magnetic tunneling junction (MTJ) device, a conductive bridge random access memory (CBRAM) device, or a resistive random access memory (RRAM) device. Non-volatile memory elements such as MTJ devices require a nominal critical switching current to switch magnetization, which depends on the area of ​​the MTJ device. As MTJ dimensions shrink, the critical switching current required to switch the memory state of the MTJ device also scales with the device area, but shrinking MTJ dimensions presents numerous challenges. If a transistor connected to the MTJ device can provide an amount of current exceeding the critical switching current requirement of the MTJ device, the feature scaling of the MTJ device can be relaxed. In one embodiment, a non-planar transistor such as NMOS transistor 100A, which can provide current boosting (via an appropriate target VT), can be advantageously coupled to non-volatile memory element 702 such as an MTJ device to overcome the critical switching current requirement.

[0097] 7C illustrates a cross-sectional view of an example non-volatile memory element 702 including a magnetic tunneling junction (MTJ) material device. In the illustrated embodiment, the MTJ device includes a bottom electrode 705, a fixed magnet 706 above the bottom electrode 705, a tunnel barrier 708 above the fixed magnet 706, a free magnet 710 above the tunnel barrier 708, and a top electrode 712 above the free magnet 710. In one embodiment, a dielectric spacer laterally surrounds (not shown) the non-volatile memory element 702.

[0098] In one embodiment, the fixed magnet 706 comprises a material having a thickness sufficient to maintain fixed magnetization. For example, the fixed magnet 706 may comprise an alloy such as CoFe and CoFeB. In one embodiment, the fixed magnet 706 comprises Co100-x-yFexBy, where X and Y each represent atomic percentages, such that X is between 50 and 80, Y is between 10 and 40, and the sum of X and Y is less than 100. In one embodiment, X is 60 and Y is 20. In one embodiment, the fixed magnet 706 is FeB, where the boron concentration is between 10 and 40 atomic percent of the total composition of the FeB alloy. In one embodiment, the fixed magnet 706 has a thickness between 1 nm and 2.5 nm.

[0099] In one embodiment, the tunnel barrier 708 is composed of a material suitable for allowing electrons with majority spin to flow through the tunnel barrier 708 while at least to some extent preventing electrons with minority spin from flowing through the tunnel barrier 708. Therefore, the tunnel barrier 708 (or spin filter layer) can also be referred to as a tunnel layer for electron flow of a specific spin orientation. In one embodiment, the tunnel barrier 708 includes a material such as, but not limited to, magnesium oxide (MgO) or aluminum oxide (Al2O7). In one embodiment, the tunnel barrier 708 including MgO has a crystal orientation of (001) and is lattice matched to the free magnet 710 below the tunnel barrier 708 and the fixed magnet 706 above the tunnel barrier 708. In one embodiment, the tunnel barrier 708 is MgO and has a thickness between 1 nm and 2 nm.

[0100] In one embodiment, the free magnet 710 comprises a magnetic material such as Co, Ni, Fe, or alloys thereof. In one embodiment, the free magnet 710 comprises a magnetic material such as FeB, CoFe, and CoFeB. In one embodiment, the free magnet 710 comprises Co 100-x-yFe xB y, where X and Y each represent atomic percentages, such that X is between 50 and 80 and Y is between 10 and 40, and the sum of X and Y is less than 100. In one embodiment, X is 60 and Y is 20. In one embodiment, the free magnet 710 is FeB, where the boron concentration is between 10 and 40 atomic percent of the total composition of the FeB alloy. In one embodiment, the free magnet 710 has a thickness between 1 nm and 2.0 nm.

[0101] In one embodiment, the bottom electrode 705 comprises an amorphous conductive layer. In one embodiment, the bottom electrode 705 is a smooth-surfaced electrode. In one embodiment, the bottom electrode 705 comprises a material such as W, Ta, TaN, or TiN. In one embodiment, the bottom electrode 705 is composed of Ru layers interleaved with Ta layers. In one embodiment, the bottom electrode 705 has a thickness between 20 nm and 50 nm. In one embodiment, the top electrode 712 comprises a material such as W, Ta, TaN, or TiN. In one embodiment, the top electrode 712 has a thickness between 30 nm and 70 nm. In one embodiment, the bottom electrode 705 and the top electrode 712 are the same metal, such as Ta or TiN. In one embodiment, the MTJ device has a combined total thickness of the individual layers between 60 nm and 100 nm and a width between 10 nm and 50 nm.

[0102] Referring again to FIG. 7B , in one embodiment, non-volatile memory element 702 is a resistive random access memory (RRAM) device operating according to the filamentary conduction principle. When the RRAM device experiences an initial breakdown voltage, a filament forms in a layer known as the switching layer. The size of the filament depends on the breakdown voltage, and at higher currents, reliable switching between different resistance states in a filamentary RRAM device can be greatly enhanced. In one embodiment, a transistor 100A that can provide additional current boost (by increasing the drive current) can be advantageously coupled to the RRAM device to provide reliable switching operation.

[0103] FIG7D illustrates a cross-sectional view of an exemplary nonvolatile memory element 702 comprising a resistive random access memory (RRAM) device. In the illustrated embodiment, the RRAM material stack includes a bottom electrode 714, a switching layer 716 above the bottom electrode 714, an oxygen exchange layer 718 above the switching layer 716, and a top electrode 720 on the oxygen exchange layer 718.

[0104] In one embodiment, bottom electrode 714 comprises an amorphous conductive layer. In one embodiment, bottom electrode 714 is a smooth electrode. In one embodiment, bottom electrode 714 comprises a material such as W, Ta, TaN, or TiN. In one embodiment, bottom electrode 714 is composed of Ru layers interleaved with Ta layers. In one embodiment, bottom electrode 714 has a thickness between 20 nm and 50 nm. In one embodiment, top electrode 720 comprises a material such as W, Ta, TaN, or TiN. In one embodiment, top electrode 720 has a thickness between 70 nm and 70 nm. In one embodiment, bottom electrode 714 and top electrode 720 are the same metal, such as Ta or TiN.

[0105] The switching layer 716 can be a metal oxide, for example, including oxygen and atoms of one or more metals, such as, but not limited to, Hf, Zr, Ti, Ta, or W. In the case of titanium or hafnium, or tantalum in an oxidation state of +4, the switching layer 716 has a chemical composition of MO X, where O is oxygen and X is or is substantially close to 2. In the case of tantalum in an oxidation state of +5, the switching layer 716 has a chemical composition of M 2 O X, where O is oxygen and X is or is substantially close to 5. In one embodiment, the switching layer 716 has a thickness between 1 nm and 5 nm.

[0106] Oxygen exchange layer 718 serves as a source of oxygen vacancies or as a sink for O 2-. In one embodiment, oxygen exchange layer 718 is composed of a metal such as, but not limited to, hafnium, tantalum, or titanium. In one embodiment, the thickness of oxygen exchange layer 718 is between 5 nm and 20 nm. In one embodiment, the thickness of oxygen exchange layer 718 is at least twice the thickness of switching layer 716. In another embodiment, the thickness of oxygen exchange layer 718 is at least twice the thickness of switching layer 716. In one embodiment, the total thickness of a single layer of the RRAM device is between 60 nm and 100 nm, and the width is between 10 nm and 50 nm.

[0107] 7B , drain contact 703 is embedded in dielectric 437. Dielectric 724 is on dielectric 437. In the illustrated embodiment, drain interconnect 704 and non-volatile memory element 702 are embedded in dielectric 724.

[0108] In one embodiment, drain contact 703 and drain interconnect 704 include a liner layer comprising ruthenium or tantalum and a fill metal such as copper or tungsten. In one embodiment, dielectric 724 includes silicon and one or more of nitrogen, oxygen, and carbon, such as silicon nitride, silicon dioxide, carbon-doped silicon nitride, silicon oxynitride, or silicon carbide.

[0109] FIG8 illustrates a computing device 800 according to an embodiment of the present disclosure. As shown, computing device 800 houses a motherboard 802. Motherboard 802 may include multiple components, including, but not limited to, a processor 801 and at least one communication chip 804 or 805. Processor 801 is physically and electrically coupled to motherboard 802. In some embodiments, communication chip 805 is also physically and electrically coupled to motherboard 802. In further embodiments, communication chip 805 is part of processor 801.

[0110] Depending on its application, the computing device 800 may include other components that may or may not be physically and electrically coupled to the motherboard 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset 806, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and mass storage devices (e.g., a hard drive, a compact disc (CD), a digital versatile disk (DVD), etc.).

[0111] Communications chip 805 implements wireless communications for transferring data to and from computing device 800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that use modulated electromagnetic radiation to transfer data over non-solid media. This term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. Communications chip 805 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 801.11 family), WiMAX (IEEE 801.11 family), Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocols designated as 3G, 4G, 8G, and beyond. Computing device 800 may include multiple communications chips 804 and 805. For example, the first communication chip 805 can be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, while the second communication chip 804 can be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, and Ev-DO.

[0112] Processor 801 of computing device 800 includes an integrated circuit die packaged within processor 801. In some embodiments, the integrated circuit die of processor 801 includes a non-volatile memory device, one or more device structures including transistors, such as transistors 100A, 100B, or 200 as described in connection with FIG. 1A , 1B, or 2A-B , respectively. Referring again to FIG. 8 , the term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory.

[0113] Communication die 805 also includes an integrated circuit die packaged within communication die 805. In another embodiment, the integrated circuit dies of communication die 804 and 805 include one or more interconnect structures, non-volatile memory devices, and capacitors. Depending on its application, computing device 800 may include other components that may or may not be physically and electrically coupled to motherboard 802. These other components may include, but are not limited to, volatile memory (e.g., DRAM) 807, 808, non-volatile memory (e.g., ROM) 810, a graphics CPU 812, flash memory, a global positioning system (GPS) device 813, a compass 814, a chipset 806, an antenna 816, a power amplifier 809, a touch screen controller 811, a touch screen display 817, a speaker 815, a camera 803, and a battery 818, as shown, as well as other components such as a digital signal processor, an encryption processor, an audio codec, a video codec, an accelerometer, a gyroscope, and mass storage devices (e.g., a hard drive, a solid-state drive (SSD), a compact disc (CD), a digital versatile disk (DVD), etc.). In further embodiments, any of the components housed within the computing device 800 and discussed above may comprise a separate integrated circuit memory die that includes one or more arrays of non-volatile memory devices.

[0114] In various embodiments, computing device 800 may be a laptop, a networked mini-notebook, a notebook computer, an ultra-thin notebook computer, a smartphone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further embodiments, computing device 800 may be any other electronic device that processes data.

[0115] FIG9 illustrates an integrated circuit (IC) structure 900 incorporating one or more embodiments of the present disclosure. IC structure 900 is an intermediate substrate used to bridge a first substrate 902 to a second substrate 904. For example, first substrate 902 may be an IC die. Second substrate 904 may be, for example, a memory module, a computer motherboard, or another IC die. Typically, the purpose of IC structure 900 is to extend connections to a wider pitch or to reroute connections to different connections. For example, IC structure 900 may couple an IC die to a ball grid array (BGA) 907, which may then be coupled to a second substrate 904. In some embodiments, first substrate 902 and second substrate 904 are attached to opposite sides of IC structure 900. In other embodiments, first substrate 902 and second substrate 904 are attached to the same side of IC structure 900. And in further embodiments, three or more substrates are interconnected through an integrated circuit (IC) structure 900.

[0116] The integrated circuit (IC) structure 900 can be formed from epoxy, glass-reinforced epoxy, ceramic materials, or polymer materials such as polyimide. In further embodiments, the IC structure can be formed from alternative rigid or flexible materials, which can include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0117] The IC structure 900 may include metal interconnects 908 and vias 910, including, but not limited to, through-silicon vias (TSVs) 912. The IC structure 900 may also include embedded devices 914, including both passive and active devices. Such embedded devices 914 include capacitors, resistors, inductors, fuses, diodes, transformers, and device structures including transistors, such as transistors 100A, 100B, or 200 described in connection with FIG. 1A , 1B, or 2A-B , respectively. Referring again to FIG. 9 , the IC structure 900 may also include embedded devices, such as one or more resistive random access devices, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, such as decoupling capacitors (as described in connection with FIG. 1A , 1B, and 2A-C ), antennas, arrays, sensors, and MEMS devices, may also be formed on the IC structure 900.

[0118] This document describes the layout of NMOS boundary walls in single MOS and CMOS architectures. In the above description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of certain embodiments. However, it will be apparent to those skilled in the art that certain embodiments can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form to avoid obscuring the description.

[0119] Besides what is described herein, various modifications may be made to the disclosed embodiments and their implementation without departing from their scope, as demonstrated by the following examples.

[0120] Example 1: A device structure includes a plurality of strip-shaped channels, wherein each strip-shaped channel includes a corresponding first sidewall and a corresponding second sidewall opposite the first sidewall, wherein the plurality of strip-shaped channels are arranged in a stack and extend in a longitudinal direction. The device structure also includes a source electrode at a first longitudinal end of the plurality of strip-shaped channels and a drain electrode at a second longitudinal end of the plurality of strip-shaped channels, and a gate electrode between the source electrode and the drain electrode. The gate electrode includes: a first layer including a first portion adjacent to the corresponding first sidewall, a second layer directly adjacent to the first layer, and a second portion of the first layer adjacent to the second layer, wherein the first portion of the first layer includes a first work function material and a first lateral thickness of a gate dielectric layer between the first layer and the corresponding first sidewall, wherein the second layer includes a second work function material and a second lateral thickness, wherein the second portion of the first layer includes a third lateral thickness, and wherein a ratio of the second lateral thickness to the first lateral thickness is less than three.

[0121] Example 2: The device structure of Example 1, wherein the second portion is adjacent to a dielectric that is a first distance away from the gate dielectric layer adjacent to the corresponding first sidewall.

[0122] Example 3: The device structure of any of Examples 1 to 2, wherein the third lateral thickness is substantially equal to the first lateral thickness, and wherein the first lateral thickness and the second lateral thickness each have a minimum value of 2 nm.

[0123] Example 4: The device structure of any one of Examples 1 to 3, wherein the first layer includes a third portion below the second layer, wherein the third portion is adjacent to the first portion and the second portion.

[0124] Example 5: The device structure of any one of Examples 1 to 4, wherein the plurality of stripe channels is a first plurality of stripe channels of a first transistor, wherein the source is a first source, wherein the drain is a first drain, wherein the gate dielectric layer is a first gate dielectric layer, wherein the gate electrode is a first gate electrode, and wherein the second portion of the first layer is directly adjacent to a second gate electrode of a second transistor. The second transistor includes a second plurality of stripe channels, each second stripe channel including a corresponding first sidewall and a corresponding second sidewall opposite the first sidewall, wherein the plurality of stripe channels are stacked and extend along a longitudinal direction. The second transistor further includes: a second source at a first longitudinal end of the second plurality of stripe channels; and a second drain at a second longitudinal end of the second plurality of stripe channels, wherein the second gate electrode is located between the second source and the second drain and surrounds each of the second plurality of stripe channels, wherein the second gate electrode includes a third work function material, and the second gate dielectric layer is located between the second gate electrode and the second plurality of stripe channels.

[0125] Example 6: The device structure of any one of Examples 1 to 5, wherein the corresponding first sidewalls of the first plurality of strip-shaped channels are proximal to the corresponding first sidewalls of the second plurality of strip-shaped channels, and wherein the corresponding first sidewalls of the first plurality of strip-shaped channels and the corresponding first sidewalls of the second plurality of strip-shaped channels are laterally separated by a distance, and wherein the second gate electrode includes a fourth lateral thickness that is equal to the difference between the distance minus the combined sum of the first thickness, the second thickness, the third thickness, the thickness of the first gate dielectric layer, and the thickness of the second gate dielectric layer.

[0126] Example 7: The device structure of any one of Examples 1 to 6, wherein the ratio is greater than 0 and less than 2.5.

[0127] Example 8: The device structure of any one of Examples 1 to 7, wherein the first gate dielectric layer and the second gate dielectric layer comprise the same material, and the third work function material is the same as the second work function material.

[0128] Example 9: A device structure according to any one of Examples 1 to 8, wherein the first layer further surrounds each of the plurality of strip-shaped channels, wherein the first layer also includes a third portion adjacent to the corresponding second sidewall, wherein the third portion includes a first lateral thickness, wherein the second layer adjacent to the first portion is the first portion of the second layer, and the second layer also includes a second portion adjacent to the third portion of the first layer, the second portion of the second layer includes a fourth lateral thickness, and wherein a ratio of the fourth lateral thickness to the first lateral thickness is greater than a ratio of the second lateral thickness to the first lateral thickness.

[0129] Example 10: The device structure of any one of Examples 1 to 9, wherein the plurality of strip-shaped channels are a first plurality of strip-shaped channels of a first transistor, wherein the source is a first source, wherein the drain is a first drain, wherein the gate dielectric layer is a first gate dielectric layer, wherein the gate electrode is a first gate electrode, and the device structure of claim 1 further comprises a second transistor. The second transistor comprises a third plurality of strip-shaped channels, each third strip-shaped channel comprising a corresponding first sidewall and a corresponding second sidewall opposite the first sidewall, and wherein the plurality of strip-shaped channels are stacked and extend in a longitudinal direction. A third source is located at a first longitudinal end of the plurality of strip-shaped channels, and a third drain is located at a second longitudinal end of the plurality of strip-shaped channels. A third gate electrode is located between the third source and the third drain, wherein the third gate electrode comprises: a third layer comprising a first portion adjacent to the corresponding first sidewall; and a fourth layer directly adjacent to the third layer. The third gate electrode further includes a second portion of the third layer adjacent to the second layer, wherein the first portion of the third layer includes a first work function material and a first lateral thickness starting from each first sidewall, wherein the fourth layer includes a second work function material and a fourth lateral thickness, wherein the second portion of the third layer includes a third lateral thickness and wherein a ratio of the fourth lateral thickness to the first lateral thickness is less than a ratio of the third lateral thickness to the first lateral thickness. The second transistor further includes a third gate dielectric layer including the material of the first gate dielectric layer, the third gate dielectric layer being between the third gate electrode and the third plurality of strip-shaped channels.

[0130] Example 11: The device structure of Example 10, wherein a threshold voltage of the third transistor is at least 30% higher than a threshold voltage of the first transistor.

[0131] Example 12: The device structure of any one of Examples 1 to 11, wherein the first layer includes hafnium, zirconium, titanium, tantalum, or aluminum, an alloy of hafnium, zirconium, titanium, tantalum, or aluminum, and carbides of hafnium, zirconium, titanium, tantalum, or aluminum, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide, and nitrides such as tantalum nitride and titanium nitride, and the second layer includes ruthenium, palladium, platinum, cobalt, or nickel, or tungsten, molybdenum, ruthenium, and nitrides or carbides of tungsten, ruthenium, or molybdenum.

[0132] Example 13: A device structure according to any one of Examples 1 to 11, wherein the vertical spacing between the lowermost surface of a first strip channel among the multiple strip channels and the uppermost surface of a second strip channel among the multiple strip channels is at most twice the first lateral thickness, wherein the second strip channel is located directly above the first strip channel.

[0133] Example 14: A method for fabricating a device structure, the method comprising receiving a workpiece comprising a first plurality of strip-shaped channels adjacent to a second plurality of strip-shaped channels embedded in a dielectric, wherein the first plurality of strip-shaped channels and the second plurality of strip-shaped channels extend in a longitudinal direction, wherein each of the first plurality of strip-shaped channels comprises a corresponding first sidewall, and wherein each of the second plurality of strip-shaped channels comprises a corresponding second sidewall, wherein an opening in the dielectric extends orthogonally across the longitudinal direction and exposes a portion of the first plurality of strip-shaped channels and the second plurality of strip-shaped channels and the first and second sidewalls. The method further comprises depositing a gate dielectric layer on the corresponding first sidewall and the corresponding second sidewall, and masking the portion of the first plurality of strip-shaped channels in the opening by forming a mask over the first plurality of strip-shaped channels, wherein the mask comprises a sidewall, and wherein the sidewall is spaced a distance from the corresponding second sidewall. The method further includes depositing a first electrode layer on the gate dielectric layer on the corresponding second sidewall and on the sidewall of the mask, depositing a second electrode layer on the first electrode layer and filling a space between the first electrode layer on the sidewall of the mask and the corresponding second sidewall, removing the mask, and forming a second gate electrode. Forming the gate electrode includes depositing a third electrode layer on the gate dielectric layer adjacent to the corresponding first sidewall.

[0134] Example 15: The method of any of Example 14, wherein forming the mask further comprises placing the sidewalls at a first distance from corresponding second sidewalls of the second plurality of fins, such that a lateral thickness of the second electrode layer is less than about 3 of a lateral thickness of the second electrode layer compared to a lateral thickness of the first electrode layer.

[0135] Example 16: The method of any of Example 15, wherein the distance is between 6 nm and 30 nm.

[0136] Example 17: The method of any of Example 16, wherein removing the mask includes removing the mask before forming the second electrode layer, and wherein forming the second electrode layer and the third electrode layer includes depositing the same material.

[0137] Example 18: The method of any of Example 17, wherein forming the second electrode layer and the third electrode layer comprises depositing the same material during a single deposition.

[0138] Example 19: A system includes a battery, an antenna, and a processor coupled to the antenna, wherein the processor includes a device structure. The device structure includes a plurality of strip-shaped channels, wherein each strip-shaped channel includes a corresponding first sidewall and a corresponding second sidewall opposite the first sidewall, wherein the plurality of strip-shaped channels are arranged in a stack and extend in a longitudinal direction. The device structure also includes: a source electrode at a first longitudinal end of the plurality of strip-shaped channels, a drain electrode at a second longitudinal end of the plurality of strip-shaped channels, and a gate electrode between the source electrode and the drain electrode. The gate electrode includes: a first layer including a first portion adjacent to the corresponding first sidewall, a second layer directly adjacent to the first layer, and a second portion of the first layer adjacent to the second layer, wherein the first portion of the first layer includes a first work function material and a first lateral thickness of a gate dielectric layer between the first layer and the corresponding first sidewall, wherein the second layer includes a second work function material and a second lateral thickness, wherein the second portion of the first layer includes a third lateral thickness, and wherein a ratio of the second lateral thickness to the first lateral thickness is less than three.

[0139] Example 20: The system of Example 19, wherein the third lateral thickness is substantially equal to the first lateral thickness and wherein the first lateral thickness and the second lateral thickness have a minimum value of 2 nm and wherein the ratio is between 0.1 and 2.5.

[0140] 101: Base region 102: Channel Area 104: Source region 106: Drain area 108: Gate electrode 110:WF layer 112:WF layer 113: Boundary 113: Wall Boundary 114: Gate dielectric layer 116: Dielectric 119: Boundary 120: Dielectric 201: Gate electrode 202:PMOS transistor 204: Channel Area 206: Source region 208: Drain area 210: Gate dielectric layer 400: Material layer stacking 405:Substrate 406: Block 408: Dielectric 410: Pseudo-gate structure 412: Mask 414: Dielectric spacer 426: Dielectric 427: Open 500: Gate dielectric layer 504:Structure 506:Mask 508: Boundary 510: Sacrificial material 512:WF layer 520:CMOS transistor 700: memory unit 701:Memory structure 702: Non-volatile memory device 703: Drain contact 704: Interconnection 705: bottom electrode 706:Fixed magnet 708: tunnel barrier 710: Free magnet 712: Top electrode 714: bottom electrode 716: Switch layer 718: oxygen exchange layer 720: Top electrode 724: Dielectric 800: computing device 801: Processor 802: Motherboard 803: Camera 804: Communication chip 805: Communication chip 806: Chipset 807: Volatile memory 808: Volatile memory 809: Power Amplifier 810: Non-volatile memory 811: Touch screen controller 812: Graphics CPU 813:GPS device 814: Compass 815: Speaker 816: Antenna 817: Touch screen display 818:Battery 900: Integrated circuit structure 902: first substrate 904: Second substrate 907:Ball Grid Array 908:Metal Interconnect 910:Through hole 912:Through silicon via 914:Embedded device 100A: Device structure 100A:NMOS transistor 102A: Side wall 102B: Sidewall 102C:Top surface 102D:lower surface 110A:WF layer part 110B:WF layer 110C:WF layer part 110D:WF layer 110E:WF layer part 112A:WF layer part 118A: Semiconductor Materials 118B: Semiconductor Materials 204A: Side wall 204B: Sidewall 401A:Double layer 401B:Double layer 402A: Sacrificial layer 402B: Sacrificial layer 402C: Sacrificial layer 404A: Channel layer 404B: Channel layer 405A:Top surface 406A: Sidewall 406B: Sidewall 408A:Top surface 506A: Side wall 506B:Top surface 508A: NMOS region 508B: PMOS area LG: Gate length S CW:Distance S CW2:Distance S CW3: Spacing S NP: distance S NW: Spacing SV: Vertical Separation T L1: thickness T L2: thickness T L2A: Transverse thickness T L3: thickness T L4: Transverse thickness VT: threshold voltage WM: horizontal width W NR: Width W NRP: Horizontal width

Claims

1. A device structure, comprising: A plurality of channel regions are located on a stack of first transistors, each of the channel regions including a first sidewall and a second sidewall opposite to the first sidewall; A source region and a drain region are coupled to opposite ends of the first plurality of channel regions; a gate electrode is located between the source region and the drain region, the gate electrode comprising: a first layer comprising a first portion adjacent to the first sidewall and a second portion adjacent to a boundary sidewall spaced apart from the first sidewall, wherein the boundary sidewall comprises a dielectric material and is spaced apart from a first gate dielectric layer adjacent to the first sidewall by a first distance; a second layer is directly adjacent to the first layer and occupies the space between the first and second portions of the first layer; wherein: the first layer has a first component associated with a first work function, wherein the first layer includes a third portion below the second layer, wherein the third portion is adjacent to the first and second portions; the first portion of the first layer has a first lateral thickness from the first sidewall; the second portion of the first layer is directly adjacent to a second gate electrode of a second transistor, the second transistor further comprising: a second gate dielectric layer; and a second plurality of channel regions located in the stack; the second layer has a second component associated with a second work function and has a second lateral thickness from the first sidewall; The ratio of the second lateral thickness to the first lateral thickness is less than three; the first sidewall of the first plurality of channel regions is laterally separated from the first sidewall of the second plurality of channel regions by a distance; and the second gate electrode has a fourth lateral thickness equal to the difference between the distance and the sum of the first lateral thickness, the second lateral thickness, the third lateral thickness of the second portion of the first layer, the lateral thickness of the first gate dielectric layer, and the lateral thickness of the second gate dielectric layer.

2. The device structure according to claim 1, wherein the third lateral thickness is substantially equal to the first lateral thickness, and wherein both the first lateral thickness and the second lateral thickness have a minimum value of 2 nm.

3. The device structure according to claim 1, wherein the second transistor comprises: The second source and the second drain are coupled to the ends of the second plurality of channel regions; The second gate electrode includes a third work function material.

4. The device structure according to claim 3, wherein the ratio of the second lateral thickness to the first lateral thickness is greater than 0 and less than 2.

5.

5. The device structure according to claim 3, wherein the first gate dielectric layer and the second gate dielectric layer comprise the same material, and the third work function material has the same composition as the second work function material.

6. The device structure according to claim 1, wherein the first layer surrounds each of the plurality of channel regions, wherein a second portion of the second layer is adjacent to a second sidewall of the channel region opposite to the first sidewall, and has a lateral thickness that is a multiple of the first lateral thickness that is greater than the ratio of the second lateral thickness to the first lateral thickness.

7. The device structure according to claim 3, wherein the device structure further includes a third transistor, the third transistor including a third gate electrode, the third gate electrode including: The third layer includes the first material associated with the first work function; The fourth layer is directly adjacent to the third layer and includes the second material associated with the second work function; wherein the third layer is adjacent to the first channel sidewall of the third transistor, and wherein the ratio of the lateral thickness of the fourth layer to the first lateral thickness is greater than the ratio of the lateral thickness of the third layer to the first lateral thickness.

8. The device structure according to claim 7, wherein the threshold voltage of the third transistor is at least 30% higher than the threshold voltage of the first transistor.

9. A computing device, comprising: Battery; antenna; and a processor coupled to the antenna, wherein the processor includes the device structure described in claim 1.

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