Two-phase clock generation circuit

Abstract

This invention provides a two-phase clock generation circuit that ensures a uniform gap between non-overlapping two-phase clocks, i.e., a uniform relationship between the rising and falling edges. The two-phase clock generation circuit 10 includes a non-overlapping signal generation circuit 2 on the logic high side and a four-terminal circuit 1a. The four-terminal circuit 1a includes: a first N-channel MOS transistor 11; a second N-channel MOS transistor 12, substantially adjacent to the first N-channel MOS transistor 11 with equal area, equal aspect ratio, and equal current direction; a first P-channel MOS transistor 13; a second P-channel MOS transistor 14, substantially adjacent to the first P-channel MOS transistor 13 with equal area, equal aspect ratio, and equal current direction; and two resistors 5a and 5b having substantially equal resistance values, wherein resistors 5a and 5b include conductor connections.

Description

Technical Field

[0001] This invention relates to a two-phase clock generation circuit. Prior Technology

[0002] There exists a system that requires the gap between non-overlapping two-phase clocks, i.e., the relationship between the rising edge and the falling edge, to be the same value. A technique is proposed to generate a complementary NRZ signal (two-phase clock) with less skew from a non-return-to-zero (NRZ) signal (see, for example, Patent Document 1 and Patent Document 2).

[0003] [Existing technical documents] [Patent Literature]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2014-127845 [Patent Document 2] Japanese Patent Application Publication No. 2010-128988 Summary of the Invention

[0005] [The problem that the invention aims to solve] However, the adjustment mechanism in Patent Document 1 requires complex logic circuitry and has a large installation scale. Furthermore, due to the presence of a delay circuit in the control loop, there are concerns about increased jitter.

[0006] The circuit structure of Patent Document 2 is not adjusted and is smaller in scale compared to Patent Document 1, but it inevitably produces a delay error corresponding to a section of the inverter circuit.

[0007] This invention provides a two-phase clock generation circuit that requires the gap between two non-overlapping clocks, i.e., the relationship between the rising edge and the falling edge, to be uniform. [Methods for solving problems]

[0008] The two-phase clock generation circuit of the present invention includes a non-overlapping signal generation circuit on the logic high side and a four-terminal circuit. The four-terminal circuit includes: a first N-channel metal-oxide-semiconductor (NMOS) transistor; a second NMOS transistor, substantially arranged adjacent to the first N-channel metal-oxide-semiconductor (MOS) transistor (hereinafter referred to as NMOS transistor) with equal area, equal aspect ratio, and equal current direction; and a first P-channel MOS transistor (hereinafter referred to as PMOS transistor). Transistor (P-channel metal-oxide-semiconductor transistor); a second PMOS transistor, substantially adjacent to the first PMOS transistor with equal area, aspect ratio, and current direction; a non-inverting input terminal; an inverting input terminal; a non-inverting output terminal; an inverting output terminal; and a first resistor and a second resistor having substantially equal resistance values, wherein the first resistor and the second resistor include conductor connections; the two output terminals of the non-overlapping signal generation circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the four-terminal circuit; the gate terminal of the first NMOS transistor is connected to the inverting input terminal; and the source terminal... The source terminal is connected to ground (GND), the drain terminal is connected to the drain terminal of the first PMOS transistor, the second resistor, and the non-inverting output terminal, the gate terminal of the second PMOS transistor is connected to the second resistor, the gate terminal of the second NMOS transistor is connected to the non-inverting input terminal, the source terminal is connected to GND, the drain terminal is connected to the drain terminal of the second PMOS transistor, the first resistor, and the inverting output terminal, the gate terminal of the first PMOS transistor is connected to the first resistor, and the source terminals of the first PMOS transistor and the second PMOS transistor are connected to the drain power supply voltage (Voltage Drain, VDD). [The effects of the invention]

[0009] According to the present invention, a two-phase clock generation circuit is provided that requires uniformity in the gap between non-overlapping two-phase clocks, i.e., the relationship between the rising edge and the falling edge. Simple Explanation of the Diagram

[0010] Figure 1 is an example of the structure of a two-phase clock generation circuit according to the first embodiment of the present invention. Figure 2 is a truth table of the four-terminal circuit according to the first embodiment of the present invention. Figure 3 is an example of a circuit diagram of a two-phase clock generation circuit according to the first embodiment of the present invention. Figure 4 is an example of a timing diagram of the rising event of the two-phase clock generation circuit according to the first embodiment of the present invention. Figure 5 is an example of a timing diagram of the two-phase clock generation circuit of the first embodiment of the present invention during the falling event. Figure 6 is another example of a four-terminal circuit in the non-overlapping signal generation circuit of the first embodiment of the present invention. Figure 7 is another example of a four-terminal circuit in the non-overlapping signal generation circuit of the first embodiment of the present invention. Figure 8 is an example of a circuit diagram of the delay circuit for all embodiments of the present invention. Figure 9 is an example of the structure of the four-terminal circuit of the two-phase clock generation circuit according to the second embodiment of the present invention. Figure 10 is the truth table of the four-terminal circuit of Figure 9 according to the second embodiment of the present invention. Figure 11 is an example of the structure of a four-terminal circuit in a two-phase clock generation circuit according to the third embodiment of the present invention. Figure 12 is a circuit diagram of a MOS transistor that can achieve inverse OR (Not OR, NOR) logic. Figure 13 is the truth table of the four-terminal circuit of Figure 11 according to the third embodiment of the present invention. Figure 14 is an example of a circuit diagram shown in the MOS transistor of the four-terminal circuit of Figure 11 according to the third embodiment of the present invention. Figure 15 is an example of the layout of Figure 14 according to the third embodiment of the present invention. Implementation

[0011] By using a two-phase clock generation circuit with the structure described below, a uniform two-phase clock with non-overlapping periods can be easily generated using a small-scale circuit. Furthermore, in the following description, the error in time uniformity from the change edge of one node to the change edge of the other node is referred to as skew or skew balance.

[0012] In recent years, even in consumer products using clock speeds in the tens of MHz range, there has been an increasing demand for analog systems that need to suppress skew within tens of picoseconds, but this invention should make it easy to achieve.

[0013] [First Implementation Method] The first embodiment of the present invention will be described with reference to the drawings. The two-phase clock generation circuit 10 in FIG1 is a two-phase clock generation circuit that achieves low skewness in the first embodiment of the present invention.

[0014] In Figure 1, the non-overlapping signal generation circuit 2 is as follows: the circuit converts the clock signal input to the input terminal In into a non-overlapping signal on the logic high side by changing the duty cycle, and outputs it to the positive input terminal In_1 and the negative input terminal In_0 of the next four-terminal circuit 1a. The output voltage of the positive and negative sets of the non-overlapping signal generation circuit 2 can be any output voltage as long as it meets the logic threshold voltage levels required for the normal operation of the next four-terminal circuit 1a.

[0015] The four-terminal circuit 1a is a circuit that obtains two-phase output from two-phase input. The four-terminal circuit 1a includes: voltage-to-current conversion elements, namely a first NMOS transistor 11 and a second NMOS transistor 12; a first PMOS transistor 13 and a second PMOS transistor 14 that realize latching operation through cross-coupling connection; a non-inverting input terminal In_1; an inverting input terminal In_0; a non-inverting output terminal Out_1; an inverting output terminal Out_0; a second resistor 5a; and a first resistor 5b.

[0016] The connection of the four-terminal circuit 1a is described below. The gate terminal of the first NMOS transistor 11 is connected to the inverting input terminal In_0, the source terminal is connected to GND, and the drain terminal is connected to the drain terminal of the first PMOS transistor 13, one end of the first resistor 5b, and the non-inverting output terminal Out_1. The gate terminal of the second NMOS transistor 12 is connected to the non-inverting input terminal In_1, the source terminal is connected to GND, and the drain terminal is connected to the drain terminal of the second PMOS transistor 14, one end of the second resistor 5a, and the inverting output terminal Out_0. The gate terminal of the second PMOS transistor 14 is connected to the other end of the first resistor 5b. The gate terminal of the first PMOS transistor 13 is connected to the other end of the second resistor 5a. The source terminals of the first PMOS transistor 13 and the second PMOS transistor 14 are connected to VDD.

[0017] The four-terminal circuit 1a is characterized in that the first NMOS transistor and the second NMOS transistor, the first PMOS transistor and the second PMOS transistor, and the first resistor and the second resistor are arranged in substantially equal shapes within the range of processing accuracy, and the directions of the DC current are equal. As a result, all electrical characteristics of each of them are equal. Therefore, from the time when the input signals of the non-inverting input terminal In_1 and the inverting input terminal In_0 are both at a low level or both at a high level, the transition of the output signals of the non-inverting output terminal Out_1 and the inverting output terminal Out_0 when the level of any input terminal changes to a different level becomes a completely symmetrical operation.

[0018] The first and second resistors are components used to: limit the charging current of the gate capacitors of the first and second PMOS transistors to avoid the problem of an excessively narrow non-overlap period during integrated circuit (IC) manufacturing processes, which could impede the circuit receiving the output of the four-terminal circuit 1a; thereby delaying the arrival time of the logic threshold value and achieving the minimum required non-overlap period for the normal operation of the downstream circuitry. The required non-overlap period is determined according to the specifications of the downstream circuitry and is calculated using the time constants of the gate capacitance value of the first or second PMOS transistor and the value of the first or second resistor.

[0019] That is, when it is desired to increase the non-overlap period, new first capacitors and second capacitors are intentionally added in parallel to the gate capacitors of the first PMOS transistor and the second PMOS transistor, respectively. Conversely, when it is desired to reduce the non-overlap period, the first resistor and the second resistor can be replaced by using a conductor such as aluminum.

[0020] Furthermore, regarding the components that delay the operation of the first PMOS transistor and the second PMOS transistor, a delay circuit 6, which is an example of a delay circuit replacing the first resistor and the second resistor, is shown in FIG8.

[0021] The delay circuit 6 consists of an even number of cascaded inverter logic gates 3c. The overall delay time of the delay circuit 6 is the sum of the signal delay times of each inverter logic gate 3c, and the delay characteristics of each inverter logic gate 3c may be different.

[0022] Figure 2 shows the truth table of the four-terminal circuit 1a.

[0023] Figure 3 shows a specific example of a two-phase clock generation circuit 10a that implements the low-skew two-phase clock generation circuit of the present invention. The inverter circuit 3a, inverter circuit 3b, and four-terminal circuit 1b enable a logic high-side non-overlapping signal generation circuit 2 with the fewest components.

[0024] Inverter circuit 3a includes a third NMOS transistor 19 and a third PMOS transistor 20. The gate terminals of the third NMOS transistor 19 and the third PMOS transistor 20 are connected to the input terminal In via node N_0. The drain terminals of the third NMOS transistor 19 and the third PMOS transistor 20 are connected to inverter circuit 3b via node N_1. The source terminal of the third NMOS transistor 19 is connected to the GND power supply. The source terminal of the third PMOS transistor 20 is connected to the VDD1 power supply. The third NMOS transistor 19 and the third PMOS transistor 20 operate as inverter circuit 3a.

[0025] The inverter circuit 3b includes a fourth NMOS transistor 21 and a fourth PMOS transistor 22. The gate terminals of the fourth NMOS transistor 21 and the fourth PMOS transistor 22 are connected to node N_1. The drain terminals of the fourth NMOS transistor 21 and the fourth PMOS transistor 22 are connected to the four-terminal circuit 1b via node N_2. The source terminal of the fourth NMOS transistor 21 is connected to GND. The source terminal of the fourth PMOS transistor 22 is connected to VDD1. The fourth NMOS transistor 21 and the fourth PMOS transistor 22 operate as the inverter circuit 3b.

[0026] The four-terminal circuit 1b includes a fifth NMOS transistor 15, a sixth NMOS transistor 16, a fifth PMOS transistor 17, and a sixth PMOS transistor 18. The gate terminal of the fifth NMOS transistor 15 is connected to node N_2, the source terminal is connected to GND, and the drain terminal is connected to the drain terminal of the fifth PMOS transistor 17, the gate terminal of the sixth PMOS transistor 18, and node N_4. The gate terminal of the sixth NMOS transistor 16 is connected to node N_1, the source terminal is connected to GND, and the drain terminal is connected to the drain terminal of the sixth PMOS transistor 18, the gate terminal of the fifth PMOS transistor 17, and node N_3. The source terminals of the fifth PMOS transistor 17 and the sixth PMOS transistor 18 are connected to VDD2.

[0027] Alternatively, as shown in Figure 6, the four-terminal circuit 1b can also be replaced by a four-terminal circuit 1c which is equipped with a seventh PMOS transistor 25 and an eighth PMOS transistor 26 for the purpose of limiting the through current.

[0028] Alternatively, as shown in Figure 7, the four-terminal circuit 1b can also use conventional logic gates. That is, it can replace the four-terminal circuit 1d, which is designed to cross-couple the first NOR logic gate 4a and the second NOR logic gate 4b to address the issue of uneven transmission characteristics. The power supplies and GND power supplies of the first NOR logic gate 4a and the second NOR logic gate 4b are respectively connected to the common VDD2 and GND.

[0029] Furthermore, for the four-terminal circuits 1b, 1c, and 1d, in order to increase the non-overlapping period, a time constant circuit containing resistors and capacitors, or a delay circuit 6 containing logic gates, is sometimes added as a delay unit.

[0030] When the well-symmetrical four-terminal circuit 1a shown in Figure 1 is connected to the non-overlapping signal generation circuit 2 on the logic high side as described above, a two-phase clock with excellent skew balance can be easily generated. The structure described above does not have a control loop, thus minimizing jitter. Symmetry is important for the four-terminal circuit 1a, but other circuits with modified topologies are also possible.

[0031] Furthermore, the voltages of VDD1, VDD2, and VDD can be selected according to the application.

[0032] Figure 4 is a timing diagram for the rising event of the low-skew two-phase clock generation circuit 10a of this embodiment. Figure 5 is a timing diagram for the falling event of the low-skew two-phase clock generation circuit 10a of this embodiment. The signal names of these timing diagrams correspond to nodes N_0 to N_6 in Figure 3.

[0033] Here, concerns regarding the symmetry of the output of the non-overlapping signal generation circuit 2 in Figure 3, namely the changes in nodes N_3 and N_4, are explained.

[0034] In Figure 4, the ascent of node N_3 during the ascent event is determined solely by the descent of node N_4. That is, if we refer to the truth table in Figure 2, the state transition becomes State 1 → State 0 → State 2.

[0035] On the other hand, the rise of node N_4 during the descent event in Figure 5 is determined by the slower of the descents of node N_3 and node N_2. In actual operation, the descents of node N_3 and node N_2 are close in time, forming a ramp waveform, so neither can be solely the cause or the result. Furthermore, it is clear that the descent of node N_2 is slower than the rise of node N_1. Therefore, if we refer to the truth table in Figure 2, the state transition becomes State2→State3→State1, which is significantly different from the case in Figure 4 via State0.

[0036] Therefore, the non-overlapping period of the four-terminal circuit 1b has different values ​​during the rising and falling events of the clock input, which compromises the skew margin for systems requiring high precision.

[0037] Next, when considering nodes N_5 and N_6 as output nodes of the four-terminal circuit 1a, nodes N_3 and N_4 as input nodes of the four-terminal circuit 1a, although they are offset, have non-overlapping periods. Therefore, the condition of passing through State0 instead of State3 in Figure 2 is guaranteed, and the symmetry of one of the rises being determined by the other fall is maintained.

[0038] As explained above, the two-phase clock generation circuit of this embodiment provides a two-phase clock generation circuit that requires uniformity in the gap between non-overlapping two-phase clocks, i.e., the relationship between the rising edge and the falling edge.

[0039] Furthermore, in the case where the non-overlapping signal generation circuit 2 is non-overlapping on the logic low side, it is sufficient to set up an inverter circuit for polarity reversal in each of the two input terminals of the four-terminal circuit 1a, namely the inverting input terminal In_0 and the non-inverting input terminal In_1. In addition, if the non-overlapping signal generation circuit 2 is non-overlapping on the logic high side and the output of the two-phase clock generation circuit requires non-overlapping on the logic low side, it can be configured by simply replacing the NMOS transistor constituting the four-terminal circuit 1a with a PMOS transistor, replacing the PMOS transistor with an NMOS transistor, replacing VDD with GND, and replacing GND with VDD.

[0040] [Second Implementation] The second embodiment of the present invention will be described with reference to the figures. Furthermore, structural elements that are the same as those in the first embodiment will be labeled with the same numbers as in the first embodiment, and their descriptions will be omitted.

[0041] In the second embodiment, the four-terminal circuit 1a in the two-phase clock generation circuit 10 of FIG1 is replaced with the four-terminal circuit 1e shown in FIG9, and the four-terminal circuit 1a in the two-phase clock generation circuit 10a of FIG3 is replaced with the four-terminal circuit 1e shown in FIG9.

[0042] The four-terminal circuit 1e is a circuit for obtaining two-phase output from two-phase input, including: voltage-to-current conversion elements namely the seventh NMOS transistor 31 and the eighth NMOS transistor 32, the ninth PMOS transistor 33 and the tenth PMOS transistor 34 which realize latching operation through cross-coupling connection, the eleventh PMOS transistor 35 and the twelfth PMOS transistor 36 which serve as switches to limit the through current, the non-inverting input terminal In_1, the inverting input terminal In_0, the non-inverting output terminal Out_1, the inverting output terminal Out_0, the second resistor 5a, and the first resistor 5b.

[0043] The connection of the four-terminal circuit 1e is explained. The gate terminal of the seventh NMOS transistor 31 is connected to the gate terminal of the eleventh PMOS transistor 35 and the inverting input terminal In_0, the source terminal is connected to GND, and the drain terminal is connected to the drain terminal of the eleventh PMOS transistor 35, one terminal of the first resistor 5b, and the non-inverting output terminal Out_1. The gate terminal of the eighth NMOS transistor 32 is connected to the gate terminal of the twelfth PMOS transistor 36 and the non-inverting input terminal In_1, the source terminal is connected to GND, and the drain terminal is connected to the twelfth PMOS transistor 36. The drain terminal of PMOS transistor 6 and one terminal of the second resistor 5a are connected to the inverting output terminal Out_0. The gate terminal of the ninth PMOS transistor 33 is connected to the other terminal of the second resistor 5a. The drain terminal is connected to the source terminal of the eleventh PMOS transistor 35. The gate terminal of the tenth PMOS transistor 34 is connected to the other terminal of the first resistor 5b. The drain terminal is connected to the source terminal of the twelfth PMOS transistor 36. The source terminals of the ninth PMOS transistor 33 and the tenth PMOS transistor 34 are connected to VDD.

[0044] The four-terminal circuit 1e is characterized in that the seventh NMOS transistor 31 and the eighth NMOS transistor 32, the ninth PMOS transistor 33 and the tenth PMOS transistor 34, the eleventh PMOS transistor 35 and the twelfth PMOS transistor 36, the first resistor 5b and the second resistor 5a are arranged in substantially equal shapes within the range of processing accuracy, and the directions of the DC current are equal. As a result, all electrical characteristics of each of them are equal. Therefore, from the time when the input signals of the positive input terminal In_1 and the negative input terminal In_0 are both at a low level or both at a high level, the transition of the output signals of the positive output terminal Out_1 and the negative output terminal Out_0 when the level of any input terminal changes to a different level becomes a completely symmetrical operation.

[0045] Figure 10 shows the truth table of the four-terminal circuit 1e.

[0046] As described above in conjunction with the first embodiment, the two-phase clock generation circuit of this embodiment can provide a two-phase clock generation circuit that requires the gap between non-overlapping two-phase clocks, i.e., the relationship between the rising edge and the falling edge, to be uniform.

[0047] Furthermore, in the case where the non-overlapping signal generation circuit 2 is non-overlapping on the logic low side, it is sufficient to set up an inverter circuit for polarity reversal in each of the two input terminals of the four-terminal circuit 1e, namely the inverting input terminal In_0 and the non-inverting input terminal In_1. In addition, if the non-overlapping signal generation circuit 2 is non-overlapping on the logic high side and the output of the two-phase clock generation circuit requires non-overlapping on the logic low side, it can be configured by simply replacing the NMOS transistor constituting the four-terminal circuit 1e with a PMOS transistor, replacing the PMOS transistor with an NMOS transistor, replacing VDD with GND, and replacing GND with VDD. [Third Implementation Method] The third embodiment of the present invention will be described with reference to the figures. Furthermore, structural elements that are the same as those in the first embodiment will be labeled with the same numbers as those in the first embodiment, and their descriptions will be omitted.

[0048] In the third embodiment, the four-terminal circuit 1a in the two-phase clock generation circuit 10 of FIG1 is replaced with the four-terminal circuit 1f shown in FIG11, and the four-terminal circuit 1a in the two-phase clock generation circuit 10a of FIG3 is replaced with the four-terminal circuit 1f shown in FIG11.

[0049] The four-terminal circuit 1f is a circuit for obtaining two-phase output from two-phase input, including: a third NOR logic gate 4c, a fourth NOR logic gate 4d, a non-inverting input terminal In_1, an inverting input terminal In_0, a non-inverting output terminal Out_1, an inverting output terminal Out_0, VDD, GND, a second resistor 5a, and a first resistor 5b.

[0050] Figure 12 shows a circuit diagram of a general NOR logic gate, which includes the structural elements of a third NOR logic gate 4c and a fourth NOR logic gate 4d, namely a MOS transistor. That is, the NOR circuit 4 includes: a ninth NMOS transistor 41, a tenth NMOS transistor 42, a thirteenth PMOS transistor 43, a fourteenth PMOS transistor 44, input terminals In_A and In_B, an output terminal Out, a VDD power supply, and a GND power supply.

[0051] The NOR circuit 4 is characterized by the following: the duality of the connections of the thirteenth PMOS transistor 43 and the fourteenth PMOS transistor 44 is poor relative to the duality of the two input terminals In_A and In_B. Therefore, since the input terminals In_A and In_B are different, even if the static logic of the circuit is the same, the transitional electrical characteristics will be different if the input terminals In_A and In_B are replaced.

[0052] The connection of the four-terminal circuit 1f containing this type of NOR logic gate is described. The input terminal In_Ac of the third NOR logic gate 4c is connected to the inverting input terminal In_0, the input terminal In_Bc is connected to one terminal of the first resistor 5b, and the output terminal Outc is connected to the non-inverting output terminal Out_1 and one terminal of the second resistor 5a. The input terminal In_Ad of the fourth NOR logic gate 4d is connected to the non-inverting input terminal In_1, the input terminal In_Bd is connected to the other terminal of the second resistor 5a, and the output terminal Outd is connected to the inverting output terminal Out_0 and the other terminal of the first resistor 5b. The power supplies and GND power supplies of the third NOR logic gate 4c and the fourth NOR logic gate 4d are respectively connected to the common VDD and GND.

[0053] Thus, the four-terminal circuit 1f is characterized by distinguishing the input terminals In_A and In_B of the NOR logic gate, and the third NOR logic gate 4c and the fourth NOR logic gate 4d, as well as the first resistor 5b and the second resistor 5a are symmetrically connected. Therefore, for all state transitions, the positive output terminal Out_1 and the inverted output terminal Out_0 can obtain symmetrical operation outputs.

[0054] The necessary conditions for this are that the third and fourth NOR logic gates are close to each other in substantially equal shape within the range of machining accuracy and that the directions of the current passing through are equal, and the first and second resistors are close to each other in substantially equal shape within the range of machining accuracy.

[0055] Figure 14 is a circuit representation of the transistor levels in the four-terminal circuit 1f shown in Figure 11. Transistors 41c, 42c, 43c, and 44c form the third NOR logic gate 4c in Figure 11, and transistors 41d, 42d, 43d, and 44d form the fourth NOR logic gate 4d in Figure 11. Figure 15 is a schematic diagram of the circuit layout in Figure 11.

[0056] Figure 13 shows the truth table of the four-terminal circuit 1f.

[0057] As described above in conjunction with the first embodiment, the two-phase clock generation circuit of this embodiment can provide a two-phase clock generation circuit that requires the gap between non-overlapping two-phase clocks, i.e., the relationship between the rising edge and the falling edge, to be uniform.

[0058] Furthermore, in the case where the non-overlapping signal generation circuit 2 is non-overlapping on the logic low side, it is sufficient to set up an inverter circuit for polarity reversal in each of the two input terminals of the four-terminal circuit 1f, namely the inverting input terminal In_0 and the non-inverting input terminal In_1. In addition, if the non-overlapping signal generation circuit 2 is non-overlapping on the logic low side and the output of the two-phase clock generation circuit requires non-overlapping on the logic low side, the NOR logic gate constituting the four-terminal circuit 1f can be replaced with an inverse (Not AND, NAND) logic gate.

[0059] In recent years, products manufactured using single-nanometer process standards have also emerged in the field of Central Processing Units (CPUs) and signal processing. Especially in systems requiring enhanced high-speed operation, the importance of setup / hold margin and signal integrity is increasing. Under this trend of miniaturization, installation techniques that minimize two-phase clock skew, as described above, are an effective means of mitigating timing margins in two-phase clocks.

[0060] 1a, 1b, 1c, 1d, 1e, 1f: Four-terminal circuit 2: Non-overlapping signal generation circuit 3a, 3b: Inverter circuits 3c: Inverter logic gate 4: NOR circuit 4a: First NOR logic gate / NOR logic gate 4b: Second NOR Logic Gate / NOR Logic Gate 4c: Third NOR logic gate / NOR logic gate 4d: Fourth NOR Logic Gate / NOR Logic Gate 5a: Second resistor / resistor 5b: First resistor / resistor 6: Delay circuit 10, 10a: Two-phase clock generation circuit 11: First NMOS transistor / First N-channel MOS transistor / NMOS transistor 12: Second NMOS transistor / Second N-channel MOS transistor / NMOS transistor 13: First PMOS transistor / First P-channel MOS transistor / PMOS transistor 14: Second PMOS transistor / Second P-channel MOS transistor / PMOS transistor 15: Fifth NMOS Transistor / NMOS Transistor 16: Sixth NMOS Transistor / NMOS Transistor 17: Fifth PMOS Transistor / PMOS Transistor 18: Sixth PMOS Transistor / PMOS Transistor 19: Third NMOS transistor / NMOS transistor 20: Third PMOS transistor / PMOS transistor 21: Fourth NMOS Transistor / NMOS Transistor 22: Fourth PMOS transistor / PMOS transistor 25: Seventh PMOS transistor 26: Eighth PMOS transistor 31: Seventh NMOS Transistor / NMOS Transistor 32: Eighth NMOS Transistor / NMOS Transistor 33: Ninth PMOS Transistor / PMOS Transistor 34: The tenth PMOS transistor / PMOS transistor 35: Eleventh PMOS Transistor / PMOS Transistor 36: The twelfth PMOS transistor / PMOS transistor 41: Ninth NMOS Transistor / NMOS Transistor 42: Tenth NMOS Transistor / NMOS Transistor 43: The thirteenth PMOS transistor / PMOS transistor 44: The Fourteenth PMOS Transistor / PMOS Transistor 41c, 42c, 43c, 44c, 41d, 42d, 43d, 44d: Transistors In, In_A, In_Ac, In_Ad, In_B, In_Bc, In_Bd: input terminal In_0: Inverting input terminal In_1: Non-inverting input terminal Out, Outc, Outd: Output terminals Out_0: Inverting output terminal Out_1: Non-inverting output terminal GND: Ground wire VDD, VDD1, VDD2: Drain power supply voltage N_0~N_6: Nodes

Claims

1. A two-phase clock generation circuit, characterized in that it includes a non-overlapping signal generation circuit on the logic high side and a four-terminal circuit, wherein the four-terminal circuit includes: First N-channel metal-oxide-semiconductor transistor; A second N-channel metal-oxide-semiconductor (MOSFET) is substantially adjacent to the first N-channel MOSFET with equal area, aspect ratio, and current direction; a first P-channel MOSFET; a second P-channel MOSFET is substantially adjacent to the first P-channel MOSFET with equal area, aspect ratio, and current direction; a non-inverting input terminal; an inverting input terminal; a non-inverting output terminal; an inverting output terminal; and a first resistor and a second resistor having substantially equal resistance values, wherein the first resistor and the second resistor include conductor connections; the two output terminals of the non-overlapping signal generation circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the four-terminal circuit; the gate terminal of the first N-channel MOSFET is connected to the inverting input terminal, the source terminal is connected to ground, and the drain terminal is connected to the drain terminal of the first P-channel MOSFET, the second resistor, and the non-inverting output terminal. The gate terminal of the second P-channel metal-oxide-semiconductor transistor is connected to the second resistor. The gate terminal of the second N-channel metal-oxide-semiconductor transistor is connected to the non-inverting input terminal, the source terminal is connected to ground, and the drain terminal is connected to the drain terminal of the second P-channel metal-oxide-semiconductor transistor, the first resistor, and the inverting output terminal. The gate terminal of the first P-channel metal-oxide-semiconductor transistor is connected to the first resistor. The source terminals of the first P-channel metal-oxide-semiconductor transistor and the second P-channel metal-oxide-semiconductor transistor are connected to the drain power supply voltage.

2. The two-phase clock generation circuit as claimed in claim 1, wherein the four-terminal circuit further includes a first capacitor and a second capacitor having substantially equal electrical characteristics, respectively connected in parallel to the gate terminals of the first P-channel metal-oxide-semiconductor transistor and the second P-channel metal-oxide-semiconductor transistor.

3. A two-phase clock generation circuit, characterized in that it includes a non-overlapping signal generation circuit on the logic high side and a four-terminal circuit, wherein the four-terminal circuit includes: First N-channel metal-oxide-semiconductor transistor; A second N-channel metal-oxide-semiconductor transistor is substantially adjacent to the first N-channel metal-oxide-semiconductor transistor with equal area, equal aspect ratio, and equal current direction; a first P-channel metal-oxide-semiconductor transistor; a second P-channel metal-oxide-semiconductor transistor is substantially adjacent to the first P-channel metal-oxide-semiconductor transistor with equal area, equal aspect ratio, and equal current direction; a non-inverting input terminal; an inverting input terminal; a non-inverting output terminal; an inverting output terminal; The circuit includes a delay circuit comprising a cascaded connection of combinational logic gates having substantially equal electrical characteristics. The two output terminals of the non-overlapping signal generation circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the four-terminal circuit. The gate terminal of the first N-channel MOSFET is connected to the inverting input terminal, the source terminal is connected to ground, and the drain terminal is connected to the drain terminal of the first P-channel MOSFET and the non-inverting output terminal. The gate terminal of the second N-channel MOSFET is connected to the non-inverting input terminal, the source terminal is connected to ground, and the drain terminal is connected to the drain terminal of the second P-channel MOSFET and the inverting output terminal. The delay circuit is inserted between the gate terminal of the second P-channel MOSFET and the drain terminal of the first N-channel MOSFET, and between the gate terminal of the first P-channel MOSFET and the drain terminal of the second N-channel MOSFET. The source terminals of the first P-channel metal-oxide-semiconductor transistor and the second P-channel metal-oxide-semiconductor transistor are connected to the drain power supply voltage.

4. A two-phase clock generation circuit, characterized in that it includes a non-overlapping signal generation circuit on the logic low side and a four-terminal circuit, wherein the four-terminal circuit includes: First P-channel metal-oxide-semiconductor transistor; A second P-channel metal-oxide-semiconductor (MOSFET) is substantially adjacent to the first P-channel MOSFET with equal area, aspect ratio, and current direction; a first N-channel MOSFET; a second N-channel MOSFET, substantially adjacent to the first N-channel MOSFET with equal area, aspect ratio, and current direction; a non-inverting input terminal; an inverting input terminal; a non-inverting output terminal; an inverting output terminal; and a first resistor and a second resistor having substantially equal resistance values, wherein the first resistor and the second resistor include conductor connections; the two output terminals of the non-overlapping signal generation circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the four-terminal circuit; the gate terminal of the first P-channel MOSFET is connected to the inverting input terminal, the source terminal is connected to the drain power supply voltage, and the drain terminal is connected to the drain terminal of the first N-channel MOSFET, the second resistor, and the non-inverting output terminal; The gate terminal of the second N-channel metal-oxide-semiconductor transistor is connected to the second resistor. The gate terminal of the second P-channel metal-oxide-semiconductor transistor is connected to the non-inverting input terminal, and the source terminal is connected to the drain power supply voltage. The drain terminal is connected to the drain terminal of the second N-channel metal-oxide-semiconductor transistor, the first resistor, and the inverting output terminal. The gate terminal of the first N-channel metal-oxide-semiconductor transistor is connected to the first resistor. The source terminals of the first N-channel metal-oxide-semiconductor transistor and the second N-channel metal-oxide-semiconductor transistor are connected to ground.

5. The two-phase clock generation circuit as claimed in claim 4, wherein the four-terminal circuit further includes a first capacitor and a second capacitor having substantially equal electrical characteristics, respectively connected in parallel to the gate terminals of the first N-channel metal-oxide-semiconductor transistor and the second N-channel metal-oxide-semiconductor transistor.

6. A two-phase clock generation circuit, characterized in that it includes a non-overlapping signal generation circuit on the logic low side and a four-terminal circuit, wherein the four-terminal circuit includes: First P-channel metal-oxide-semiconductor transistor; A second P-channel metal-oxide-semiconductor transistor is substantially adjacent to the first P-channel metal-oxide-semiconductor transistor in terms of area, aspect ratio, and current direction; a first N-channel metal-oxide-semiconductor transistor; a second N-channel metal-oxide-semiconductor transistor is substantially adjacent to the first N-channel metal-oxide-semiconductor transistor in terms of area, aspect ratio, and current direction; a non-inverting input terminal; an inverting input terminal; a non-inverting output terminal; an inverting output terminal; The circuit includes a delay circuit comprising a cascaded connection of combinational logic gates having substantially equal electrical characteristics. The two output terminals of the non-overlapping signal generation circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the four-terminal circuit. The gate terminal of the first P-channel metal-oxide-semiconductor (MOSFET) is connected to the inverting input terminal, the source terminal is connected to the drain power supply voltage, and the drain terminal is connected to the drain terminal of the first N-channel MOSFET and the non-inverting output terminal. The gate terminal of the second P-channel MOSFET is connected to the non-inverting input terminal, the source terminal is connected to the drain power supply voltage, and the drain terminal is connected to the drain terminal of the second N-channel MOSFET and the inverting output terminal. The delay circuit is inserted between the gate terminal of the second N-channel MOSFET and the drain terminal of the first P-channel MOSFET, and between the gate terminal of the first N-channel MOSFET and the drain terminal of the second P-channel MOSFET. The source terminals of the first N-channel metal-oxide-semiconductor transistor and the second N-channel metal-oxide-semiconductor transistor are connected to ground.

7. A two-phase clock generation circuit, characterized in that it includes a non-overlapping signal generation circuit on the logic high side and a four-terminal circuit, wherein the four-terminal circuit includes: First N-channel metal-oxide-semiconductor transistor; A second N-channel metal-oxide-semiconductor (MOS) transistor is substantially adjacent to the first N-channel MOS transistor with equal area, equal aspect ratio, and equal current direction; a first P-channel MOS transistor; a second P-channel MOS transistor is substantially adjacent to the first P-channel MOS transistor with equal area, equal aspect ratio, and equal current direction; a third P-channel MOS transistor; a fourth P-channel MOS transistor is substantially adjacent to the third P-channel MOS transistor with equal area, equal aspect ratio, and equal current direction; a non-inverting input terminal; an inverting input terminal; a non-inverting output terminal; an inverting output terminal; and a first resistor and a second resistor having substantially equal resistance values, wherein the first resistor and the second resistor include conductor connections; the two output terminals of the non-overlapping signal generation circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the four-terminal circuit. The gate terminal of the first N-channel MOSFET is connected to the inverting input terminal, the source terminal is connected to ground, and the drain terminal is connected to the drain terminal of the third P-channel MOSFET, the second resistor, and the non-inverting output terminal. The gate terminal of the second P-channel MOSFET is connected to the second resistor. The gate terminal of the second N-channel MOSFET is connected to the non-inverting input terminal, the source terminal is connected to ground, and the drain terminal is connected to the drain terminal of the fourth P-channel MOSFET, the first resistor, and the inverting output terminal. The gate terminal of the first P-channel MOSFET is connected to the first resistor. The gate terminal of the third P-channel MOSFET is connected to the inverting input terminal, and the source terminal is connected to the drain terminal of the first P-channel MOSFET. The gate terminal of the fourth P-channel MOSFET is connected to the non-inverting input terminal, and the source terminal is connected to the drain terminal of the second P-channel MOSFET. The source terminals of the first P-channel metal-oxide-semiconductor transistor and the second P-channel metal-oxide-semiconductor transistor are connected to the drain power supply voltage.

8. The two-phase clock generation circuit as claimed in claim 7, wherein the four-terminal circuit further includes a first capacitor and a second capacitor having substantially equal electrical characteristics, respectively connected in parallel to the gate terminals of the first P-channel metal-oxide-semiconductor transistor and the second P-channel metal-oxide-semiconductor transistor.

9. A two-phase clock generation circuit, characterized in that it includes a non-overlapping signal generation circuit on the logic high side and a four-terminal circuit, wherein the four-terminal circuit includes: First N-channel metal-oxide-semiconductor transistor; A second N-channel metal-oxide-semiconductor transistor is substantially adjacent to the first N-channel metal-oxide-semiconductor transistor with equal area, equal aspect ratio, and equal current direction; a first P-channel metal-oxide-semiconductor transistor; a second P-channel metal-oxide-semiconductor transistor is substantially adjacent to the first P-channel metal-oxide-semiconductor transistor with equal area, equal aspect ratio, and equal current direction; a third P-channel metal-oxide-semiconductor transistor; a fourth P-channel metal-oxide-semiconductor transistor is substantially adjacent to the third P-channel metal-oxide-semiconductor transistor with equal area, equal aspect ratio, and equal current direction; a non-inverting input terminal; an inverting input terminal; a non-inverting output terminal; and an inverting output terminal. The circuit includes a delay circuit comprising a cascaded connection of combinational logic gates having substantially equal electrical characteristics. The two output terminals of the non-overlapping signal generation circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the four-terminal circuit. The gate terminal of the first N-channel MOSFET is connected to the inverting input terminal, the source terminal is connected to ground, and the drain terminal is connected to the drain terminal of the third P-channel MOSFET and the non-inverting output terminal. The gate terminal of the second N-channel MOSFET is connected to the non-inverting input terminal, the source terminal is connected to ground, and the drain terminal is connected to the drain terminal of the fourth P-channel MOSFET and the inverting output terminal. Delay circuits are inserted between the gate terminal of the second P-channel MOSFET and the drain terminal of the first N-channel MOSFET, and between the gate terminal of the first P-channel MOSFET and the drain terminal of the second N-channel MOSFET. The gate terminal of the third P-channel metal-oxide-semiconductor transistor is connected to the inverting input terminal, and the source terminal is connected to the drain terminal of the first P-channel metal-oxide-semiconductor transistor. The gate terminal of the fourth P-channel metal-oxide-semiconductor transistor is connected to the non-inverting input terminal, and the source terminal is connected to the drain terminal of the second P-channel metal-oxide-semiconductor transistor. The source terminals of the first P-channel metal-oxide-semiconductor transistor and the second P-channel metal-oxide-semiconductor transistor are connected to the drain power supply voltage.

10. A two-phase clock generation circuit, characterized in that it includes a non-overlapping signal generation circuit on the logic low side and a four-terminal circuit, wherein the four-terminal circuit includes: First P-channel metal-oxide-semiconductor transistor; A second P-channel metal-oxide-semiconductor (MOS) transistor is substantially adjacent to the first P-channel MOS transistor in terms of area, aspect ratio, and current direction; a first N-channel MOS transistor; a second N-channel MOS transistor is substantially adjacent to the first N-channel MOS transistor in terms of area, aspect ratio, and current direction; a third N-channel MOS transistor; a fourth N-channel MOS transistor is substantially adjacent to the third N-channel MOS transistor in terms of area, aspect ratio, and current direction; a non-inverting input terminal; an inverting input terminal; a non-inverting output terminal; an inverting output terminal; and a first resistor and a second resistor having substantially equal resistance values, wherein the first resistor and the second resistor include conductor connections; the two output terminals of the non-overlapping signal generation circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the four-terminal circuit. The gate terminal of the first P-channel MOSFET is connected to the inverting input terminal, and the source terminal is connected to the drain power supply voltage. The drain terminal is connected to the drain terminal of the third N-channel MOSFET, the second resistor, and the non-inverting output terminal. The gate terminal of the second N-channel MOSFET is connected to the second resistor. The gate terminal of the second P-channel MOSFET is connected to the non-inverting input terminal, and the source terminal is connected to the drain power supply voltage. The drain terminal is connected to the drain terminal of the fourth N-channel MOSFET, the first resistor, and the inverting output terminal. The gate terminal of the first N-channel MOSFET is connected to the first resistor. The gate terminal of the third N-channel MOSFET is connected to the inverting input terminal, and the source terminal is connected to the drain terminal of the first N-channel MOSFET. The gate terminal of the fourth N-channel MOSFET is connected to the non-inverting input terminal, and the source terminal is connected to the drain terminal of the second N-channel MOSFET. The source terminals of the first N-channel metal-oxide-semiconductor transistor and the second N-channel metal-oxide-semiconductor transistor are connected to ground.

11. The two-phase clock generation circuit as claimed in claim 10, wherein the four-terminal circuit further includes a first capacitor and a second capacitor having substantially equal electrical characteristics, respectively connected in parallel to the gate terminals of the first N-channel metal-oxide-semiconductor transistor and the second N-channel metal-oxide-semiconductor transistor.

12. A two-phase clock generation circuit, characterized in that it includes a non-overlapping signal generation circuit on the logic low side and a four-terminal circuit, wherein the four-terminal circuit includes: First P-channel metal-oxide-semiconductor transistor; A second P-channel metal-oxide-semiconductor (MOS) transistor is substantially adjacent to the first P-channel MOS transistor in terms of area, aspect ratio, and current direction; a first N-channel MOS transistor; a second N-channel MOS transistor is substantially adjacent to the first N-channel MOS transistor in terms of area, aspect ratio, and current direction; a third N-channel MOS transistor; a fourth N-channel MOS transistor is substantially adjacent to the third N-channel MOS transistor in terms of area, aspect ratio, and current direction; a non-inverting input terminal; an inverting input terminal; a non-inverting output terminal; and an inverting output terminal. The circuit includes a delay circuit comprising a cascaded connection of combinational logic gates having substantially equal electrical characteristics. The two output terminals of the non-overlapping signal generation circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the four-terminal circuit. The gate terminal of the first P-channel MOSFET is connected to the inverting input terminal, and its source terminal is connected to the drain power supply voltage. The drain terminal is connected to the drain terminal of the third N-channel MOSFET and the non-inverting output terminal. The gate terminal of the second P-channel MOSFET is connected to the non-inverting input terminal, and its source terminal is connected to the drain power supply voltage. The drain terminal is connected to the drain terminal of the fourth N-channel MOSFET and the inverting output terminal. The delay circuit is inserted between the gate terminal of the second N-channel MOSFET and the drain terminal of the first P-channel MOSFET, and between the gate terminal of the first N-channel MOSFET and the drain terminal of the second P-channel MOSFET. The gate terminal of the third N-channel metal-oxide-semiconductor transistor is connected to the inverting input terminal, and the source terminal is connected to the drain terminal of the first P-channel metal-oxide-semiconductor transistor. The gate terminal of the fourth N-channel metal-oxide-semiconductor transistor is connected to the non-inverting input terminal, and the source terminal is connected to the drain terminal of the second P-channel metal-oxide-semiconductor transistor. The source terminals of the first N-channel metal-oxide-semiconductor transistor and the second N-channel metal-oxide-semiconductor transistor are connected to ground.

13. A two-phase clock generation circuit, characterized in that it includes a non-overlapping signal generation circuit on the logic high side and a four-terminal circuit, wherein the four-terminal circuit includes: First inverse OR logic gate; A second inverse OR logic gate, configured with a shape substantially equal to that of the first inverse OR logic gate and arranged such that the directions of the current flowing through it are equal; a first resistor; a second resistor, configured substantially equal to that of the first resistor; a non-inverting input terminal; an inverting input terminal; a non-inverting output terminal; and an inverting output terminal, wherein the first resistor and the second resistor include conductor connections; the two output terminals of the non-overlapping signal generation circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the four-terminal circuit; all input terminals of the first inverse OR logic gate and the second inverse OR logic gate are distinguished; the first input terminal of the first inverse OR logic gate is connected to the inverting input terminal, the second input terminal is connected to the first resistor, and the output terminal is connected to the non-inverting output terminal and the second resistor; the first input terminal of the second inverse OR logic gate is connected to the non-inverting input terminal, the second input terminal is connected to the second resistor, and the output terminal is connected to the inverting output terminal and the first resistor. The power supply terminals of the first and second anti-OR logic gates are connected to the same drain power supply voltage, and the ground terminals of the first and second anti-OR logic gates are connected to the same ground wire.

14. The two-phase clock generation circuit as claimed in claim 13, wherein the four-terminal circuit further includes a first capacitor and a second capacitor having substantially equal electrical characteristics, respectively connected in parallel to the second input terminal of the first inverse OR gate and the second input terminal of the second inverse OR gate.

15. A two-phase clock generation circuit, characterized in that it includes a non-overlapping signal generation circuit on the logic high side and a four-terminal circuit, wherein the four-terminal circuit includes: First inverse OR logic gate; The second inverse OR logic gate is configured to have a shape substantially equal to that of the first inverse OR logic gate and to be arranged such that the directions of the through current are equal; the delay circuit includes a cascaded connection of combinational logic gates having substantially equal electrical characteristics; a positive input terminal; an inverting input terminal; and a positive output terminal. The circuit includes an inverting output terminal, and two output terminals of the non-overlapping signal generation circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the four-terminal circuit. All input terminals of the first inverse OR gate and the second inverse OR gate are distinguished. The first input terminal of the first inverse OR gate is connected to the inverting input terminal, and the first input terminal of the second inverse OR gate is connected to the non-inverting input terminal. Delay circuits are inserted between the second input terminal of the second inverse OR gate and the output terminal of the first inverse OR gate, and between the second input terminal of the first inverse OR gate and the output terminal of the second inverse OR gate. The power supply terminals of the first inverse OR gate and the second inverse OR gate are connected to the same drain power supply voltage, and the ground terminals of the first inverse OR gate and the second inverse OR gate are connected to the same ground wire.

16. A two-phase clock generation circuit, characterized in that it includes a non-overlapping signal generation circuit on the logic low side and a four-terminal circuit, wherein the four-terminal circuit includes: First inverse and logic gate; A second inverting logic gate, configured with a shape substantially equal to that of the first inverting logic gate and arranged such that the directions of the current flowing through it are equal; a first resistor; a second resistor, configured substantially equal to that of the first resistor; a non-inverting input terminal; an inverting input terminal; a non-inverting output terminal; and an inverting output terminal, wherein the first resistor and the second resistor include conductor connections; the two output terminals of the non-overlapping signal generation circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the four-terminal circuit; all input terminals of the first inverting logic gate and the second inverting logic gate are distinguished; the first input terminal of the first inverting logic gate is connected to the inverting input terminal, the second input terminal is connected to the first resistor, and the output terminal is connected to the non-inverting output terminal and the second resistor; the first input terminal of the second inverting logic gate is connected to the non-inverting input terminal, the second input terminal is connected to the second resistor, and the output terminal is connected to the inverting output terminal and the first resistor. The power supply terminals of the first reverse logic gate and the second reverse logic gate are connected to the same drain power supply voltage, and the ground terminals of the first reverse logic gate and the second reverse logic gate are connected to the same ground wire.

17. The two-phase clock generation circuit as claimed in claim 16, wherein the four-terminal circuit further includes a first capacitor and a second capacitor having substantially equal electrical characteristics, respectively connected in parallel to the second input terminal of the first inverting logic gate and the second input terminal of the second inverting logic gate.

18. A two-phase clock generation circuit, characterized in that it includes a non-overlapping signal generation circuit on the logic low side and a four-terminal circuit, wherein the four-terminal circuit includes: First inverse and logic gate; The second inverting logic gate is configured to have a shape substantially equal to that of the first inverting logic gate and to be arranged such that the directions of the current passing through it are equal; the delay circuit includes a cascaded connection of combination logic gates having substantially equal electrical characteristics; a positive input terminal; an inverting input terminal; and a positive output terminal. The circuit includes an inverting output terminal, and two output terminals of the non-overlapping signal generation circuit are respectively connected to the non-inverting input terminal and the inverting input terminal of the four-terminal circuit. All input terminals of the first inverting logic gate and the second inverting logic gate are distinguished. The first input terminal of the first inverting logic gate is connected to the inverting input terminal, and the first input terminal of the second inverting logic gate is connected to the non-inverting input terminal. Delay circuits are inserted between the second input terminal of the second inverting logic gate and the output terminal of the first inverting logic gate, and between the second input terminal of the first inverting logic gate and the output terminal of the second inverting logic gate. The power supply terminals of the first inverting logic gate and the second inverting logic gate are connected to the same drain power supply voltage, and the ground terminals of the first inverting logic gate and the second inverting logic gate are connected to the same ground wire.

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