Bonding layer and process of making

Abstract

A process for forming a semiconductor package is disclosed. The process includes providing a first substrate comprising a first dielectric layer. The process includes covering a first surface of the first dielectric layer with a first adhesive layer comprising aluminum. The process includes providing a second substrate comprising a second dielectric layer. The process includes covering a second surface of the second dielectric layer with a second adhesive layer comprising alkoxysilicon oxide. The process includes forming a third adhesive layer by bonding the first adhesive layer and the second adhesive layer to adhere the first substrate to the second substrate.

Description

Technical Field

[0001] [Cross-reference to related applications] This application claims priority to U.S. Provisional Patent Application No. 63 / 240,312, the basis of which was filed on September 2, 2021 (invention entitled 'Bonding Layer and Process of Making'), the entire contents of which are incorporated herein by reference for all purposes.

[0002] This disclosure relates to microelectronic devices, including semiconductor elements, transistors, and integrated circuits, and includes methods for microfabrication. Prior Technology

[0003] The semiconductor industry has experienced rapid growth due to continuous improvements in the integrated density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this improvement in integrated density stems from the continuous reduction in the minimum feature size, allowing more components to be integrated into a given area. With the recent growth in demand for miniaturization, higher speeds, greater bandwidth, and lower power consumption and latency, the demand for smaller and more innovative semiconductor die packaging technologies is also growing. Summary of the Invention

[0004] Wafer-to-wafer and chip-to-chip bonding is being implemented to continue power-performance-area-cost (PPAC) scaling of composite circuits, such as those implemented in System-on-Chip (SoC). Many bonding technologies utilize oxide-to-oxide bonding and hybrid bonding techniques to form integrated interconnect structures, where interconnects are formed at the bonding interface between two wafers or dies. However, current technologies typically create permanent electrical connections between the individual interconnect structures of the bonded wafer / die. In other words, current bonded wafer / die interconnect structures cannot switch between connected and disconnected states.

[0005] This disclosure provides various embodiments of interconnect structures for two wafers (or dies) electrically interconnected by bonding two selectively grown adhesive layers. For example, a first wafer may include a first substrate having a first dielectric layer (e.g., having an oxide surface) formed thereon, and a second wafer may include a second substrate having a second dielectric layer (also having an oxide surface) formed thereon. Within the first dielectric layer, a plurality of first interconnect structures are formed therein, and within the second dielectric layer, a plurality of second interconnect structures are formed therein. One of these oxide surfaces (but not both) is treated to selectively form a first adhesive layer comprising aluminum thereon. The other oxide surface is treated to selectively form a second adhesive layer comprising silicon alkoxides thereon. Based on the bonding of the first and second adhesive layers, the first substrate can be coupled to the second substrate, and each of the first interconnect structures is in physical contact with a corresponding one of the second interconnect structures.

[0006] One embodiment of this disclosure relates to a structure (e.g., a semiconductor package). The structure may include a first substrate; a second substrate; and an adhesive layer comprising AlSiO, wherein the first substrate is bonded to the second substrate.

[0007] The first substrate includes: a first dielectric layer disposed on the first substrate; and a first interconnect structure embedded in the first dielectric layer and having a first upper surface not covered by the first dielectric layer. The second substrate includes: a second dielectric layer disposed on the second substrate; and a second interconnect structure embedded in the second dielectric layer and having a second upper surface not covered by the second dielectric layer.

[0008] The first interconnect structure contacts the second interconnect structure, and the first upper surface and the second upper surface are in contact with each other. The adhesive layer surrounds a portion of a common sidewall of the contacted first and second interconnect structures. The adhesive layer extends only between the first and second dielectric layers. The first substrate includes a first element structure covered by the first dielectric layer, wherein the first element structure is electrically coupled to the first interconnect structure, and the second substrate includes a second element structure covered by the second dielectric layer, wherein the second element structure is electrically coupled to the second interconnect structure. The adhesive layer has a thickness of less than about 4 nanometers.

[0009] Another embodiment of this disclosure relates to a process for forming a semiconductor package. The process may include providing a first substrate comprising a first dielectric layer. The process includes covering a first surface of the first dielectric layer with a first adhesive layer comprising aluminum. The process includes providing a second substrate comprising a second dielectric layer. The process includes covering a second surface of the second dielectric layer with a second adhesive layer comprising alkoxysilane oxide. The process includes bonding the first substrate to the second substrate by forming a third adhesive layer by bonding the first adhesive layer and the second adhesive layer.

[0010] The process further includes coating the second surface with gaseous or liquid trimethylaluminum to form the second adhesive layer.

[0011] The process further includes coating the second surface with gaseous or liquid dimethylisopropyl alumina to form the second adhesive layer.

[0012] The process further includes coating the second surface with gaseous or liquid tris(tert-pentoxy)silicon (dimethylamide) to form the second adhesive layer.

[0013] The process further includes bringing the first adhesive layer into solid contact with the second adhesive layer; and annealing at least the contacted first adhesive layer and the second adhesive layer at an elevated temperature to form the third adhesive layer. The elevated temperature is less than approximately 500 degrees Celsius. Annealing at least the contacted first adhesive layer and the second adhesive layer catalyzes the rearrangement of the alkoxide coordination groups in the second adhesive layer via a β-removal process in the aluminum of the first adhesive layer.

[0014] Each of the first adhesive layer and the second adhesive layer has a thickness of less than about 2 nanometers.

[0015] The first dielectric layer embeds a first interconnect structure, and the first upper surface of the first interconnect structure is not covered by the first dielectric layer or the first adhesive layer. The second dielectric layer embeds a second interconnect structure, and the second upper surface of the second interconnect structure is not covered by the second dielectric layer or the second adhesive layer. Simultaneously with forming the third adhesive layer, the process further includes bringing the first upper surface of the first interconnect structure into solid contact with the second upper surface of the second interconnect structure.

[0016] Another embodiment of this disclosure relates to a process for forming a semiconductor package. This process may include forming a first dielectric layer on a first substrate, wherein the first dielectric layer embeds a first interconnect structure; covering a first surface of the first dielectric layer with a first adhesive layer comprising aluminum; forming a second dielectric layer on a second substrate, wherein the second dielectric layer embeds a second interconnect structure; covering a second surface of the second dielectric layer with a second adhesive layer comprising alkoxysilicon oxide; and connecting the first interconnect structure to the second interconnect structure based on bonding the first adhesive layer and the second adhesive layer.

[0017] The combination of the first adhesive layer and the second adhesive layer further includes bringing the first adhesive layer and the second adhesive layer into solid contact; and annealing at least the contacted first adhesive layer and the second adhesive layer at an elevated temperature to form a third adhesive layer comprising AlSiO.

[0018] The temperature rise is less than approximately 500 degrees Celsius.

[0019] These and other embodiments and practices are discussed in detail below. The above information and the following detailed description contain illustrative examples of various embodiments and practices, and provide an overview or framework for understanding the nature and characteristics of the claimed embodiments and practices. The drawings provide illustrations and further understanding of various embodiments and practices, and are incorporated into and constitute a part of this specification. Embodiments may be combined, and it will be readily understood that the features described in the context of one embodiment of the invention may be combined with other embodiments. Embodiments may be implemented in any convenient form. As used in the specification and claims, the singular forms of 'a', 'an', and 'the' include plural objects, unless the context expressly specifies otherwise. Simple Explanation of the Diagram

[0020] The non-limiting embodiments of this disclosure are illustrated by way of example and with reference to the accompanying drawings, which are schematic and not intended to be drawn to scale. Unless otherwise specified, these drawings represent embodiments of this disclosure. For clarity, every component may not be labeled in each drawing. In these drawings:

[0021] According to some embodiments, Figure 1 illustrates a flowchart of an exemplary method for fabricating a semiconductor package.

[0022] According to certain embodiments, Figures 2 to 6 illustrate various cross-sectional views of a semiconductor package manufactured by the method of Figure 1 during various processing stages.

[0023] According to some embodiments, Figure 7 illustrates a flowchart of another exemplary method for fabricating a semiconductor package. Implementation

[0024] Reference will now be made to the exemplary embodiments depicted in the drawings, and specific language will be used to describe these embodiments herein. However, it will be understood that this is not intended to limit the scope of the claims or this disclosure. Changes and further modifications to the inventive features illustrated herein, as well as additional applications of the principles of the subject matter illustrated herein, that may occur to those skilled in the art and with access to this disclosure, will be considered within the scope of the subject matter disclosed herein. Other embodiments and / or other variations may be used without departing from the spirit or scope of this disclosure. The exemplary embodiments described in the detailed description are not intended to limit the subject matter presented.

[0025] According to one implementation, a chemical bonding technique is used to form an adhesive layer, whereby each substrate is treated with a precursor, which can be selectively applied only to the dielectric regions. During bonding, these precursors chemically react with each other to create an adhesive layer between the substrates. Compared to some conventional bonding techniques, using a chemically driven process for adhesive formation can reduce the temperature. To avoid interfering with the metal-to-metal contacts used to interconnect the substrates, chemical surface treatments can be selectively applied to oxides or other insulating layers.

[0026] According to one process, a carrier wafer (or die) having an oxide surface over a semiconductor can be bonded to a substrate wafer (or die) having an oxide surface over a series of elements or surfaces. One of the oxide surfaces of the carrier oxide or the substrate oxide (but not both) is treated to form a thin layer containing Al. The other oxide surface is treated to form a thin surface layer containing Si alkoxide. As an example, due to the self-saturation of 1-2 monolayers, the Al-containing layer (preferably Al oxide) can be 1-2 nanometers (nm) thick, while the alkoxy-siloxide can be about 2 nm or less. However, the thickness of each of these layers can be less than 1 nm. The substrate and carrier are then bonded together by creating a solid contact between the oxide surfaces and annealing the substrate and carrier under pressure. During the annealing step under pressure, the Al system on the first oxide surface undergoes a beta-elimination process that catalyzes the rearrangement of alkoxide ligands to form Si-O-Si and Si-O-Al bonds via a process similar to sol-gel silicon oxide formation, as is well known to those skilled in the art. This process can be performed at relatively low temperatures (e.g., around 400-500°C or lower).

[0027] Figure 1 illustrates a flowchart of an exemplary method 100 for forming a semiconductor package having at least two couplings (e.g., adhesives) on a wafer, die, or substrate based on two different adhesive layers originally formed on two substrates. It should be noted that method 100 is merely an example and is not intended to limit the scope of this disclosure. Therefore, it is understood that additional operations may be provided before, during, and after method 100 of Figure 1, and only a brief description of some of these additional operations is provided herein.

[0028] In various embodiments, the operation of method 100 may be associated with cross-sectional views of exemplary semiconductor package 200 at various processing stages as shown in Figures 3 to 6, which will be discussed in more detail below. It should be understood that the semiconductor element 200 shown in Figures 3 to 6 may include several other elements (e.g., inductors, fuses, capacitors, coils, etc.) and remain within the scope of this disclosure.

[0029] According to various embodiments, in one of the various processing stages, corresponding to operation 102 in FIG1, FIG2 is a cross-sectional view of a semiconductor package 200, in which a first substrate 202 is provided with a plurality of first interconnect structures 210A, 210B, 210C and 210D.

[0030] The first substrate 202 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The first substrate 202 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the first substrate 202 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a composition thereof.

[0031] In some embodiments, the first substrate 202 includes a plurality of element features / structures 203 (e.g., transistors, diodes, resistors, etc., not shown for clarity) formed along the surface of the first substrate 202 (e.g., the front side) and a plurality of interconnect structures (e.g., metal lines, metal dielectrics, etc., not shown for clarity) formed on the element structures. The interconnect structures are configured to electrically connect the element structures to each other in order to form an integrated circuit that functions as a logic element, memory element, input / output element, etc. These interconnect structures (e.g., formed of conductive materials such as Cu, Al, W, Ti, TiN, Ta, TaN, or multiple layers or combinations thereof) may be embedded in one or more dielectric layers (e.g., formed of low-k dielectric materials such as SiO2), which are sometimes referred to as metallization layers, such as 204. In other words, each metallization layer 204 may include a plurality of metal lines and a plurality of metal dielectrics embedded therein. A plurality of such metallization layers 204 may be formed on the surface of the first substrate 202 (e.g., the front side).

[0032] Furthermore, a surface dielectric layer 206 is formed on the uppermost metallization layer among these metallization layers. In some embodiments, the surface dielectric layer 206, formed of one or more low-k dielectric materials (e.g., SiO2), has a plurality of first interconnect structures 210A to 210D disposed therein. The first interconnect structures 210A to 210D are formed using a damascene process, wherein the blanket dielectric material of the surface dielectric layer 206 is deposited on the workpiece (e.g., the uppermost metallization layer), and the dielectric material is patterned using a photolithography process. The patterned dielectric material is filled with a conductive material, and excess portions of the conductive material are removed from the top surface of the dielectric material using a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof. In other embodiments, a conductive material may be deposited and patterned using a lithography process, and a dielectric material of the surface dielectric layer 206 may be formed on the conductive material to form the first interconnect structures 210A to 210D using a subtractive etch process. Excess dielectric material is then removed from the first interconnect structures 210A to 210D using a CMP process, an etching process, or a combination thereof.

[0033] According to various embodiments, in one of the various processing stages, corresponding to operation 104 in FIG1, FIG3 is a cross-sectional view of a semiconductor package 200, in which a first adhesive layer 302 is selectively formed on a surface dielectric layer 206.

[0034] After forming the first interconnect structures 210A to 210D, at least one deposition process is performed to selectively form a first adhesive layer 302 on the surface dielectric layer 206. As shown, the first adhesive layer 302 may be formed only on the region where the surface dielectric layer 206 is present. In other words, the first adhesive layer 302 may not be formed on the exposed surface of any of the first interconnect structures 210A to 210D. In various embodiments, the first adhesive layer 302 comprising an alkoxysilicon oxide is formed by using a gas-phase or liquid-phase surface treatment on the surface dielectric layer 206. For example, tris(tert-pentoxy)silicon(dimethylamide) or similar compounds / composites may selectively react with OH groups on one or more surfaces of the surface dielectric layer 206 (e.g., portions of the surface of the surface dielectric layer 206 laterally adjacent to the exposed surfaces of the first interconnect structures 210A to 210D). In various embodiments, the first adhesive layer 302 may have a thickness of about 2 nanometers or less due to the self-saturation of 1-2 monolayers.

[0035] According to various embodiments, in one of the various processing stages, corresponding to operation 106 in FIG1, FIG4 is a cross-sectional view of a semiconductor package 200, in which a second substrate 402 is provided with a plurality of second interconnect structures 410A, 410B, 410C and 410D.

[0036] The second substrate 402 may be a semiconductor substrate, such as a host semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The second substrate 402 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the second substrate 402 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or compositions thereof.

[0037] In some embodiments, the second substrate 402 includes several element features / structures 403 (e.g., transistors, diodes, resistors, etc., not shown for clarity) formed along the surface of the second substrate 402 (e.g., the front side) and several interconnect structures (e.g., metal lines, metal dielectrics, etc., not shown for clarity) formed on the element structures. The interconnect structures are configured to electrically connect the element structures to each other to form an integrated circuit that functions as logic elements, memory elements, input / output elements, etc. These interconnect structures (e.g., formed of conductive materials such as Cu, Al, W, Ti, TiN, Ta, TaN, or multiple layers or combinations thereof) may be embedded in one or more dielectric layers (e.g., formed of low-k dielectric materials such as SiO2), which are sometimes referred to as metallization layers, such as 404. In other words, each metallization layer 404 may include several metal lines and several metal dielectrics embedded therein. A plurality of such metallization layers 404 may be formed on the surface of the second substrate 402 (e.g., the front side).

[0038] Furthermore, a surface dielectric layer 406 is formed on the uppermost metallization layer among these metallization layers. In some embodiments, the surface dielectric layer 406, formed of one or more low-k dielectric materials (e.g., SiO2), has several second interconnect structures 410A to 410D disposed therein. The second interconnect structures 410A to 410D are formed using a damascene process, wherein the overlay dielectric material of the surface dielectric layer 406 is deposited on a workpiece (e.g., the uppermost metallization layer), and the dielectric material is patterned using a photolithography process. The patterned dielectric material is filled with a conductive material, and excess portions of the conductive material are removed from the top surface of the dielectric material using a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof. In other embodiments, a conductive material may be deposited and patterned using a photolithography process, and the dielectric material of the surface dielectric layer 406 may be formed on the conductive material to form the second interconnect structures 410A to 410D using a subtractive etching process. Then, CMP, etching, or a combination thereof are used to remove excess dielectric material from the second interconnect structures 410A to 410D.

[0039] According to various embodiments, in one of the various processing stages, corresponding to operation 108 in FIG1, FIG5 is a cross-sectional view of a semiconductor package 200, in which a second adhesive layer 502 is selectively formed on the surface dielectric layer 406.

[0040] After forming the second interconnect structures 410A to 410D, at least one deposition process is performed to selectively form a second adhesive layer 502 on the surface dielectric layer 406. As shown, the second adhesive layer 502 may be formed only on the region where the surface dielectric layer 406 is present. In other words, the second adhesive layer 502 may not be formed on the exposed surface of any of the second interconnect structures 410A to 410D. In various embodiments, the second adhesive layer 502 comprising aluminum (Al) is formed by treating one or more surfaces of the surface dielectric layer 406 (e.g., portions of the surface of the surface dielectric layer 406 laterally adjacent to the exposed surfaces of the second interconnect structures 410A to 410D) with a liquid or gaseous Al precursor. For example, trimethyl aluminum or dimethyl aluminum isopropoxide may be used as the precursor. In various embodiments, the second adhesive layer 502 may have a thickness of about 1 nanometer to about 2 nanometers.

[0041] According to various embodiments, in one of the various processing stages, corresponding to operation 110 in FIG1, FIG6 is a cross-sectional view of a semiconductor package 200, in which a first substrate 202 (first semiconductor die) is coupled to a second substrate 402 (or second semiconductor die).

[0042] In some embodiments, a hybrid bonding process is used to bond the first semiconductor die together by coupling the top surface of the first semiconductor die (e.g., the top surface of the first adhesive layer 302) to the top surface of the second semiconductor die (e.g., the top surface of the second adhesive layer 502). For example, the second semiconductor die is inverted, i.e., rotated 180 degrees from the view shown in FIG6. Next, the first interconnect structures 210A to 210D of the first semiconductor die are aligned with the second interconnect structures 410A to 410D of the second semiconductor die, respectively. As an example, optical sensing can be used to complete the alignment of the first and second semiconductor dies. Also, a portion of the top surface of the first adhesive layer 302 (which rises from the top surfaces of the first interconnect structures 210A to 210D) is aligned with a portion of the top surface of the second adhesive layer 502 (which rises from the top surfaces of the second interconnect structures 410A to 410D).

[0043] After the alignment process of the first and second semiconductor wafers, pressure and heat are applied to mix and bond the first and second semiconductor wafers together. In various embodiments, the Al in the second adhesive layer 502 can catalyze the alkoxysilane oxide in the first adhesive layer 302 through β-H elimination, thereby forming a third adhesive layer 602 (e.g., containing AlSiO) bonded to and sandwiched between the substrates. In some embodiments, since the first adhesive layer 302 and the second adhesive layer 502 are each formed to have a thickness of less than 2 nanometers, the third adhesive layer 602 can have a thickness of less than about 4 nm. As an example, the applied pressure can include a pressure of less than about 30 MPa, and the applied heat can include an annealing process at a temperature of about 100 to 500 degrees Celsius; however, alternatively, other amounts of pressure and heat can be used in the mixing and bonding process. The mixed bonding process can be performed in the following environments: N2 environment, Ar environment, He environment, (about 4 to 10% H2) / (about 90 to 96% inert gas or N2) environment, inert gas mixture environment, combination thereof, or other types of environment.

[0044] The hybrid bonding process generates a third bonding layer 602 formed between surface dielectric layers 206 and 406, and the first interconnect structures 210A to 210D are respectively connected to the second interconnect structures 410A to 410D. That is, several non-metal-to-non-metal bonding systems (through the third bonding layer 602) are formed between portions of surface dielectric layers 206 and 406, and several metal-to-metal bonding systems are formed between the first interconnect structures 210A to 210D and the second interconnect structures 410A to 410D. For example, a portion of the hybrid bonding process may include a fusion process for forming non-metal-to-non-metal bonds, and a portion of the hybrid bonding process may include a copper-to-copper bonding process for forming metal-to-metal bonds. For example, the term "hybrid" refers to using a single bonding process to form two different types of bonds, rather than forming only one type of bond as in other types of wafer-to-wafer or die-to-die bonding processes.

[0045] Figure 7 illustrates a flowchart of another exemplary method 700 for forming a semiconductor package having at least two couplings (e.g., adhesives) on a wafer, die, or substrate based on two different adhesive layers originally formed on two substrates. Note that method 700 is substantially similar to method 100 of Figure 1, except that it may not include a hybrid adhesive process. Therefore, the operation of method 700 of Figure 7 can be briefly described below.

[0046] For example, method 700 begins at operation 702, in which a first substrate is provided. The first substrate may be covered by a first dielectric layer, which is formed of one or more low-k dielectric materials (e.g., SiO2). Method 700 continues to operation 704, in which a first adhesive layer is formed on the first substrate (e.g., in contact with the first dielectric layer). The first adhesive layer comprising an alkoxysilane oxide is formed by applying a gas-phase or liquid-phase surface treatment to the first dielectric layer. For example, tris(tert-pentoxy)silicon (dimethylamino)amine, or similar compounds / composite materials, may selectively react with OH groups on the top surface of the first dielectric layer. Method 700 continues to operation 706, in which a second substrate is provided. The second substrate may also be covered by a second dielectric layer, which is formed of one or more low-k dielectric materials (e.g., SiO2). Method 700 continues to operation 708, in which a second adhesive layer is formed on the second substrate (e.g., in contact with the second dielectric layer). The top surface of the second dielectric layer is treated with a liquid or gaseous Al precursor to form a second adhesive layer comprising aluminum (Al). For example, trimethylaluminum or dimethylisopropyl alumina can be used as the precursor. Method 700 then continues to operation 710, in which the first substrate is coupled to the second substrate based on the bonding of the first adhesive layer and the second adhesive layer. According to various embodiments, the bonded adhesive layer (e.g., a single adhesive layer) may comprise AlSiO.

[0047] In the foregoing description, specific details, such as the particular geometry of the processing system and the description of the various components and processes used herein, have been set forth. However, it should be understood that the technology herein may be implemented in other embodiments departing from these specific details, and such details are for illustrative purposes and not for limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for illustrative purposes, specific numbers, materials, and configurations have been set forth to provide a complete understanding. Nevertheless, embodiments may be implemented without such specific details. Components having substantially the same functional structure are indicated by similar reference numerals, and therefore any lengthy description may be omitted.

[0048] Various techniques have been described as multiple separate operations to aid in understanding the various embodiments. The order of description should not be construed as implying that these operations must depend on that order. These operations do not necessarily need to be performed in the presented order. The operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the operations may be omitted in additional embodiments.

[0049] According to this invention, the terms "substrate" or "target substrate" as used herein generally refer to the object being processed. A substrate may include any material portion or structure of an element (particularly a semiconductor or other electronic component), and may be, for example, a substrate structure such as a semiconductor wafer, a photomask, or a layer (e.g., a thin film) on or covering a substrate structure. Therefore, a substrate is not limited to any particular substrate structure, underlying layer, or overlay, whether patterned or unpatterned, but is considered to include any such layer or substrate structure, and any combination of layers and / or substrate structures. This description may refer to specific types of substrates, but this is for illustrative purposes only.

[0050] Those skilled in the art will also understand that many variations can be made to the operation of the techniques explained above while still achieving the same objective of the invention. Such variations are intended to be covered by the scope of this disclosure. In itself, the above description of the embodiments of the invention is not intended to be limiting. Any limitations on the embodiments of the invention are presented rather in the following claims.

[0051] 100: Method 102: Operation 104: Operation 106: Operation 108: Operation 110: Operation 200: Semiconductor package 202: First substrate 203: Component Features / Structure 204: Metallization layer 206: Surface dielectric layer 210A: First interconnect structure 210B: First interconnect structure 210C: First interconnect structure 210D: First interconnect structure 302: First adhesive layer 402: Second substrate 403: Component Features / Structure 404: Metallization layer 406: Surface dielectric layer 410A: Second interconnect structure 410B: Second Interconnect Structure 410C: Second interconnect structure 410D: Second interconnect structure 502: Second adhesive layer 602: Third adhesive layer 700: Method 702: Operation 704: Operation 706: Operation 708: Operation 710: Operation

Claims

1. A bonded semiconductor structure comprising: a first substrate, wherein the first substrate includes: a first dielectric layer disposed on the first substrate; and a first interconnect structure embedded in the first dielectric layer and having a first upper surface not covered by the first dielectric layer; a second substrate, wherein the second substrate includes: a second dielectric layer disposed on the second substrate; and a second interconnect structure embedded in the second dielectric layer and having a second upper surface not covered by the second dielectric layer; and an adhesive layer comprising AlSiO and bonding the first substrate to the second substrate; wherein the adhesive layer is sandwiched between the first dielectric layer and the second dielectric layer and does not cover the first upper surface of the first interconnect structure and the second upper surface of the second interconnect structure.

2. The bonded semiconductor structure as claimed in claim 1, wherein the first interconnect structure contacts the second interconnect structure, and the first upper surface and the second upper surface are in contact with each other.

3. The adhesive semiconductor structure as described in claim 2, wherein the adhesive layer surrounds a portion of a common sidewall of the first interconnect structure and the second interconnect structure in contact.

4. The adhesive semiconductor structure as described in claim 1, wherein the adhesive layer extends only between the first dielectric layer and the second dielectric layer.

5. The bonded semiconductor structure as claimed in claim 1, wherein the first substrate includes a first element structure covered by the first dielectric layer, wherein the first element structure is electrically coupled to the first interconnect structure, and wherein the second substrate includes a second element structure covered by the second dielectric layer, wherein the second element structure is electrically coupled to the second interconnect structure.

6. The adhesive semiconductor structure as described in claim 1, wherein the adhesive layer has a thickness of less than about 4 nanometers.

7. A process for forming an adhesive semiconductor structure, comprising: providing a first substrate including a first dielectric layer; covering a first surface of the first dielectric layer with a first adhesive layer comprising aluminum; providing a second substrate including a second dielectric layer; covering a second surface of the second dielectric layer with a second adhesive layer comprising alkoxysilicon oxide; and forming a third adhesive layer by bonding the first adhesive layer and the second adhesive layer to adhesively bond the first substrate to the second substrate.

8. The process for forming the bonded semiconductor structure as described in claim 7 further includes coating the second surface with gaseous or liquid trimethylaluminum to form the second adhesive layer.

9. The process for forming the bonded semiconductor structure as described in claim 7 further includes coating the second surface with gaseous or liquid dimethylisopropyl alumina to form the second adhesive layer.

10. The process for forming the bonded semiconductor structure as described in claim 7 further includes coating the second surface with gaseous or liquid tris(tert-pentoxy)silicon (dimethylamide) to form the second adhesive layer.

11. The process for forming the bonded semiconductor structure as described in claim 7 further includes: bringing the first adhesive layer into physical contact with the second adhesive layer; and annealing at least the first adhesive layer and the second adhesive layer in contact at an elevated temperature to form the third adhesive layer.

12. The process for forming a bonded semiconductor structure as described in claim 11, wherein the temperature rise is less than about 500 degrees Celsius.

13. The process for forming an adhesive semiconductor structure as described in claim 11, wherein at least the first adhesive layer and the second adhesive layer are annealed to catalyze the rearrangement of the alkoxide ligands of the second adhesive layer via a β-removal process.

14. The process for forming an adhesive semiconductor structure as described in claim 7, wherein each of the first adhesive layer and the second adhesive layer has a thickness of more than about 2 nanometers (nm).

15. The process of forming an adhesive semiconductor structure as described in claim 7, wherein the first dielectric layer embeds a first interconnect structure and the first upper surface of the first interconnect structure is not covered by the first dielectric layer or the first adhesive layer, and the second dielectric layer embeds a second interconnect structure and the second upper surface of the second interconnect structure is not covered by the second dielectric layer or the second adhesive layer.

16. The process of forming the bonded semiconductor structure as described in claim 15 further includes, while forming the third adhesive layer, bringing the first upper surface of the first interconnect structure into physical contact with the second upper surface of the second interconnect structure.

17. A process for forming an adhesive semiconductor structure, comprising: forming a first dielectric layer on a first substrate, wherein the first dielectric layer embeds a first interconnect structure; covering a first surface of the first dielectric layer with a first adhesive layer comprising aluminum; forming a second dielectric layer on a second substrate, wherein the second dielectric layer embeds a second interconnect structure; covering a second surface of the second dielectric layer with a second adhesive layer comprising alkoxysilicon oxide; and connecting the first interconnect structure to the second interconnect structure based on bonding the first adhesive layer and the second adhesive layer.

18. The process for forming an adhesive semiconductor structure as described in claim 17, wherein bonding the first adhesive layer and the second adhesive layer further comprises: bringing the first adhesive layer and the second adhesive layer into physical contact; and annealing at least the contacted first adhesive layer and the second adhesive layer at an elevated temperature to form a third adhesive layer comprising AlSiO.

19. The process for forming a bonded semiconductor structure as described in claim 18, wherein the temperature rise is less than about 500 degrees Celsius.

Images