Latch circuit, transmission circuit including latch circuit, and semiconductor apparatus including transmission circuit

Abstract

This technology may include: a first detection unit configured to generate an output signal during normal read operations by detecting the level of an input terminal in response to a change in a control clock signal; and a second detection unit configured to generate an output signal during status information read operations by detecting the level of an input terminal independently of a change in a control clock signal.

Description

Technical Field

[0001] The various embodiments generally relate to a semiconductor circuit, and more specifically, to a latch circuit, a transmission circuit including the latch circuit, and a semiconductor device including the transmission circuit. Prior Technology

[0002] Semiconductor devices (e.g., semiconductor memory devices) can store externally supplied data in a memory area and output the data stored in the memory area to the outside of the semiconductor memory device. A problem with semiconductor memory devices is that as the operating speed increases (i.e., as the operating frequency increases), the layout margin of the circuitry associated with data output decreases, and current consumption increases. Summary of the Invention

[0003] A latching circuit according to one embodiment of the present invention may include: a first detection unit configured to generate an output signal by detecting the level of an input terminal in response to a transition of a control clock signal during a normal read operation; and a second detection unit configured to generate an output signal by detecting the level of an input terminal independently of a transition of a control clock signal during a status information read operation.

[0004] A latching circuit according to one embodiment of the present invention may include: a cross-connected latch configured to latch the level of an input terminal in response to a change in a control clock signal and to output the latched data through an output terminal; and a switch portion connected between the output terminal and the input terminal and configured to output the status information input through the input terminal through the output terminal in response to a status information read signal, regardless of the change in the control clock signal.

[0005] A transmission circuit according to one embodiment of the present invention may include: a latch circuit configured to generate an output signal during a normal read operation by detecting the level of data input through a plurality of differential input terminals according to a transition of a control clock signal, and configured to generate an output signal during a status information read operation by detecting the level of status information input through the plurality of differential input terminals independently of a transition of the control clock signal; and a serializer configured to be connected in series and output an output signal.

[0006] A semiconductor device according to one embodiment of the present invention may include: a memory cell array configured to store normal data; a control circuit configured to generate a control signal including a multiphase clock signal in response to an external clock signal, and configured to output internally stored state information in response to a state information read command; an input / output terminal unit; and a transmission circuit configured to generate an output signal by detecting the level of normal data input through a plurality of differential input terminals according to a transition of the control clock signal, and configured to generate an output signal during a state information read operation by detecting the level of state information input through the plurality of differential input terminals independently of a transition of the control clock signal, and to output the output signal to an external device through the input / output terminal unit. Simple Explanation of the Diagram

[0007] Figure 1 is a diagram showing the configuration of a semiconductor system 10 according to an embodiment of the present invention.

[0008] Figure 2 is a diagram showing the configuration of a semiconductor device 100 according to an embodiment of the present invention.

[0009] Figure 3 is a diagram illustrating the configuration of a transmission circuit 200 according to an embodiment of the present invention.

[0010] Figure 4 is a diagram showing the configuration of the first latch circuit 210 in Figure 3.

[0011] Figure 5 is a diagram showing the configuration of the second latch circuit 220 in Figure 3.

[0012] Figure 6 is a diagram showing the configuration of the clock control circuit 230 in Figure 3.

[0013] Figure 7 is a diagram illustrating the configuration of a transmission circuit 300 according to another embodiment of the present invention.

[0014] Figure 8 is a diagram showing the configuration of the latch circuit 310 in Figure 7.

[0015] Figure 9 is a diagram showing the configuration of the clock control circuit 330 in Figure 7.

[0016] Figure 10 is the timing diagram of the clock control circuit 330 in Figure 9. Implementation

[0017] In the following description, embodiments of the invention will be described in more detail with reference to the accompanying drawings.

[0018] Various embodiments are intended to provide a latch circuit, a transmission circuit including the latch circuit, and a semiconductor device including the transmission circuit, which can increase layout margin and reduce current consumption.

[0019] Figure 1 is a diagram showing the configuration of a semiconductor system 10 according to an embodiment of the present invention.

[0020] Referring to FIG1, a semiconductor system 10 according to an embodiment of the present invention may include a semiconductor device 100 and a controller 101. The semiconductor device 100 may operate under the control of the controller 101. The semiconductor device 100 may operate according to a command CMD provided from the controller 101. The command CMD may include a write command, a read command, and a status information read command. The semiconductor device 100 may write data to a memory cell array in response to a write command provided from the controller 101. The semiconductor device 100 may perform a read operation in response to a read command provided from the controller 101. When receiving a read command and an address from the controller 101, the semiconductor device 100 may read data corresponding to the address in the memory cell array and may output the read data to the controller 101. The semiconductor device 100 may perform a status information read operation in response to a status information read command provided from the controller 101. When receiving a status information read command from the controller 101, the semiconductor device 100 may read status information from a register (hereinafter referred to as a status information register) separately from the memory cell array and may output the read status information to the controller 101.

[0021] Semiconductor device 100 may include at least one of NAND flash memory, vertical NAND (hereinafter referred to as VNAND) flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc. The semiconductor device 100 of the present invention can be implemented as a three-dimensional array structure. The present invention can be applied not only to flash memory devices in which the charge storage layer is configured as a conductive floating gate, but also to charge trap flash memory (CTF) in which the charge storage layer is configured as an insulating film.

[0022] Controller 101 can be connected between semiconductor device 100 and host computer. Host computer may include CPU, GPU, etc. Controller 101 can be configured to enable interface connection between host computer and semiconductor device 100. Controller 101 can send write commands and read commands to semiconductor device 100 under the control of host computer.

[0023] Between the controller 101 and the semiconductor device 100, signal lines for transmitting data DQ, data strobe signal DQS, and an external clock signal (hereinafter referred to as the clock signal) CLK can be connected. The data strobe signal DQS can be a bidirectional signal. During the data output operation of the semiconductor device 100, the semiconductor device 100 can provide the data strobe signal DQS to the controller 101. During the read operation of the semiconductor device 100, the controller 101 can provide the data strobe signal DQS to the semiconductor device 100.

[0024] Figure 2 is a diagram showing the configuration of a semiconductor device 100 according to an embodiment of the present invention.

[0025] Referring to Figure 2, the semiconductor device 100 may include a memory cell array 110, peripheral circuitry 120, control circuitry 130, and input / output terminal units 140. Peripheral circuitry 120 may include an address decoder 121, a voltage generator 122, read / write circuitry 123, and data input / output circuitry 124.

[0026] The input / output terminal unit 140 can receive commands CMD, addresses ADD, and clock signals CLK, and includes multiple terminals 141 for input / output data DQ.

[0027] The memory cell array 110 can be connected to the address decoder 121 via column lines RL and to the read / write circuitry 123 via bit lines BL1 to BLm. The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. These memory cells may be non-volatile memory cells. Each memory block included in the memory cell array 110 may include multiple pages. A page may be defined as a memory cell connected to substantially the same word line among the multiple memory cells. The multiple memory blocks BLK1 to BLKz may store normal data, i.e., data sent and received through normal read and write operations.

[0028] Each memory cell of the semiconductor device 100 can be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0029] Peripheral circuitry 120 can drive memory cell array 110 to perform programming operations, read operations, and erase operations.

[0030] Address decoder 121 can be connected to memory cell array 110 via column line RL. Address decoder 121 can be configured to operate in response to control of control circuitry 130. Address decoder 121 can receive address ADD from control circuitry 130.

[0031] Address decoder 121 can decode block addresses in address ADD. Address decoder 121 can select at least one memory block from memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can be configured to decode column addresses in received address ADD. Address decoder 121 can select at least one word line of the selected memory block by applying a voltage received from voltage generator 122 to at least one word line WL based on the decoded column address.

[0032] Address decoder 121 can perform programming operations by applying a programming voltage Vpgm to the selected word line and applying a pass voltage Vpass, which has a lower level than the programming voltage, to the unselected word line.

[0033] Address decoder 121 can perform a read operation by applying a read voltage Vread to a selected word line and a pass voltage Vpass, which has a higher level than the read voltage Vread, to an unselected word line.

[0034] Erasing operations on the semiconductor device 100 can be performed on a block-by-block basis. The address decoder 121 can decode the block address and select a memory block based on the decoded block address. The address decoder 121 can perform the erasure operation by applying a ground voltage to the word line input to the selected memory block and applying an erase voltage Vers to the bulk area where the selected memory block is formed.

[0035] Voltage generator 122 can generate various voltages required for the operation of semiconductor device 100. Voltage generator 122 can generate read voltage Vread, pass voltage Vpass, programmable voltage Vpgm, erase voltage Vers, etc., and provide the generated voltages to address decoder 121. For example, voltage generator 122 may include multiple pump capacitors, and multiple voltages can be generated by selectively activating multiple pump capacitors under the control of control circuitry 130.

[0036] The read / write circuit 123 may include multiple page buffers (e.g., multiple page buffers PB1 to PBm). The multiple page buffers PB1 to PBm may be connected to the memory cell array 110 via first bit line BL1 to m-th bit line BLm, respectively. The multiple page buffers PB1 to PBm may operate in response to a control signal CTRL received from the control circuit 130.

[0037] Multiple page buffers PB1 to PBm can communicate with the data input / output circuit 124. The multiple page buffers PB1 to PBm can receive data to be stored through the data input / output circuit 124 and data lines, and transfer the received data to the memory cell array 110, thereby performing programming operations. The read / write circuit 123 can read data from the memory cell of a selected page through the bit line BL, and output the read data to the data input / output circuit 124, thereby performing a read operation. The read / write circuit 123 can perform an erase operation by floating the bit line BL.

[0038] Data input / output circuit 124 can be connected between multiple page buffers PB1 to PBm and input / output terminal unit 140. Data input / output circuit 124 can perform data input and output operations in response to the control signal CTRL received from control circuit 130. During a read operation, data input / output circuit 124 can output data transferred from multiple memory blocks BLK1 to BLKz via multiple page buffers PB1 to PBm to controller 101 through input / output terminal unit 140. During a write operation, data input / output circuit 124 can transfer data input from controller 101 through input / output terminal unit 140 to multiple page buffers PB1 to PBm. During a status information read operation, data input / output circuit 124 can output status information transmitted from control circuit 130 to controller 101 through input / output terminal unit 140.

[0039] Control circuit 130 can be connected to address decoder 121, voltage generator 122, read / write circuit 123, data input / output circuit 124, and input / output terminal unit 140. Control circuit 130 can receive command CMD, address ADD, and clock signal CLK through input / output terminal unit 140. Control circuit 130 may include a division circuit, which can generate multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB by phase-separating and dividing the clock signal CLK. Multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB may have frequencies, for example, corresponding to half the frequency of clock signal CLK. Control circuit 130 can generate a control signal CTRL for controlling the overall operation of semiconductor device 100 according to command CMD. Control signal CTRL may include at least one of the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB. Command CMD may include a read command, a write command, and a status information read command. Control circuit 130 may include a status information register 131. Control circuit 130 may read status information SR stored in status information register 131 in response to a status information read command provided by controller 101, and output the read status information SR to data input / output circuit 124. The status information SR output from control circuit 130 may be provided to controller 101 via data input / output circuit 124 and input / output terminal unit 140. Status information SR may include multiple data bits. Each of the multiple data bits may define whether the most recently entered command has been executed normally, whether a previously entered command has been executed normally, whether there is an ongoing operation, whether there is an operation currently in standby, etc., thereby allowing controller 101, which has received status information SR, to determine the operating state of semiconductor device 100.

[0040] Figure 3 is a diagram showing the configuration of a transmission circuit 200 according to an embodiment of the present invention.

[0041] The transmission circuit 200 may be included in the data input / output circuit 124 in FIG2.

[0042] Referring to FIG3, the transmission circuit 200 performs data transmission by latching and serializing data according to a predetermined timing sequence and driving the terminals of the input / output terminal unit 140 according to the serialized signal.

[0043] The transmission circuit 200 may include a first latch circuit 210, a second latch circuit 220, a clock control circuit 230, a serializer 240, a buffer 250, and a driver 260.

[0044] The first latch circuit 210 can generate a first output signal DLT1<0:N-1> by latching data D<0:N-1> according to the first control clock signals CLKCA<0:N-1> and CLKCAb<0:N-1>. The first latch circuit 210 can be implemented as a level trigger circuit that causes an output change based on the current level of the state variables (i.e., the input signals and / or the clock signals).

[0045] The second latch circuit 220 can generate second output signals DLT2<0:N-1> and DLT2B<0:N-1> using the first output signal DLT1<0:N-1> according to the second control clock signal CLKCB<0:N-1> and the third control clock signal CLKCC<0:N-1>. The second latch circuit 220 can be implemented as a level trigger circuit.

[0046] The clock control circuit 230 can generate first control clock signals CLKCA<0:N-1> and CLKCAb<0:N-1>, second control clock signal CLKCB<0:N-1>, and third control clock signal CLKCC<0:N-1> using multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB based on multiple clock enable signals CLKEN<0:N-1>, status information read enable signal SRENB, and bypass signal BYPS. The status information read enable signal SRENB and bypass signal BYPS can be generated based on a status information read command.

[0047] The serial converter 240 can be connected in series and output second output signals DLT2<0:N-1> and DLT2B<0:N-1>.

[0048] Buffer 250 can pre-drive and output the output of serial unit 240.

[0049] The driver 260 can drive the terminals of the input / output terminal unit 140 according to the output of the buffer 250.

[0050] Figure 4 is a diagram showing the configuration of the first latch circuit 210 in Figure 3.

[0051] Referring to FIG4, the first latch circuit 210 may include a plurality of latching units 210-1 to 210-N for generating a first output signal DLT1<0:N-1> respectively by latching data D<0:N-1>. Since the plurality of latching units 210-1 to 210-N may be configured identically to each other, only the configuration of latching unit 210-1 is shown and will be described only.

[0052] The latch unit 210-1 may include a first logic gate 211 to a third logic gate 213. The first logic gate 211 can be based on a first control clock signal CLKCA. <0> and CLKCAb <0> And make data D <0> Invert the output and output inverted data. When the first control clock signal CLKCA... <0> and CLKCAb <0> When the data is at the low level and the high level respectively, the first logic gate 211 can convert the data D... <0> Invert and output. The second logic gate 212 can generate the first output signal DLT1 by inverting the output of the first logic gate 211. <0> The third logic gate 213 can be based on the first control clock signal CLKCA. <0> and CLKCAb <0> This latches the output of the second logic gate 212. When the first control clock signal CLKCA... <0> and CLKCAb <0> When in the high-level and low-level positions respectively, the third logic gate 213 can latch the output of the second logic gate 212.

[0053] When the first control clock signal CLKCA <0> and CLKCAb <0> When the latch unit 210-1 is basically maintained at the low level and the high level respectively, it can latch the data D <0> Bypass without latching data D <0> .

[0054] Although not shown in Figure 4, when the signals of the first control clock signals CLKCA<0:N-1> and CLKCAb<0:N-1> corresponding to other latching units 210-2 to 210-N repeatedly change, the other latching units 210-2 to 210-N can latch the data bits in data D<0:N-1> corresponding to other latching units 210-2 to 210-N. When the signals of the first control clock signals CLKCA<0:N-1> and CLKCAb<0:N-1> corresponding to other latching units 210-2 to 210-N remain basically at a predetermined level, the other latching units 210-2 to 210-N can bypass the data bits in data D<0:N-1> corresponding to other latching units 210-2 to 210-N without latching the data bits. For example, when the first control clock signal CLKCA... <n-1>and CLKCAb <n-1>During repeated transitions, latch unit 210-N can latch data D. <n-1>And when the first control clock signal CLKCA <n-1>and CLKCAb <n-1>Basically maintaining the predetermined position and timing, the latch unit 210-N can monitor data D. <n-1>Bypass without latching data D <n-1>As described above, the first latch circuit 210 can be called a level trigger circuit, which operates using a level triggering method that changes the output level based on the level of the clock signal rather than the transition of the clock signal.

[0055] Figure 5 is a diagram showing the configuration of the second latch circuit 220 in Figure 3.

[0056] Referring to FIG5, the second latch circuit 220 may include a plurality of latching units 220-1 to 220-N for generating second output signals DLT2<0:N-1> and DLT2B<0:N-1> respectively by latching the first output signal DLT1<0:N-1>. Since the plurality of latching units 220-1 to 220-N may be configured identically to each other, only the configuration of latching unit 220-1 is shown and will be described only.

[0057] The latch unit 220-1 may include multiple transistors 221-1 to 221-9 and 222-1 to 222-3, as well as an inverter 223. In the first transistor 221-1, a first electrode may be connected to a second node N2, a second electrode may be connected to a power supply terminal VCCQ, and a third electrode may be connected to a first node N1. The first, second, and third electrodes may be one of a gate terminal, a source terminal, and a drain terminal, respectively. In one embodiment of the invention, it is assumed that the first electrode is a gate terminal, the second electrode is a source terminal, and the third electrode is a drain terminal. In the second transistor 221-2, the first electrode may receive a second control clock signal CLKCB. <0> Furthermore, the third electrode can be connected to the first node N1. The voltage level of the third electrode of the second transistor 221-2 can be used as the second output signal DLT2. <0> Output. Inverter 223 can output the first output signal DLT1. <0> Inverting and outputting. In the third transistor 221-3, the first electrode can receive the output of the inverter 223, and the third electrode can be connected to the second electrode of the second transistor 221-2. In the fourth transistor 221-4, the first electrode can receive the second control clock signal CLKCB. <0> The second electrode can be connected to the power supply terminal VCCQ, and the third electrode can be connected to the first node N1. In the fifth transistor 221-5, the first electrode can be connected to the first node N1, the second electrode can be connected to the power supply terminal VCCQ, and the third electrode can be connected to the second node N2. In the sixth transistor 221-6, the first electrode can receive the second control clock signal CLKCB. <0> Furthermore, the third electrode can be connected to the second node N2. The voltage level of the third electrode of the sixth transistor 221-6 can be used as the second output signal DLT2B. <0> Output. In the seventh transistor 221-7, the first electrode can receive the first output signal DLT1. <0> Furthermore, the third electrode can be connected to the second electrode of the sixth transistor 221-6. In the eighth transistor 221-8, the first electrode can receive the second control clock signal CLKCB. <0> The second electrode can be connected to the power supply terminal VCCQ, and the third electrode can be connected to the second node N2. In the ninth transistor 221-9, the first electrode can receive the second control clock signal CLKCB. <0> The second electrode (or the third electrode) can be connected to the first node N1, and the third electrode (or the second electrode) can be connected to the second node N2. In the tenth transistor 222-1, the first electrode can receive the third control clock signal CLKCC. <0> The second electrode can be connected to the ground terminal, and the third electrode can be connected together to the second electrode of the third transistor 221-3 and the second electrode of the seventh transistor 221-7.In the eleventh transistor 222-2, the first electrode can receive the third control clock signal CLKCC. <0> The second electrode can be connected to the power supply terminal VCCQ, and the third electrode can be connected to the first node N1. In the twelfth transistor 222-3, the first electrode can receive the third control clock signal CLKCC. <0> The second electrode can be connected to the power supply terminal VCCQ, and the third electrode can be connected to the second node N2.

[0058] When the second control clock signal CLKCB <0> When at a low level, latch unit 220-1 can precharge the first node N1 and the second node N2 to the level of power supply terminal VCCQ, and in the second control clock signal CLKCB <0> and the third control clock signal CLKCC <0> During the high-level quasi-period, according to the first output signal DLT1 <0> Level change of the second output signal DLT2 <0> and DLT2B <0> The bit level. Other latch units 220-2 to 220-N can operate in essentially the same way as latch unit 220-1. For example, when the second control clock signal CLKCB... <n-1>When at a low level, latch unit 220-N can precharge the first node N1 and the second node N2 to the level of power supply terminal VCCQ, and in the second control clock signal CLKCB <n-1>and the third control clock signal CLKCC <n-1>During the high-level quasi-time period, it can be based on the first output signal DLT1 <n-1>The level of the second output signal DLT2 is used to change the level of the second output signal. <n-1>and DLT2B <n-1>The level. As described above, the second latch circuit 220 can be called a level trigger circuit because it operates using a level triggering method that changes the output level based on the level of the clock signal rather than the transition of the clock signal.

[0059] Figure 6 is a schematic diagram showing the configuration of the clock control circuit 230 in Figure 3.

[0060] Referring to Figure 6, the clock control circuit 230 may include multiple clock control units 230-1 to 230-N for generating first control clock signals CLKCA<0:N-1> and CLKCAb<0:N-1>, a second control clock signal CLKCB<0:N-1>, and a third control clock signal CLKCC<0:N-1> using multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB according to multiple clock enable signals CLKEN<0:N-1>, a status information read enable signal SRENB, and a bypass signal BYPS. Since the multiple clock control units 230-1 to 230-N can be configured identically to each other, only the configuration of clock control unit 230-1 is shown and will be described.

[0061] Multiple clock enable signals CLKEN<0:N-1> can be signals used to control the activation of multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB, and can correspond to the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB respectively. For example, when N is 4, CLKEN <0> It can correspond to ICLK, CLKEN <1> It can correspond to QCLK, CLKEN <2> It can correspond to ICLKB, and CLKEN <3> This can correspond to QCLKB. The status information read enable signal SRENB is a signal generated based on the status information read operation, and can be generated at a low level during the status information read operation. The bypass signal BYPS can also be a signal generated based on the status information read operation, and can be generated at a high level during the status information read operation.

[0062] The clock control unit 230-1 may include multiple logic gates 231-1 to 231-9. The first logic gate 231-1 can handle any one of the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB (e.g., ICLK) and the clock enable signal CLKEN. <0> The first logic gate 231-1 performs a NAND operation on the state information read enable signal SRENB and the output of the first logic gate 231-1, and outputs the NAND signal. The second logic gate 231-2 performs a NAND operation on the state information read enable signal SRENB and the output of the first logic gate 231-1, and outputs the NAND signal. The third logic gate 231-3 inverts the bypass signal BYPS and outputs it. The fourth logic gate 231-4 performs a NAND operation on the outputs of the second logic gate 231-2 and the third logic gate 231-3 to generate the first control clock signal CLKCAb. <0> The fifth logic gate 231-5 can invert the output of the fourth logic gate 231-4 to generate the first control clock signal CLKCA. <0> The sixth logic gate 231-6 and the seventh logic gate 231-7 can buffer the output of the second logic gate 231-2 to generate the second control clock signal CLKCB. <0> The eighth logic gate 231-8 and the ninth logic gate 231-9 can buffer the output of the first logic gate 231-1 to generate the third control clock signal CLKCC. <0> .

[0063] During normal read operations of the semiconductor device 100, multiple parallel data need to be latched based on the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB, and the multiple parallel data are output to the outside of the semiconductor device 100. During normal read operations, the status information read enable signal SRENB is at a high level, and the bypass signal BYPS is at a low level. Therefore, the clock control circuit 230 can cause the first control clock signals CLKCA<0:N-1> and CLKCAb<0:N-1>, the second control clock signal CLKCB<0:N-1>, and the third control clock signal CLKCC<0:N-1> to repeatedly change in response to the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB. Therefore, the transmission circuit 200 can latch and serialize parallel data D<0:N-1> according to the timing of the multiphase clock signals ICLK, QCLK, ICLKB and QCLKB, and drive the terminals of the input / output terminal unit 140 according to the serialized signals, thereby performing data transmission.

[0064] Meanwhile, the status information reading operation of the semiconductor device 100 may only include the operation of sequentially outputting serial status information, and is independent of the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB. During the status information reading operation, the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB may be fixed at a predetermined level (e.g., a high level), the status information reading enable signal SRENB may be at a low level, and the bypass signal BYPS may be at a high level. Therefore, the clock control circuit 230 may substantially maintain the first control clock signal CLKCA<0:N-1> at a low level, substantially maintain the first control clock signal CLKCAb<0:N-1> at a high level, and substantially maintain the second control clock signal CLKCB<0:N-1> and the third control clock signal CLKCC<0:N-1> at a high level. Therefore, the first latch circuit 210 can bypass the parallel data D<0:N-1> without performing a latching operation, and the second latch circuit 220 can also generate the second output signals DLT2<0:N-1> and DLT2B<0:N-1> according to the level of the first output signal DLT1<0:N-1> without performing a latching operation. Since the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB are fixed at a high level, the second output signals DLT2<0:N-1> and DLT2B<0:N-1> are driven to the input / output terminal unit 140 via the serializer 240, the buffer 250, and the driver 260, thereby enabling status information transmission.

[0065] Figure 7 is a diagram illustrating the configuration of a transmission circuit 300 according to another embodiment of the present invention.

[0066] The transmission circuit 300 may be included in the data input / output circuit 124 in FIG2.

[0067] Referring to Figure 7, the transmission circuit 300 can perform data transmission by latching and serializing data according to a predetermined timing sequence and driving the terminals of the input / output terminal unit 140 according to the serialized signal.

[0068] The transmission circuit 300 may include a latch circuit 310, a clock control circuit 330, a serializer 340, a buffer 350, and a driver 360. The transmission circuit 300 may also include a logic gate 370 for generating an inverted state information read enable signal SREN by inverting the state information read enable signal SRENB.

[0069] The latch circuit 310 can latch data D<0:N-1> by reading the enable signal SRENB and the control clock signal CLK_CHOP<0:N-1> according to the state information, thereby generating output signals DLT<0:N-1> and DLTB<0:N-1>. The latch circuit 310 can be configured to support both edge-triggered operation and the aforementioned level-triggered operation. By reading the enable signal SRENB according to the state information, it can switch to one of the level-triggered circuit operation and the edge-triggered circuit operation. The edge-triggered method can change the output level according to the input level in response to state variables (i.e., the rising or falling edge of the clock signal), and can achieve stable signal processing at a higher operating frequency than that in the level-triggered method.

[0070] The clock control circuit 330 can generate a control clock signal CLK_CHOP<0:N-1> based on multiple clock enable signals CLKEN<0:N-1> and multi-phase clock signals ICLK, QCLK, ICLKB and QCLKB.

[0071] The serial converter 340 can be connected in series and output signals DLT<0:N-1> and DLTB<0:N-1>.

[0072] The buffer 350 can pre-drive and output the output of the serial unit 340.

[0073] The driver 360 can drive the terminals of the input / output terminal unit 140 according to the output of the buffer 350.

[0074] Figure 8 is a diagram showing the configuration of the latch circuit 310 in Figure 7.

[0075] The latch circuit 310 can be configured to generate output signals DLT<0:N-1> and DLTB<0:N-1> by detecting the level of data D<0:N-1> in response to the transition of the control clock signal CLK_CHOP<0:N-1> during normal read operations, and to generate output signals DLT<0:N-1> and DLTB<0:N-1> by detecting the level of data D<0:N-1> in response to the transition of the control clock signal CLK_CHOP<0:N-1> during status information read operations.

[0076] The latch circuit 310 may include a first detection unit and a second detection unit. The first detection unit is configured to generate output signals DLT<0:N-1> and DLTB<0:N-1> by detecting the level of data D<0:N-1> in response to the transition of the control clock signal CLK_CHOP<0:N-1> during normal read operations. The second detection unit is configured to generate output signals DLT<0:N-1> and DLTB<0:N-1> by detecting the level of data D<0:N-1> independently of the transition of the control clock signal CLK_CHOP<0:N-1> during status information read operations.

[0077] Referring to FIG8, the latch circuit 310 may include a plurality of latch units 310-1 to 310-N. Since the plurality of latch units 310-1 to 310-N may be configured identically to each other, the configuration of latch unit 310-1 is shown and will be described.

[0078] The latch unit 310-1 may include differential input terminals 321 to 323, a current sink 324, a cross-connected latch 311, and switching sections 325 and 326.

[0079] Differential input terminals 321 to 323 may include a first transistor 321, a second transistor 322, and a logic gate 323. The logic gate 323 can control data D. <0> Invert to produce an inverted DB <0> .

[0080] The current drawer 324 can be configured as a transistor and can be controlled according to the control clock signal CLK_CHOP. <0> Connect the differential input terminals 321 to 323 and the ground terminal to connect or disconnect the current path of the latch unit 310-1.

[0081] The cross-connect latch 311 can respond to the control clock signal CLK_CHOP <0> The output signal DLT is generated by detecting the level of the differential input terminals 321 to 323 during the transition. <0> and DLTB <0> Furthermore, the output signal DLT can be output via differential output terminals N11 and N12. <0> and DLTB <0> The cross-connect latch 311 may include multiple transistors 312 to 317. Differential output terminals N11 and N12 may include a first node N11 and a second node N12. In the first transistor 312, a first electrode may be connected to the second node N12, a second electrode may be connected to the power supply terminal VCCQ, and a third electrode may be connected to the first node N11. In the second transistor 313, a first electrode may be connected to the second node N12 and the first electrode of the first transistor 312, a third electrode may be connected to the first node N11, and a second electrode may be connected to the first transistor 321 in the differential input terminals 321 to 323. In the third transistor 314, the first electrode may receive the control clock signal CLK_CHOP. <0> The second electrode can be connected to the power supply terminal VCCQ, and the third electrode can be connected to the first node N11. In the fourth transistor 315, the first electrode can be connected to the first node N11, the second electrode can be connected to the power supply terminal VCCQ, and the third electrode can be connected to the second node N12 and the first electrode of the first transistor 312. In the fifth transistor 316, the first electrode can be connected to the first node N11 and the first electrode of the fourth transistor 315, the third electrode can be connected to the second node N12, and the second electrode can be connected to the second transistor 322 among the differential input terminals 321 to 323. In the sixth transistor 317, the first electrode can receive the control clock signal CLK_CHOP. <0> The second electrode can be connected to the power supply terminal VCCQ, and the third electrode can be connected to the second node N12. The third transistor 314 can operate as the first detection unit, and the sixth transistor 317 can operate as the second detection unit.

[0082] Switches 325 and 326 can be connected between differential input terminals 321 to 323 and differential output terminals N11 and N12, and can be configured to change the levels of differential output terminals N11 and N12 according to the level changes of differential input terminals 321 to 323 when the inverted state information read enable signal SREN is at a high level, in conjunction with the control clock signal CLK_CHOP. <0> The transition is irrelevant. Switching sections 325 and 326 may include a first switch 325 connected between the first node N11 and the first transistor 321 in the differential inputs 321 to 323, and a second switch 326 connected between the second node N12 and the second transistor 322 in the differential inputs 321 to 323.

[0083] Other latch units 310-2 to 310-N can operate in essentially the same manner as latch unit 310-1. For example, when the inverted state information read enable signal SREN is at a low level, latch unit 310-N can respond to the control clock signal CLK_CHOP. <n-1>The output signal DLT is generated by latching the levels of the differential input terminals 321 to 323 during the transition. <n-1>and DLTB <n-1>The output signal DLT is output through differential output terminals N11 and N12. <n-1>and DLTB <n-1>When the inverted state information read enable signal SREN is at a high level, the latch unit 310-N can change the level of the differential output terminals N11 and N12 according to the level changes of the differential input terminals 321 to 323, regardless of the transition of the control clock signal CLK_CHOP<0:N-1>.

[0084] Figure 9 is a diagram showing the configuration of the clock control circuit 330 in Figure 7, and Figure 10 is an operation timing diagram of the clock control circuit 330 in Figure 9.

[0085] Referring to Figure 9, the clock control circuit 330 may include multiple clock synthesis units 330-1 to 330-N for generating a control clock signal CLK_CHOP<0:N-1> by selectively combining multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB according to multiple clock enable signals CLKEN<0:N-1>. Since the multiple clock synthesis units 330-1 to 330-N may be configured identically to each other, only the configuration of clock synthesis unit 330-1 is shown and will be described only.

[0086] The clock synthesis unit 330-1 may include multiple logic gates 331 to 334. The first logic gate 331 and the second logic gate 332 can process any one of the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB (e.g., ICLK) and the clock enable signal CLKEN. <0> The second logic gate 332 performs a bitwise AND operation on the output of the third logic gate 332 and another of the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB (e.g., QCLKB), and outputs the result as the control clock signal CLK_CHOP. <0> .

[0087] Other clock synthesis units 330-2 to 330-N can operate in essentially the same manner as clock synthesis unit 330-1. For example, clock synthesis unit 330-N can generate a control clock signal CLK_CHOP by synthesizing two signals from the polyphase clock signals ICLK, QCLK, ICLKB, and QCLKB that correspond to clock synthesis unit 330-N. <n-1>.

[0088] Referring to Figure 10, the clock synthesis unit 330-1 can generate the control clock signal CLK_CHOP by synthesizing ICLK and QCLKB. <0> ICLK and QCLKB are clock signals such as polyphase clock signals ICLK, QCLK, ICLKB, and QCLKB with a predetermined phase difference (e.g., a 1 / 4-cycle difference between the rising and falling edges). The control clock signal CLK_CHOP... <0> The frequency of the latch can be approximately the same as the frequency of the external clock signal CLK. The latch circuit 310 can be controlled solely by a control clock signal CLK_CHOP, whose frequency is approximately the same as the frequency of the external clock signal CLK. <0> This allows for easy control, ensuring high-speed operation and operation timing margin of the transmission circuit 300.

[0089] During normal read operations of the semiconductor device 100, multiple parallel data items need to be latched based on the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB, and then output to the outside of the semiconductor device 100. During normal read operations, the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB can repeatedly change in response to the external clock signal CLK, and the inverted status information read enable signal SREN can be at a low level. Therefore, the latch circuit 310 can detect the level of the data D<0:N-1> in response to the transitions (i.e., rising and falling edges) of the control clock signal CLK_CHOP<0:N-1> to generate output signals DLT<0:N-1> and DLTB<0:N-1>. Therefore, the transmission circuit 300 can latch and serialize parallel data D<0:N-1> according to the timing of the multiphase clock signals ICLK, QCLK, ICLKB and QCLKB, and drive the terminals of the input / output terminal unit 140 according to the serialized signals, thereby performing data transmission.

[0090] Meanwhile, the status information reading operation of the semiconductor device 100 can include only the sequential output of serial status information, independent of the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB. During the status information reading operation, the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB can be fixed at a predetermined level (e.g., a high level), and the inverted status information reading enable signal SREN can be at a high level. Since the multiphase clock signals ICLK, QCLK, ICLKB, and QCLKB can be fixed at a high level, the clock control circuit 330 can essentially maintain the control clock signal CLK_CHOP<0:N-1> at a high level. Therefore, in the latch circuit 310, the switching sections 325 and 326 can change the levels of the differential output terminals N11 and N12 according to the level changes of the differential input terminals 321 to 323, regardless of the transition of the control clock signal CLK_CHOP<0:N-1>, thereby generating output signals DLT<0:N-1> and DLTB<0:N-1>. Therefore, the transmission circuit 300 can transmit status information by driving the output signals DLT<0:N-1> and DLTB<0:N-1> to the input / output terminal unit 140 via the serial connector 340, buffer 350, and driver 360.

[0091] Those skilled in the art will understand that the invention can be implemented in other specific forms without altering its technical spirit or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of the invention is defined by the appended claims rather than the specific description, and it should be understood that the meaning and scope of the claims, as well as all variations or modifications derived from their equivalents, are included within the scope of the invention.

[0092] Cross-reference to related applications: This application claims priority to Korean Patent Application No. 10-2021-0133018, filed on October 7, 2021, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

[0093] 10: Semiconductor Systems 100: Semiconductor devices 101: Controller 110: Memory Cell Array 120: Peripheral Circuits 121: Address Decoder 122: Voltage Generator 123: Read / Write Circuit 124: Data Input / Output Circuit 130: Control Circuit 131: Status Information Register 140: Input / output terminal unit 141: Terminal 200: Transmission Circuit 210: First latch circuit 210-1 to 210-N: Latch Units 211: First Logic Gate 212: Second Logic Gate 213: Third Logic Gate 220: Second latch circuit 220-1 to 220-N: Latch Units 221-1 to 221-9: Transistors 222-1 to 222-3: Transistors 223: Inverter 230: Clock control circuit 230-1 to 230-N: Clock control unit 231-1 to 231-9: Logic Gates 240: Series Connector 250: Buffer 260: Driver 300: Transmission Circuit 310: Latch circuit 310-1 to 310-N: Latch Units 311: Cross-connect latch 312 to 317: Transistors 321: Differential Input Terminal / First Transistor 322: Differential Input Terminal / Second Transistor 323: Differential Input Terminal / Logic Gate 324: Current drawer 325: Switch section / First switch 326: Switch section / Second switch 330: Clock control circuit 330-1 to 330-N: Clock Synthesis Unit 331: (First) Logic Gate 332: (Second) Logic Gate 333: (Third) Logic Gate 334: (Fourth) Logic Gates 340: Series Connector 350: Buffer 360: Driver 370: Logic Gates

Claims

1. A latching circuit, the latching circuit comprising: The first detection unit generates an output signal by detecting the level of the input terminal in response to changes in the control clock signal during normal readout operation. The system also includes a second detection unit that generates the output signal by detecting the level of the input terminal in response to the control clock signal during the status information reading operation. During the normal reading operation, the control clock signal changes repeatedly, and during the status information reading operation, the control clock signal is fixed at the first logic level.

2. The latching circuit as described in claim 1, wherein, The first detection unit generates the output signal by detecting the level of the data input through the input terminal in response to the rising or falling edge that occurs when the control clock signal changes.

3. The latching circuit as described in claim 1, wherein, The status information includes multiple data bits that define at least one of the following: whether the most recently entered command has been executed normally, whether the previously entered command has been executed normally, whether there is an operation currently in progress, and whether there is an operation currently in standby.

4. The latching circuit as described in claim 3, wherein, The first detection unit operates as an edge-triggered circuit, and the second detection unit operates as a level-triggered circuit.

5. A latching circuit, the latching circuit comprising: A cross-connect latch that latches the level of the input terminal in response to changes in the control clock signal and outputs the latched data through the output terminal; And a switch section connected between the output terminal and the input terminal, which outputs the status information input through the input terminal through the output terminal in response to the status information read signal, regardless of the change of the control clock signal.

6. The latching circuit as described in claim 5, wherein, The cross-connect latch detects the level of the input terminal in response to rising or falling edges that occur when the control clock signal changes.

7. The latching circuit as described in claim 5, wherein, The status information includes multiple data bits that define at least one of the following: whether the most recently entered command has been executed normally, whether the previously entered command has been executed normally, whether there is an operation currently in progress, and whether there is an operation currently in standby.

8. The latching circuit as described in claim 5, wherein, The latch circuit operates as an edge-triggered circuit during normal read operations and as a level-triggered circuit during status information read operations.

9. A transmission circuit, the transmission circuit comprising: A latch circuit that generates an output signal during normal read operations by detecting the level of each data input through a plurality of differential input terminals according to each of the rising and falling edges of a control clock signal, and generates the output signal during status information read operations by detecting the level of status information input through the plurality of differential input terminals in response to the control clock signal; and a serializer that is connected in series and outputs the output signal, wherein the control clock signal changes repeatedly during normal read operations and is fixed at a first logic level during status information read operations.

10. The transmission circuit as claimed in claim 9, further comprising: A driver that drives the terminals of the input / output terminal unit based on the output of the serial unit.

11. The transmission circuit as claimed in claim 9, further comprising: The frequency divider circuit generates a multiphase clock signal by dividing the external clock signal. And a clock control circuit that generates a control clock signal with a frequency equal to that of the external clock signal by selectively combining the multiphase clock signal according to multiple clock enable signals.

12. The transmission circuit as described in claim 9, wherein, The latching circuit includes a plurality of latching units, wherein at least one of the plurality of latching units includes: a cross-connected latch that latches the level of a first differential input terminal among the plurality of differential input terminals in response to a change in a first control clock signal in the control clock signal, and outputs the latched data through a first output terminal; and a switching portion that is connected between the first differential input terminal and the first output terminal, and outputs the status information input through the first differential input terminal through the first output terminal in response to a status information read signal, regardless of the change in the first control clock signal.

13. The transmission circuit as claimed in claim 12, wherein, The cross-connect latch detects the level of the first differential input terminal in response to a rising or falling edge that occurs when the first control clock signal changes.

14. The transmission circuit as claimed in claim 9, wherein, The status information includes multiple data bits that define at least one of the following: whether the most recently entered command has been executed normally, whether the previously entered command has been executed normally, whether there is an operation currently in progress, and whether there is an operation currently in standby.

15. The transmission circuit as claimed in claim 9, wherein, The latch circuit operates as an edge-triggered circuit during the normal read operation and as a level-triggered circuit during the status information read operation.

16. A semiconductor device comprising: The system includes: a memory cell array storing normal data; a control circuit that generates a control signal including a multi-phase clock signal in response to an external clock signal and outputs internally stored status information in response to a status information read command; an input / output terminal unit; and a transmission circuit that: during a normal read operation, generates an output signal by detecting the level of each of the normal data input through a plurality of differential input terminals according to each of the rising and falling edges of the control clock signal, and outputs the output signal to an external device through the input / output terminal unit; and during a status information read operation, generates the output signal by detecting the level of the status information input through the plurality of differential input terminals in response to the control clock signal, and outputs the output signal to an external device through the input / output terminal unit, wherein during the normal read operation, the control clock signal changes repeatedly, and during the status information read operation, the control clock signal is fixed at a first logic level.

17. The semiconductor device as claimed in claim 16, wherein, The control circuit includes a frequency divider circuit that generates the multiphase clock signal by performing phase separation and frequency division on the external clock signal.

18. The semiconductor device as claimed in claim 16, wherein, The transmission circuit includes: a latch circuit that generates the output signal by detecting the level of input data according to the transition of the control clock signal during the normal read operation, and generates the output signal by detecting the level of input state information independently of the transition of the control clock signal during the state information read operation; and a clock control circuit that generates the control clock signal with a frequency equal to the frequency of the external clock signal by selectively combining the multiphase clock signal according to a plurality of clock enable signals.

19. The semiconductor device as claimed in claim 18, wherein, The latching circuit includes a plurality of latching units, wherein at least one of the plurality of latching units includes: a cross-connected latch that latches the level of a first differential input terminal in response to a change in a first control clock signal in the control clock signal, and outputs the latched signal through a first output terminal; and a switching portion that is connected between the first differential input terminal and the first output terminal, and outputs the signal input through the first differential input terminal through the first output terminal in response to a status information read signal, regardless of a change in the first control clock signal.

20. The semiconductor device as claimed in claim 16, wherein, The status information includes multiple data bits that define at least one of the following: whether the most recently entered command has been executed normally, whether the previously entered command has been executed normally, whether there is an operation currently in progress, and whether there is an operation currently in standby.

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