Circuits, methods and systems using current generators for memory sensing

Abstract

According to one embodiment, a circuit includes: a finely tuned reference current generator having a temperature-dependent current output node, the finely tuned reference current generator including: a temperature-to-absolute-temperature (PTAT) current generation circuit; a first programmable current scaling circuit coupled to the PTAT current generation circuit and including a first output coupled to the temperature-dependent current output node; a constant current generation circuit; a second programmable current scaling circuit coupled to the constant current generation circuit and including the first output coupled to the temperature-dependent current output node; and a reference interface circuit having an input coupled to the temperature-dependent current output node and an output configured to be coupled to a reference current input of a memory sense amplifier.

Description

Technical Field

[0001] This invention is generally related to current generators used for memory sensing. [Cross-reference to related applications] []

[0002] This application claims U.S. Provisional Patent Application No. 63 / 286,851, filed December 7, 2021, under 35 USC § 119(e), the entire contents of which are incorporated herein by reference for all purposes. Prior Technology

[0003] Non-volatile memory (such as electrically erasable programmable read-only memory (EEPROM) and flash memory) is commonly found in many electronic systems. In principle, non-volatile memory consists of a large array of programmable memory cells that remain in their programmed state without the application of a power supply voltage, making them suitable for applications requiring long-term, reliable data storage.

[0004] Non-volatile memory cells can be implemented in various forms using a variety of semiconductor technologies. A specific example of a non-volatile memory cell is a silicon-oxide-nitride-oxide-silicon (SONOS) cell, in which a MOSFET transistor is formed with a gate comprising a nitride layer sandwiched between oxide layers. During programming, a high voltage is applied to the control gate, causing electrons to tunnel through the oxide layer and become trapped in the nitride layer, effectively altering the threshold voltage of the MOSFET transistor. The contents of the non-volatile memory cell are read by applying a voltage across the source / drain terminals of the MOSFET transistor and measuring the resulting current. When the non-volatile memory cell is in a programmed state, little or no current flows. On the other hand, when the non-volatile memory cell is in an unprogrammed or "erase" state, a larger current flows. In typical applications, this current is measured using a sense amplifier that compares the current flowing through the non-volatile memory cell to a reference current. Therefore, when the measured current is less than the reference current, the first logic state is assigned to a non-volatile memory cell; if the measured current is greater than the reference current, the second logic state is assigned to a non-volatile memory cell. In some applications, an unprogrammed or erased state may be assigned logic "0", while a programmed state may be assigned logic "1"; however, the reverse convention may also be used.

[0005] As with many semiconductor circuits, the output current generated by a non-volatile memory cell during readback is highly sensitive to many factors, including semiconductor process parameters, temperature, applied voltage, and the lifespan of the memory cell. Therefore, a specific reference current optimized for a particular temperature may provide insufficient noise tolerance or may not be effective at certain temperatures. Furthermore, as non-volatile memory ages and / or undergoes many programming cycles, the output current generated by the non-volatile memory can shift. Thus, a specific reference current suitable when the memory cell was initially manufactured may become unsuitable after the memory cell has been operating for several years.

[0006] The aforementioned problems may worsen when non-volatile memory operates over a very wide temperature range. For example, non-volatile memory that operates reliably in a commercial temperature range between 0°C and 70°C may no longer operate reliably when the operating temperature range is extended, making it unsuitable for the extended temperature range required for industrial (-40°C to 85°C) and military (-55°C to 125°C) applications. Summary of the Invention

[0007] According to one embodiment, a circuit includes: a finely adjustable reference current generator having a temperature-dependent current output node, the finely adjustable reference current generator including: a temperature-to-absolute-scale (PTAT) current generation circuit; a first programmable current scaling circuit coupled to the PTAT current generation circuit and including a first output coupled to the temperature-dependent current output node; a constant current generation circuit; a second programmable current scaling circuit coupled to the constant current generation circuit and including the first output coupled to the temperature-dependent current output node; and a reference interface circuit having an input coupled to the temperature-dependent current output node and an output configured to be coupled to a reference current input of a memory sense amplifier.

[0008] According to another embodiment, a method includes: measuring the output current of a programmable PTAT generator of a reference current generator at a first temperature using a first scaling setting among a plurality of programmable scaling settings to obtain a first current measurement; measuring the output current of the programmable PTAT generator at the first temperature using a second scaling setting among the plurality of programmable scaling settings to obtain a second current measurement; measuring the output current of the programmable PTAT generator at a second temperature using the first scaling setting among the plurality of programmable scaling settings to obtain a third current measurement; measuring the output current of the programmable PTAT generator at the second temperature using the second scaling setting among the plurality of programmable scaling settings to obtain a fourth current measurement; and based on the first current measurement, the second... The scaling setting is determined among the plurality of programmable scaling settings, including the current measurement, the third current measurement, and the fourth current measurement, which configures the programmable PTAT generator to generate an output current with a predetermined temperature coefficient; the programmable PTAT generator is set to the determined scaling setting to provide a finely tuned temperature-dependent current; a constant current compensation is determined to provide a predetermined DC compensation current at a third temperature when subtracted from the finely tuned temperature-dependent current; a programmable constant current generator of the reference current generator is set to provide the determined constant current compensation; a reference current is generated by the reference current generator based on the finely tuned temperature-dependent current and the determined constant current compensation; and the output current of the memory cell of the memory circuit is compared with the reference current.

[0009] According to a further embodiment, a system includes: a memory array including a plurality of memory cells; a plurality of sense amplifiers coupled to the plurality of memory cells, each of the plurality of sense amplifiers being configured to compare a current flowing through a corresponding memory cell in the plurality of memory cells with a reference current; a finely adjustable reference current generator configured to generate a first current including a difference between a predetermined current proportional to temperature and a first predetermined constant current; and a reference interface circuit configured to receive the first current, scale the received first current to form a scaled second current, and add the scaled second current to the second predetermined constant current to form the reference current. Simple Explanation of the Diagram

[0010] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0011] [Figure 1A] illustrates the memory sensing system according to an embodiment, and Figure 1B illustrates a graph showing the relationship between the output current of the memory cell and the temperature;

[0012] [Figure 2A] and [Figure 2B] respectively illustrate a reference current generator according to one embodiment and a test environment according to one embodiment;

[0013] [Figures 3A, 3B, and 3C] illustrate current versus temperature curves for various current signals in the reference current generator of the embodiment;

[0014] [Figures 4A], [Figures 4B], [Figures 4C] and [Figures 4D] illustrate schematic diagrams of a reference current generator according to one embodiment;

[0015] [Figure 5] A flowchart illustrating a method according to one embodiment;

[0016] [Figure 6] illustrates an integrated circuit including a memory system and a reference current generator according to one embodiment; and

[0017] [Figure 7] illustrates a processing system that can be used to implement a part of the system in the embodiment.

[0018] Unless otherwise stated, corresponding numbers and symbols in the different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of preferred embodiments and are not necessarily drawn to scale. To further illustrate certain embodiments, letters indicating variations in the same structure, materials, or processing steps may follow the figure numbers. Implementation

[0019] The preparation and use of the presently preferred embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using the invention and do not limit the scope of the invention.

[0020] In one embodiment, a finely tuned reference current generator for a memory sense amplifier in a memory circuit includes a first programmable scaling circuit configured to generate a scaled temperature-to-absolute-aspect-adjustable (PTAT) current and a second programmable scaling circuit configured to generate a scaled constant current. The sum of the scaled PTAT current and the scaled reference current forms the finely tuned reference current. The reference current generator also includes additional scaling circuitry that further modifies the temperature coefficient and DC current value of the finely tuned reference current to generate a reference current for the sense amplifier used in the memory system.

[0021] During fine-tuning and / or calibration, the first and second scaling circuits are adjusted such that the adjustable reference current has a predetermined temperature coefficient and a predetermined DC current value at a reference temperature (e.g., room temperature). By fine-tuning the adjustable reference current to have the predetermined temperature coefficient and predetermined DC current, a high-precision sense amplifier reference current can be formed, which is advantageously suitable for sensing the state of memory cells over a very wide temperature range without process variations. In some embodiments, the sense amplifier reference current can be advantageously configured to provide sufficient sensing tolerance as memory cells degrade over time and operation.

[0022] Figure 1A illustrates an embodiment of a memory circuit sensing system 100 including a memory cell 102, a sense amplifier 104, and a reference current generator 106. The memory cell 102 may be a non-volatile memory cell, such as a floating-gate memory cell, configured to generate an output current Icell that depends on the memory state of the memory cell. For example, when the memory cell 102 is in a programmed state, a lower bit-line current Icell is generated. On the other hand, when the memory cell 102 is in an unprogrammed or erased state, a higher bit-line current Icell is generated. Therefore, by comparing the output current Icell of the memory cell 102 provided as a sensing input to the sense amplifier 104 with the reference current Isense generated by the current generator 106 provided as a reference current input to the sense amplifier 104, the state of the memory cell 102 can be determined using the sense amplifier 104.

[0023] In various embodiments, the memory sensing system 100 may be disposed on a single monolithic semiconductor integrated circuit, such as a single semiconductor substrate, and / or disposed on the same monolithic semiconductor integrated circuit as other described system components.

[0024] In the depicted embodiment, the sense amplifier 104 generates a first logic state with respect to the output signal Dout when the output current Icell of the memory 102 is less than the reference current Isense, and generates a second logic state when the output current Icell is greater than the reference current Isense. The first and second logic states may be referred to as a "low" state and a "high" state, or a "0" state and a "1" state, respectively. In some embodiments, such designation may be reversed so that the first and second logic states are referred to as a "high" state and a "low" state, or a "1" state and a "0" state, respectively.

[0025] The memory cell 102 and the sense amplifier 104 can be constructed using memory cell and sense amplifier circuits known in the art. For example, the memory cell 102 can be a SONOS memory cell or a floating gate memory cell, and the sense amplifier 104 can be implemented using cross-coupled CMOS latch circuitry. In alternative embodiments, other memory cell and sense amplifier circuits can be used.

[0026] In embodiments of the present invention, the reference current generator 106 may be implemented using the finely adjustable reference current generation circuit described below.

[0027] Figure 1B illustrates the relationship between the reference current Isense generated by the reference current generator 106 and the output current Icell of the memory cell 102 under different programming states and aging conditions, as well as temperature. For example, traces 110 and 114 represent the output current Icell of the memory cell 102 in the programmed and unprogrammed states of a newly manufactured device, respectively. It can be seen that each of these currents increases with increasing temperature. For example, the programmed output current Icell, represented by trace 110, increases from approximately 4 µA at -55°C to approximately 7.2 µA at 125°C, while the unprogrammed output current Icell, represented by trace 114, increases from approximately 0 µA at -55°C to approximately 1.3 µA at 125°C. However, as the memory cell 102 is used for an extended period, the output current of the memory cell 102 shifts over time, causing the current Icell of the memory cell 102 to decrease in its programmed state but increase in its unprogrammed state. These offsets in the output current are represented by traces 112 and 116, where trace 112 represents the output current Icell of the memory cell 102 in the programmed state of the aging device, and trace 116 represents the output current Icell of the memory cell 102 in the unprogrammed state of the aging device. In this example, the programming current is reduced by approximately 0.7 µA, and the unprogrammed current is increased by approximately 0.7 µA, thus effectively reducing the sensing tolerance of the memory cell.

[0028] To enable sufficient tolerance in sensing the state of memory cell 102, the temperature coefficient and DC compensation of the reference current Isense generated by reference current generator 106 are fine-tuned to provide sufficient sensing tolerance over a wide temperature range and various aging conditions. As shown in the example of Figure 1B, the reference current Isense, represented by trace 118, increases from approximately 2 µA at -55°C to approximately 4 µA at 125°C. It should be understood that the current graph shown in Figure 1B is an illustrative example describing a specific memory cell and reference current distribution. Specific memory cells and reference current distributions can vary depending on the specific system, semiconductor technology, and memory cell circuitry used.

[0029] Figure 2A illustrates a reference current generator 200 according to an embodiment of the present invention, which can be used to implement the reference current generator 106 shown in Figure 1A. As shown, the reference current generator 200 includes a programmable current reference circuit 202, a current scaler 216, a summing circuit 220, and a test / fine-tuning interface 222. In an embodiment of the invention, the programmable current reference circuit 202 is configured to provide a substantially temperature-independent current Icref and a scaled, temperature-proportional current Ipref. The programmable current reference circuit 202 can be fine-tuned such that the current Ipref has a predetermined temperature coefficient and DC compensation, while the current Icref can be fine-tuned to have a substantially temperature-independent current with a predetermined DC value.

[0030] Current scaler 216 scales the temperature-independent current Icref to form the current Icm, and scales the temperature-dependent current Ipref to form Ipm. The currents Icm and Ipm are summed together via summing circuit 220 to form the reference current Isense. Test / adjustment interface 222 is used to control the operation of current reference circuit 202 and current scaler 216; provides an interface between reference current generator 200 and test circuitry; and provides fine-tuning and calibration capabilities for reference current generator 200. In some embodiments, current scaler 216 and summing circuit 220 serve as a reference interface circuit between programmable current reference circuit 202 and a sense amplifier configured to receive the reference current Isense.

[0031] In some embodiments, the fine-tuned values ​​of Ipref and Icref generated by the current reference circuit 202 can be the same predetermined target values ​​for many different categories of products. For example, different categories of semiconductor IC products comprising different categories of non-volatile memory may each include a reference current generator 200, which is fine-tuned to produce the same target DC compensation and temperature coefficient values ​​for Ipref and Icref. This advantageously provides a precise process-independent current reference that can be used over a very wide temperature range.

[0032] While the current reference circuit 202 can be used to provide a similar reference current across many different products, the current scaler 216 can scale Ipref and Icref using product-specific scaling factors. These product-specific scaling factors can be determined, for example, by characterizing the memory cells of a specific product being manufactured. By separating the fine-tuning of the current reference circuit 202 from the product-specific scaling factors provided by the current scaler 216, the task of providing an accurate and process-independent reference current can be distinguished from the challenge of implementing a product-specific reference current. This is particularly useful for product testing because the same test and calibration procedures targeting the same values ​​can be reused across many products. In other words, the same validated test procedures can be used for multiple products to ensure an accurate reference current across multiple products.

[0033] The programmable current reference circuit 202 includes a current bandgap circuit 204 and a scaling circuit 206. The current bandgap circuit 204 can be implemented using a Delta Vbe circuit and / or a bandgap reference circuit to generate temperature-dependent constant currents Icref and Irefp, and a temperature-dependent (PTAT) proportional current Iptat. The portion of the current bandgap circuit 204 responsible for generating currents Icref and Irefp can be referred to as a constant current generation circuit, while the portion of the current bandgap circuit 204 responsible for generating the PTAT current Iptat can be referred to as a PTAT current generation circuit. Although the specific circuit implementation of the current bandgap 204 will be discussed below with reference to FIG4B, it should be understood that the current bandgap 204 circuit can be implemented using various current and voltage reference circuits known in the art. For example, a PTAT current generation circuit known in the art can be used to generate the PTAT current Iptat (also known as a temperature-dependent reference current), and a constant current generation circuit known in the art can be used to generate the constant current Irefp. It should also be understood that, due to process variations and second-order behavior in the current bandgap circuit 204, the temperature-constant currents Icref and Irefp may exhibit a small temperature drift. In some embodiments, the currents Icref and Irefp may drift by approximately + / - 1% over a temperature range between -55°C and 125°C. It should be understood that this temperature drift is less than the temperature dependence of the PTAT current Irefp.

[0034] Scaling circuit 206 applies a scaling factor k (also called scaling setting or fine-tuning setting) to a constant current Irefp to produce a current k*Irefp, and applies a scaling factor m to the PTAT current Iptat to produce a current m*Iptat. Subtracting the currents k*Irefp and m*Iptat yields a scaled, temperature-proportional current Ipref. In some embodiments, a current digital-to-analog converter (implemented using a current mirror with optional output) is used to apply the scaling settings k and m, as discussed below with respect to Figures 4A-4D. In some embodiments, the current m*Iptat is greater than the current k*Irefp. During testing and calibration, the final values ​​of the scaling settings k and m are determined by measuring the current Ipref at different temperatures and under different applied scaling settings, as discussed below with respect to the method of Figure 5.

[0035] The current scaler 216 includes current mirrors 210 and 214, which are effectively used as programmable current scaling circuitry, and control logic 212. Current mirror 210 is configured to scale a temperature-independent current Icref according to a digital word IDAC, and current mirror 214 is configured to scale a temperature-proportional current Ipref according to a digital word SDAC. Control logic 212 is configured to provide digital control words IDAC and SDAC to the respective current mirrors 210 and 214. In various embodiments, the control word SDAC is used to adjust the temperature coefficient of the reference current Isense, and the control word IDAC is used to control the dc value of the reference current Isense. Current mirrors 210 and 214 can be implemented using the current mirror circuitry and switching circuitry described below with respect to Figures 4A-4D. Control logic 212 can be implemented, for example, using digital register circuitry known in the art. In alternative embodiments, the scaling settings of current mirrors 210 and / or 214 can be fixed, and control logic 212 can be omitted.

[0036] The outputs of current scaler 216 are summed together by summing circuit 220. In the depicted embodiment, summing circuit 220 simply connects the outputs Icm and Ipm of current scaler 216 together at a common node to provide a summed current for forming a reference current Isense. In an alternative embodiment, summing circuit 220 may include other circuitry (such as a current mirror) to form a sum of the currents provided by current scaler 216.

[0037] Test / tune interface 222 may include a digital interface configured to read and write values ​​in registers used to control various scaling settings in current reference circuit 202 and current scaler 216; and may include non-volatile memory and / or programmable fuses to permanently store tuning and configuration values. Test / tune interface 222 may also include an analog multiplexer configured to route voltages and currents generated within reference current generator 200 to test circuitry, such as an external tester via analog signal bus ABUS. In some embodiments, test / tune interface 222 may include digital interface circuitry configured to communicate with external components via digital bus DBUS. The digital interface of test / tune interface 222 may be a serial bus interface circuitry, a parallel bus interface circuitry, and / or may conform to any bus standard, including but not limited to SPI, CAN, I2C, LVDS, and USB. Therefore, the number n of signal pins of a digital bus DBUS can be any number suitable for the bus protocol implemented.

[0038] Figure 2B illustrates a block diagram of a test environment that can be used to calibrate and fine-tune the reference current generator 200. As shown, the reference current generator 200 is coupled to the tester 230 via an analog bus ABUS and a digital bus DBUS. The tester 230 can be coupled to the reference current generator 200 when it is being calibrated or fine-tuned. For example, the tester 230 can be coupled to the reference current generator 200 during wafer testing, package testing, manufacturing testing, or during routine maintenance or calibration operations. The tester 230 can be implemented, for example, using wafer test fixtures, package test fixtures, automated semiconductor test equipment (ATE), or any other system configured to be coupled to the reference current generator 200 for testing purposes. In some embodiments, the functionality of the tester 230 may reside in the same integrated circuit as the reference current generator 200.

[0039] As shown, the tester 230 includes current and voltage measurement circuitry 232 configured to measure the current and voltage generated by the reference current generator 200. Such measurement circuitry may include, for example, voltage and current measurement circuitry known in the art. In some embodiments, this voltage and current measurement circuitry may include an analog-to-digital converter configured to digitize an analog signal present on the analog bus ABUS.

[0040] The controller 234 may be implemented using digital control circuitry known in the art, such as a microcontroller or microprocessor, comprising software programs stored on a non-transitory computer-readable medium (such as memory or other storage media) that include instructions to calibrate and fine-tune the reference current generator 200 according to the method described below with respect to FIG. 5. In an alternative embodiment, the controller 234 may be implemented using hard-wired logic and / or programmable logic, such as a field-programmable gate array (FPGA).

[0041] The controller 234 is configured to receive digitized current and voltage measurements from the current and voltage measurement circuit 232 and is configured to issue commands to the reference current generator 200 via a digital bus DBUS. These commands may include, for example, commands to adjust various current scaling settings, commands to write fine-tuning values, and commands to route specific signals to the tester 230 via an analog bus ABUS.

[0042] In various embodiments, the tester 230, under the control of the controller 234, uses the heated clamp 240 during wafer testing to measure the analog signal generated by the reference current generator 200 under different temperature conditions. During fine-tuning and calibration of the reference current generator 200, the controller 234 may issue a temperature change command to the heated clamp 240 via the control signal Temp_ctl. Alternatively, the temperature of the reference current generator 200 may be changed using other types of devices, such as a temperature chamber or other systems or devices configured to provide heating and cooling.

[0043] Figures 3A-C illustrate current versus temperature curves for various current signals within the reference current generator 200. Figure 3A illustrates the PTAT current Iptat generated by the current bandgap circuit 204 under different process variations, where Iptat is nominally designed to have a temperature coefficient of 1.5 nA / °C and a current compensation of 0.5 µA at 27°C. It can be seen that, in the illustrative example, the temperature coefficient of Iptat varies considerably throughout the process from 1.0 nA / °C to 2.0 nA / °C.

[0044] Figure 3B illustrates a series of graphs showing the relationship between the temperature-proportional current Ipref generated by the current reference circuit 202 and the reference current Isense generated by the reference current generator 200. In one embodiment of the invention, the current Iptat generated by the current bandgap 202 is scaled by a factor m and a constant current Irefp scaled by a factor k is subtracted to generate a temperature-proportional current Ipref, represented by trace 302 in Figure 3B. In the illustrated embodiment, Iptat and Irefp are scaled and subtracted to generate the current Ipref, which has a temperature coefficient of 3.0 nA / °C at 27°C and a dc compensation of 0.5 µA. The current Ipref is further scaled by the current mirror 214 of the current scaler 216 and added to a scaled version of the constant current Icref to form the reference current Isense, represented by trace 304. In the illustrated embodiment, the reference current Isense is shown to have a dc compensation of 2.0 µA at 27°C, and corresponding optional temperature coefficients of 0.0 nA / °C, 3.0 nA / °C, 6.0 nA / °C, 9.0 nA / °C, and 12.0 nA / °C, respectively, depending on the specific scaling factor applied by the current mirrors 210 and 214 of the current scaler 216.

[0045] Figure 3C illustrates another example of a possible relationship between the temperature-proportional current Ipref and the reference current Isense, where the temperature-proportional current Ipref is fine-tuned to have a temperature coefficient of 3.0 nA / °C at 27°C and a dc compensation of 0.5 μA (trace 302), while the reference current Isense is a fine-tuned value of Ipref based on various scaling settings applied by the current scaler 216 represented by traces 310, 312, 314, 316, 318 and 320. As shown in the figure, trace 310 indicates that Isense has a temperature coefficient of 6.0 nA / °C and a DC compensation of 1.0 µA at 27°C; trace 312 indicates that Isense has a temperature coefficient of 9.0 nA / °C and a DC compensation of 1.5 µA at 27°C; trace 314 indicates that Isense has a temperature coefficient of 12.0 nA / °C and a DC compensation of 2.0 µA at 27°C; trace 316 indicates that Isense has a temperature coefficient of 6.0 nA / °C and a DC compensation of 3.0 µA at 27°C; trace 318 indicates that Isense has a temperature coefficient of 9.0 nA / °C and a DC compensation of 3.5 µA at 27°C; and trace 320 indicates that Isense has a temperature coefficient of 12.0 nA / °C and a DC compensation of 4.0 µA at 27°C. In some embodiments, once the DC value and temperature coefficient (trace 302) of Ifref have been fine-tuned and / or calibrated, settings can be applied to the current scaler 216 to generate a reference current Isense with an accurate predetermined DC compensation value and temperature coefficient.

[0046] It should be understood that the graphs depicted in Figures 3A-C represent only a small fraction of the many possible reference current settings and configurations. In alternative embodiments, the actual current, temperature coefficient, and fine-tuning settings may differ.

[0047] Figure 4A illustrates an embodiment of the current reference circuit 402 that can be used to implement the current reference circuit 202 illustrated in Figure 2A. As shown, the current reference circuit 402 includes a bandgap circuit 404 that generates a reference voltage Vref and a PTAT current Iptat. A voltage / current converter 405 converts the reference voltage Vref into constant currents Irefp and Icref. An adjustable current mirror 412 scales the PTAT current Iptat by a factor of m, and an adjustable current mirror 408 scales the constant current Irefp by a factor of k. In various embodiments, the adjustable current mirror 408, together with the voltage / current converter 405 and the bandgap circuit 404, can be used as a programmable constant current generator. Control logic 406 controls the scaling factor k of the adjustable current mirror 408, control logic 410 controls the scaling factor m of the adjustable current mirror 412, and control logic 440 controls at least one fine-tuning setting of the bandgap circuit 404. The adjustable current mirror 412, together with the bandgap circuit 404, can be used as a programmable PTAT current generator.

[0048] Figure 4B illustrates a schematic diagram of one possible implementation of the current reference circuit 402 illustrated in Figure 4A, which includes a bandgap circuit 404, a voltage / current converter 405, adjustable current mirrors 408 and 412, and control logic 406, 410, and 440.

[0049] As shown in the figure, the bandgap circuit 404 includes npn bipolar transistors Q1, Q2, and Q3, resistors R1 and R2, a digital potentiometer 434, an amplifier 432, and a current mirror 402. The current mirror 402 includes an input Iin configured to receive current and a plurality of outputs Io configured to output a current proportional to the current received at the input Iin. The npn bipolar transistors Q1 and Q2, the amplifier 432, and the current mirror 422 form a PTAT current generator, which generates a PTAT current Iptat. During operation, the feedback loop formed by the amplifier 432 and the current mirror 422 forces the base-emitter voltage of the diode-connected transistor Q1 to be the same as the voltage across the series combination of the diode-connected transistor Q2 and the resistor R1. When the ratio of the emitter region of transistor Q2 to that of transistor Q1 is N, and the same current flows through both transistors Q1 and Q2, it can be seen that the current flowing through transistors Q1 and Q2 (and the current flowing through all branches of current mirror 422) is: VT is the diode thermal voltage, and R1 is the resistance of resistor R. Since the diode thermal voltage is proportional to the absolute temperature, the current Iptat generated by the bandgap circuit 404 is also proportional to the absolute temperature.

[0050] In some embodiments, the bandgap circuit 404 is further configured to generate a programmable reference voltage using a reference voltage generation circuit, which includes an npn bipolar transistor Q3, a resistor R2, and a digital potentiometer 434. During operation, the voltage vctat across the base-emitter junction of the diode-connected transistor Q3 is complementary to the absolute temperature (e.g., inversely proportional to temperature), while the voltage across the resistor R2 (receiving the PTAT current from the current mirror 422) is proportional to the temperature. The digital potentiometer 434 forms a voltage divider between the temperature-complementary voltage vctat and the temperature-proportional voltage vptat. In some embodiments, the digital setting of the digital potentiometer 434 is configured such that the reference voltage node Vref coupled to the pointer voltage of the digital potentiometer 434 is set such that the voltage / current converter 405 generates a substantially temperature-independent current Irefp. In various embodiments, the current Irefp varies by less than + / - 0.5% over the available temperature range. In some embodiments, this available temperature range is from -55°C to 125°C.

[0051] In some embodiments, the digital potentiometer 434 is implemented using a resistor network having a plurality of resistors coupled in series and a plurality of switches configured to connect pointer terminals to selected nodes within the resistor network. Each of the plurality of switches may be implemented using, for example, a MOS transistor.

[0052] The voltage-to-current converter 405 includes an amplifier 436, a portion of a current mirror 424, and a resistor R3. During operation, the feedback loop formed by the amplifier 436 and the current mirror 424 forces the voltage across the resistor R3 to be approximately the same as the reference voltage Vref at the positive terminal of the amplifier 436. Therefore, the current Irefp across the resistor R3 is Vref / R3, which is referred to herein as a constant current. In some embodiments, control logic 440 is used to select the setting of the digital potentiometer 434 such that the constant current Irefp is substantially constant over the entire temperature range, while the temperature variation of Irefp is less than + / - 0.5% within its operating range.

[0053] Adjustable current mirror 408 scales a constant current Irefp according to a scaling factor k to select one of the n-1 binary weighted outputs of current mirror 424 using switching network 425. In some embodiments, adjustable current mirror 408 provides a scaled current with a bit resolution between 4 and 6; however, bit resolutions outside this range may also be used depending on the specific embodiment and its specification. As shown, current mirror 424 includes a current output Io that produces a first current proportional to Irefp. In some embodiments, the output current Io may be equal to the constant current Irefp, or may be some other multiple of the constant current Irefp. Current 2Io is twice the current Irefp, and current 2n-1Io is 2n-1 times the current Io. Current mirror 424 may also include outputs (not shown) that provide 2 multiplied by Io (e.g., 22, 23) up to other powers of 2n-1 to form selectable binary weighted current outputs.

[0054] The adjustable current mirror 412 scales the PTAT current Iptat according to a scaling factor m, so that the switching network 427 can be used to select one of the n-1 binary weighted outputs of the current mirror 426. In some embodiments, the adjustable current mirror 412 provides a scaled current with a bit resolution between 6 and 8; however, bit resolutions outside this range may also be used depending on the specific embodiment and its specification. The operation of the current mirror 426 and the switching network 427 may be similar to the operation of the current mirror 424 and the switching network 425 described above.

[0055] In some embodiments, all or a portion of the adjustable current mirrors 408 and 412 may provide thermometer-encoded outputs. Switching networks 425 and 427 may be implemented, for example, using MOS switches. In an alternative embodiment, switching networks 425 and 427 may be omitted, and current mirrors 424 and 426 are configured to selectively enable and disable individual current mirror output stages based on control word sets provided by control logic 406 and 410.

[0056] In various embodiments, current mirrors 422 and 424 may be implemented using current mirrors including PMOS transistors, and current mirror 426 may be implemented using current mirrors including NMOS transistors, as described below with respect to Figures 4C and 4D. Alternatively, other types of current mirrors may be used.

[0057] Figure 4C illustrates a current mirror circuit that can be used to implement the current mirror 424 shown in Figure 4B. As shown, the current mirror 424 includes current mirror transistors MP1s, MP2s, MP3s, MP4s, MP5s, and MP6s, and cascaded transistors MP1c, MP2c, MP3c, MP4c, MP5c, and MP6c. Resistor RC1 is used to provide bias voltage to the gates of the cascaded transistors MP1c, MP2c, MP3c, MP4c, MP5c, and MP6c.

[0058] The current mirror transistors MP3s, MP4s, MP5s, and MP6s that form the binary weighted current output of the current mirror 424, as well as the cascaded transistors MP3c, MP4c, MP5c, and MP6c, have corresponding binary weighted device dimensions. In some embodiments, some or all of the transistors in the current mirror 424 may be implemented using unit-size PMOS devices for better matching. For example, transistor MP4s may be implemented using a single-unit-size PMOS transistor, transistor MP5s may be implemented using two unit-size PMOS transistors, and transistor MP6s may be implemented using 2n-1 unit-size PMOS transistors. Current mirror circuits similar to current mirror 424 can be used to implement current mirror 422 shown in FIG. 4B and current mirror 210 shown in FIG. 2A, with necessary adjustments and modifications.

[0059] Figure 4D illustrates a current mirror circuit that can be used to implement the current mirror 426 shown in Figure 4B. As shown, the current mirror circuit 426 includes current mirror transistors MN1s, MN2s, MN3s, and MN4s, and cascaded transistors MN1c, MN2c, MN3c, and MN4c. Resistor RC2 is used to provide a bias voltage to the gates of the cascaded transistors MN1c, MN2c, MN3c, and MN4c. The current mirror transistors MN2s, MN3s, and MP4s, and the cascaded transistors MP2c, MP3c, and M45c that form the binary weighted current output of the current mirror 426 have corresponding binary weighted device dimensions. In some embodiments, some or all of the transistors in the current mirror 426 are implemented using unit-size NMOS devices for better matching. A current mirror circuit similar to the current mirror 426 can be used to implement the current mirror 214 shown in Figure 2A, with necessary adjustments and modifications.

[0060] It should be understood that the embodiments in Figures 4A-4D are merely one example of many possible ways to physically implement the current generator of the embodiments. In alternative embodiments, other known circuits and methods may be used to generate temperature-proportional currents, generate substantially temperature-independent currents, and scale currents.

[0061] Figure 5 illustrates a flowchart of a method 500 for fine-tuning an embodiment current generator according to an embodiment of the present invention. In various embodiments, method 500 is used for fine-tuning and calibrating the embodiment reference current generator 106 shown in Figure 1A, the reference current generator 200 shown in Figures 2A and 2B, and / or the circuitry shown in Figures 4A-4D. This method can be implemented, for example, using a tester (such as tester 230 shown in Figure 2B) and a device for changing the temperature of the current generator (such as the thermal clamp 240 shown in Figure 2B).

[0062] In step 502, the constant current Irefp is fine-tuned. In one embodiment, the constant current Irefp is fine-tuned by measuring it at multiple temperatures and selecting a fine-tuning setting that causes it to produce a substantially temperature-independent current and / or reduces or minimizes its dependence on temperature. The calibration in step 502 can be performed, for example, by using a thermal clamp 240 to change the temperature of the reference current generator 200, performing a series of measurements of the current Irefp via the test / fine-tuning interface 222, determining a fine-tuning value based on these measurements, and applying the fine-tuning value to a fine-tuning register and / or a set of fuses. In the embodiment of FIG. 4B, the fine-tuning value can be applied to a digital potentiometer 434 via control logic 440. Alternatively, other known methods can be used to fine-tune and / or calibrate a substantially temperature-independent current. In some embodiments, the measurements in step 502 performed at different temperatures can be performed simultaneously with steps 504 and 506 described below.

[0063] In step 504, the PTAT current Iptat is measured at a high temperature TH with two fine-tuning settings. In one embodiment, the current generator is heated to a first temperature using, for example, a heated clamp 240. A first scaling setting m is applied to the current Iptat using, for example, control logic 410 and an adjustable current mirror 412. Next, a tester 230 is used to measure m*Iptat to form a measurement IPTAT_H_MIN. Then, a second scaling setting m is applied to the current Iptat, and m*Iptat is measured again to form a measurement IPTAT_H_MAX. In some embodiments, the first applied temperature is the maximum operating temperature, and the two applied scaling settings m are maximum scaling settings and minimum scaling settings that provide the maximum and minimum currents from the adjustable current mirror 412, respectively. However, it should be understood that other temperatures and / or non-minimum and non-maximum scaling settings may be used depending on the specific embodiment and its specifications.

[0064] In step 506, the PTAT current Iptat is measured at a cold temperature TC with two fine-tuning settings. In one embodiment, the current generator is cooled to a second temperature using, for example, a heated clamp 240. A first scaling setting m is applied to the current Iptat and m*Iptat is measured using a tester 230 to form a measured value IPTAT_C_MIN. Next, a second scaling setting m is applied to the current Iptat and m*Iptat is measured again to form a measured value IPTAT_L_MAX. It should be understood that measurement steps 504 and 506 do not need to be performed in any particular order relative to each other before calculation steps 508 and 510.

[0065] In step 508, a fine-tuning setting m is calculated based on the measurements performed in steps 502 and 504, such that the temperature-proportional current m*Ipref achieves a predetermined temperature coefficient. In one embodiment, the fine-tuning setting m is calculated according to the following formula: m = ([(TH– TL)*SD– I PTAT_H_MIN+ I PTAT_C_MIN]*N STEPS) / [(I PTAT_H_MAX– I PTAT_H_MIN) – (I PTAT_C_MAX- I PTAT_C_MIN)], Where SD is the predetermined or target temperature coefficient, and N STEPS is the number of programmable scaling settings that the adjustable current mirror 412 can achieve.

[0066] In step 510, a fine-tuning setting k is calculated based on the measurements performed in steps 502 and 504, to apply a constant current Irefp to compensate for m*Iptat to achieve a predetermined temperature slope. In one embodiment, the fine-tuning setting k is calculated according to the following formula: I OFFSET= I PTAT_C_MIN+ m*[(I PTAT_C_MAX– I PTAT_C_MIN) / N STEPS1] + SD(T REF- TL)-I TARG, Where I OFFSET is the final fine-tuning current k*Irefp (also known as constant current compensation) to be subtracted from m*Iptat to generate the current Ipref, and I TARG is the target value of Ipref at the reference temperature Tref. The value of k can be found by the following formula: k = I OFFSET / Irefp, Where Irefp is the finely adjusted constant current.

[0067] In step 512, the fine-tuning settings are programmed to scale settings m and k so that the difference between m*Iptat and k*Irefp forms a generating current Ipref with a predetermined temperature coefficient SD and a predetermined compensation value ITARG.

[0068] In step 514, a fine-tuning value is set for the current scaler 216 shown in FIG. 2A. In one embodiment, the amplitude value IDAC is applied to the current mirror 210 and the temperature coefficient value SDAC is applied to the current mirror 214 so that the sum of the currents Icm and Ipm output by the current mirrors 210 and 214, respectively, forms a predetermined reference current used by the sense amplifier 104 in FIG. 1A. These values ​​may be predetermined based on previously measured characteristics of the memory cell 102.

[0069] Figure 6 illustrates an integrated circuit 600 including memory, which utilizes a reference current generator according to the present invention. As shown, the integrated circuit 600 includes a memory array 604, a column decoder 602, a controller 606, a sense amplifier 610, a row decoder 612, I / O logic 614, and an embodiment reference current generator 608. The memory array 604 includes an array of memory cells, which may include non-volatile memory cells, such as floating-gate memory cells or SONOS memory cells. The sense amplifier 610 is coupled to a row of the memory array and is configured to compare current from selected memory cells with a reference current generated by the embodiment reference current generator 608. The reference current generator 608 can be implemented using any reference current generation circuitry described with respect to the embodiments herein. During operation, based on the address data ADDR provided at the input of I / O logic 614, column decoder 602 selects a column of memory cells within memory array 604 to be read by sense amplifier 610, and row decoder 612 selects the row of memory array to be output via data line DATA through I / O logic 614. Controller 606 is a memory controller that controls memory operations.

[0070] Embodiments of the present invention can be implemented using various semiconductor processes, such as standard CMOS processes and / or CMOS processes modified to accommodate one or more specific types of nonvolatile memory.

[0071] Referring now to FIG. 7, a block diagram of a processing system 700 according to an embodiment of the present invention is provided. The processing system 700 depicts a general platform and general components and functionality that can be used to implement portions of the embodiments described herein, such as the controller 234 of the tester 230 described above with respect to FIG. 2B. For example, the processing system 700 can be used to implement some or all of the processing performed by the tester 230 to measure and fine-tune the current reference circuit of the embodiments. The processing system 700 can also be used to implement portions of the methods of the embodiments described herein with respect to FIG. 6.

[0072] The processing system 700 may include, for example, a central processing unit (CPU) 702 and memory 704 connected to a bus 708, and may be configured to perform the processes discussed above according to programming instructions stored in memory 704 or other non-transitory computer-readable media. Depending on expectation or need, the processing system 700 may also include a display adapter 710 to provide connectivity to a local display 712, and an input / output (I / O) adapter 714 to provide an input / output interface for one or more input / output devices 716 (such as a mouse, keyboard, USB flash drive, etc.).

[0073] The processing system 700 may also include a network interface 718, which may be implemented using a network adapter configured to couple to a wired link (such as a network cable, USB interface, etc.) and / or a wireless / cellular link for communicating with the network 720. The network interface 718 may also include suitable receivers and transmitters for wireless communication. It should be noted that the processing system 700 may include other components. For example, if implemented externally, the processing system 700 may include hardware components such as power supplies, cables, motherboards, removable storage media, and housings. Although these other components are not shown, they are considered to be part of the processing system 700. In some embodiments, the processing system 700 may be implemented on a single monolithic semiconductor integrated circuit and / or on the same monolithic semiconductor integrated circuit as other described system components.

[0074] Embodiments of the present invention are summarized herein. Other embodiments may also be understood from the entire specification and claims herein.

[0075] Example 1: A circuit includes: a finely tuned reference current generator having a temperature-dependent current output node, the finely tuned reference current generator including: a temperature-to-absolute-temperature (PTAT) current generation circuit; a first programmable current scaling circuit coupled to the PTAT current generation circuit and including a first output coupled to the temperature-dependent current output node; a constant current generation circuit; a second programmable current scaling circuit coupled to the constant current generation circuit and including the first output coupled to the temperature-dependent current output node; and a reference interface circuit having an input coupled to the temperature-dependent current output node and an output configured to be coupled to a reference current input of a memory sense amplifier.

[0076] Example 2: The circuit of Example 1, wherein the reference interface circuit includes: a third programmable current scaling circuit having an input coupled to a temperature-dependent current output node; a fourth programmable current scaling circuit having an input coupled to a constant current generation circuit, wherein the output of the reference interface circuit is configured to provide a sum of the outputs of the third programmable current scaling circuit and the fourth programmable current scaling circuit; and a summing circuit coupled to the outputs of the third programmable current scaling circuit, the fourth programmable current scaling circuit, and the reference interface circuit.

[0077] Example 3: The circuit of Example 2, wherein the third programmable current scaling circuit includes a third current mirror having a plurality of selectable outputs; the fourth programmable current scaling circuit includes a fourth current mirror having a plurality of selectable outputs; and the summing circuit includes a node that connects the outputs of the third programmable current scaling circuit, the outputs of the fourth programmable current scaling circuit and the outputs of the reference interface circuit together.

[0078] Example 4: A circuit as described in any of Examples 1 to 3, further comprising a reference voltage generating circuit coupled to the PTAT current generating circuit, wherein the constant current generating circuit includes a voltage / current converter having an input coupled to the output of the reference voltage generating circuit.

[0079] Example 5: The circuit is similar to that in Example 4, wherein the PTAT current generation circuit includes: a first bipolar transistor having a first emitter region, a second bipolar transistor having a second emitter region different from the first emitter region, coupled in series with a resistor, and a current mirror coupled to the first bipolar transistor and the second bipolar transistor; and the reference voltage generation circuit includes: a third bipolar transistor coupled to the current mirror, and a resistor network coupled to the current mirror and the third bipolar transistor, wherein the voltage / current converter is coupled to the output of the resistor network.

[0080] Example 6: The circuit is similar to that in Example 5, where the resistor network is configured to generate a reference voltage that, when applied to a voltage / current converter, causes the voltage / current converter to generate a substantially temperature-independent current.

[0081] Example 7: A circuit similar to Example 5 or 6, where the resistor network is finely adjustable.

[0082] Example 8: A circuit as described in any of Examples 1 to 7, wherein the first programmable current scaling circuit includes a first current mirror circuit having a plurality of selectable outputs; and the second programmable current scaling circuit includes a second current mirror circuit having a plurality of selectable outputs.

[0083] Example 9: A circuit as described in any of Examples 1 to 8, wherein a first programmable current scaling circuit and a second programmable current scaling circuit are programmed to generate a value of a first temperature-dependent reference current having a first predetermined DC value and a first predetermined temperature coefficient at a first temperature.

[0084] Example 10: The circuit of Example 9, wherein the reference interface circuit is configured to: scale a first temperature-dependent reference current to form a first scaled current; and add a constant current to the first scaled current to generate a second temperature-dependent reference current having a second predetermined DC value and a second predetermined temperature coefficient at a first temperature.

[0085] Example 11: A method includes: measuring the output current of a programmable PTAT generator of a reference current generator at a first temperature using a first scaling setting among a plurality of programmable scaling settings to obtain a first current measurement; measuring the output current of the programmable PTAT generator at a first temperature using a second scaling setting among a plurality of programmable scaling settings to obtain a second current measurement; measuring the output current of the programmable PTAT generator at a second temperature using the first scaling setting among a plurality of programmable scaling settings to obtain a third current measurement; measuring the output current of the programmable PTAT generator at a second temperature using the second scaling setting among a plurality of programmable scaling settings to obtain a fourth current measurement; based on the first current measurement and the second current measurement... The process involves measuring, third, and fourth currents to determine a scaling setting among a plurality of programmable scaling settings, configuring a programmable PTAT generator to generate an output current with a predetermined temperature coefficient; setting the programmable PTAT generator to the determined scaling setting to provide a finely tuned temperature-dependent current; determining a constant current compensation that provides a predetermined DC compensation current at a third temperature when subtracted from the finely tuned temperature-dependent current; setting a programmable constant current generator of a reference current generator to provide the determined constant current compensation; generating a reference current by the reference current generator based on the finely tuned temperature-dependent current and the determined constant current compensation; and comparing the output current of the memory cell of the memory circuit with the reference current.

[0086] Example 12: The method of Example 11, wherein the first temperature corresponds to the lowest operating temperature of the memory circuit; the second temperature corresponds to the highest operating temperature of the memory circuit; the first scaling setting corresponds to the minimum current setting of the programmable PTAT generator; and the second scaling setting corresponds to the maximum current setting of the programmable PTAT generator.

[0087] Example 13: The method of Example 11 or 12, wherein generating a reference current by means of a reference current generator includes: subtracting a determined constant current compensation from a finely tuned temperature-dependent current to provide a first temperature-dependent reference current; scaling the first temperature-dependent reference current to form a second temperature-dependent current; scaling the constant current to provide a scaled constant current; and adding the second temperature-dependent current and the scaled constant current to form a reference current.

[0088] Example 14: The method of Example 13, wherein scaling a first temperature-dependent reference current to form a second temperature-dependent current includes selecting one or more optional output branches from a current mirror having an input configured to receive the first temperature-dependent reference current; and scaling a constant current to provide a scaled constant current includes selecting one or more optional output branches from a current mirror having an input configured to receive a constant current.

[0089] Example 15: The method of one of Examples 11 to 14, which further includes fine-tuning a programmable constant current generator to provide a temperature-dependent current.

[0090] Example 16: A method as in any of Examples 11 to 15, wherein the programmable constant current generator includes a reference voltage generation circuit coupled to a voltage / current converter; and the fine-tuning programmable constant current generator includes fine-tuning the reference voltage of the reference voltage generation circuit.

[0091] Example 17: The method of one of Examples 11 to 16, wherein setting the programmable PTAT generator to the determined scaling settings includes selecting at least one optional output of the first current mirror; and setting the programmable constant current generator of the reference current generator includes selecting at least one optional output of the second current mirror.

[0092] Example 18: A method as in any of Examples 11 to 17, wherein determining the scaling settings includes: determining the scaling settings in a plurality of programmable scaling settings used to configure the programmable PTAT generator to generate an output current having a predetermined temperature coefficient, including calculating: m = ([(TH– TL)*SD– I PTAT_H_MIN+ I PTAT_C_MIN]*N STEPS) / [(I PTAT_H_MAX– I PTAT_H_MIN) – (I PTAT_C_MAX- I PTAT_C_MIN)], Where m is the scaling setting determined in a plurality of programmable scaling settings, TH is the first temperature, TL is the second temperature, SD is the predetermined temperature coefficient, N STEPS is a plurality of programmable scaling settings, I PTAT_H_MAX is the first current measurement, I PTAT_H_MIN is the second current measurement, I PTAT_C_MAX is the third current measurement, and I PTAT_C_MIN is the fourth current measurement.

[0093] Example 19: The method is the same as in Example 18, where determining the constant current compensation includes calculating: I OFFSET= I PTAT_C_MIN+ m*[(I PTAT_C_MAX– I PTAT_C_MIN) / N STEPS1] + SD(T REF- TL)-I TARG, Where I OFFSET is the determined constant current compensation, I TARG is the predetermined dc compensation current, and TRAFF is the third temperature.

[0094] Example 20: A system includes: a memory array including a plurality of memory cells; a plurality of sense amplifiers coupled to the plurality of memory cells, each of the plurality of sense amplifiers being configured to compare a current flowing through a corresponding memory cell of the plurality of memory cells with a reference current; a finely adjustable reference current generator configured to generate a first current including a difference between a predetermined current proportional to temperature and a first predetermined constant current; and a reference interface circuit configured to receive the first current, scale the received first current to form a scaled second current, and add the scaled second current to the second predetermined constant current to form the reference current.

[0095] Example 21: A system as in Example 20, wherein the plurality of memory units include the plurality of SONOS memory units.

[0096] Example 22: A system as in Example 20 or 21 further includes a tester configured to: measure a first PTAT current generated by the adjustable current reference generator at a first temperature when in a first scaling setting; measure a second PTAT current generated by the adjustable current reference generator at the first temperature when in a second scaling setting; measure a third PTAT current generated by the adjustable current reference generator at a second temperature when in the first scaling setting; measure a fourth PTAT current generated by the adjustable current reference generator at a second temperature when in the second scaling setting, wherein the first temperature is greater than the second temperature, and the first scaling setting causes the adjustable current reference generator to generate a larger current than in the second scaling setting; determine a fine-tuning setting for the adjustable current reference generator based on the measured first PTAT current, the measured second PTAT current, the measured third PTAT current, the measured fourth PTAT current, and a target temperature coefficient; and apply the determined fine-tuning setting to the adjustable current reference generator.

[0097] Example 23: A system as described in any one of Examples 20 to 22, wherein the reference interface circuitry includes: a first adjustable current mirror configured to receive a first current and provide a scaled second current via a plurality of first selectable current mirror outputs; a second adjustable current mirror configured to receive a constant reference current and provide a predetermined constant current via a plurality of second selectable current mirror outputs; and a common node coupled to one or more selected outputs of the plurality of first selectable current mirror outputs, one or more selected outputs of the plurality of second selectable current mirror outputs, and the outputs of the reference interface circuitry.

[0098] While the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of exemplary embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reference to this description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

[0099] 100: Memory Circuit Sensing System 102: Memory Unit 104: Sensing Amplifier 106: Reference Current Generator 110: Track 112: Trajectory 114: Trajectory 116: Trajectory 118: Trajectory 200: Reference Current Generator 202: Programmable Current Reference Circuit 204: Current bandgap circuit 206: Scaling circuit 210: Current Mirror 212: Control Logic 214: Current Mirror 216: Current scaler 220: Summarizing circuit 222: Test / Fine-tuning Interface 230: Tester 232: Current and Voltage Measurement Circuit 234: Controller 240: Hot clamping plate 302: Trace 304: Trace 310: Traces 312: Trajectory 314: Traces 316: Trajectory 318: Traces 320: Trajectory 402: Current Reference Circuit 404: Bandgap circuit 405: Voltage / Current Converter 406: Control Logic 408: Adjustable current mirror 410: Control Logic 412: Adjustable current mirror 422: Current Mirror 424: Current Mirror 425: Switch network 426: Current Mirror 427: Switch network 432: Amplifier 434: Digital potentiometer 436: Amplifier 440: Control Logic 500: Methods 502, 504, 506, 508, 510, 512, 514: Steps 600: Integrated Circuits 602: Column Decoder 604: Memory Array 606: Controller 608: Reference Current Generator 610: Sensing Amplifier 612: Line Decoder 614:I / O logic 700: Processing System 702: Central Processing Unit (CPU) 704: Memory 708: Busbar 710: Monitor Adapter 712: Monitor 714: Input / Output (I / O) Adapter 716: Input / Output Device 718: Network Interface 720: Internet

Claims

1. A circuit for memory sensing, comprising: A finely tuned reference current generator having a temperature-dependent current output node, the finely tuned reference current generator comprising: a temperature-to-absolute-time (PTAT) current generation circuit including a PTAT current output; a first programmable current scaling circuit including a first input coupled to the PTAT current output of the PTAT current generation circuit and a first output coupled to the temperature-dependent current output node; a constant current generation circuit including an input coupled to the PTAT current output and a constant current output; a second programmable current scaling circuit including a second input coupled to the constant current output of the constant current generation circuit and a second output coupled to the temperature-dependent current output node; a reference voltage generation circuit coupled to the PTAT current generation circuit; and a reference interface circuit having an input coupled to the temperature-dependent current output node and an output configured to be coupled to a reference current input of a memory sense amplifier, wherein the PTAT current generation circuit includes: a first bipolar transistor having a first emitter region. A second bipolar transistor having a second emitter region different from the first emitter region, coupled in series with a resistor, and a current mirror coupled to the first bipolar transistor and the second bipolar transistor; wherein the reference voltage generation circuit includes: a third bipolar transistor coupled to the current mirror, and a resistor network coupled to the current mirror and the third bipolar transistor; and wherein the constant current generation circuit includes a voltage / current converter having an input coupled to the output of the reference voltage generation circuit, and the voltage / current converter being coupled to the output of the resistor network.

2. The circuit of claim 1, wherein the reference interface circuit includes: A third programmable current scaling circuit has an input coupled to the temperature-dependent current output node; A fourth programmable current scaling circuit having an input coupled to the constant current generating circuit, wherein the output of the reference interface circuit is configured to provide a summation of the output of the third programmable current scaling circuit and the output of the fourth programmable current scaling circuit; and a summing circuit coupled to the output of the third programmable current scaling circuit, the output of the fourth programmable current scaling circuit, and the output of the reference interface circuit.

3. The circuit as described in request item 2, wherein: The third programmable current scaling circuit includes a third current mirror having a plurality of selectable outputs; the fourth programmable current scaling circuit includes a fourth current mirror having a plurality of selectable outputs; and the summing circuit includes a node that connects the output of the third programmable current scaling circuit, the output of the fourth programmable current scaling circuit, and the output of the reference interface circuit together.

4. The circuit of claim 3, wherein the resistor network is configured to generate a reference voltage that, when applied to the voltage / current converter, causes the voltage / current converter to generate a substantially temperature-independent current.

5. The circuit as requested in item 4, wherein the resistor network is adjustable.

6. The circuit as described in request item 1, wherein: The first programmable current scaling circuit includes a first current mirror circuit having a plurality of selectable outputs; and the second programmable current scaling circuit includes a second current mirror circuit having a plurality of selectable outputs.

7. The circuit of claim 1, wherein the first programmable current scaling circuit and the second programmable current scaling circuit are programmed to generate a value of a first temperature-dependent reference current having a first predetermined DC value and a first predetermined temperature coefficient at a first temperature.

8. The circuit of claim 1, wherein the reference interface circuit is configured to: scale the first temperature-dependent reference current to form a first scaled current; and add a constant current to the first scaled current to generate a second temperature-dependent reference current having a second predetermined DC value and a second predetermined temperature coefficient at the first temperature.

9. A method for memory sensing, comprising: The output current of a programmable PTAT generator of a reference current generator is measured at a first temperature using a first scaling setting among a plurality of programmable scaling settings to obtain a first current measurement; the output current of the programmable PTAT generator is measured at the first temperature using a second scaling setting among the plurality of programmable scaling settings to obtain a second current measurement; the output current of the programmable PTAT generator is measured at a second temperature using the first scaling setting among the plurality of programmable scaling settings to obtain a third current measurement; the output current of the programmable PTAT generator is measured at the second temperature using the second scaling setting among the plurality of programmable scaling settings to obtain a fourth current measurement; based on the first current measurement, the second current measurement, the third current measurement, and the fourth current measurement, a scaling setting among the plurality of programmable scaling settings is determined, which configures the programmable PTAT generator to generate an output current having a predetermined temperature coefficient; the programmable PTAT generator is set to the determined scaling setting to provide a finely tuned temperature-dependent current; a constant current compensation is determined, which provides a predetermined DC compensation current at a third temperature when subtracted from the finely tuned temperature-dependent current; Configure the programmable constant current generator of the reference current generator to provide the determined constant current compensation; generate a reference current by the reference current generator based on the finely tuned temperature-dependent current and the determined constant current compensation; and compare the output current of the memory cell of the memory circuit with the reference current.

10. As in request item 9, wherein: The first temperature corresponds to the lowest operating temperature of the memory circuit; the second temperature corresponds to the highest operating temperature of the memory circuit; the first scaling setting corresponds to the minimum current setting of the programmable PTAT generator; and the second scaling setting corresponds to the maximum current setting of the programmable PTAT generator.

11. The method of claim 9, wherein generating the reference current by means of the reference current generator includes: The determined constant current compensation is subtracted from the finely tuned temperature-dependent current to provide a first temperature-dependent reference current; The first temperature-dependent reference current is scaled to form a second temperature-dependent current; a constant current is scaled to provide a scaled constant current; and the second temperature-dependent current and the scaled constant current are added together to form the reference current.

12. As in request item 9, wherein: Scaling the first temperature-dependent reference current to form the second temperature-dependent current includes selecting one or more optional output branches from a current mirror having an input configured to receive the first temperature-dependent reference current; and scaling the constant current to provide the scaled constant current includes selecting one or more optional output branches from a current mirror having an input configured to receive the constant current.

13. The method of claim 9 further includes fine-tuning the programmable constant current generator to provide a temperature-dependent current.

14. As in request item 13, wherein: The programmable constant current generator includes a reference voltage generation circuit coupled to a voltage / current converter; and fine-tuning the programmable constant current generator includes fine-tuning the reference voltage of the reference voltage generation circuit.

15. As in request item 13, wherein: Setting the programmable PTAT generator to the determined scaling settings includes selecting at least one optional output of the first current mirror; and setting the programmable constant current generator of the reference current generator includes selecting at least one optional output of the second current mirror.

16. The method of request item 9, wherein determining the scaling setting includes: Determining the scaling setting among the plurality of programmable scaling settings used to configure the programmable PTAT generator to generate the output current having the predetermined temperature coefficient includes calculating: m = ([(TH – TL)*SD – IPTAT_H_MIN + IPTAT_C_MIN]*NSTEPS) / [(IPTAT_H_MAX – IPTAT_H_MIN) – (IPTAT_C_MAX - IPTAT_C_MIN)], where m is the scaling setting determined among the plurality of programmable scaling settings, TH is the first temperature, TL is the second temperature, SD is the predetermined temperature coefficient, NSTEPS is the number of the plurality of programmable scaling settings, IPTAT_H_MAX is the first current measurement, IPTAT_H_MIN is the second current measurement, IPTAT_C_MAX is the third current measurement, and IPTAT_C_MIN is the fourth current measurement.

17. The method of claim 16, wherein determining the constant current compensation includes calculating: IOFFSET = IPTAT_C_MIN + m*[(IPTAT_C_MAX – IPTAT_C_MIN) / NSTEPS1] + SD(TREF - TL)-ITARG, where IOFFSET is the determined constant current compensation, ITARG is the predetermined DC compensation current, and TREF is the third temperature.

18. A system for memory sensing, comprising: A memory array comprising a plurality of memory cells; A plurality of sense amplifiers coupled to the plurality of memory cells, each of the plurality of sense amplifiers being configured to compare a current flowing through a corresponding memory cell of the plurality of memory cells with a reference current; a finely tuned reference current generator configured to generate a first current comprising the difference between a predetermined current proportional to temperature and a first predetermined constant current; a reference interface circuit configured to receive the first current, scale the received first current to form a scaled second current, and add the scaled second current to a second predetermined constant current to form the reference current; and a tester configured to: measure a first PTAT current generated by the finely tuned current reference generator at a first temperature when in a first scaling setting; measure a second PTAT current generated by the finely tuned current reference generator at the first temperature when in a second scaling setting; and measure a third PTAT current generated by the finely tuned current reference generator at a second temperature when in the first scaling setting. When in the second scaling setting, a fourth PTAT current generated by the adjustable current reference generator at the second temperature is measured, wherein the first temperature is greater than the second temperature, and the first scaling setting causes the adjustable reference current generator to generate a larger current than in the second scaling setting; a fine-tuning setting of the adjustable reference current generator is determined based on the measured first PTAT current, the measured second PTAT current, the measured third PTAT current, the measured fourth PTAT current, and the target temperature coefficient; and the determined fine-tuning setting is applied to the adjustable reference current generator.

19. The system of claim 18, wherein the plurality of memory units includes a plurality of SONOS memory units.

20. The system of claim 18, wherein the reference interface circuitry includes: A first adjustable current mirror is configured to receive the first current and provide the scaled second current via a plurality of first selectable current mirror outputs; a second adjustable current mirror is configured to receive a constant reference current and provide the predetermined constant current via a plurality of second selectable current mirror outputs; and a common node coupled to one or more selected outputs of the plurality of first selectable current mirror outputs, one or more selected outputs of the plurality of second selectable current mirror outputs, and the output of the reference interface circuit.

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