Semiconductor device and method for fabricating the same

Abstract

The semiconductor device includes: a dielectric structure in which etch-stop structures and low-k layers are alternately stacked on a substrate; and a metal interconnect in the dielectric structure electrically connected to the substrate, wherein each of the etch-stop structures includes: a first etch-stop layer comprising a hydrogen-blocking material; and a second etch-stop layer formed on the first etch-stop layer.

Description

[Technical Field]

[0001] Various specific embodiments of the present invention relate to methods for manufacturing semiconductor devices, and more specifically, to methods for manufacturing semiconductor devices including an etch stop layer having a hydrogen barrier material. Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0179567, filed on December 15, 2021, the entire contents of which are incorporated herein by reference. [Previous Technology]

[0003] Semiconductor manufacturing processes require etching, which damages the surface of the semiconductor substrate. As semiconductor devices become increasingly integrated, the spacing between patterns becomes smaller, which also leads to increased damage to the substrate surface. As a result, the dangling bonds of silicon forming the semiconductor substrate increase, which becomes a source of electronic leakage current and can cause leakage current in transistors. [Summary of the Invention]

[0004] Specific examples of the present invention relate to semiconductor devices having improved electrical characteristics and reliability, and to methods for manufacturing such semiconductor devices.

[0005] According to a specific embodiment of the present invention, a semiconductor device includes: a dielectric structure in which etch-stop structures and low-k layers are alternately stacked on a substrate; and a metal interconnect in the dielectric structure electrically connected to the substrate, wherein each of the etch-stop structures includes: a first etch-stop layer comprising a hydrogen-blocking material; and a second etch-stop layer formed on the first etch-stop layer.

[0006] According to another specific embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a dielectric structure in which etch stop structures and low-k layers are alternately stacked on a substrate having a transistor including a gate dielectric layer; and forming a metal interconnect electrically connected to the substrate in the dielectric structure, wherein each of the etch stop structures includes: a first etch stop layer including a hydrogen barrier material; and a second etch stop layer formed on the first etch stop layer.

Implementation Method

[0010] Various specific embodiments of the present invention will be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these specific embodiments are provided so that this disclosure will be exhaustive and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and specific embodiments of the invention.

[0011] The accompanying drawings are not necessarily to scale, and in some instances, the scale may have been exaggerated in order to clearly show the features of a particular instance. When the first layer is referred to as being "on" the second layer or "on" the substrate, it means not only that the first layer is formed directly on the second layer or the substrate, but also that the third layer exists between the first and second layers or between the substrates.

[0012] FIG1 is a cross-sectional view showing a semiconductor device according to a specific example of the present invention.

[0013] Referring to FIG1, the semiconductor device may include a device region DR and an interconnect region LR. The device region DR may be a region including a substrate 101 and a plurality of transistors Tr formed on the substrate 101. The interconnect region LR may include a plurality of inter-metal dielectric layers 132, 143 and 153, a plurality of etch stop structures 140, 150 and 160, a plurality of inter-layer dielectric layers 131, 163 and 164, and multi-level metal interconnects M1, M2, M3 and M4.

[0014] Substrate 101 may be a material suitable for semiconductor processing. Substrate 101 may include a semiconductor substrate. Substrate 101 may include a silicon-containing material. Substrate 101 may include silicon, single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, single-crystal silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. Substrate 101 may include other semiconductor materials such as germanium. Substrate 101 may include a group III / V semiconductor substrate, for example, a compound substrate such as GaAs. Substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0015] The substrate 101 may include an isolation layer 111 defining an active region 112. A transistor Tr may be formed on the active region 112, wherein the transistor Tr includes a stacked structure of a gate dielectric layer 121, a gate electrode 122, and a gate hard photomask 123, and gate spacers 124 formed on the sidewalls of the stacked structure. Impurity regions 125 may be formed in the substrate 101 on both sides of the transistor Tr. The impurity regions 125 may be referred to as "source / drain regions".

[0016] Multilayer metal interconnects M1, M2, M3, and M4 may extend through multiple intermetallic dielectric layers 132, 143, and 153. Intermetallic dielectric layers 132, 143, and 153 may include dielectric materials with low dielectric constants to reduce parasitic capacitance between metal interconnects M1, M2, M3, and M4. Intermetallic dielectric layers 132, 143, and 153 may be referred to as "low-k layers." Intermetallic dielectric layers 132, 143, and 153 may include low-k materials having a dielectric constant lower than that of silicon oxide (SiO2). For example, silicon oxide may have a dielectric constant of about 3.9 to 4.5. Intermetallic dielectric layers 132, 143, and 153 may have a dielectric constant of about 3.5 or lower, for example, a dielectric constant of about 2.0 to 3.5. For example, the intermetallic dielectric layers 132, 143 and 153 can be made of silicon oxide (SiCOH) containing carbon and hydrogen.

[0017] Interlayer dielectric layers 131, 163, and 164 may be located above the transistor Tr and the substrate 101, and between and above the fourth metal interconnect M4, which is the uppermost metal interconnect. Interlayer dielectric layers 131, 163, and 164 may comprise oxide materials having a higher dielectric constant than intermetallic dielectric layers 132, 143, and 153. For example, the first interlayer dielectric layer 131 and the second interlayer dielectric layer 163 may comprise tetraethyl orthosilicate (TEOS) oxide. According to another specific embodiment of the invention, the first interlayer dielectric layer 131 and the second interlayer dielectric layer 163 may comprise silicon oxide having a dielectric constant of about 3.9 to 4.5.

[0018] The third interlayer dielectric layer 164 may include a hydrogen-containing silicon oxide. Compared to the second interlayer dielectric layer 163, the third interlayer dielectric layer 164 may include a dielectric material with a relatively high hydrogen supply capability. For example, the third interlayer dielectric layer 164 may include a high-density plasma (HDP) oxide. The third interlayer dielectric layer 164 may be referred to as a "hydrogen passivation layer" or a "hydrogen supply layer". When hydrogen is supplied through the hydrogen supply layer, it can be less affected by layers that block hydrogen diffusion compared to annealing in a hydrogen atmosphere.

[0019] Passivation layer 170 may be formed on the third interlayer dielectric layer 164. Passivation layer 170, together with the third interlayer dielectric layer 164, may act as a hydrogen source for supplying hydrogen to the surface of substrate 101. Passivation layer 170 may be used to protect all structures stacked in a direction perpendicular to substrate 101. Passivation layer 170 may, for example, include silicon nitride.

[0020] During the hydrogen passivation process, hydrogen in the third interlayer dielectric layer 164 can diffuse to the surface of the substrate 101 through the multilayer metal interconnects M1, M2, M3, and M4 electrically connected to the substrate 101. The surface of the substrate 101 reached by hydrogen can be the interface 100 between the transistor Tr and the substrate 101. Therefore, the trap sites at the interface 100 can be filled by the diffused hydrogen, which significantly reduces the interface trap density. Thus, the leakage current characteristics of the transistor can be improved.

[0021] The etch stop structures 140, 150, and 160 may include a dielectric material having etch selectivity with respect to the interlayer dielectric layers 131, 163, and 164 and the intermetallic dielectric layers 132, 143, and 153. The etch stop structures 140, 150, and 160 may have a higher film density and strength than the intermetallic dielectric layers 132, 143, and 153. The etch stop structures 140, 150, and 160 can prevent certain gases from escaping from or flowing into the intermetallic dielectric layers 132, 143, and 153. In other words, the etch stop structures 140, 150, and 160 can suppress the escape of gases (e.g., hydrogen (H2), water vapor (H2O), fluorine, and chlorine) from the intermetallic dielectric layers 132, 143, and 153. Similarly, etch stop structures 140, 150 and 160 can be provided to prevent hydrogen or water vapor from flowing into the intermetallic dielectric layers 132, 143 and 153.

[0022] The first etch stop structure 140 may include a stacked structure of a first etch stop layer 141 and a second etch stop layer 142. The second etch stop structure 150 may include a stacked structure of a third etch stop layer 151 and a fourth etch stop layer 152. The third etch stop structure 160 may include a stacked structure of a fifth etch stop layer 161 and a sixth etch stop layer 162. The thickness of each etch stop structure 140, 150, and 160 may be less than the thickness of each inter-metal dielectric layer 132, 143, and 153. The thickness of each etch stop structure 140, 150, and 160 may be less than the thickness of each inter-layer dielectric layer 131, 163, and 164. The thickness of the first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 may be less than the thickness of the second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162, respectively. For example, when the thickness of the second etch stop layer 142 is about 250 Å to 700 Å, the thickness of the first etch stop layer 141 can be about 20 Å to 40 Å.

[0023] The first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 can be used to prevent hydrogen in the lower layer from diffusing into the upper layer through the annealing process, etc. In other words, during the annealing process (which is performed for hydrogen diffusion into the surface of the substrate), the first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 can prevent hydrogen from being captured by the second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162 by blocking the diffusion of hydrogen in the lower layer into the upper layer. Ultimately, the first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 can increase the efficiency of the annealing process for hydrogen diffusion by guiding the hydrogen transport path to concentration.

[0024] Each of the first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 may include a hydrogen barrier material. Compared to silicon nitride (Si3N4) having a stoichiometric composition, the first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 may include a dielectric material having a higher silicon content in the layer. The first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 may be formed of silicon-rich silicon nitride (SRN) having a higher silicon content than silicon nitride (Si3N4) having a stoichiometric composition. Specifically, each of the first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 may be formed by pretreatment during the deposition process of each of the second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162, rather than by a separately performed deposition process. Each of the first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 may be formed in situ in the same cavity as each of the second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162.

[0025] Compared to silicon nitride (Si3N4) with a stoichiometric composition, the second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162 may include materials with a lower dielectric constant. The second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162 may include carbon-doped silicon nitride (NDC). The second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162 may include Si, C, and N. For example, the second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162 may include SiCN.

[0026] Although the first etch stop structure to the third etch stop structure are shown in this specific example, according to another specific example of the invention, the etch stop structure may also be located between the first interlayer dielectric layer 131 and the first intermetallic dielectric layer 132.

[0027] The multi-level metal interconnects M1, M2, M3, and M4 may include metal interconnect contacts and conductive lines. Metal interconnect contacts 135, 145, 155, and 165 can be used to electrically connect lower and upper conductive lines to each other. The two ends of the first metal interconnect contact 135 can be coupled to the substrate 101 and the first conductive line 136, thereby electrically connecting the substrate 101 and the first conductive line 136 to each other. The two ends of the second metal interconnect contact 145 can be coupled to the first conductive line 136 and the second conductive line 146, thereby electrically connecting the first conductive line 136 and the second conductive line 146 to each other. The two ends of the third metal interconnect contact 155 can be coupled to the second conductive line 146 and the third conductive line 156, thereby electrically connecting the second conductive line 146 and the third conductive line 156 to each other. The two ends of the fourth metal interconnect contact 165 can be coupled to the third conductive line 156 and the fourth conductive line 166, thereby electrically connecting the third conductive line 156 and the fourth conductive line 166 to each other. Each of the conductive lines 136, 146, 156, and 166 may extend in one direction while contacting the upper surface of each of the metal interconnect contacts 135, 145, 155, and 165. The plurality of metal interconnect contacts 135, 145, 155, and 165 may be provided at the same horizontal level and spaced apart from each other, and each of the conductive lines 136, 146, 156, and 166 may be simultaneously coupled to the plurality of metal interconnect contacts located at the same horizontal level.

[0028] The first to third conductive lines 136, 146, and 156 may comprise the same material. For example, the first to third conductive lines 136, 146, and 156 may comprise copper (Cu). A barrier layer may be formed at the interface between the first to third conductive lines 136, 146, and 156 and the intermetallic dielectric layers 132, 143, and 153. The barrier layer may comprise titanium, titanium nitride, tantalum, or tantalum nitride.

[0029] The fourth metal interconnect contact 165 may be the uppermost contact plug. The fourth metal interconnect contact 165 may include a material different from the material of the first to third conductive lines 136, 146, and 156. The fourth metal interconnect contact 165 may include a conductive material having a lower resistance than the first to third conductive lines 136, 146, and 156. For example, the fourth metal interconnect contact 165 may include tungsten (W). A barrier layer may be formed at the interface between the fourth metal interconnect contact 165 and the second interlayer dielectric layer 163. The barrier layer may include tungsten nitride.

[0030] The fourth conductive line 166 may be the uppermost conductive line. The fourth conductive line 166 may be formed on the fourth metal interconnect contact 165 and the second interlayer dielectric layer 163. The fourth conductive line 166 may have a shape extending in one direction when contacting the upper surface of the fourth metal interconnect contact 165. The fourth conductive line 166 may include a conductive material having a lower resistance than the fourth metal interconnect contact 165. The fourth conductive line 166 may include a metallic material that can be eroded by oxidation. For example, the fourth conductive line 166 may include aluminum. In the case of aluminum, when the surface is oxidized, aluminum oxide may be formed and used as an oxide film agent for the aluminum underneath.

[0031] In the manufacturing processes of semiconductor devices (e.g., oxidation processes and plasma etching processes), defects may occur in the cell device, thereby degrading its electrical characteristics. For example, dangling bonds can form at the interface between the silicon oxide layer and the silicon substrate of the cell device, and between the gate oxide layer and the substrate. This can increase leakage current and thus degrade the electrical characteristics of the semiconductor device. In the case of dynamic random access memory (DRAM) semiconductor devices, it is necessary to perform an operation to restore existing data at a predetermined period using a refresh method for newly restored data. In this case, the predetermined period may be referred to as the refresh period or data retention time. In order to reduce the power consumption of DRAM and increase the operating speed, it is necessary to increase the data retention time. However, due to structural defects such as dangling bonds in the silicon crystal, the leakage current in the transistor may increase and the data retention time may decrease.

[0032] To address issues such as dangling bonds, a third interlayer dielectric layer 164 can be formed on top of the uppermost metal interconnect (in this specific example, a fourth metal interconnect M4) as a hydrogen supply layer, and hydrogen can be supplied to the interface between the substrate 101 and the transistor Tr through an annealing process.

[0033] As a comparative example, when silicon nitride (Si3N4) with a stoichiometric composition having a thickness similar to that of this specific example is used as an etch stop layer, the speed characteristics of the device may deteriorate due to the increase in the dielectric constant of the entire dielectric layer, which may be a problem.

[0034] In contrast, according to a specific embodiment of the present invention, a low dielectric constant can be maintained by applying an etch stop layer having a lower dielectric constant (compared to silicon nitride (Si3N4) with a stoichiometric composition). Moreover, when a silicon-rich silicon nitride (which has a higher silicon content but is thinner compared to silicon nitride (Si3N4) with a stoichiometric composition) is applied to the lower part of the etch stop layer as an etch stop layer, hydrogen diffusion from the lower layer to the upper layer during the annealing process for supplying hydrogen can be prevented without any increase in dielectric constant, and the efficiency of the annealing process for hydrogen diffusion can be increased by guiding the hydrogen transport path.

[0035] Figures 2 and 3 are cross-sectional views illustrating semiconductor devices according to other specific embodiments of the present invention. Figure 2 shows etch stop structures 240, 250, and 260 having structures different from those in Figure 1. Figure 3 shows a substrate and device region having structures different from those in Figure 1. In Figures 2 and 3, the same reference numerals that also appear in Figure 1 can indicate the same structures shown in Figure 1. For ease of description, descriptions of reference numerals that also appear in Figure 1 will be omitted or can be briefly described.

[0036] Referring to FIG. 2, etch stop structures 240, 250, and 260 may include dielectric materials having etch selectivity with respect to interlayer dielectric layers 131, 163, and 164 and intermetallic dielectric layers 132, 143, and 153. Etch stop structures 240, 250, and 260 may have higher film density and strength than intermetallic dielectric layers 132, 143, and 153. Etch stop structures 240, 250, and 260 can prevent certain gases from escaping from or flowing into intermetallic dielectric layers 132, 143, and 153. In other words, etch stop structures 240, 250, and 260 can suppress the emission of gases such as hydrogen (H2), water vapor (H2O), fluorine, and chlorine from intermetallic dielectric layers 132, 143, and 153. Etching stop structures 240, 250 and 260 can be provided to prevent hydrogen or water vapor from flowing into the intermetallic dielectric layers 132, 143 and 153.

[0037] The first etch stop structure 240 may include a stacked structure of first to third etch stop layers 241, 242, and 243. The second etch stop structure 250 may include a stacked structure of fourth to sixth etch stop layers 251, 252, and 253. The third etch stop structure 260 may include a stacked structure of seventh to ninth etch stop layers 261, 262, and 263. The thickness of each etch stop structure 240, 250, and 260 may be less than the thickness of each inter-metal dielectric layer 132, 143, and 153. The thickness of each etch stop structure 240, 250, and 260 may be less than the thickness of each inter-layer dielectric layer 131, 163, and 164. The thicknesses of the first etch stop layer 241, the third etch stop layer 243, the fourth etch stop layer 251, the sixth etch stop layer 253, the seventh etch stop layer 261, and the ninth etch stop layer 263 may be less than the thicknesses of the second etch stop layer 242, the fifth etch stop layer 252, and the eighth etch stop layer 262. For example, when the thickness of the second etch stop layer 242 is approximately 250 Å to 700 Å, the thicknesses of the first etch stop layer 241 and the third etch stop layer 243 may be approximately 20 Å to 40 Å, but the concept and spirit of the present specific example are not limited thereto.

[0038] The first etch stop layer 241, the third etch stop layer 243, the fourth etch stop layer 251, the sixth etch stop layer 253, the seventh etch stop layer 261, and the ninth etch stop layer 263 can be used to prevent hydrogen from diffusing from the lower layer to the upper layer or from the upper layer to the lower layer through annealing processes, etc. In other words, during the annealing process used to allow hydrogen to diffuse to the surface of the substrate, the first etch stop layer 241, the third etch stop layer 243, the fourth etch stop layer 251, the sixth etch stop layer 253, the seventh etch stop layer 261, and the ninth etch stop layer 263 can prevent hydrogen from escaping (wherein hydrogen in the lower layer diffuses to the upper layer). Similarly, hydrogen diffusing from the upper layer can be prevented from being captured by the second etch stop layer 242, the fifth etch stop layer 252, and the eighth etch stop layer 262 when it comes down to the lower layer.

[0039] Therefore, the first etch stop layer 241, the third etch stop layer 243, the fourth etch stop layer 251, the sixth etch stop layer 253, the seventh etch stop layer 261, and the ninth etch stop layer 263 can prevent hydrogen loss due to hydrogen expulsion and unnecessary hydrogen capture, and guide the hydrogen transport path to concentration. Therefore, the efficiency of the annealing process for hydrogen diffusion into the substrate can be increased.

[0040] According to another specific embodiment of the present invention, an etch stop layer including a hydrogen barrier material can be applied to the interface between metal interconnects M1, M2, M3 and M4 and etch stop structures 240, 250 and 260.

[0041] Each of the first etch stop layer 241, the third etch stop layer 243, the fourth etch stop layer 251, the sixth etch stop layer 253, the seventh etch stop layer 261, and the ninth etch stop layer 263 may include a hydrogen barrier material. The first etch stop layer 241, the third etch stop layer 243, the fourth etch stop layer 251, the sixth etch stop layer 253, the seventh etch stop layer 261, and the ninth etch stop layer 263 may include a dielectric material having a silicon content higher than that of silicon nitride (Si3N4) having a stoichiometric composition. The first etch stop layer 241, the third etch stop layer 243, the fourth etch stop layer 251, the sixth etch stop layer 253, the seventh etch stop layer 261, and the ninth etch stop layer 263 may include silicon-rich silicon nitride (SRN) having a silicon content higher than that of silicon nitride (Si3N4) having a stoichiometric composition. Specifically, the first etch stop layer 241, the fourth etch stop layer 251, and the seventh etch stop layer 261 may be formed through a pretreatment process during the deposition processes of the second etch stop layer 242, the fifth etch stop layer 252, and the eighth etch stop layer 262, rather than through separate deposition processes. The third etch stop layer 243, the sixth etch stop layer 253, and the ninth etch stop layer 263 may be formed through a pretreatment process during the deposition process of the upper dielectric layer of the third etch stop layer 243, the sixth etch stop layer 253, and the ninth etch stop layer 263, rather than through separate deposition processes. For example, the first etch stop layer 241 may be formed through a pretreatment process during the deposition process of the second etch stop layer 242. The third etch stop layer 243 may be formed through a pretreatment process during the deposition process of the second intermetallic dielectric layer 143.

[0042] The second etch stop layer 242, the fifth etch stop layer 252, and the eighth etch stop layer 262 may include silicon nitride (Si3N4) having a lower dielectric constant than silicon nitride with a stoichiometric composition. The second etch stop layer 242, the fifth etch stop layer 252, and the eighth etch stop layer 262 may include carbon-doped silicon nitride (NDC). The second etch stop layer 242, the fifth etch stop layer 252, and the eighth etch stop layer 262 may include Si, C, and N. For example, the second etch stop layer 242, the fifth etch stop layer 252, and the eighth etch stop layer 262 may include SiCN.

[0043] Although the first etch stop structure to the third etch stop structure are shown in this specific example, according to another specific example of the invention, the etch stop structure may also be located between the first interlayer dielectric layer 131 and the first intermetallic dielectric layer 132.

[0044] Referring to FIG. 3, the semiconductor device may include a device region DR and an interconnect region LR. The device region DR may be a region including a substrate 101 and a plurality of transistors formed on the substrate 101. When the semiconductor device of the present invention is a memory device, the device region DR may include a cell array region R1 and a peripheral circuit region R2 for driving the cell array region R1. The cell array region R1 may be a region where memory cells are disposed. The peripheral circuit region R2 may be a region where word line drivers, sense amplifiers, row decoders, column decoders, and control circuitry are disposed. When the semiconductor device of the present invention is a non-memory device, the device region DR may not include the cell array region R1.

[0045] The cell array region R1 may include a cell transistor region CS and an information storage structure MS above the cell transistor region CS. When the semiconductor memory device of the present invention is a DRAM device, the information storage structure MS may include a capacitor. The capacitor may include a stacked structure of a lower electrode, a dielectric layer, and an upper electrode.

[0046] The unit transistor region CS may include a unit memory cell, a word line WL, and a bit line BL, wherein the unit memory cell includes an active region 112 defined by an isolation layer 111, the word line WL is formed in the active region 112, and the bit line BL is formed on the active region 112. Multiple impurity regions separated from each other by the word line WL may be provided in the active region 112. From a planar perspective, the bit line BL may extend in a direction intersecting the word line WL. The bit line BL may be electrically connected to the substrate 101 via bit line contacts. A capacitor may be electrically connected to the substrate 101 via storage node contacts. Although a specific example of the present invention has been described with reference to DRAM, the semiconductor memory device of the present invention is not limited to DRAM, but may be a memory device including a variable resistor (such as a phase change material).

[0047] The peripheral circuit region R2 may include a peripheral transistor region PS. The peripheral transistor region PS may include an active region 112 and a transistor, wherein the active region 112 is defined by an isolation layer 111 and the transistor is formed on the active region 112.

[0048] Multiple intermetallic dielectric layers 132, 143 and 153, multiple etch stop structures 140, 150 and 160, multiple interlayer dielectric layers 231, 163 and 164, and multi-level metal interconnects M1, M2, M3 and M4 may be included in the substrate 101, the unit transistor region CS and the peripheral transistor region PS of the cell array region R1 and the peripheral circuit region R2.

[0049] Although, according to this specific embodiment of the invention, the multi-level metal interconnects M1, M2, M3 and M4 and the plurality of etch stop structures 140, 150 and 160 are included in each of the cell array region R1 and the peripheral circuit region R2, according to another specific embodiment of the invention, the plurality of etch stop structures 140, 150 and 160 may be applied only to the multi-level metal interconnects M1, M2, M3 and M4 in one of the cell array region R1 and the peripheral circuit region R2.

[0050] Multilayer metal interconnects M1, M2, M3, and M4 may extend through intermetallic dielectric layers 132, 143, and 153. Intermetallic dielectric layers 132, 143, and 153 may include dielectric materials with low dielectric constants to reduce parasitic capacitance between metal interconnects M1, M2, M3, and M4. For example, intermetallic dielectric layers 132, 143, and 153 may be made of silicon oxide (SiCOH) containing carbon and hydrogen.

[0051] Interlayer dielectric layers 231, 163, and 164 may be located above the transistor Tr and the substrate 101, and between and above the fourth metal interconnect M4, which is the uppermost metal interconnect. Interlayer dielectric layers 231, 163, and 164 may comprise oxide materials having a higher dielectric constant than intermetallic dielectric layers 132, 143, and 153. For example, the first interlayer dielectric layer 231 and the second interlayer dielectric layer 163 may comprise tetraethyl orthosilicate (TEOS) oxide. According to another specific embodiment of the invention, the first interlayer dielectric layer 231 and the second interlayer dielectric layer 163 may comprise silicon oxide having a dielectric constant of about 3.9 to 4.5. Depending on the structure of the device region DR, the first interlayer dielectric layer 231 according to a specific embodiment of the invention may be formed as multiple layers 230-1 and 230-2.

[0052] The third interlayer dielectric layer 164 may include a hydrogen-containing silicon oxide. Compared to the second interlayer dielectric layer 163, the third interlayer dielectric layer 164 may include a dielectric material with a relatively high hydrogen supply capability. For example, the third interlayer dielectric layer 164 may include a high-density plasma (HDP) oxide. The third interlayer dielectric layer 164 may be referred to as a "hydrogen passivation layer" or a "hydrogen supply layer". When hydrogen is supplied through the hydrogen supply layer, it can be less affected by layers that block hydrogen diffusion compared to annealing in a hydrogen atmosphere.

[0053] A passivation layer 170 may be formed on the third interlayer dielectric layer 164. The passivation layer 170, together with the third interlayer dielectric layer 164, may act as a hydrogen source for supplying hydrogen to the surface of the substrate 101. The passivation layer 170 may be used to protect all structures stacked in a direction perpendicular to the substrate 101. The passivation layer 170 may, for example, include silicon nitride.

[0054] During the hydrogen passivation process, hydrogen in the third interlayer dielectric layer 164 can diffuse to the surface of the substrate 101 through the multilayer metal interconnects M1, M2, M3, and M4 electrically connected to the substrate 101. The surface of the substrate 101 to which hydrogen reaches can be the interface D1 of the gate dielectric layer forming the word line WL in the cell array region R1, and the interface D2 between the peripheral transistor region PS and the substrate 101 in the peripheral circuit region R2. Therefore, the trap sites at each interface D1 and interface D2 are filled with diffused hydrogen to significantly reduce the interface trap density. Thus, the leakage current characteristics of the transistor can be improved.

[0055] Etch stop structures 140, 150, and 160 may include a dielectric material having etch selectivity with respect to interlayer dielectric layers 231, 163, and 164 and intermetallic dielectric layers 132, 143, and 153. Etch stop structures 140, 150, and 160 may have a higher film density and strength than intermetallic dielectric layers 132, 143, and 153. Etch stop structures 140, 150, and 160 can prevent certain gases from escaping from or flowing into intermetallic dielectric layers 132, 143, and 153. In other words, etch stop structures 140, 150, and 160 can suppress the emission of gases such as hydrogen (H2), water vapor (H2O), fluorine, and chlorine from intermetallic dielectric layers 132, 143, and 153. Similarly, etch stop structures 140, 150 and 160 can be provided to prevent hydrogen or water vapor from flowing into the intermetallic dielectric layers 132, 143 and 153.

[0056] The etch stop structures 140, 150, and 160 of FIG3 may include the same stacking structure as the stacking structure of the etch stop structures 140, 150, and 160 shown in FIG1. ​​According to another specific embodiment of the present invention, the etch stop structures 140, 150, and 160 of FIG3 may be replaced by the etch stop structures 240, 250, and 260 of FIG2.

[0057] The first etch stop structure 140 may include a stacked structure of a first etch stop layer 141 and a second etch stop layer 142. The second etch stop structure 150 may include a stacked structure of a third etch stop layer 151 and a fourth etch stop layer 152. The third etch stop structure 160 may include a stacked structure of a fifth etch stop layer 161 and a sixth etch stop layer 162. The thickness of each etch stop structure 140, 150, and 160 may be less than the thickness of each inter-metal dielectric layer 132, 143, and 153. The thickness of each etch stop structure 140, 150, and 160 may be less than the thickness of each inter-layer dielectric layer 231, 163, and 164. The thickness of the first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 may be less than the thickness of the second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162, respectively. For example, when the thickness of the second etch stop layer 142 is about 250 Å to 700 Å, the thickness of the first etch stop layer 141 can be about 20 Å to 40 Å.

[0058] The first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 can be used to prevent hydrogen in the lower layer from diffusing into the upper layer through annealing processes, etc. In other words, the first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 can block hydrogen in the lower layer from diffusing into the upper layer during annealing processes used to allow hydrogen to diffuse into the surface of the substrate, and prevent hydrogen from being captured by the second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162. Therefore, the first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 can increase the efficiency of the annealing process for hydrogen diffusion by guiding it to concentrate along the hydrogen transport path.

[0059] Each of the first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 may include a hydrogen barrier material. The first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 may include a dielectric material having a silicon content higher than that of silicon nitride (Si3N4) having a stoichiometric composition. The first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 may be formed from silicon-rich silicon nitride (SRN) having a silicon content higher than that of silicon nitride (Si3N4) having a stoichiometric composition. Specifically, each of the first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 may be formed, not by a individually performed deposition process, but by pretreatment during the deposition process of each of the second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162. Each of the first etch stop layer 141, the third etch stop layer 151, and the fifth etch stop layer 161 may be formed in situ in the same cavity as each of the second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162.

[0060] The second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162 may include silicon nitride (Si3N4) having a lower dielectric constant than silicon nitride with a stoichiometric composition. The second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162 may include carbon-doped silicon nitride (NDC). The second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162 may include Si, C, and N. For example, the second etch stop layer 142, the fourth etch stop layer 152, and the sixth etch stop layer 162 may include SiCN.

[0061] The multi-level metal interconnects M1, M2, M3 and M4 may include metal interconnect contacts and conductive lines.

[0062] Figures 4A to 4G are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a specific example of the present invention. Although Figures 4A to 4G illustrate a method for manufacturing the semiconductor device shown in Figure 1, it can also be applied to the method for manufacturing the semiconductor devices shown in Figures 2 and 3.

[0063] Referring to FIG4A, the isolation layer 12 and the active region 13 may be formed in the substrate 11.

[0064] The active region 13 may be defined by the isolation layer 12. The isolation layer 12 may be formed by a shallow trench isolation (STI) process.

[0065] Subsequently, a transistor Tr can be formed on the substrate 11. The transistor Tr can have the same structure as the transistor Tr shown in FIG1.

[0066] Subsequently, impurity regions 14 may be formed in the substrate on both sides of the transistor Tr. Impurity regions 14 may be referred to as "source / drain regions". Impurity regions 14 may include N-type impurities, such as arsenic (As) or phosphorus (P).

[0067] Subsequently, a first interlayer dielectric layer 15 may be formed on the substrate 11 including the transistor Tr. The upper surface of the first interlayer dielectric layer 15 may be located at a higher horizontal level than the upper surface of the transistor Tr. For example, the first interlayer dielectric layer 15 may comprise TEOS oxide. According to another specific embodiment of the invention, the first interlayer dielectric layer 15 may comprise silicon oxide having a dielectric constant of about 3.9 to 4.5.

[0068] Subsequently, a first metal interconnect contact 21 coupled to the substrate 11 may be formed through the first interlayer dielectric layer 15. The substrate 11 coupled to the first metal interconnect contact 21 may be an impurity region 14. During the subsequent hydrogen passivation process, hydrogen transferred through the first metal interconnect contact 21 may be supplied to the interface 100 between the transistor Tr and the substrate 11 through the impurity region 14.

[0069] Referring to Figures 4B and 4C, a first intermetallic dielectric layer 31 including an opening OP can be formed on the first intermetallic dielectric layer 15 and the first metal interconnect contact 21.

[0070] To this end, a low-k material layer can be formed on the first interlayer dielectric layer 15 and the first metal interconnect contact 21, and a photomask pattern for opening the conductive line region can be formed on the low-k material layer. Subsequently, a series of processes for etching the low-k material layer can be performed using the photomask pattern.

[0071] The first intermetallic dielectric layer 31 may include a low-k material having a dielectric constant lower than that of silicon oxide (SiO2). The first intermetallic dielectric layer 31 may be referred to as a "low-k layer". For example, silicon oxide may have a dielectric constant of about 3.9 to 4.5. The first intermetallic dielectric layer 31 may have a dielectric constant of about 3.5 or less, for example, a dielectric constant of about 2.0 to 3.5. For example, the first intermetallic dielectric layer 31 may be a silicon oxide (SiCOH) comprising carbon and hydrogen.

[0072] Subsequently, a first conductive line 22 for filling the gap of the opening OP can be formed. The first conductive line 22 can be formed by a series of processes, including forming a conductive material on the first intermetallic dielectric layer 31 including the opening OP and etching the conductive material by using a target that exposes the upper surface of the first intermetallic dielectric layer 31. A barrier layer can be formed at the interface between the first intermetallic dielectric layer 31 and the first conductive line 22. The first metal interconnect contact 21 and the first conductive line 22 can be referred to as the first metal interconnect M1.

[0073] Referring to Figures 4D to 4F, the first etch stop structure 40 may be formed on the first intermetallic dielectric layer 31 including the first metal interconnect M1.

[0074] The first etch stop structure 40 may include a stacked structure of a first etch stop layer 41 and a second etch stop layer 42. The thickness of the first etch stop layer 41 may be less than the thickness of the second etch stop layer 42.

[0075] The first etch stop layer 41 may include a hydrogen barrier material. The first etch stop layer 41 may include a dielectric material having a silicon content higher than that of silicon nitride (Si3N4) having a stoichiometric composition. The first etch stop layer 41 may include a silicon-rich silicon nitride (SRN) having a silicon content higher than that of silicon nitride (Si3N4) having a stoichiometric composition. Specifically, the first etch stop layer 41 may be formed by pretreatment during the deposition process of the second etch stop layer 42, rather than by a separately performed deposition process. The first etch stop layer 41 may be formed in situ in the same cavity as the cavity of the second etch stop layer 42.

[0076] The second etch stop layer 42 may include a dielectric material having a lower dielectric constant than silicon nitride (Si3N4) having a stoichiometric composition. The second etch stop layer 42 may include carbon-doped silicon nitride (NDC). The second etch stop layer 42 may include Si, C, and N. For example, the second etch stop layer 42 may include SiCN.

[0077] Although the etch stop structure shown in FIG1 is illustrated in a specific example of the present invention, it will be apparent to those skilled in the art that the etch stop structure shown in FIG2 can also be applied.

[0078] Subsequently, a second intermetallic dielectric layer 43 may be formed on the first etch stop structure 40. The second intermetallic dielectric layer 43 may include the same material as the first intermetallic dielectric layer 31. The thickness of the second intermetallic dielectric layer 43 may be greater than the entire thickness of the first etch stop structure 40.

[0079] Subsequently, the second intermetallic dielectric layer 43 and the first etch stop structure 40 can be etched to form via V1 and trench T1.

[0080] The via V1 and the trench T1 can be formed using separate processes with a photomask. According to another specific embodiment of the invention, the via V1 and the trench T1 can be formed using a single photomask through a separate etching process, wherein the width of the single photomask is adjusted by a trimming process. For example, the trench T1 can be formed after the via V1 is formed. According to another specific embodiment of the invention, the via V1 can be formed after the trench T1 is formed.

[0081] Referring to Figures 4F and 4G, the second metal interconnect M2 can be formed in the via (V1, see Figure 4E) and the trench (T1, see Figure 4E).

[0082] The second metal interconnect M2 may include a second metal interconnect contact 45 filling the via V1 and a second conductive line 46 filling the trench T1. A barrier layer may be formed at the interface between the via V1 and the trench T1 and the second metal interconnect M2. The barrier layer may include titanium, titanium nitride, tantalum, or tantalum nitride.

[0083] The second metal interconnect contact 45 and the second conductive line 46 may comprise the same material. The second metal interconnect M2 may, for example, comprise copper (Cu). The second metal interconnect M2 may be formed by forming a conductive material filling the via V1 and trench T1 and performing a damascene process in which a planarization process is performed. The second metal interconnect M2 may be formed by forming a seed layer and performing an electroplating process. After performing the electroplating process, a separate annealing process may be performed separately.

[0084] Subsequently, the second etch stop structure 50 and the third intermetallic dielectric layer 53 including the third metal interconnect M3 can be formed on the second intermetallic dielectric layer 43 by repeating the processes of FIG4D and FIG4E and the conductive material forming process.

[0085] Subsequently, the third etch stop structure 60 and the second inter-metal dielectric layer 63 can be sequentially formed on the third inter-metal dielectric layer 53.

[0086] The third etch stop structure 60 can be formed by the same process as the first etch stop structure 40 and the second etch stop structure 50 (see FIG4E).

[0087] The second interlayer dielectric layer 63 may comprise the same material as the first interlayer dielectric layer 15. The second interlayer dielectric layer 63 may, for example, comprise tetraethyl orthosilicate (TEOS) oxide. According to another specific embodiment of the invention, the second interlayer dielectric layer 63 may comprise a silicon oxide having a dielectric constant of about 3.9 to 4.5.

[0088] Subsequently, a via V2 exposing a portion of the third metal interconnect M3 can be formed through the second interlayer dielectric layer 63 and the third etch stop structure 60.

[0089] Subsequently, a fourth metal interconnect contact 65 for gap filling of the via V2 can be formed. The fourth metal interconnect contact 65 may be the uppermost contact plug. The fourth metal interconnect contact 65 may include a material different from the first to third metal interconnects M1, M2, and M3. The fourth metal interconnect contact 65 may include a conductive material having a lower resistance than the first to third metal interconnects M1, M2, and M3. For example, the fourth metal interconnect contact 65 may include tungsten (W). A barrier layer may be formed at the interface between the fourth metal interconnect contact 65 and the second interlayer dielectric layer 63. The barrier layer may include tungsten nitride.

[0090] Subsequently, a fourth conductive line 66 may be formed on the fourth metal interconnect contact 65 and the second interlayer dielectric layer 63. The fourth metal interconnect contact 65 and the fourth conductive line 66 may be referred to as the fourth metal interconnect M4. Although the fourth metal interconnect M4 is illustrated as the uppermost metal interconnect in this specific example, the concept and spirit of the invention are not limited thereto.

[0091] The fourth conductive line 166 may have a shape extending in one direction when in contact with the upper surface of the fourth metal interconnect contact 65. The fourth conductive line 66 may include a conductive material having a lower resistance than the fourth metal interconnect contact 65. The fourth conductive line 66 may include a metallic material that exhibits reduced corrosion due to oxidation. For example, the fourth conductive line 66 may include aluminum. In the case of aluminum, when the surface is oxidized, aluminum oxide may be formed and used as an oxide film agent for the aluminum below.

[0092] Subsequently, a third interlayer dielectric layer 71 may be formed over the second interlayer dielectric layer 63 and the fourth conductive line 66. The third interlayer dielectric layer 71 may include a silicon oxide comprising hydrogen. For example, the third interlayer dielectric layer 71 may include HDP oxide. The third interlayer dielectric layer 71 may be referred to as a "hydrogen passivation layer" or a "hydrogen supply layer".

[0093] Subsequently, a passivation layer 72 may be formed on the third interlayer dielectric layer 71. The passivation layer 72 may, for example, include silicon nitride.

[0094] Subsequently, an annealing process AP can be performed to supply hydrogen from the third interlayer dielectric layer 71 to the surface of the substrate 11 (which is the interface 100 between the substrate 11 and the transistor Tr).

[0095] The heating for the annealing process can be applied from one side of the passivation layer 72, and hydrogen can be transferred to the substrate 11 through a hydrogen transport path including metal interconnects. During the annealing process, the passivation layer 72 can prevent hydrogen from being released in the direction opposite to the hydrogen transport path.

[0096] According to a specific embodiment of the present invention, the leakage current characteristics of the device can be improved by increasing the efficiency of hydrogen passivation, thereby ensuring reliability.

[0097] Although the present invention has been described with reference to specific examples, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims. [Simplified Explanation of the Diagram]

[0007] [Figure 1] is a cross-sectional view showing a semiconductor device according to a specific example of the present invention.

[0008] [Figure 2] and [Figure 3] are cross-sectional views illustrating semiconductor devices according to other specific examples of the present invention.

[0009] [Figures 4A] to [Figures 4G] are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a specific example of the present invention.

Claims

1. A semiconductor device comprising: A dielectric structure in which etch-stop structures and low-k layers are alternately stacked on a substrate; And a metal interconnect in the dielectric structure, the metal interconnect being electrically connected to the substrate, wherein each of the etch stop structures includes: a first etch stop layer, which is a silicon-rich silicon nitride having a higher silicon content than silicon nitride (Si3N4); and a second etch stop layer, which is a carbon-containing silicon nitride on the first etch stop layer.

2. The semiconductor device according to claim 1, wherein the second etch stop layer comprises SiCN.

3. The semiconductor device according to claim 1, wherein the thickness of the first etch stop layer is less than the thickness of the second etch stop layer.

4. The semiconductor device according to claim 1, wherein the thickness of each of the etch stop structures is less than the thickness of each of the low k layers.

5. The semiconductor device according to claim 1, wherein the low-k layer comprises a silicon oxide (SiCOH) containing carbon and hydrogen.

6. The semiconductor device according to claim 1, further comprising: Hydrogen supply layer on top of this dielectric structure.

7. The semiconductor device according to claim 6, wherein the hydrogen supply layer comprises high-density plasma (HDP) oxide, silicon nitride, or a combination thereof.

8. The semiconductor device according to claim 1, wherein the etch stop structure further comprises: A third etch stop layer is placed above the second etch stop layer, and the third etch stop layer includes another hydrogen barrier material.

9. The semiconductor device according to claim 8, wherein the third etch stop layer comprises a silicon-rich silicon nitride having a higher silicon content than silicon nitride (Si3N4).

10. The semiconductor device according to claim 1, wherein the metal interconnect comprises a multi-level metal interconnect.

11. The semiconductor device according to claim 1, wherein the substrate is provided with a transistor including a gate dielectric layer.

12. A method for manufacturing a semiconductor device, comprising: A dielectric structure is formed in which etch stop structures and low-k layers are alternately stacked on a substrate having a transistor including a gate dielectric layer. The dielectric structure forms a metal interconnect electrically connected to the substrate, wherein each of the etch stop structures includes: a first etch stop layer, which is a silicon-rich silicon nitride having a higher silicon content than silicon nitride (Si3N4); and a second etch stop layer, which is a carbon-containing silicon nitride on the first etch stop layer.

13. The method according to claim 12, wherein the first etch stop layer and the second etch stop layer are formed in situ in the same cavity.

14. The method according to claim 12, wherein the second etch stop layer comprises SiCN.

15. The method according to claim 12, wherein each of the low k layers comprises a silicon oxide (SiCOH) containing carbon and hydrogen.

16. The method according to claim 12, wherein each of the etch stop structures further comprises: A third etch stop layer is placed above the second etch stop layer, and the third etch stop layer includes another hydrogen barrier material.

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