Schmitt trigger circuit

Abstract

This invention provides a Schmitt trigger circuit that does not jitter its output even when connected to a communication bus without impedance matching and when the input signal is superimposed with reflected noise. The Schmitt trigger circuit of this invention includes a first signal detection circuit, a second signal detection circuit, a latch circuit, a selection signal generation circuit, a first input terminal, and a first output terminal. The first signal detection circuit is connected to the first input terminal, the latch circuit, and the selection signal generation circuit. The second signal detection circuit is connected to the first input terminal, the latch circuit, and the selection signal generation circuit. The latch circuit is connected to the selection signal generation circuit and the output terminal. The selection signal generation circuit includes a delay circuit.

Description

[Technical Field]

[0001] This invention relates to a Schmitt trigger circuit. [Previous Technology]

[0002] Conventional Schmitt trigger circuits sometimes exhibit reflected noise when the input terminals are connected to a communication bus or similar device without impedance matching. Furthermore, if an input signal with reflected noise is input to a conventional Schmitt trigger circuit, the output of the circuit may chatter, leading to device malfunction (see, for example, Patent Document 1). Prior Art Documents Patent Documents

[0003] Patent Document 1: Japanese Patent Application Publication No. 2000-332580 [Summary of the Invention]

[0004] The object of the present invention is to provide a Schmitt circuit in which the output of the Schmitt circuit does not jitter even when the input terminal is connected to a communication bus or the like where impedance matching is not achieved and the input signal is superimposed with reflected noise.

[0005] The Schmitt trigger circuit of the present invention is configured as follows: it includes a first signal detection circuit, a second signal detection circuit, a latch circuit, a selection signal generation circuit, a first input terminal, and a first output terminal. The first signal detection circuit has a second input terminal, a first selection signal input terminal, and a second output terminal. The first input terminal is connected to the second input terminal. The first selection signal input terminal is connected to the selection signal generation circuit. The second output terminal is connected to one of the inputs of the latch circuit. The second signal detection circuit has a third input terminal, a second selection signal input terminal, and a third output terminal. The first input terminal is connected to the third input terminal. The second selection signal input terminal is connected to the selection signal generation circuit. The third output terminal is connected to the other input of the latch circuit. The latch circuit is connected to the selection signal generation circuit and the output terminal. The selection signal generation circuit has a delay circuit.

[0006] Based on the above, even if the input signal is superimposed with reflected noise, the output of the Schmitt circuit will not jitter.

Implementation Method

[0008] [First Embodiment]

[0009] Hereinafter, the first embodiment of the present invention will be described with reference to the drawings. FIG1 is a circuit diagram showing an example of the Schmitt circuit 1 of this embodiment.

[0010] The structure of the Schmitt circuit 1 in this embodiment will be described. The Schmitt circuit 1 in this embodiment includes a first signal detection circuit 100, a second signal detection circuit 110, a reset set (RS) latch circuit 120, a selection signal generation circuit 130, an inverter 150, an inverter 151, an input terminal IN, and an output terminal OUT.

[0011] The first signal detection circuit 100 includes a first P-channel metal-oxide-semiconductor (MOS) transistor (hereinafter referred to as PMOS transistor) 101, a second PMOS transistor 102, a first N-channel MOS transistor (hereinafter referred to as NMOS transistor) 103, a second NMOS transistor 104, an input terminal 105, a selection signal input terminal 106, and an output terminal 107.

[0012] The second signal detection circuit 110 includes a third PMOS transistor 111, a fourth PMOS transistor 112, a third NMOS transistor 113, a fourth NMOS transistor 114, an input terminal 115, a selection signal input terminal 116, and an output terminal 117.

[0013] The RS latch circuit 120 includes a first NOR circuit 121, a second NOR circuit 122, a first input terminal 123, a second input terminal 124, and an output terminal 125.

[0014] The selection signal generation circuit 130 includes an input terminal 131 and an output terminal 132, and internally includes a delay circuit 140.

[0015] The connection of the Schmitt trigger circuit in this embodiment will be described. The input terminal IN is connected to the input terminal 105 of the first signal detection circuit 100 and the input terminal 115 of the second signal detection circuit 110. The output terminal 107 of the first signal detection circuit 100 is connected to the first input terminal 123 of the RS latch circuit 120 via an inverter 150. The output terminal 117 of the second signal detection circuit 110 is connected to the second input terminal 124 of the RS latch circuit 120. The output terminal 125 of the RS latch circuit 120 is connected to the input terminal 131 of the selection signal generation circuit 130 and to the output terminal OUT via an inverter 151. The output terminal 132 of the selection signal generation circuit 130 is connected to the selection signal input terminal 106 of the first signal detection circuit 100 and the selection signal input terminal 116 of the second signal detection circuit 110.

[0016] The connections of the first signal detection circuit 100 will be described. The input terminal 105 of the first signal detection circuit 100 is connected to the gate terminal of the second PMOS transistor 102 and the gate terminal of the first NMOS transistor 103. The selection signal input terminal 106 of the first signal detection circuit 100 is connected to the gate terminal of the first PMOS transistor 101 and the gate terminal of the second NMOS transistor 104. The source terminals of the first PMOS transistor 101 and the second PMOS transistor 102 are connected to the VDD terminal. The source terminal of the first NMOS transistor 103 is connected to the drain terminal of the second NMOS transistor 104. The source terminal of the second NMOS transistor 104 is connected to the ground (GND) terminal. The drain terminals of the first PMOS transistor 101, the second PMOS transistor 102, and the first NMOS transistor 103 are connected to the output terminal 107 of the first signal detection circuit 100.

[0017] The connection of the second signal detection circuit 110 will be described. The input terminal 115 of the second signal detection circuit 110 is connected to the gate terminal of the fourth PMOS transistor 112 and the gate terminal of the fourth NMOS transistor 114. The selection signal input terminal 116 of the second signal detection circuit 110 is connected to the gate terminal of the third PMOS transistor 111 and the gate terminal of the third NMOS transistor 113. The source terminal of the third PMOS transistor 111 is connected to the VDD terminal, and the drain terminal is connected to the source terminal of the fourth PMOS transistor 112. The source terminals of the third NMOS transistor 113 and the fourth NMOS transistor 114 are connected to the GND terminal. The drain terminals of the fourth PMOS transistor 112, the third NMOS transistor 113, and the fourth NMOS transistor 114 are connected to the output terminal 117 of the second signal detection circuit 110.

[0018] The connection of the RS latch circuit 120 will be described. The first input terminal of the first NOR circuit 121 is connected to the first input terminal 123 of the RS latch circuit 120, the second input terminal is connected to the output terminal of the second NOR circuit 122, and the output terminal is connected to the output terminal 125 of the RS latch circuit 120 and the first input terminal of the second NOR circuit 122. The second input terminal of the second NOR circuit 122 is connected to the second input terminal 124 of the RS latch circuit 120.

[0019] The operation of the Schmitt trigger circuit 1 of this embodiment will be described with reference to Figures 2(a) to 2(g) to 5. In Figures 2(a) to 2(g) to 5, the horizontal axis represents time and the vertical axis represents voltage. Figure 2(a) shows an example of the signal VIN input to the input terminal IN. Figure 2(b) shows the signal SETX at the output terminal 107 of the first signal detection circuit 100, and Figure 2(c) shows the signal SET obtained by inverting the signal SETX using the inverter 150. Figure 2(d) shows the signal RST at the output terminal 117 of the second signal detection circuit 110. Figure 2(e) shows the signal SELECT at the output terminal 132 of the selection signal generation circuit 130. Figure 2(f) shows the signal DOX at the output terminal 125 of the RS latch circuit 120, and Figure 2(g) shows the signal VOUT at the output terminal OUT obtained by inverting the signal DOX using the inverter 151. Regarding Figures 3(a) to 3(g) and Figures 5(a) to 5(g), (a) to (g) also represent an example of the same signal.

[0020] The voltage VIH shown in Figure 2(a) represents the threshold voltage of the first signal detection circuit 100. The voltage VIL represents the threshold voltage of the second signal detection circuit 110. Voltages VIH and VIL are set such that VIH > VIL. The threshold voltage VIH of the first signal detection circuit 100 is determined by the size ratio of the second PMOS transistor 102 to the first NMOS transistor 103. Similarly, the threshold voltage VIL of the second signal detection circuit 110 is determined by the size ratio of the fourth PMOS transistor 112 to the fourth NMOS transistor 114. When the channel length L of the MOS transistors is the same, if the channel width W of the PMOS transistor is greater than the channel width W of the NMOS transistor, the threshold voltage becomes higher; if the channel width W of the PMOS transistor is less than the channel width W of the NMOS transistor, the threshold voltage becomes lower. For example, by making the channel width W of the second PMOS transistor 102 greater than the channel width W of the first NMOS transistor 103, and making the channel width W of the fourth PMOS transistor 112 less than the channel width W of the fourth NMOS transistor 114, the voltage VIH can be set to be greater than the voltage VIL. Furthermore, this setting example is one instance; the threshold voltage can also be set by adjusting anything other than the channel width W.

[0021] [Explanation of typical actions]

[0022] Referring to Figures 2(a) to 2(g) and Figures 3(a) to 3(g), the operation of the first signal detection circuit 100 will be explained. Figures 2(a) to 2(g) show the state where the signal VIN rises from a low level to a high level. The signal VIN shown in Figure 2(a) rises from time T0 and rises again after the voltage VIH exceeds the time T2. The signal VIN is applied from the input terminal IN to the input terminal 105 of the first signal detection circuit 100. If the signal SELECT input to the selection signal input terminal 106 is at a high level from time T0 to time T7 as shown in Figure 2(e), and the signal VIN shown in Figure 2(a) is input to the input terminal 105, then the signal SETX output from the output terminal 107 will fall from a high level to a low level at time T2, as shown in Figure 2(b). If the signal SELECT falls to a low level at time T7 after the delay time Delay, then the signal SETX will rise from a low level to a high level at time T7.

[0023] When the signal SELECT is high, the first signal detection circuit 100 outputs a high-level signal SETX from the output terminal 107 when the signal VIN applied to the input terminal 105 is lower than the voltage VIH, and outputs a low-level signal SETX from the output terminal 107 when the signal VIN is higher than the voltage VIH. When the signal SELECT is low, the first signal detection circuit 100 outputs a high-level signal SETX from the output terminal 107 regardless of the voltage of the signal VIN applied to the input terminal 105.

[0024] Figures 3(a) to 3(g) show the state of signal VIN decreasing from high level to low level. In Figure 3(a), signal VIN begins to decrease from time T10 and decreases again after exceeding voltage VIL at time T12. Signal VIN is applied from input terminal IN to input terminal 105 of the first signal detection circuit 100. If signal SELECT, input to selection signal input terminal 106, is low from time T10 to time T17 as shown in Figure 3(e), and signal VIN as shown in Figure 3(a) is input to input terminal 105, then signal SETX, output from output terminal 107, as shown in Figure 3(b), remains high from time T10 to time T17 without change. If signal SELECT rises to high level at time T17 after the delay time Delay, then signal SETX remains high at time T17 without change.

[0025] Referring to Figures 2(a) to 2(g) and Figures 3(a) to 3(g), the operation of the second signal detection circuit 110 will be explained. The signal VIN shown in Figure 2(a) is applied from the input terminal IN to the input terminal 115 of the second signal detection circuit 110. If the signal SELECT input to the selection signal input terminal 116 is at a high level from time T0 to time T7 as shown in Figure 2(e), and the signal VIN shown in Figure 2(a) is input to the input terminal 115, then the signal RST output from the output terminal 117 remains at a low level from time T0 to time T7 as shown in Figure 2(d). If the signal SELECT drops to a low level at time T7 after the delay time Delay, then the signal RST remains at a low level at time T7.

[0026] The signal VIN shown in Figure 3(a) is applied from the input terminal IN to the input terminal 115 of the second signal detection circuit 110. If the signal SELECT input to the selection signal input terminal 116 is at a low level from time T10 to time T17 as shown in Figure 3(e), and the signal VIN shown in Figure 3(a) is input to the input terminal 115, then the signal RST output from the output terminal 117, as shown in Figure 3(d), rises from a low level to a high level at time T12. If the signal SELECT rises to a high level at time T17 after the delay time Delay, then the signal RST falls from a high level to a low level at time T17.

[0027] When the signal SELECT is low, the second signal detection circuit 110 outputs a low-level signal RST from the output terminal 117 if the signal VIN applied to the input terminal 115 is higher than the voltage VIL, and outputs a high-level signal RST from the output terminal 117 if the signal VIN applied to the input terminal 115 is lower than the voltage VIL. When the signal SELECT is high, the second signal detection circuit 110 outputs a low-level signal RST from the output terminal 117 regardless of the voltage of the signal VIN applied to the input terminal 115.

[0028] Referring to Figures 2(a) to 2(g) and Figures 3(a) to 3(g), the operation of the RS latch circuit 120 will be described. The RS latch circuit 120 inputs the signal SET (inverted by the inverter 150 to the signal SETX) to its first input terminal 123, the signal RST to its second input terminal 124, and the signal DOX to its output terminal 125. Figure 2 shows the state where the signal VIN rises from low to high. In Figure 2(c), the signal SET rises from low to high at time T2 and falls from high to low at time T7. In Figure 2(d), the signal RST remains low from time T0 to time T7. In Figure 2(f), the signal DOX falls from high to low at time T2. In Figure 2(g), the signal VOUT at the output terminal OUT rises from low to high at time T2. The RS latch circuit is described as an example of a latch circuit, but it is not limited to the RS latch circuit. For example, the JK latch circuit can also be used as long as it has the same function.

[0029] Figures 3(a) to 3(g) show the state of signal VIN falling from high level to low level. The signal RST shown in Figure 3(d) rises from low level to high level at time T12 and falls from high level to low level at time T17. The signal SET shown in Figure 3(c) remains low from time T10 to time T17. The signal DOX shown in Figure 3(f) rises from low level to high level at time T12. The signal VOUT at the output terminal OUT shown in Figure 3(g) falls from high level to low level at time T12.

[0030] Referring to Figures 2(a) to 2(g) and Figures 3(a) to 3(g), the operation of the selection signal generation circuit 130 will be described. The selection signal generation circuit 130 inputs a signal DOX to its input terminal 131 and outputs a signal SELECT from its output terminal 132. The selection signal generation circuit 130 has an internal delay circuit 140. After the input signal DOX changes, the signal SELECT changes after a delay time Delay based on the delay circuit 140. If the signal DOX shown in Figure 2(f) decreases at time T2, then the signal SELECT shown in Figure 2(e) decreases at time T7 after the delay time Delay. If the signal DOX shown in Figure 3(f) increases at time T12, then the signal SELECT shown in Figure 3(e) increases at time T17 after the delay time Delay.

[0031] If the selection signal generation circuit 130 is configured to perform this operation, it can be constructed as a combinational logic circuit, and may include an application-specific integrated circuit (ASIC), or a programmable single-chip microcomputer. The delay time of the internal delay circuit 140 is set to be longer than the noise of the reflected signal as envisioned based on the signal wiring length, etc., and shorter than the pulse width of the input signal.

[0032] In the Schmitt circuit 1 of this embodiment, if the signal VIN input to the input terminal IN as shown in FIG2(a) rises above the voltage VIH (which is higher than the voltage VIL) at time T2, then the signal VOUT output from the output terminal OUT as shown in FIG2(g) rises from a low level to a high level at time T2. Furthermore, in the Schmitt circuit 1 of this embodiment, if the signal VIN input to the input terminal IN as shown in FIG3(a) falls below the voltage VIL (which is lower than the voltage VIH) at time T12, then the signal VOUT output to the output terminal OUT as shown in FIG3(g) falls from a high level to a low level at time T12.

[0033] [Description of the operation with superimposed reflected noise input]

[0034] Referring to Figures 4(a) to 4(g) and Figures 5(a) to 5(g), the operation of the Schmitt trigger circuit 1 in this embodiment when a signal VIN superimposed with reflected noise is input to the input terminal IN is described. Figure 4(a) shows the state in which the signal VIN superimposed with reflected noise rises from a low level to a high level. The signal VIN shown in Figure 4(a) has reflected noise superimposed on it, and it starts to rise at time T20, rises again at time T22 after exceeding the voltage VIH, falls again at time T23 after exceeding the voltage VIH, falls again at time T24 after exceeding the voltage VIL, rises again at time T25 after exceeding the voltage VIL, and rises again at time T26 after exceeding the voltage VIH.

[0035] The operation of the first signal detection circuit 100 will be described with reference to Figures 4(a) to 4(g). The signal VIN is applied from the input terminal IN to the input terminal 105 of the first signal detection circuit 100. If the signal SELECT, which is input to the selection signal input terminal 106, is at a high level from time T20 to time T27 as shown in Figure 4(e), and the signal VIN shown in Figure 4(a) is input to the input terminal 105, then the signal SETX output from the output terminal 107, as shown in Figure 4(b), decreases from a high level to a low level at time T22, increases from a low level to a high level at time T23, and decreases from a high level to a low level at time T26. If the signal SELECT decreases to a low level at time T27 after the delay time Delay, then the signal SETX increases from a low level to a high level at time T27.

[0036] The operation of the second signal detection circuit 110 will be described with reference to Figures 4(a) to 4(g). The signal VIN is applied from the input terminal IN to the input terminal 115 of the second signal detection circuit 110. If the signal SELECT, which is input to the selection signal input terminal 116, is at a high level from time T20 to time T27 as shown in Figure 4(e), and the signal VIN shown in Figure 4(a) is input to the input terminal 115, then the signal RST output from the output terminal 117 remains at a low level from time T20 to time T27 as shown in Figure 4(d). If the signal SELECT drops to a low level at time T27 after the delay time Delay, then the signal RST remains at a low level at time T27.

[0037] The operation of the RS latch circuit 120 will be explained with reference to Figures 4(a) to 4(g). The signal SET shown in Figure 4(c) rises from low to high at time T22, falls from high to low at time T23, rises from low to high at time T26, and falls from high to low at time T27. The signal RST shown in Figure 4(d) remains low from time T20 to time T27. The signal DOX shown in Figure 4(f) falls from high to low at time T22. The signal VOUT at the output terminal OUT shown in Figure 4(g) rises from low to high at time T22. The operation of the selection signal generation circuit 130 will be explained with reference to Figures 4(a) to 4(g). If the signal DOX shown in Figure 4(f) falls at time T22, then the signal SELECT shown in Figure 4(e) falls at time T27 after the delay time Delay.

[0038] In the Schmitt circuit 1 of this embodiment, even if the signal VIN shown in FIG4(a), which rises above voltage VIH, falls above voltage VIL, and rises above voltage VIH again, is input to the input terminal IN, the signal VOUT output from the output terminal OUT will not jitter.

[0039] Figure 5(a) shows the state of the signal VIN with superimposed reflection noise decreasing from high level to low level. The signal VIN shown in Figure 5(a) has superimposed reflection noise, which starts to rise at time T30, falls below voltage VIL at time T32, rises above voltage VIL at time T33, rises above voltage VIH at time T34, falls below voltage VIH at time T35, and falls below voltage VIL at time T36.

[0040] The operation of the first signal detection circuit 100 will be described with reference to Figures 5(a) to 5(g). The signal VIN shown in Figure 5(a) is applied from the input terminal IN to the input terminal 105 of the first signal detection circuit 100. If the signal SELECT input to the selection signal input terminal 106 is at a low level from time T30 to time T37 as shown in Figure 5(e), and the signal VIN shown in Figure 5(a) is input to the input terminal 105, then the signal SETX output from the output terminal 107 remains at a high level from time T30 to time T37 as shown in Figure 5(b). If the signal SELECT drops to a low level at time T37 after the delay time Delay, then the signal SETX remains at a high level at time T37.

[0041] The operation of the second signal detection circuit 110 will be described with reference to Figures 5(a) to 5(g). The signal VIN is applied from the input terminal IN to the input terminal 115 of the second signal detection circuit 110. If the signal SELECT, which is input to the selection signal input terminal 116, is at a low level from time T30 to time T37 as shown in Figure 5(e), and the signal VIN shown in Figure 5(a) is input to the input terminal 115, then the signal RST output from the output terminal 117, as shown in Figure 5(d), rises from a low level to a high level at time T32, falls from a high level to a low level at time T33, and rises from a low level to a high level at time T36. If the signal SELECT falls to a low level at time T37 after the delay time Delay, then the signal RST falls from a high level to a low level at time T37.

[0042] The operation of the RS latch circuit 120 will be explained with reference to Figures 5(a) to 5(g). The signal SET shown in Figure 5(c) remains low from time T30 to time T37. The signal RST shown in Figure 5(d) rises from low to high at time T32, falls from high to low at time T33, rises from low to high at time T36, and falls from high to low at time T37. The signal DOX shown in Figure 5(f) rises from low to high at time T32. The signal VOUT at the output terminal OUT shown in Figure 5(g) falls from high to low at time T32. The operation of the selection signal generation circuit 130 will be explained with reference to Figures 5(a) to 5(g). If the signal DOX shown in Figure 5(f) rises at time T32, then the signal SELECT shown in Figure 5(e) rises at time T37 after the delay time Delay.

[0043] In the Schmitt circuit 1 of this embodiment, even if the signal VIN shown in FIG5(a), which drops after exceeding voltage VIL, rises after exceeding voltage VIH, and drops again after exceeding voltage VIL, is input to the input terminal IN, the signal VOUT output from the output terminal OUT will not jitter.

[0044] As explained above, the Schmitt circuit 1 of this embodiment operates as a Schmitt circuit that does not produce jitter whether the signal VIN, which is superimposed with reflected noise, rises or falls.

[0045] [Second Embodiment]

[0046] Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG6 is a circuit diagram showing an example of the Schmitt circuit 1a of this embodiment. The same symbols are used to denote structural elements that are the same as those in the first embodiment, and their descriptions are omitted.

[0047] The Schmitt circuit 1a of this embodiment includes a first signal detection circuit 100, a second signal detection circuit 110, an RS latch circuit 120, a second selection signal generation circuit 130a, an inverter 150, an inverter 151, an inverter 152, a fifth NMOS transistor 153, an input terminal IN, an output terminal OUT, and an enable input terminal EN.

[0048] The Schmitt circuit 1a of this embodiment differs from the Schmitt circuit 1 of the first embodiment in that the Schmitt circuit 1a of this embodiment includes an enable input terminal EN, an inverter 152, a fifth NMOS transistor 153, and a second selection signal generation circuit 130a that replaces the selection signal generation circuit 130. The second selection signal generation circuit 130a includes an input terminal 131, a third output terminal 133, a fourth output terminal 134, and an enable terminal 135, and internally includes a delay circuit 140.

[0049] The connections of the Schmitt trigger circuit 1a in this embodiment will be described. The enable input terminal EN is connected to the enable terminal 135 of the second selection signal generation circuit 130a, and is connected to the gate terminal of the fifth NMOS transistor 153 via the inverter 152. The third output terminal 133 of the second selection signal generation circuit 130a is connected to the selection signal input terminal 106 of the first signal detection circuit 100. The fourth output terminal 134 of the second selection signal generation circuit 130a is connected to the selection signal input terminal 116 of the second signal detection circuit 110. The drain terminal of the fifth NMOS transistor 153 is connected to the output terminal 125 of the RS latch circuit 120 and the input terminal 131 of the second selection signal generation circuit 130a. The source terminal of the fifth NMOS transistor 153 is connected to the GND terminal.

[0050] The operation of the Schmitt circuit 1a in this embodiment will be explained.

[0051] [Explanation of the operation when the enable signal is high]

[0052] The operation of the Schmitt circuit 1a in this embodiment when a high-level signal is input to the enable input terminal EN will be described. If a high-level signal is input to the enable input terminal EN, a low-level signal is input to the gate terminal of the fifth NMOS transistor 153 via the inverter 152, and a high-level signal is input to the enable terminal 135 of the second selection signal generation circuit 130a. The fifth NMOS transistor 153 becomes off. If the second selection signal generation circuit 130a inputs the signal DOX to the input terminal 131, after a delay time Delay based on the delay circuit 140, the SELECT1 signal is output from the third output terminal 133, and the SELECT2 signal is output from the fourth output terminal 134. The SELECT1 and SELECT2 signals when the enable signal is high are the same as the SELECT signal in the first embodiment. The operation of the Schmitt circuit 1a in this embodiment when the enable signal is high is the same as that of the Schmitt circuit 1 in the first embodiment.

[0053] [Explanation of the operation when the enable signal is low]

[0054] The operation of the Schmitt trigger circuit 1a in this embodiment when a low-level signal is input to the enable input terminal EN will be described. If a low-level signal is input to the enable input terminal EN, a high-level signal is input to the gate terminal of the fifth NMOS transistor 153 via the inverter 152, and a low-level signal is input to the enable terminal 135 of the second selection signal generation circuit 130a. The fifth NMOS transistor 153 becomes ON.

[0055] If a low-level signal is input to the enable terminal 135, the second selection signal generation circuit 130a outputs a low-level signal SELECT1 from the third output terminal 133 and a high-level signal SELECT2 from the fourth output terminal 134. The low-level signal SELECT1 is input to the selection signal input terminal 106 of the first signal detection circuit 100. The first signal detection circuit 100 outputs a high-level signal SETX from the output terminal 107, regardless of the signal input to the input terminal 105. The high-level signal SELECT2 is input to the selection signal input terminal 116 of the second signal detection circuit 110. The second signal detection circuit 110 outputs a low-level signal RST from the output terminal 117, regardless of the signal input to the input terminal 115.

[0056] The RS latch circuit 120 inputs a low-level SET signal from the output terminal 107 of the first signal detection circuit 100 to the first input terminal 123 via the inverter 150, and inputs a low-level RST signal from the output terminal 117 of the second signal detection circuit 110 to the second input terminal 124. The output of the RS latch circuit 120's output terminal 125 maintains the voltage level of the previous output signal. On the other hand, the output terminal 125 of the RS latch circuit 120 is connected to the GND terminal via the fifth NMOS transistor 153. A high-level signal VOUT is continuously output via the output terminal OUT of the inverter 151. In this embodiment, the fifth NMOS transistor 153 operates as a switch connecting the output terminal 125 of the RS latch circuit 120 to the GND terminal.

[0057] The second selection signal generation circuit 130a, if structured to perform this operation, can be constructed using combinational logic circuits, and may include ASICs, or programmable single-chip microcomputers, etc. The delay time of the internal delay circuit 140 is set to be longer than the noise of the reflected signal as envisioned based on the signal wiring length, etc., and shorter than the pulse width of the input signal.

[0058] As described above, if a high-level signal is input to the enable input terminal EN, the Schmitt circuit 1a of this embodiment performs the same operation as the Schmitt circuit 1 of the first embodiment. If a low-level signal is input to the enable input terminal EN, a high-level signal VOUT is output from the output terminal OUT regardless of the signal at the input terminal IN.

[0059] [Third Embodiment]

[0060] Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. FIG7 is a block diagram showing an example of the Schmitt circuit 1b of this embodiment. Structural elements that are the same as those in the first embodiment are labeled with the same reference numerals, and their descriptions are omitted.

[0061] The structure of the Schmitt circuit 1b in this embodiment will be described. The Schmitt circuit 1b in this embodiment includes a third signal detection circuit 100a, a fourth signal detection circuit 110a, an RS latch circuit 120, a third selection signal generation circuit 130b, an inverter 151, an input terminal IN, and an output terminal OUT.

[0062] The third signal detection circuit 100a includes a fifth signal detection circuit 160, a first AND circuit 163, an input terminal 105a, a selection signal input terminal 106a, and an output terminal 107a. Input terminal 105a is connected to input terminal 161 of the fifth signal detection circuit 160. Output terminal 162 of the fifth signal detection circuit 160 is connected to the first input terminal of the first AND circuit 163. Selection signal input terminal 106a is connected to the second input terminal of the first AND circuit 163.

[0063] The fourth signal detection circuit 110a includes a sixth signal detection circuit 170, a second AND circuit 173, an input terminal 115a, a selection signal input terminal 116a, and an output terminal 117a. Input terminal 115a is connected to input terminal 171 of the sixth signal detection circuit 170. Output terminal 172 of the sixth signal detection circuit 170 is connected to the first input terminal of the second AND circuit 173. Selection signal input terminal 116a is connected to the second input terminal of the second AND circuit 173. The third selection signal generation circuit 130b includes an input terminal 131, a fifth output terminal 136, and a sixth output terminal 137.

[0064] The connection of the Schmitt trigger circuit 1b in this embodiment will be described. The input terminal IN is connected to the input terminal 105a of the third signal detection circuit 100a and the input terminal 115a of the fourth signal detection circuit 110a. The output terminal 107a of the third signal detection circuit 100a is connected to the first input terminal 123 of the RS latch circuit 120. The output terminal 117a of the fourth signal detection circuit 110a is connected to the second input terminal 124 of the RS latch circuit 120. The output terminal 125 of the RS latch circuit 120 is connected to the input terminal 131 of the third selection signal generation circuit 130b and is connected to the output terminal OUT via the inverter 151. The fifth output terminal 136 of the third selection signal generation circuit 130b is connected to the selection signal input terminal 106a of the third signal detection circuit 100a. The sixth output terminal 137 of the third selection signal generation circuit 130b is connected to the selection signal input terminal 116a of the fourth signal detection circuit 110a.

[0065] Referring to Figures 8(a) to 8(g) and Figures 9(a) to 9(g), the operation of the Schmitt trigger circuit 1b of this embodiment will be described. Figure 8(a) shows the state in which the signal VIN, superimposed with reflected noise, rises from a low level to a high level. The signal VIN shown in Figure 8(a) is superimposed with reflected noise, and it starts to rise at time T40, rises above voltage VIL at time T41, rises above voltage VIH at time T42, falls below voltage VIH at time T43, falls below voltage VIL at time T44, rises above voltage VIL at time T45, and rises above voltage VIH at time T46. Here, voltage VIH is the threshold voltage of the fifth signal detection circuit, voltage VIL is the threshold voltage of the sixth signal detection circuit, and voltage VIH and voltage VIL have a relationship of voltage VIH > voltage VIL.

[0066] As shown in Figure 8(b), if the voltage at input terminal 105a exceeds voltage VIH, the third signal detection circuit 100a outputs a high-level DET1 signal from output terminal 107a; if the voltage at input terminal 105a falls below voltage VIH, the third signal detection circuit 100a outputs a low-level DET1 signal from output terminal 107a. As shown in Figure 8(c), if the voltage at input terminal 115a exceeds voltage VIL, the fourth signal detection circuit 110a outputs a low-level DET2 signal from output terminal 117a; if the voltage at input terminal 115a falls below voltage VIL, the fourth signal detection circuit 110a outputs a high-level DET2 signal from output terminal 117a.

[0067] If the signal DOX is input at the input terminal 131, the third selection signal generation circuit 130b outputs a signal SELECT3 with the same voltage level as the signal DOX from the fifth output terminal 136 after a delay time based on the delay circuit 140, and outputs a signal SELECT4 that inverts the signal DOX from the sixth output terminal.

[0068] If the signal VIN from Figure 8(a) is input to the input terminal IN, the third signal detection circuit 100a outputs the signal DET1 shown in Figure 8(b) from the output terminal 107a, that is, it rises to a high level at time T42, falls to a low level at time T43, and rises to a high level at time T46. The fourth signal detection circuit 110a outputs the signal DET2 shown in Figure 8(c) from the output terminal 117a, that is, it falls to a low level at time T41, rises to a high level at time T44, and falls to a low level at time T45.

[0069] If the signal DOX at the output terminal 125 of the RS latch circuit 120 is initialized to a high level, then between time T40 and time T47, the third selection signal generation circuit 130b outputs a high-level signal SELECT3, as shown in Figure 8(d), from the fifth output terminal 136, and a low-level signal SELECT4, as shown in Figure 8(e), which is the result of inverting the signal DOX, from the sixth output terminal. The RS latch circuit 120 inputs the signal DET1 from the third signal detection circuit 100a to the first input terminal 123, and inputs a low-level signal from the fourth signal detection circuit 110a to the second input terminal 124. The RS latch circuit 120 outputs the signal DOX, as shown in Figure 8(f), which falls at time T42, from the output terminal 125. After a delay time Delay based on the delay circuit 140, the third selection signal generation circuit 130b outputs the signals SELECT3 and SELECT4, which are inverted at time T47. In this embodiment, the Schmitt circuit 1b outputs a signal VOUT, as shown in Figure 8(g), which is generated by inverting the signal DOX using inverter 151, from the output terminal OUT.

[0070] Figure 9(a) shows the state of the signal VIN with superimposed reflection noise decreasing from high level to low level. The signal VIN shown in Figure 9(a) has superimposed reflection noise, which starts to rise at time T50, falls after exceeding voltage VIH at time T51, falls after exceeding voltage VIL at time T52, rises after exceeding voltage VIL at time T53, rises after exceeding voltage VIH at time T54, falls after exceeding voltage VIH at time T55, and falls after exceeding voltage VIL at time T56.

[0071] If the signal VIN from Figure 9(a) is input to the input terminal IN, the third signal detection circuit 100a outputs the signal DET1 shown in Figure 9(b) from the output terminal 107a, that is, it drops to a low level at time T51, rises to a high level at time T54, and drops to a low level at time T55. The fourth signal detection circuit 110a outputs the signal DET2 shown in Figure 9(c) from the output terminal 117a, that is, it rises to a high level at time T52, drops to a low level at time T53, and rises to a high level at time T56.

[0072] Between time T50 and time T57, the third selection signal generation circuit 130b outputs a low-level signal SELECT3, as shown in Figure 9(d), from the fifth output terminal 136, which is the same as the signal DOX from time T50 to time T52. It also outputs a high-level signal SELECT4, as shown in Figure 9(e), which is the inversion of signal SELECT3. The RS latch circuit 120 inputs a low-level signal from the third signal detection circuit 100a to the first input terminal 123, and inputs the signal DET2 from the fourth signal detection circuit 110a to the second input terminal 124. The RS latch circuit 120 outputs a rising signal DOX, as shown in Figure 9(f), from the output terminal 125. After a delay time Delay based on the delay circuit 140, the third selection signal generation circuit 130b outputs signals SELECT3 and SELECT4, which are inverted at time T57. In this embodiment, the Schmitt circuit 1b outputs a signal VOUT, as shown in Figure 9(g), which is generated by inverting the signal DOX using inverter 151, from the output terminal OUT.

[0073] In addition, the Schmitt circuit 1b of this embodiment may also have a structure including an enable input terminal EN, just like the Schmitt circuit 1a of the second embodiment.

[0074] As explained above, according to the Schmitt circuit of the present invention, even if the input terminal of the Schmitt circuit is connected to a signal line or the like that is not impedance matched, and the input signal is superimposed with reflected noise due to impedance mismatch, the output signal can still be output without jitter. [Simplified Explanation of the Diagram]

[0007] FIG1 is a circuit diagram showing an example of a Schmitt trigger circuit according to a first embodiment of the present invention. FIG2 is a diagram showing an example of the input-output waveforms of a Schmitt trigger circuit according to a first embodiment of the present invention. FIG3 is a diagram showing another example of the input-output waveforms of a Schmitt trigger circuit according to a first embodiment of the present invention. FIG4 is a diagram showing another example of the input-output waveforms of a Schmitt trigger circuit according to a first embodiment of the present invention. FIG5 is a diagram showing another example of the input-output waveforms of a Schmitt trigger circuit according to a first embodiment of the present invention. FIG6 is a circuit diagram showing an example of a Schmitt trigger circuit according to a second embodiment of the present invention. FIG7 is a circuit diagram showing an example of a Schmitt trigger circuit according to a third embodiment of the present invention. FIG8 is a diagram showing an example of the input-output waveforms of a Schmitt trigger circuit according to a third embodiment of the present invention. FIG9 is a diagram showing another example of the input-output waveforms of a Schmitt trigger circuit according to a third embodiment of the present invention.

Claims

1. A Schmitt trigger circuit, comprising: The circuit includes a first signal detection circuit, a second signal detection circuit, a latch circuit, a selection signal generation circuit, a first input terminal, a first output terminal, and an enable input terminal. A switch is connected to the output terminal of the latch circuit. The first signal detection circuit has a second input terminal, a first selection signal input terminal, and a second output terminal. The first input terminal is connected to the second input terminal. The first selection signal input terminal is connected to the selection signal generation circuit. The second output terminal is connected to one of the inputs of the latch circuit. The second signal detection circuit has a third input terminal, a second selection signal input terminal, and a third output terminal. The first input terminal is connected to the third input terminal. The second selection signal input terminal is connected to the selection signal generation circuit. The third output terminal is connected to the other input of the latch circuit. The latch circuit is connected to the selection signal generation circuit and the first output terminal. The selection signal generation circuit has a delay circuit. The enable input terminal is connected to the selection signal generation circuit and the switch. The selection signal generation circuit outputs a high-level signal from the first signal detection circuit and a low-level signal from the second signal detection circuit according to the signal from the enable input terminal. The switch is connected between the output terminal of the latch circuit and the ground terminal.

2. The Schmitt trigger circuit as described in claim 1, wherein, The latch circuit is a reset latch circuit.

3. The Schmitt trigger circuit as described in claim 1, wherein, The absolute value of the detection voltage of the first signal detection circuit is greater than the absolute value of the detection voltage of the second signal detection circuit.

4. The Schmitt trigger circuit as described in claim 2, wherein, The absolute value of the detection voltage of the first signal detection circuit is greater than the absolute value of the detection voltage of the second signal detection circuit.

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