Through-electrode substrate, assembly substrate, and manufacturing method of through-electrode substrate

Abstract

A through-electrode substrate includes: a substrate comprising a first surface and a second surface, having a through-hole, the through-hole including a wall extending from the first surface to the second surface; and a through-electrode located in the through-hole, extending from the first surface to the second surface. The through-electrode includes: a seed layer located on the aforementioned wall surface, extending along the wall surface from the first surface toward the second surface; a first portion covering the seed layer; and a second portion connected to the first portion at an interface traversing the through-hole.

Description

Technical Field

[0001] The embodiments disclosed herein relate to a through electrode substrate, an assembly substrate, and a method for manufacturing the through electrode substrate. Prior Technology

[0002] Through-electrode substrates are used in a variety of applications. A through-electrode substrate comprises a substrate with through-holes and electrodes located within the through-holes. For example, a through-electrode substrate is used as an interposer between two LSI wafers. Furthermore, through-electrode substrates are sometimes used between components such as LSI wafers and assembly substrates such as motherboards. Additionally, in the following description, the electrodes located inside the through-holes are sometimes referred to as through-electrodes. [Previous Technical Documents] [Patent Literature]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-61554 Summary of the Invention

[0004] Examples of through-hole electrodes include filled vias and conformal vias. A conformal via consists of a conductive material such as copper filling the interior of the via. A conformal via also includes a conductive layer extending along the walls of the via. From the viewpoint of reducing resistance, filled vias are preferable. However, when filled vias are formed through plating, voids are easily generated. A void is a hole defect that forms inside the filled via. Voids can occur if the plating growth rate inside the via is not properly controlled.

[0005] The implementation disclosed herein was created with these problems in mind, and its purpose is to provide a through electrode substrate with through electrodes that suppress voids.

[0006] The implementation of this disclosure relates to the following [1]~

[21] . [1] A through-electrode substrate, comprising: A substrate, comprising a first surface and a second surface located opposite to the first surface, is provided with a through hole, the through hole including a wall surface extending from the first surface to the second surface; and A through electrode is located in the aforementioned through hole, extending from the aforementioned first surface to the aforementioned second surface; The aforementioned through-hole electrode comprises: a seed layer located on the aforementioned wall surface, extending along the aforementioned wall surface from the aforementioned first surface toward the aforementioned second surface; a first portion covering the aforementioned seed layer; and a second portion connected to the aforementioned first portion at an interface traversing the aforementioned through-hole.

[0007] [1] As described in [2], the through electrode substrate may also have a size in the thickness direction of the substrate that is smaller than the size of the second part.

[0008] [3] As described in [1] or [2], the through electrode substrate may also be such that the ratio of the size T11 of the seed layer in the thickness direction of the substrate to the thickness T0 of the substrate, i.e., T11 / T0, is 0.025 or more and 0.275 or less.

[0009] [4] The through electrode substrate described in any of [1] to [3] may also include a depression in the aforementioned interface that is recessed toward the aforementioned first surface.

[0010] [5] The through electrode substrate described in any of [1] to [4] may also be a substrate with a thickness T0 of the substrate relative to the size R1 of the through hole on the first surface, i.e., T0 / R1, which is 3.0 or more and 25.0 or less.

[0011] [6] The through electrode substrate described in any of [1] to [5] may also be a seed layer with a thickness of 5 nm or more and 50 nm or less.

[0012] [7] The through electrode substrate described in any of [1] to [6] may also include a superconducting material in the first part mentioned above, which contains at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In and Al.

[0013] [8] The through electrode substrate described in any of [1] to [7] may also include a superconducting material in the second part mentioned above, which contains at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In and Al.

[0014] [9] The through electrode substrate described in any of [1] to [8] may also include: a first pad located on the first surface and covering the through hole when viewed from above, and connected to the first part.

[0015]

[10] As described in [9], the through electrode substrate may also include the first pad having a superconducting material comprising at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In and Al.

[0016]

[11] The through electrode substrate described in [9] or

[10] may also be the first pad and the first part described above integrally formed.

[0017]

[12] The through electrode substrate described in any of [9] to

[11] may also be such that the first pad does not cover the through hole when viewed from above.

[0018]

[13] The through electrode substrate described in any of [9] to

[12] may also include: a first inorganic layer located on the first surface and adjacent to the first pad in the surface direction, comprising an inorganic insulating material.

[0019]

[14] The through electrode substrate described in any of [1] to

[13] may also include: a first wiring located on the first surface and connected to the first part.

[0020]

[15] As described in

[14] , the through electrode substrate may also include the aforementioned first wiring having a superconducting material comprising at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In and Al.

[0021]

[16] The through electrode substrate described in

[14] or

[15] may also be the first wiring and the first part of the above-mentioned being integrally formed.

[0022]

[17] An assembly substrate comprising: a through electrode substrate as described in any one of [1] to

[16] ; and an element electrically connected to the through electrode of the through electrode substrate.

[0023]

[18] As described in

[17] , the assembly substrate may also include a quantum chip containing qubits.

[0024]

[19] A method for manufacturing a through-electrode substrate, comprising: The process of preparing a substrate, the substrate including a first surface and a second surface located opposite to the first surface, having a through hole, the through hole including a wall surface extending from the first surface to the second surface; and The through-electrode formation process for forming through-holes; The aforementioned through-electrode formation process, The process of forming a seed layer, wherein the seed layer is located on the aforementioned wall surface and extends along the aforementioned wall surface from the aforementioned first surface toward the aforementioned second surface; The process of forming a first plating portion covering the aforementioned seed layer by using a first plating treatment with a first plating solution; and A process is formed by using a second plating solution to create a second plating portion that is in contact with the first plating portion; comprising: The aforementioned second plating portion is connected to the aforementioned first plating portion at the interface that traverses the aforementioned through hole.

[0025]

[20] The method for manufacturing a through electrode substrate as described in

[19] may also include a first plating solution comprising a superconducting material comprising at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In and Al.

[0026]

[21] The method of manufacturing a through electrode substrate as described in

[19] or

[20] may also include a second plating solution comprising a superconducting material comprising at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In and Al.

[0027] According to the embodiments disclosed herein, a through electrode substrate having a through electrode that suppresses voids can be provided. Simple Explanation of the Diagram

[0028] [Figure 1] Schematic cross-sectional view of the assembly substrate in the first embodiment. [Figure 2] Enlarged schematic cross-sectional view of the through electrode substrate in the first embodiment. [Figure 3] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the first embodiment. [Figure 4] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the first embodiment. [Figure 5] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the first embodiment. [Figure 6A] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the first embodiment. [Figure 6B] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the first embodiment. [Figure 7] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the first embodiment. [Figure 8] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the first embodiment. [Figure 9] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the first embodiment. [Figure 10] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the first modified example. [Figure 11] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the first modified example. [Figure 12] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the first modified example. [Figure 13] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the first modified example. [Figure 14] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the second modified example. [Figure 15] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the second modified example. [Figure 16] Schematic cross-sectional view of the manufacturing process of the through electrode substrate in the second modified example. [Figure 17] Schematic diagram of an example of a product with a through electrode substrate. [Figure 18] Schematic diagram of manufacturing conditions and evaluation results of the through electrode substrate in the embodiment. [Figure 19] Schematic diagram of manufacturing conditions and evaluation results of the through electrode substrate in the embodiment. [Figure 20] Schematic diagram of manufacturing conditions and evaluation results of the through electrode substrate in the embodiment. [Figure 21] Schematic diagram of manufacturing conditions and evaluation results of the through electrode substrate in the embodiment. Implementation

[0029] The following describes in detail, with reference to the accompanying drawings, the structure and manufacturing method of the through electrode substrate and assembly substrate of the embodiments disclosed herein. The embodiments shown below are examples of embodiments of the present disclosure, and the present disclosure is not limited to these embodiments. Terms used in this specification regarding shape or geometric conditions and the degree to which they are identified, such as "parallel" or "orthogonal," or values ​​of length or angle, are not limited to a strict meaning, but are interpreted to encompass the range of degrees to which the same functionality is expected to be obtained.

[0030] In this specification, when multiple candidate upper limit values ​​and multiple candidate lower limit values ​​are given for a certain parameter, the numerical range of the parameter can also be formed by combining any one candidate upper limit value with any one candidate lower limit value. For example, consider the case where "parameter B is, for example, above A1, or above A2, or above A3. Parameter B is, for example, below A4, or below A5, or below A6." In this case, the numerical range of parameter B can be above A1 and below A4, above A1 and below A5, above A1 and below A6, above A2 and below A4, above A2 and below A5, above A2 and below A6, above A3 and below A4, above A3 and below A5, or above A3 and below A6.

[0031] In the drawings referenced in the implementation, the same or similar symbols are used to mark the same part or parts with the same function, and sometimes repeated explanations are omitted. In addition, the dimensional ratios in the drawings sometimes differ from the actual ratios for ease of explanation, or a part of a component is sometimes omitted from the drawings.

[0032] (Assembled substrate) Figure 1 is a schematic cross-sectional view of an example of the assembly substrate 60. The assembly substrate 60 includes a through electrode substrate 10 and a component 61. The component 61 may be an LSI chip such as a logic IC or a memory IC. The component 61 may also be a MEMS (Micro Electro Mechanical Systems) chip. A MEMS chip is an electronic component that integrates mechanical parts, sensors, actuators, electronic circuits, etc., on a single substrate. The component 61 has a terminal 62 electrically connected to the through electrode substrate 10.

[0033] Component 61 may also include a quantum chip. The quantum chip functions as a quantum computer. A quantum computer is a computer that processes information using phenomena from quantum mechanics. A quantum chip contains qubits. A qubit is the smallest unit of quantum information. The specific structure of a qubit is not particularly limited. For example, a qubit can also be constructed using circuits containing superconducting materials.

[0034] Component 61 may also have a superconducting wafer. A superconducting wafer is a wafer driven by the superconducting phenomenon. The superconducting phenomenon is, for example, a permanent electric current.

[0035] Although not illustrated, the assembly substrate 60 may also include a cooling device. The cooling device cools the through-electrode substrate 10 and the element 61. When the through-electrode substrate 10 or the element 61 contains a superconducting material, the cooling device can also cool the through-electrode substrate 10 and the element 61 to below the superconducting critical temperature. The superconducting critical temperature is the temperature at which a superconducting material exhibits a superconducting state. The superconducting critical temperature may also be below 77K.

[0036] (Through-through electrode substrate) The through electrode substrate 10 shown in Figure 1 includes a substrate 12, a through electrode 22, a first wiring 25, and a post pad 41.

[0037] (Substrate) The substrate 12 includes a first surface 13 and a second surface 14. The second surface 14 is located on the opposite side of the first surface 13. As shown in FIG1, the component 61 may also be located on the first surface 13. Although not shown, the component 61 may also be located on the second surface 14.

[0038] A plurality of through holes 20 are provided on the substrate 12, penetrating the substrate 12. Each through hole 20 includes a wall 21. The wall 21 extends from the first surface 13 to the second surface 14. In the following description, the direction from the first surface 13 to the second surface 14 is also referred to as the thickness direction D1. The thickness direction D1 may also be parallel to the normal direction of the first surface 13. The direction in which the first surface 13 extends is also referred to as the surface direction D2.

[0039] The substrate 12 is made of an inorganic material with insulating properties. For example, the substrate 12 includes a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al₂O₃) substrate, an aluminum nitride (AlN) substrate, a zirconium oxide (ZrO₂) substrate, etc.

[0040] When the substrate 12 is a silicon substrate, the surfaces of the first surface 13, the second surface 14, and the wall surface 21 of the substrate 12 can also be formed by an insulating film. For example, the insulating film is formed by oxidizing the substrate 12 with the through holes 20 formed thereon at high temperature.

[0041] The thickness T0 of the substrate 12 is, for example, 100 μm or more, or 150 μm or more, or 200 μm or more. By having a thickness T0 of 100 μm or more, the deflection of the substrate 12 can be suppressed. Therefore, it is possible to prevent difficulties in handling the substrate 12 during manufacturing processes, or to prevent warping of the substrate 12 due to internal stress in the layers formed on the substrate 12. The thickness T0 of the substrate 12 is, for example, 600 μm or less, or 500 μm or less, or 400 μm or less. By having a thickness T0 of 600 μm or less, it is possible to suppress the increase in the processing time required to form the through-hole 12 on the substrate 12.

[0042] The wall 21 of the through hole 20 may extend along the thickness direction D1. Alternatively, although not shown, the wall 21 may also extend in a direction deviating from the thickness direction D1. For example, the wall 21 may also include a portion extending in a direction inclined relative to the thickness direction D1, such that the size of the through hole 20 decreases from the first surface 13 toward the second surface 14. Conversely, the wall 21 may also include a portion extending in a direction inclined relative to the thickness direction D1, such that the size of the through hole 20 decreases from the second surface 14 toward the first surface 13. The wall 21 may also include a portion extending in a direction inclined relative to the thickness direction D1 such that the size of the through hole 20 decreases from the first surface 13 toward the center of the through hole 20 in the thickness direction D1, and a portion extending in a direction inclined relative to the thickness direction D1 such that the size of the through hole 20 decreases from the second surface 14 toward the center of the through hole 20 in the thickness direction D1. A portion of the wall 21 may also be curved.

[0043] Figure 2 is an enlarged schematic cross-sectional view of the through-hole substrate. The through-hole 20 has a dimension R1 on the first surface 13. The through-hole 20 has a dimension R2 on the second surface 14. Dimensions R1 and R2 can be the same. Dimensions R1 and R2 can also be different. For example, dimension R1 can be larger than dimension R2, or it can be smaller than dimension R2.

[0044] Dimension R1 can be 5 μm or more, or 10 μm or more, or 20 μm or more. Dimension R1 can be 100 μm or less, or 80 μm or less, or 60 μm or less. The numerical range of dimension R2 can be the same as that of dimension R1.

[0045] The ratio of thickness T0 to dimension R1, i.e., T0 / R1, can be, for example, 3.0 or more, or 4.0 or more, or 5.0 or more. T0 / R1 can be, for example, 25.0 or less, or 20.0 or less, or 15.0 or less. For example, T0 / R1 can also be 3.0 or more and 25.0 or less. By having T0 / R1 of 3.0 or more, it is possible to prevent the through-hole 20 from being blocked by the through electrode 22 on the first surface 13. By having T0 / R1 of 25.0 or less, it is possible to reduce the time required to form the through electrode 22 through the plating process.

[0046] The shape of the through hole 20 viewed from above is not particularly limited. For example, the through hole 20 viewed from above may be circular or non-circular. When the through hole 20 viewed from above is circular, the aforementioned dimensions R1 and R2 are the diameters of the through hole 20 on the first surface 13 and the second surface 14, respectively. When the through hole 20 viewed from above is not circular, the aforementioned dimensions R1 and R2 are defined by the direction in which the size of the through hole 20 viewed from above is maximized. For example, when the through hole 20 viewed from above is elliptical, the aforementioned dimensions R1 and R2 are defined by the direction of the major axis of the ellipse.

[0047] (Through-through electrode) The through electrode 22 is located inside the through hole 20 and is a conductive component. The through electrode 22 fills the through hole 20. The through electrode 22 is the so-called hole filler.

[0048] As shown in Figure 1, the through electrode 22 may also include a first end face 221 located on the first surface 13 and a second end face 222 located on the second surface 14. The first end face 221 may also extend on the same surface as the first surface 13. The second end face 222 may also extend on the same surface as the second surface 14.

[0049] As shown in Figure 2, the through electrode 22 includes a seed layer 31, a first portion 23, and a second portion 24. As described later, the first portion 23 is formed by a first plating process. The second portion 24 is formed by a second plating process performed after the first plating process. The through electrode 22 includes an interface 223 where the first portion 23 and the second portion 24 meet. The interface 223 extends through the through hole 20. The interface 223 can also be formed by grain boundaries of the material constituting the first portion 23.

[0050] The seed layer 31 extends along the wall surface 21 in the circumferential direction of the through hole 20. Furthermore, the seed layer 31 extends along the wall surface 21 from the first surface 13 toward the second surface 14. The seed layer 31 extends in a manner that does not reach the second surface 14. That is, the dimension T11 of the seed layer 31 located in the through hole 20 in the thickness direction D1 is smaller than the thickness T0 of the substrate 12. The ratio of the dimension T11 to the thickness T0, i.e., T11 / T0, is, for example, 0.025 or more, or 0.05 or more, or 0.10 or more. T11 / T0 is, for example, 0.275 or less, or 0.25 or less, or 0.20 or less.

[0051] The thickness T12 of the seed layer 31 is, for example, 5 nm or more, or 10 nm or more, or 15 nm or more, or 20 nm or more. The thickness T12 of the seed layer 31 is, for example, 50 nm or less, or 40 nm or less, or 30 nm or less. For example, the thickness T12 of the seed layer 31 can also be 5 nm or more and 50 nm or less. By having a thickness T12 of 5 nm or more, defects such as pinholes in the seed layer 31 can be suppressed. Furthermore, by having a thickness T12 of 5 nm or more, portions not covered by the seed layer 31 on the wall surface 21 can be suppressed. By having a thickness T12 of 50 nm or less, unevenness in the thickness of the first portion 23 can be suppressed. For example, the decrease in thickness of the first portion 23 from the wall surface 21 towards the center of the through hole 20 when viewed from above can be suppressed. If the thickness of the first part 23 decreases from the wall surface 21 toward the center of the through hole 20 when viewed from above, the depression 223a described later is likely to occur. The thickness T12 of the seed layer 31 is defined by the center of the first part 23 in the thickness direction D1.

[0052] The material of the seed layer 31 is selected in a manner that allows the first portion 23 to precipitate onto the seed layer 31. The material of the seed layer 31 may be the same as or different from the material of the first portion 23. The seed layer 31 may, for example, contain metallic materials such as Cu, Ti, or Cr. The seed layer 31 may also contain compounds of these metallic materials. For example, the seed layer 31 may contain TiN. The seed layer 31 may also contain multiple layers. For example, the seed layer 31 may contain layers of TiN and Cu.

[0053] The seed layer 31 may also contain general metallic materials, as described later. The seed layer 31 may also contain superconducting materials, as described later.

[0054] Although not shown in the figure, other layers such as barrier layers and sealing layers may also be provided between the wall surface 21 and the seed layer 31. The barrier layer is provided, for example, to suppress the diffusion of metal elements contained in the seed layer 31, part 23, part 24, etc., into the interior of the substrate 12. The barrier layer is made of, for example, titanium, titanium nitride, molybdenum, molybdenum nitride, tantalum, tantalum nitride, etc., or formed by laminating them. The sealing layer is provided to improve the adhesion of the through electrode 22 to the wall surface 21. The sealing layer is made of, for example, titanium, molybdenum, tungsten, tantalum, nickel, chromium, aluminum, their compounds, their alloys, or laminated together.

[0055] The first part 23 is formed by a precipitation reaction using the charge supplied from the seed layer 31. In the through hole 20, the first part 23 covers the seed layer 31. For example, the first part 23 extends in the thickness direction D1, from the first surface 13 to the position on the second surface 14 side relative to the seed layer 31.

[0056] Part 1, Section 23 may also include metallic materials such as Cu, Au, Ag, Pt, Rh, Ni, Cr, and Pd. Part 1, Section 23 may also include compounds of these metallic materials. In the following description, metallic materials such as Cu, Au, Ag, Pt, Rh, Ni, Cr, and Pd, as well as compounds of these metallic materials, are also referred to as general metallic materials.

[0057] Part 1, section 23 may also include superconducting materials. Superconducting materials may, for example, contain at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In, and Al. The percentage of at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In, and Al in the superconducting material may be, for example, 10% by mass or more, or 20% by mass or more, or 30% by mass or more. Superconducting materials may also contain metallic materials such as Nb, Pb, Ta, Sn, In, and Al. Superconducting materials may also contain compounds of these metallic materials.

[0058] Part 24 is connected to Part 1 23 at interface 223. Part 24 extends in the thickness direction D1, from interface 223 to the second surface 14. Interface 223, which traverses the through hole 20, may not be flat. For example, interface 223 may include a depression 223a recessed toward the first surface 13. The depth K of depression 223a may be, for example, 1.5 μm or more, or 3.0 μm or more, or 5.0 μm or more. The depth K of depression 223a may be, for example, less than 15 μm, or less than 12 μm, or less than 10 μm. For example, the depth K of depression 223a may also be 1.5 μm or more but less than 15 μm.

[0059] As shown in Figures 6A and 7 below, the growth of the second plating portion 34 of the second part 24 sometimes progresses more easily in the center of the through hole 20 when viewed from above than in the vicinity of the wall surface 21 of the through hole 20. By including a depression 223a in the interface 223, excessive protrusion of the second part 24 from the second surface 14 in the center of the through hole 20 when viewed from above can be suppressed. By ensuring that the depth K of the depression 223a is less than 15 μm, defects such as voids can be suppressed during the growth of the second plating portion 34.

[0060] In the thickness direction D1, the dimension T21 of the first part 23 may also be smaller than the dimension T22 of the second part 24. Dimensions T21 and T22 may also be determined by the outer edges of the first part 23 and the second part 24 in the surface direction D2. For example, dimensions T21 and T22 may also be determined by the positions of the first part 23 and the second part 24 that are in contact with the wall surface 21.

[0061] The ratio of size T21 to size T22, i.e., T21 / T22, can be, for example, 0.90 or less, or 0.80 or less, or 0.70 or less. T21 / T22 can also be, for example, 0.05 or more, or 0.10 or more, or 0.20 or more. For example, T21 / T22 can also be 0.05 or more and 0.90 or less. By having T21 / T22 be 0.05 or more, the time or difficulty required for the growth of the second plating portion 34 can be prevented from becoming excessive. By having T21 / T22 be 0.90 or less, the thickness of the first portion 23 can be prevented from becoming uneven.

[0062] Part 2, 24, like Part 1, 23, may also include general metallic materials. Part 2, 24, like Part 1, 23, may also include superconducting materials.

[0063] The material in Part 2, 24, may be the same as or different from the material in Part 1, 23. For example, both Part 1, 23, and Part 2, 24 may contain general metallic materials or may contain superconducting materials. Alternatively, Part 1, 23 may contain superconducting materials, and Part 2, 24 may contain general metallic materials. Or, Part 1, 23 may contain general metallic materials, and Part 2, 24 may contain superconducting materials.

[0064] (Wire 1) The first wiring 25 is connected to the through electrode 22. The first wiring 25 is configured not to cover the through hole 20 when viewed from above. The first wiring 25 extends in the surface direction D2. Since the first wiring 25 does not cover the through hole 20, gas generated in the through hole 20 can be discharged from the through hole 20 on the first surface 13. This suppresses the increase in pressure inside the through hole 20. Therefore, the deformation of the first wiring 25 due to the internal pressure of the through hole 20 can be suppressed.

[0065] The thickness T3 of the first wiring 25 is, for example, 1.0 μm or more, or 1.5 μm or more, or 2.0 μm or more. The thickness T3 is, for example, 5.0 μm or less, or 4.5 μm or less, or 4.0 μm or less.

[0066] Like Part 1 23, the first wiring 25 may also contain general metallic materials. Like Part 1 23, the first wiring 25 may also contain superconducting materials. The material of the first wiring 25 and the material of Part 1 23 may be the same or different.

[0067] (Column pad) The pad 41 is located, for example, between the first wiring 25 and the component 61 in the thickness direction D1. The pad 41 may also be connected to the terminal 62 of the component 61.

[0068] The thickness T4 of the post pad 41 is, for example, 1.0 μm or more, or 1.5 μm or more, or 2.0 μm or more. The thickness T4 is, for example, 5.0 μm or less, or 4.5 μm or less, or 4.0 μm or less.

[0069] Like Part 1, 23, the pillar pad 41 may also contain a general metallic material. Like Part 1, 23, the pillar pad 41 may also contain a superconducting material. The material of the pillar pad 41 may be the same as or different from the material of Part 1, 23.

[0070] The material combinations of seed layer 31, Part 1 23, Part 2 24, First wiring 25, and pillar pad 41 are arbitrary. Several examples of material combinations are illustrated in Table 1. In Table 1, "superconducting" refers to superconducting materials, and "general" refers to general metallic materials. [Table 1] Seed layer Part 1 Part 2 Wiring 1 Column pad Example 1 Superconductivity Superconductivity Superconductivity Superconductivity Superconductivity Example 2 generally generally generally generally generally Example 3 generally Superconductivity Superconductivity Superconductivity Superconductivity Example 4 generally Superconductivity generally Superconductivity Superconductivity Example 5 generally generally Superconductivity Superconductivity Superconductivity

[0071] Thickness T0, dimension T11, thickness T12, dimension T21, dimension T22, thickness T3, thickness T4, dimension R1, dimension R2, etc. are calculated based on the cross-sectional image of the through electrode substrate 10 obtained by scanning electron microscopy.

[0072] (Manufacturing method of through-electrode substrate) An example of a manufacturing method for the through electrode substrate 10 will be described below with reference to Figures 3 to 9.

[0073] (Through-hole formation project) First, a substrate 12 is prepared. Next, a resist layer is formed on at least one of the first surface 13 or the second surface 14. Then, an opening is formed in the resist layer at a position corresponding to the through-hole 20. Next, the substrate 12 is processed through the opening in the resist layer. In this way, the through-hole 20 can be formed on the substrate 12 as shown in FIG3. As a method for processing the substrate 12, dry etching, wet etching, etc., can be used. Dry etching methods include reactive ion etching (RIE) and deep reactive ion etching (Deep-RIE).

[0074] A through-hole 20 can also be formed on the substrate 12 by irradiating it with a laser. In this case, a resist layer may not be required. Excimer lasers, Nd:YAG lasers, femtosecond lasers, etc., can be used as lasers. When using an Nd:YAG laser, it is possible to use a fundamental wave with a wavelength of 1064 nm, a second harmonic with a wavelength of 532 nm, and a third harmonic with a wavelength of 355 nm.

[0075] Furthermore, laser irradiation and wet etching can be appropriately combined. Specifically, a modified layer is first formed in the area of ​​the substrate 12 where the through-hole 20 should be formed by laser irradiation. Next, the substrate 12 is immersed in hydrogen fluoride or the like to etch the modified layer. In this way, the through-hole 20 can be formed in the substrate 12.

[0076] In addition, through holes 20 can also be formed on substrate 12 by sandblasting with abrasive material.

[0077] (Seed Layer Formation Engineering) Next, as shown in Figure 4, a seed layer 31 is formed on the wall surface 21 of the through hole 20. The seed layer 31 is formed by physical film formation methods such as vapor deposition, sputtering, and ion plating.

[0078] An example illustrating the method of adjusting the size T11 of the seed layer 31.

[0079] This section describes the formation of the seed layer 31 using a vapor deposition method. In the vapor deposition process, the material constituting the seed layer 31 is deposited towards the first surface 13. As shown in Figure 4, this allows the seed layer 31 to extend along the wall 21 from the first surface 13 towards the second surface 14. The seed layer 31 is also formed on the first surface 13. By adjusting the angle of inflow during the vapor deposition process, the depth of the seed layer 31 penetrating the through-hole 20 from the first surface 13, i.e., the size T11 of the seed layer 31, can be controlled.

[0080] This section describes the formation of the seed layer 31 using sputtering or ion plating. First, the seed layer 31 is formed on the first surface 13 side using sputtering or ion plating. This forms a seed layer 31 extending from the first surface 13 towards the second surface 14 along the wall 21 inside the through-hole 20. The seed layer 31 has a thickness dimension D1 that is larger than the desired dimension T11. Next, a resist layer is formed on the portion of the seed layer 31 located inside the through-hole 20 that has the desired dimension T11. Then, an etching solution is supplied to the inside of the through-hole 20 from the second surface 14 side. This removes the portion of the seed layer 31 not covered by the resist layer. In this way, a seed layer 31 with the desired dimension T11 can be formed inside the through-hole 20.

[0081] (First plating process) Next, a first plating process is performed by supplying a first plating solution to the first surface 13. As shown in FIG5, a first plating portion 33 covering the seed layer 31 is formed by electrolytic plating. The seed layer 31 serves as the cathode. As shown by the dashed line in FIG5, the anode 50 is arranged facing the seed layer 31 on the first surface 13. The first plating portion 33 is formed not only inside the through hole 20 but also on the first surface 13.

[0082] The first plated portion 33 includes a third surface 331 and a fourth surface 332. The fourth surface 332 is located in the through hole 20. The fourth surface 332 may also include a recess 332a that is recessed toward the first surface 13. The third surface 331 is located on the opposite side of the fourth surface 332 in the thickness direction D1. The third surface 331 may also be located outside the through hole 20.

[0083] The first plating process is performed by blocking the through hole 20 on the first surface 13 with the first plating portion 33. In this case, the fourth surface 332 will expand in a manner that traverses the through hole 20. The fourth surface 332 and the depression 332a constitute the aforementioned interface 223 and depression 223a.

[0084] The first plating solution may also contain general metallic materials such as Cu, Au, Ag, Pt, Rh, Ni, and Cr. The first plating solution may also contain superconducting materials such as Nb, Pb, Ta, Sn, In, and Al. The concentration of the conductive materials (including general metallic materials and superconducting materials) contained in the first plating portion 33 in the first plating solution is referred to as the first concentration. Furthermore, the current supplied to the seed layer 31 during the first plating process is referred to as the first current.

[0085] The first plating solution may also contain an accelerator to promote the precipitation reaction. The first plating solution may also contain an inhibitor to suppress the precipitation reaction.

[0086] (Second plating process) Next, a second plating process is performed by supplying a second plating solution to the second surface 14. As shown in FIG6A, the second plating portion 34 is formed by electrolytic plating. FIG6B is a schematic diagram of the further growth of the second plating portion 34. As shown by the dashed lines in FIG6A and FIG6B, the anode 50 is arranged facing the fourth surface 332 of the first plating portion 33. This arrangement can also be achieved by reversing the substrate 12 in the plating apparatus.

[0087] As shown in Figures 6A and 6B, no seed layer is provided on the wall surface 21 between the seed layer 31 and the second surface 14. In this case, as shown in Figures 6A and 6B, the second plating portion 34 grows from the first plating portion 33 toward the second surface 14 in the thickness direction D1. Therefore, compared to the case where the second plating portion 34 grows from the wall surface 21 toward the center of the through hole 20 in the surface direction, defects such as voids in the second plating portion 34 can be suppressed. Figure 7 is a schematic cross-sectional view showing the growth progress of the second plating portion 34 onto the second surface 14.

[0088] The second plating portion 34 includes a fifth surface 341 and a sixth surface 342. The fifth surface 341 is in contact with the fourth surface 332 of the first plating portion 33. The fourth surface 332 and the fifth surface 341 constitute the interface 223 described above. The sixth surface 342 is located on the opposite side of the fifth surface 341 in the thickness direction D1. The sixth surface 342 may also be located outside the through hole 20.

[0089] Like the first plating solution, the second plating solution may also contain general metallic materials. Like the first plating solution, the second plating solution may also contain superconducting materials. The concentration of elements constituting the conductive materials included in the second plating portion 34, such as general metallic materials and superconducting materials, in the second plating solution is referred to as the second concentration. Furthermore, the current supplied to the seed layer 31 during the second plating process is referred to as the second current.

[0090] The second concentration can be even lower than the first concentration. This helps to suppress defects such as voids in the second plating portion 34.

[0091] The second current can also be lower than the first current. In this way, defects such as voids can be suppressed in the second plating portion 34.

[0092] The second plating solution may also contain an accelerator to promote the precipitation reaction. The concentration of the accelerator in the second plating solution may also be lower than the concentration of the accelerator in the first plating solution.

[0093] The second plating solution may also contain inhibitors to suppress the precipitation reaction. The concentration of the inhibitors in the second plating solution may also be higher than the concentration of the inhibitors in the first plating solution.

[0094] (Excluding engineering) Next, the removal of unwanted plating can be carried out. For example, as shown in Figure 8, a first removal process can be performed to remove the first plating portion 33 located on the first surface 13. The first removal process can also remove the first plating portion 33 on the first surface 13 by chemical mechanical polishing. The first removal process can also remove the seed layer 31 on the first surface 13. A first end face 221 extending on the same surface as the first surface 13 can also be obtained through the first removal process. For example, as shown in Figure 8, a second removal process can be performed to remove the second plating portion 34 located on the second surface 14. The second removal process can also remove the second plating portion 34 on the second surface 14 by chemical mechanical polishing. A second end face 222 extending on the same surface as the second surface 14 can also be obtained by the second removal process.

[0095] (Wiring Formation Engineering) Next, as shown in FIG9, the first wiring forming process for forming the first wiring 25 on the first surface 13 can be performed. The method for forming the first wiring 25 is arbitrary. For example, a conductive layer is first formed on the first surface 13 by sputtering. Next, a resist layer is formed on the portion of the conductive layer corresponding to the first wiring 25. Next, the portion of the conductive layer not covered by the resist layer is removed by etching or the like. In this manner, the first wiring 25 containing the conductive layer is formed on the first surface 13.

[0096] (Column pad formation project) Next, a pillar pad forming process can be performed to form the pillar pad 41. The method for forming the pillar pad 41 is arbitrary. For example, the pillar pad 41 can be formed by sputtering, forming a resist layer, and etching, just like the first wiring 25. In this way, the through electrode substrate 10 shown in FIG1 is obtained.

[0097] According to this embodiment, defects such as voids generated in the second part 24 can be suppressed. Therefore, it is possible to provide a through electrode substrate 10 that has a through electrode 22 that suppresses defects such as voids.

[0098] Various modifications can be made to the above-described embodiments. Hereinafter, variations will be described with reference to the drawings, as necessary. In the following description and the drawings used in the following description, the same symbols are used for parts that can be constructed as in the above-described embodiments, and the same symbols are used for the corresponding parts in the first embodiment, thus omitting repeated descriptions. Furthermore, when the effects obtained in the above-described embodiments are also clearly obtained in the variations, such descriptions are sometimes omitted.

[0099] (First variation) Referring to Figures 10 to 13, the manufacturing method of the through electrode substrate 10 of the first modified example will be described.

[0100] First, as in the embodiment described above, a seed layer 31 is formed on the substrate 12 where the through-hole 20 is provided. Next, as shown in FIG10, a first resist layer 35 is partially formed on the seed layer 31 on the first surface 13. The first resist layer 35 may also include a side surface 351 surrounding the through-hole 20 when viewed from above. Furthermore, a second resist layer 36 may also be partially formed on the second surface 14. The second resist layer 36 may also include a side surface 361 surrounding the through-hole 20 when viewed from above.

[0101] Next, as shown in FIG11, a first plating process is performed to form the first plating portion 33. The third surface 331 of the first plating portion 33, when viewed from above, includes an outer edge surrounded by the first resist layer 35.

[0102] Next, as shown in FIG11, a second plating process is performed to form the second plating portion 34. The sixth surface 342 of the second plating portion 34, when viewed from above, includes an outer edge surrounded by the second resist layer 36.

[0103] Next, as shown in FIG12, the first resist layer 35 and the second resist layer 36 are removed. Next, as shown in FIG12, the portion of the seed layer 31 covered by the first resist layer 35 is removed. This yields a through-electrode substrate 10 having a first pad 27 and a second pad 28. The first pad 27 includes a first plating portion 33 and the seed layer 31. The second pad 28 includes a second plating portion 34.

[0104] The first pad 27 is located on the first surface 13 and covers the through hole 20 when viewed from above. The first pad 27 is connected to the first portion 23 of the through electrode 22. The first plated portion 33 of the first pad 27 and the first plated portion 33 of the first portion 23 of the through electrode 22 are integral. That is, the first pad 27 and the first portion 23 are integrally formed. Therefore, most of the material of the first pad 27 is the same as the material of the first portion 23. When the first portion 23 contains a superconducting material, the first pad 27 also contains a superconducting material. When the first portion 23 contains a general metallic material, the first pad 27 also contains a general metallic material.

[0105] The thickness T5 of the first pad 27 is, for example, 1.0 μm or more, or 1.5 μm or more, or 2.0 μm or more. The thickness T5 is, for example, 5.0 μm or less, or 4.5 μm or less, or 4.0 μm or less.

[0106] The dimension R5 of the first pad 27 viewed from above may be 10 μm or more, or 15 μm or more, or 20 μm or more. The dimension R5 may be less than 100 μm, or less than 80 μm, or less than 60 μm. The value range of the dimension R6 of the second pad 28 viewed from above may also be the same as the value range of the dimension R5.

[0107] The second pad 28 is located on the second surface 14 and covers the through hole 20 when viewed from above. The second pad 28 is connected to the second portion 24 of the through electrode 22. The second pad 28 and the second plated portion 34 of the second portion 24 of the through electrode 22 are integral. That is, the second pad 28 and the second portion 24 are integrally formed. Therefore, most of the material of the second pad 28 is the same as the material of the second portion 24. When the second portion 24 contains a superconducting material, the second pad 28 also contains a superconducting material. When the second portion 24 contains a general metallic material, the second pad 28 also contains a general metallic material.

[0108] The thickness T6 of the second pad 28 is, for example, 1.0 μm or more, or 1.5 μm or more, or 2.0 μm or more. The thickness T6 is, for example, 5.0 μm or less, or 4.5 μm or less, or 4.0 μm or less.

[0109] Next, as shown in Figure 13, a first inorganic layer 37 can be formed. The first inorganic layer 37 is located on the first surface 13. The first inorganic layer 37 can also be adjacent to the first pad 27 in the surface direction D2.

[0110] The first inorganic layer 37 comprises an inorganic insulating material. The inorganic insulating material may be, for example, SiN or SiO2. The first inorganic layer 37 may also comprise a layer of SiN and a layer of SiO2.

[0111] Inorganic insulating materials exhibit greater mechanical stability at low temperatures compared to organic insulating materials. For example, layers composed of inorganic insulating materials are less prone to defects such as cracks when subjected to temperature changes between low and normal temperatures, compared to layers composed of organic insulating materials. Low temperatures include, for example, the temperatures at which superconductivity occurs. Superconductivity occurs near absolute zero, such as the temperature of liquid helium.

[0112] (Second variation) Referring to Figures 14 to 16, the manufacturing method of the through electrode substrate 10 of the second modified example will be described.

[0113] First, as in the embodiment described above, a seed layer 31 is formed on the substrate 12 where the through hole 20 is provided. Next, as shown in FIG14, a first resist layer 35 is partially formed on the seed layer 31 on the first surface 13. The first resist layer 35 is formed such that a portion of the seed layer 31 located at the position for forming the first wiring 25 is exposed from the first resist layer 35.

[0114] Next, as shown in FIG15, a first plating process is performed to form the first plating portion 33. The outer edge of the third surface 331 of the first plating portion 33 is defined by the side surface 351 of the first resist layer 35.

[0115] Next, as shown in Figure 15, the second plating process for forming the second plating portion 34 is carried out.

[0116] Next, as shown in FIG. 16, the first resist layer 35 is removed. Next, as shown in FIG. 16, the portion of the seed layer 31 covered by the first resist layer 35 is removed. This yields a through electrode substrate 10 having the first wiring 25. The first wiring 25 includes a first plating portion 33 and the seed layer 31. As in the embodiment described above, a second removal process can also be performed to remove the second plating portion 34 located on the second surface 14.

[0117] The first wiring 25, when viewed from above, can also be located on the first surface 13 without covering the through hole 20. The first wiring 25 is connected to the first portion 23 of the through electrode 22. The first plated portion 33 of the first wiring 25 and the first plated portion 33 of the first portion 23 of the through electrode 22 are integral. That is, the first wiring 25 and the first portion 23 are integrally formed. Therefore, most of the material of the first wiring 25 is the same as the material of the first portion 23. When the first portion 23 contains a superconducting material, the first wiring 25 also contains a superconducting material. When the first portion 23 contains a general metallic material, the first wiring 25 also contains a general metallic material.

[0118] (Example of a product with a through-electrode substrate) Figure 17 is a schematic diagram of an example of a product capable of incorporating the through electrode substrate 10 of the present disclosure embodiment. The through electrode substrate 10 of the present disclosure embodiment can be used in various products. For example, it can be incorporating a notebook computer 110, a tablet computer 120, a mobile phone 130, a smartphone 140, a digital camcorder 150, a digital camera 160, a digital watch 170, a server 180, etc. [Example]

[0119] The present disclosure will now be illustrated in more detail by way of examples, but the present disclosure is not limited to the description of the following examples as long as it does not depart from its spirit.

[0120] (Example 1) The through electrode substrate 10 shown in Figure 2 was fabricated using the manufacturing process shown in Figures 3 to 8.

[0121] Specifically, first, a silicon substrate 12 with a diameter of 8 inches and a thickness T0 of 400 μm is prepared. Next, a plurality of through electrodes 22 are formed on the substrate 12. Specifically, 100 wafer regions are formed on the substrate 12. Each wafer region is a square area with approximately 12 mm on each side when viewed from above. Each wafer region contains 1000 through electrodes 22.

[0122] The method for forming the through-hole 22 is explained. First, as shown in FIG3, a through-hole 20 is formed on the substrate 12 by a depth reactive ion etching method. The through-hole 20 has a circular outline when viewed from above. The dimensions R1 and R2 of the through-hole 20 are 50 μm. Next, the substrate 12 with the through-hole 20 formed is subjected to an oxidation treatment at 1050 °C. Thereby, an insulating film is formed on the first surface 13, the second surface 14, and the wall surface 21 of the substrate 12.

[0123] Next, a dense layer of Cr is formed on the wall surface 21. Then, as shown in Figure 4, a seed layer 31 of Cu is formed by vapor deposition. The dimension T11 of the seed layer 31 in the thickness direction D1 is 50 μm. The thickness T12 of the seed layer 31 is 3 nm.

[0124] Next, as shown in Figure 5, a first plated portion 33 made of Cu is formed by electrolytic plating. Next, a first observation process is performed to observe the shape of the first plated portion 33. Specifically, the shape of the first plated portion 33 is observed using an X-ray transmission device. Based on the observation results, for example, the flatness of the fourth surface 332 of the first plated portion 33 is evaluated.

[0125] Next, as shown in Figures 6A and 7, a second plated portion 34 made of Cu is formed by electrolytic plating. The plating process continues until the thickness of the second plated portion 34, which bulges outward from the through hole 20, reaches 50 μm.

[0126] Subsequently, an annealing process was carried out by heating the substrate 12 in a nitrogen environment. The annealing temperature was 250°C and the annealing time was 1 hour.

[0127] Next, as shown in FIG8, a first removal process is performed to remove the first plating portion 33 located on the first surface 13, and a second removal process is performed to remove the second plating portion 34 located on the second surface 14. In this manner, a through electrode substrate 10 having through electrodes 22 is fabricated. Next, a second observation process is performed to observe the shape of the through electrode substrate 10. Specifically, the shape of the through electrodes 22 is observed using an X-ray transmission apparatus. Furthermore, based on the observation results, it is confirmed whether voids are generated inside the through electrodes 22. When voids are generated inside the through electrodes 22, a portion of the through electrodes 22 appears white. The through electrodes 22 containing the white portion are counted as defective through electrodes. The number of through electrodes 22 formed on one substrate 12 is 100,000. In the second observation process, it is confirmed whether voids are generated in all through electrodes 22.

[0128] (Example 2~Example 18) The through-electrode substrate 10 was fabricated using manufacturing conditions modified from those in Example 1. Furthermore, as in Example 1, the flatness of the surface of the first plated portion 33 and the voids in the through-electrode 22 were assessed. The results are shown in Figure 18.

[0129] In the "Method for Forming Seed Layer" column of Figure 18, "DEPO" means that the seed layer 31 is formed by vapor deposition, "SP" means that the seed layer 31 is formed by sputtering, and "IP" means that the seed layer 31 is formed by ion plating. When the seed layer 31 is formed by sputtering or ion plating, the excess portion of the seed layer 31 is removed by etching.

[0130] In the "Surface flatness" column of Figure 18, "good" means that the maximum height of the unevenness of the surface of the fourth surface 332 of the first plated portion 33 is less than 15μm, "great" means that the maximum height of the unevenness of the surface of the fourth surface 332 is less than 10μm, and "not good" means that the maximum height of the unevenness of the surface of the fourth surface 332 is more than 15μm.

[0131] In the "Void Generation" column of Figure 18, "good" means that the ratio of the number of defective through electrodes to the number of observed through electrodes 22 (hereinafter also referred to as void ratio) is less than 5%, "great" means that the void ratio is 0%, and "not good" means that the void ratio is more than 5%.

[0132] As shown in Figure 18, good results can be obtained when the seed layer 31 has a thickness dimension T11 of 10 μm to 110 μm in the thickness direction D1 and a thickness T12 of 5 nm to 50 nm. The thickness T0 of the substrate 12 is 400 μm. Therefore, in examples where good results can be obtained, the range of T11 / T0 is 0.025 to 0.275.

[0133] (Example 19) Except that the dimensions R1 and R2 of the through hole 20 are set to 20 μm, the through electrode substrate 10 is manufactured under the same manufacturing conditions as in Example 1. In addition, as in Example 1, the flatness of the surface of the first plated portion 33 and the voids of the through electrode 22 are evaluated.

[0134] (Example 20~Example 36) A through-hole substrate 10, comprising through-holes 20 having dimensions R1 and R2 of 20 μm, was fabricated using manufacturing conditions modified from Example 19. The manufacturing conditions of Examples 20 to 36 each correspond to the manufacturing conditions of Examples 2 to 18. Furthermore, as in Example 1, the flatness of the surface of the first plating portion 33 and the voids in the through-hole electrode 22 were evaluated. The results are shown in Figure 19.

[0135] As in Examples 1 to 18, good results can be obtained when the size T11 of the seed layer 31 in the thickness direction D1 is 10 μm or more and 110 μm or less, and the thickness T12 of the seed layer 31 is 5 nm or more and 50 nm or less.

[0136] (Example 37~Example 44) A silicon substrate 12 with a diameter of 8 inches and a thickness T0 of 250 μm is prepared. Next, as in Example 1, a plurality of through-holes 22 are formed on the substrate 12. The through-holes 20 have a circular outline when viewed from above. The dimensions R1 and R2 of the through-holes 20 are 30 μm. Next, as in Example 1, the through-holes 22 are fabricated by forming an insulating film, a Cr-based bonding layer, a Cu-based seed layer 31, a first Cu-based plating portion 33, and a second Cu-based plating portion 34. In Examples 37 to 44, the vapor deposition conditions are adjusted so that the dimension T11 of the Cu-based seed layer 31 in the thickness direction D1 is the value shown in Figure 20. Furthermore, as in Example 1, the surface flatness of the first plating portion 33 and the voids in the through-holes 22 are evaluated. The results are shown in Figure 20.

[0137] As shown in Figure 20, good results can be obtained when T11 / T0 is in the range of 0.025 to 0.275.

[0138] (Example 45~Example 53) A silicon substrate 12 with a diameter of 8 inches and a thickness T0 of 600 μm is prepared. Next, as in Example 1, a plurality of through-holes 22 are formed on the substrate 12. The through-holes 20 have a circular outline when viewed from above. The dimensions R1 and R2 of the through-holes 20 are 90 μm. Next, as in Example 1, the through-holes 22 are fabricated by forming an insulating film, a Cr-based bonding layer, a Cu-based seed layer 31, a first Cu-based plating portion 33, and a Cu-based second Cu-based plating portion 34. In Examples 45-53, the vapor deposition conditions are adjusted so that the dimension T11 of the Cu-based seed layer 31 in the thickness direction D1 is the value shown in Figure 20. Furthermore, as in Example 1, the surface flatness of the first plating portion 33 and the voids in the through-holes 22 are evaluated. The results are shown in Figure 20.

[0139] As shown in Figure 20, good results can be obtained when T11 / T0 is in the range of 0.025 to 0.275.

[0140] (Example 54~Example 62) A silicon substrate 12 with a diameter of 8 inches and a thickness T0 of 400 μm is prepared. Next, as in Example 1, a plurality of through-holes 22 are formed on the substrate 12. The through-holes 20 have a circular outline when viewed from above. The diameter of the through-holes 20 increases from the first surface 13 towards the second surface 14. The dimension R1 of the through-holes 20 on the first surface 13 is 50 μm. The dimension R2 of the through-holes 20 on the second surface 14 is 90 μm. Next, as in Example 1, the through-holes 22 are fabricated by forming an insulating film, a Cr-based bonding layer, a Cu-based seed layer 31, a Cu-based first plating portion 33, and a Cu-based second plating portion 34. In Examples 54 to 62, the conditions of the vapor deposition method are adjusted so that the thickness T12 of the seed layer 31 is the value shown in FIG. 21. The thickness T12 is defined by the position of the seed layer 31 at the center of the thickness direction of the substrate 12. Furthermore, as in Example 1, the flatness of the surface of the first plated portion 33 and the confirmation of voids in the through electrode 22 are performed. The results are shown in Figure 21.

[0141] As shown in Figure 21, good results can be obtained when the thickness T12 of the seed layer 31 is in the range of 5 nm to 50 nm.

[0142] (Example 63~Example 70) A silicon substrate 12 with a diameter of 8 inches and a thickness T0 of 600 μm is prepared. Next, as in Example 1, a plurality of through-holes 22 are formed on the substrate 12. The through-holes 20 have a circular outline when viewed from above. The through-holes 20 have a diameter that increases from the first surface 13 towards the second surface 14. The dimensions R1 and R2 of the through-holes 20 are 100 μm. Next, as in Example 1, the through-holes 22 are fabricated by forming an insulating film, a Cr-based bonding layer, a Cu-based seed layer 31, a Cu-based first plating portion 33, and a Cu-based second plating portion 34. In Examples 63-70, the conditions of the vapor deposition method are adjusted so that the thickness T12 of the seed layer 31 is the value shown in FIG. 21. The thickness T12 is defined by the position of the seed layer 31 at the center in the thickness direction of the substrate 12. Furthermore, as in Example 1, the flatness of the surface of the first plated portion 33 and the voids in the through electrode 22 were assessed. The results are shown in Figure 21.

[0143] As shown in Figure 21, good results can be obtained when the thickness T12 of the seed layer 31 is in the range of 5 nm to 50 nm.

[0144] 10: Through-electrode substrate 12:Substrate 13: Page 1 14: Page 2 20: Through hole 21: Wall 22: Through electrode 23: Part 1 24: Part 2 25: Wiring 1 27: First pad 28: Second pad 31: Seed layer 33: First plating section 331: Page 3 332: Page 4 332a: Depression 34: Second plating section 35: First inhibitor layer 36: Second inhibitor layer 37: First Inorganic Layer 38: Second Inorganic Layer 41: Column Pad 60: Assemble the substrate 61: Components 62:Terminal

Claims

1. A through-electrode substrate, comprising: a substrate including a first surface and a second surface located opposite to the first surface, having a through hole, the through hole including a wall extending from the first surface to the second surface; and a through-electrode located in the through hole, extending from the first surface to the second surface; the through-electrode comprising: a seed layer located on the wall surface, extending from the first surface toward the second surface along the wall surface; a first portion covering the seed layer; and a second portion connected to the first portion at an interface traversing the through hole, wherein the ratio of the dimension T11 of the seed layer in the thickness direction of the substrate to the thickness T0 of the substrate, i.e., T11 / T0, is 0.025 or more and 0.275 or less.

2. The through-electrode substrate as described in claim 1, wherein, In the thickness direction of the aforementioned substrate, the size of the first portion is smaller than the size of the second portion.

3. The through-electrode substrate as described in claim 1, wherein, The aforementioned interface includes a depression that is recessed toward the aforementioned first surface.

4. The through-electrode substrate as described in any one of claims 1 to 3, wherein, The ratio of the thickness T0 of the aforementioned substrate to the size R1 of the aforementioned through hole on the aforementioned first surface, i.e., T0 / R1, is 3.0 or more and 25.0 or less.

5. The through-electrode substrate as described in any one of claims 1 to 3, wherein, The thickness of the aforementioned seed layer is between 5 nm and 50 nm.

6. The through-electrode substrate as described in any one of claims 1 to 3, wherein, The aforementioned first part comprises a superconducting material containing at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In and Al.

7. The through-electrode substrate as described in any one of claims 1 to 3, wherein, The aforementioned second part comprises a superconducting material containing at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In and Al.

8. The through-electrode substrate as described in any one of claims 1 to 3, wherein, It includes: a first pad, located on the aforementioned first surface and covering the aforementioned through hole when viewed from above, and connected to the aforementioned first part.

9. The through-electrode substrate as described in claim 8, wherein, The aforementioned first pad has a superconducting material comprising at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In and Al.

10. The through-electrode substrate as described in claim 8, wherein, The aforementioned first pad and the aforementioned first part are integrally formed.

11. The through-electrode substrate as described in claim 8, wherein, The aforementioned first pad covers the aforementioned through hole when viewed from above.

12. The through-electrode substrate as described in claim 8, wherein, It comprises: a first inorganic layer located on the aforementioned first surface, adjacent to the aforementioned first pad in the surface direction, and containing an inorganic insulating material.

13. The through-electrode substrate as described in any one of claims 1 to 3, wherein, It includes: a first wiring, located on the aforementioned first surface and connected to the aforementioned first part.

14. The through-electrode substrate as described in claim 13, wherein, The aforementioned first wiring has a superconducting material comprising at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In and Al.

15. The through-electrode substrate as described in claim 13, wherein, The aforementioned first wiring and the aforementioned first part are integrally formed.

16. An assembly substrate comprising: a through electrode substrate as described in any one of claims 1 to 3; and an element electrically connected to the through electrode of the through electrode substrate.

17. The assembly substrate as described in claim 16, wherein, The aforementioned components include a quantum chip containing qubits.

18. A method for manufacturing a through-electrode substrate, comprising: a process for preparing a substrate, the substrate including a first surface and a second surface located opposite to the first surface, having a through-hole, the through-hole including a wall surface extending from the first surface to the second surface; and a through-electrode forming process for forming a through-electrode in the through-hole; the through-electrode forming process comprising: a process for forming a seed layer located on the wall surface and extending from the first surface toward the second surface along the wall surface; a process for forming a first plating portion covering the seed layer by means of a first plating process using a first plating solution; and a process for forming a second plating portion in contact with the first plating portion by means of a second plating process using a second plating solution; the second plating portion being in contact with the first plating portion at an interface traversing the through-hole. The ratio of the seed layer dimension T11 in the thickness direction of the aforementioned substrate to the thickness T0 of the aforementioned substrate, i.e., T11 / T0, is 0.025 or more and 0.275 or less.

19. A method for manufacturing a through-electrode substrate as described in claim 18, wherein, The aforementioned first plating solution contains a superconducting material, which includes at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In and Al.

20. A method for manufacturing a through-electrode substrate as described in claim 18 or 19, wherein, The aforementioned second plating solution contains a superconducting material, which includes at least one element selected from the group consisting of Nb, Pb, Ta, Sn, In and Al.

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