Three-dimensional storage device, training method for input / output reference voltage thereof, and memory system

Abstract

This invention discloses a method for training the input / output voltage of a three-dimensional (3D) storage device. The method may include the following operations: (1) setting a reference voltage value with on-die terminal (ODT) enabled; (2) controlling the 3D storage device to perform a write training process; (3) determining whether a further write training process is required; (4) repeating operations (1), (2), and (3) in response to determining that a further write training process is required; and (5) setting the reference voltage value to an optimized reference voltage value in response to determining that a further write training process is not required.

Description

Technical Field

[0001] The present invention relates generally to the field of semiconductor technology, and more particularly to a method, related system, and related medium for input / output voltage training of a three-dimensional (3D) memory. Prior Art

[0002] As storage devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling planar storage cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures (e.g., 3D NAND flash storage devices) can address the density and performance limitations of planar storage cells. To improve the accuracy of signals communicated between 3D NAND flash storage devices and a host (e.g., a processor device) or other integrated circuit (IC) devices, many conventional techniques can be used to calibrate circuits (e.g., receivers and transmitters) within these devices. The initialization process for a 3D NAND flash storage device can include four phases: power-up and initialization, ZQ calibration, Vref DQ calibration, and read / write training. Summary of the Invention

[0003] Aspects of three-dimensional (3D) memory elements and methods for input / output voltage training are described herein.

[0004] One aspect of the present invention provides a method for input / output voltage training of a three-dimensional (3D) storage element. The method may include the following operations: (1) setting a reference voltage value in an on-die terminal (ODT) enabled state; (2) controlling the 3D storage element to perform a write training process; (3) determining whether a further write training process is required; (4) in response to determining that a further write training process is required, repeating operations (1), (2), and (3); and (5) in response to determining that a further write training process is not required, setting the reference voltage value to an optimized reference voltage value.

[0005] In some embodiments, setting the reference voltage value is performed regardless of whether an on-die termination (ODT) is enabled or disabled.

[0006] In some embodiments, setting the reference voltage value includes: controlling a main voltage source to generate a reference voltage generating signal by using a first trimming signal.

[0007] In some embodiments, setting the reference voltage value further includes: controlling a voltage booster to generate a reference voltage boost signal by using a second trim signal and a booster enable control signal.

[0008] In some embodiments, setting the reference voltage value further includes generating the reference voltage value based on at least a reference voltage generation signal and a reference voltage boost signal.

[0009] In some embodiments, setting the reference voltage value further includes: changing the reference voltage from an older value to a preset value during a first duration of a first high level of the boost enable control signal; and changing the reference voltage from the preset value to a new value for write training during a second duration of a second high level of the boost enable control signal.

[0010] In some embodiments, setting the reference voltage value further includes: controlling the voltage booster to generate a reference voltage boost signal by using the first trimming signal and the booster enable control signal; and controlling the reference voltage initiation circuit to generate a reference voltage initiation signal by using the first trimming signal and the initiation enable control signal.

[0011] In some embodiments, setting the reference voltage value further includes generating the reference voltage value based on at least a reference voltage generation signal, a reference voltage boost signal, and a reference voltage initiation signal.

[0012] In some embodiments, setting the reference voltage value further includes: changing the reference voltage from an older value to a preset value during a first duration of the high level of the initiation enable control signal; and changing the reference voltage from an older value to the preset value during a first duration of the high level of the boost enable control signal.

[0013] In some embodiments, performing a write training process includes performing a data write operation and a data read operation; and determining whether a further write training process is required based at least on a result of the data read operation.

[0014] Another aspect of the present invention provides a three-dimensional (3D) storage element, comprising: a storage cell array; and a peripheral circuit coupled to the storage cell array. The peripheral circuit comprises: a control circuit configured to: (1) set a reference voltage value in an on-die terminal (ODT) enabled state; (2) control the storage cell array to perform a write training process; (3) determine whether a further write training process is required; (4) in response to determining that a further write training process is required, repeat operations (1), (2), and (3); and (5) in response to determining that a further write training process is not required, set the reference voltage value to an optimized reference voltage value.

[0015] In some embodiments, the logic control circuit is further configured to set the reference voltage value regardless of whether an on-die termination (ODT) is enabled or disabled.

[0016] In some embodiments, the peripheral circuit further includes: a main voltage source configured to receive the first trimming signal from the logic control circuit and generate a reference voltage generation signal.

[0017] In some embodiments, the peripheral circuit further includes: a voltage booster configured to receive the second trimming signal and a booster enable control signal from the logic control circuit to generate a reference voltage boost signal.

[0018] In some embodiments, the peripheral circuit further includes: a multiplexer configured to generate a reference voltage value based on at least a reference voltage generation signal and a booster enable control signal.

[0019] In some embodiments, the multiplexer is configured to: change the reference voltage from an older value to a preset value during a first duration of a first high level of the booster enable control signal; and change the reference voltage from the preset value to a new value for write training during a second duration of a second high level of the booster enable control signal.

[0020] In some embodiments, the peripheral circuit further includes: a voltage booster, which is configured to receive a first trimming signal and a booster enable control signal from the logic control circuit to generate a booster enable control signal; and a reference voltage initiation circuit, which is configured to receive the first trimming signal and the initiation enable control signal from the logic control circuit to generate a reference voltage initiation signal.

[0021] In some embodiments, the peripheral circuit further includes: a multiplexer configured to generate a reference voltage value based on at least a reference voltage generation signal, a booster enable control signal, and a reference voltage initiation signal.

[0022] In some embodiments, the multiplexer is further configured to: change the reference voltage from an older value to a preset value during a first duration of the high level of the initiate enable control signal; and change the reference voltage from an older value to the preset value during a first duration of the high level of the boost enable control signal.

[0023] In some embodiments, the control circuit is further configured to: control the storage cell array to perform a data write operation and a data read operation; and determine whether a further write training process is required based at least on a result of the data read operation.

[0024] Another aspect of the present invention provides a memory system comprising: the 3D storage element described above; and a memory controller configured to control the 3D storage element.

[0025] Those skilled in the art may understand other aspects of the present invention based on the description, claims and drawings of the present invention. Simple diagram description

[0026] The drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the invention and, together with the description, further serve to explain the principles of the invention and enable one skilled in the relevant art to make and use the invention.

[0027] FIG. 1A illustrates a block diagram of an exemplary system having a storage element according to aspects of the present disclosure.

[0028] 1B shows a diagram of an exemplary memory card having a storage element according to aspects of the present disclosure.

[0029] 1C illustrates a diagram of an exemplary solid-state drive (SSD) having memory according to aspects of the present disclosure.

[0030] FIG2 illustrates a schematic block diagram of an example hardware module configuration of a memory system according to some aspects.

[0031] 3 illustrates a schematic circuit diagram of an exemplary storage element including peripheral circuitry according to aspects of the present disclosure.

[0032] 4A illustrates a perspective view of a portion of an exemplary three-dimensional (3D) storage array structure according to aspects of the present disclosure.

[0033] 4B shows a schematic diagram of an exemplary 3D storage element in plan view, according to aspects of the present disclosure.

[0034] 5 illustrates a schematic block diagram of an example circuit for NAND reference voltage application according to aspects of the present invention.

[0035] FIG. 6 is a schematic flow chart illustrating an example method 600 for IO reference voltage training of a NAND memory according to aspects of the present invention.

[0036] 7 illustrates a schematic timing diagram of exemplary operations of the method of FIG. 6 for training a first reference voltage according to aspects of the present disclosure.

[0037] 8A illustrates a schematic block diagram of an exemplary peripheral circuit for IO reference voltage training of a NAND storage device according to aspects of the present invention.

[0038] 8B illustrates a schematic timing diagram of exemplary operations of the method of FIG. 6 for training a first reference voltage according to aspects of the present invention of FIG. 8A .

[0039] FIG. 9A is a schematic block diagram illustrating an exemplary peripheral circuit for IO reference voltage training of a NAND storage device according to some other aspects of the present invention.

[0040] 9B illustrates a schematic timing diagram of exemplary operations of the method of FIG. 6 for training a first reference voltage according to aspects of the present invention of FIG. 9A .

[0041] 10A shows a schematic circuit diagram of an exemplary resistor divider according to aspects of the present disclosure.

[0042] 10B shows a schematic circuit diagram of an exemplary combination of a reference voltage generator and an analog buffer according to aspects of the present invention.

[0043] FIG. 11 illustrates a schematic block diagram of an exemplary computer system according to aspects of the present disclosure.

[0044] The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the accompanying drawings, in which like reference numerals identify corresponding elements throughout. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit in the corresponding reference numeral.

[0045] Aspects of the present invention will be described with reference to the drawings. Implementation Method

[0046] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present invention. It will be apparent to those skilled in the relevant art that the present invention may also be employed in a variety of other applications.

[0047] Note that references to "one aspect," "aspects," "example aspects," "some aspects," and the like throughout the specification indicate that the described aspects may include a particular feature, structure, or characteristic, but not necessarily every aspect. Furthermore, these phrases do not necessarily refer to the same aspect. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an aspect, it would be within the knowledge of a person skilled in the relevant art to affect such feature, structure, or characteristic in conjunction with other aspects, whether or not explicitly described.

[0048] In general, terms can be understood, at least in part, based on their use in context. For example, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense, depending, at least in part, on the context. Similarly, again, terms such as "a," "an," or "the" can be understood to convey singular or plural usage, depending, at least in part, on the context. Furthermore, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but rather can allow for the presence of additional factors that are not necessarily explicitly described, again, depending, at least in part, on the context.

[0049] It should be readily understood that the meanings of “on,” “over,” and “above” in the present invention should be interpreted in the broadest possible manner, such that “on” not only means “directly on something,” but also includes the meaning of “on something with intervening features or layers therebetween.” Furthermore, “on” or “above” not only means “on something” or “above something,” but also includes the meaning of “on something with no intervening features or layers therebetween” or “above something with no intervening features or layers therebetween” (i.e., directly on something).

[0050] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," and the like may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or processing steps in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0051] As used herein, the term "substrate" refers to the material onto which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The front surface of a substrate is typically where semiconductor devices are formed, so unless otherwise specified, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the front surface, so the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer).

[0052] As used herein, the term "layer" refers to a portion of a material comprising a region having a thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer may extend over the entirety of an underlying structure or an overlying structure, or may extend to a lesser extent than the underlying structure or the overlying structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, a layer may be located between any set of horizontal planes between the top and bottom surfaces of a continuous structure, or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (in which contacts, interconnect lines, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0053] In this disclosure, for ease of description, the term "tier" is used to refer to components that have substantially the same height along the vertical direction. For example, a word line and the underlying gate dielectric layer may be referred to as a "tier," a word line and the underlying insulating layer may be collectively referred to as a "tier," and word lines of substantially the same height may be referred to as a "tier of word lines" or similar terms.

[0054] As used herein, the term "nominal" refers to a desired or target value for a characteristic or parameter of a component or process step, as well as a range of values ​​above and / or below the desired value, set during the design phase of a product or process. The range of values ​​may be due to minor variations or tolerances in the manufacturing process. As used herein, the term "approximately" refers to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" may refer to a value of a given quantity that varies within, for example, 10%-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0055] In the present invention, the terms "horizontal / horizontally / lateral / laterally" mean nominally parallel to the lateral surface of the substrate, and the terms "perpendicular" or "perpendicularly" mean nominally perpendicular to the lateral surface of the substrate.

[0056] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "string," e.g., a NAND string) on ​​a laterally oriented substrate, such that the string extends in a vertical direction relative to the substrate.

[0057] The Open NAND Flash Interface (ONFI) standard is one of the interfaces used for NAND flash memory devices, including communication between NAND flash memory devices and other devices (e.g., a host, such as a processor device). The technology defines a NAND memory device input / output (IO) interface (NAND interface) operating at a maximum speed of up to 800 megatransfers per second (MT / s). Future storage solutions are targeting host interfaces such as Peripheral Component Interconnect Express (PICe) Gen 3 and Gen 4 (PCIe-Gen 3 / 4) and Universal Flash Storage version 3.0 (UFS 3.0) or higher for the NAND interface to achieve large storage capacities. In order to saturate a PCIe / UFS host interface with a lower number of lanes, the NAND IO interface speed needs to scale much faster than the IO interface speed defined by the NAND interface (e.g., up to 1600 MT / s or higher). Some recently developed NAND interfaces (e.g., Toggle mode NAND interfaces) can have increased speeds of up to 1200 MT / s.

[0058] Operating an IO interface at relatively high speeds (e.g., up to 1600 MT / s or higher) can experience significant AC timing margin loss due to channel losses, internal NAND variations (e.g., due to process, voltage, and temperature (PVT) and internal timing mismatches), and host-side inherited losses (e.g., due to host-side DQ (data) and DQS (clock) mismatches). These factors can result in read AC timing margin loss or incorrect read data (e.g., data transmitted from the NAND device to the host). These losses can be particularly severe for higher-density stacked NAND storage devices. Overcoming these losses can result in excessive power consumption. Another NAND implementation involves using a relay device (e.g., interface wafer / repeater / retimer) between the host and the NAND storage device to accommodate higher die stacks. Operating such a relay device at relatively high speeds can also experience significant AC timing margin loss, which can result in read timing margin loss or incorrect read data.

[0059] NAND devices operating at speeds exceeding 800 MT / s in heavily loaded systems can support data training features. Digital Command Control (DCC) training is a feature used by NAND devices to compensate for duty cycle mismatches in the RE_t / c signals. Read / write DQ training is a feature used by the host to align DQS and DQ signals caused by mismatched DQS paths. Read DQ training outputs a 16-bit user-defined pattern on each of the DQ pins. This means the NAND device outputs a total of 16 bytes (note that some vendors may provide 32-bit patterns).

[0060] FIG1A illustrates a block diagram of an exemplary system 100 having a storage element according to aspects of the present disclosure. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage element. As shown in FIG1A , system 100 may include a host 108 and a memory system 102 having one or more storage elements 104 and a memory controller 106. Host 108 may be a processor of the electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). Host 108 may be configured to send data to or receive data from storage element 104.

[0061] Storage element 104 can be any storage element disclosed herein, such as a NAND flash storage element. Consistent with the scope of the present invention, memory controller 106 can control multi-pass programming of storage element 104 such that NGS operations are enabled on all storage cells during a programming pass other than the last programming pass of the multi-pass programming, even those that have passed the corresponding verification operation. Peripheral circuitry, such as a word line driver, can apply a low voltage (e.g., a ground (GND) voltage) to the DSG of each storage string coupled to a selected word line, and can apply a low voltage or negative voltage to a selected word line to enable NGS operations on all storage cells coupled to the selected word line during a programming pass other than the last programming pass.

[0062] According to some implementations, memory controller 106 is coupled to storage element 104 and host 108 and is configured to control storage element 104. Memory controller 106 can manage data stored in storage element 104 and communicate with host 108. In some implementations, memory controller 106 is designed to operate in a low-duty-cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash memory drive, or other media used in electronic devices (e.g., personal computers, digital cameras, cell phones, etc.). In some implementations, memory controller 106 is designed to operate in a high-duty-cycle environment, such as an SSD or embedded multi-media-card (eMMC), which is used as a data storage device for mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 106 can be configured to control operations of the storage element 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored in or to be stored in the storage element 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, the memory controller 106 is also configured to process error correction code (ECC) for data read from or written to the storage element 104. Any other suitable functions (e.g., programming the storage element 104) can also be performed by the memory controller 106. The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol.For example, the memory controller 106 can communicate with an external device via at least one of various interface protocols (e.g., the USB protocol, the MMC protocol, the peripheral component interconnection (PCI) protocol, the PCI-Express (PCI-E) protocol, the advanced technology attachment (ATA) protocol, the serial ATA protocol, the parallel ATA protocol, the small computer small interface (SCSI) protocol, the enhanced small disk interface (ESDI) protocol, the integrated drive electronics (IDE) protocol, the FireWire protocol, etc.).

[0063] The memory controller 106 and one or more storage elements 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In one example, as shown in FIG1B , the memory controller 106 and a single storage element 104 can be integrated into a memory card 112. Memory card 112 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a MultiMediaCard (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS card, and the like. Memory card 112 can also include a memory card connector 114 that couples memory card 112 to a host (e.g., host 108 in FIG1A ). In another example, as shown in FIG1C , the memory controller 106 and the plurality of storage elements 104 can be integrated into an SSD 116. The SSD 116 can also include an SSD connector 118 that couples the SSD 116 to a host (e.g., the host 108 in FIG1A ). In some implementations, the storage capacity and / or operating speed of the SSD 116 is greater than the storage capacity and / or operating speed of the storage card 112.

[0064] FIG2 shows a diagram of an exemplary storage device 104 (e.g., a NAND flash memory) having a storage cell array 202 and peripheral circuitry, wherein the peripheral circuitry includes a page buffer 204, a column decoder / bit line driver 206, a row decoder / word line driver 208, a voltage generator 210, control logic 212, a register 214, and an interface 216. FIG3 shows a schematic circuit diagram of an exemplary storage device 104, including the storage cell array 202 and peripheral circuitry 302 coupled to the storage cell array 202. For ease of illustration, some elements in FIG2 and FIG3 are described together. Peripheral circuitry 302 may include the page buffer 204, the column decoder / bit line driver 206, the row decoder / word line driver 208, the voltage generator 210, control logic 212, the register 214, and the interface 216 of FIG2. It will be appreciated that in some examples, additional peripheral circuitry may also be included.

[0065] In some aspects, voltage generator 210 may include multiple charge pumps and linear regulators. In some aspects, the storage cell array may include multiple planes (i.e., Plane 0, Plane 1, Plane 2, and Plane 3). Although FIG2 illustrates four planes (Plane 0, Plane 1, Plane 2, and Plane 3), in some other aspects, the NAND die may be divided into fewer or more than four planes (e.g., 1, 2, 6, 8, etc.). A plane includes multiple storage cells, which may be grouped into storage blocks. A storage block is typically the smallest erasable entity in a NAND flash memory die. In one example, a storage block includes multiple cells coupled to the same bit line. A storage block includes one or more pages of cells. The size of a page may vary depending on the implementation. In one example, the page size is 16 kB. Page sizes smaller or larger than 16 kB are also possible (e.g., 512 B, 2 kB, 4 kB, etc.).

[0066] As shown in FIG3 , storage cell array 202 may be a NAND flash storage cell array, in which storage cells 306 are arranged in an array of NAND strings 308, each NAND string 308 extending vertically above a substrate (not shown). In some implementations, each NAND string 308 includes a plurality of storage cells 306 coupled in series and stacked vertically. Each storage cell 306 can store a continuous analog value (e.g., voltage or charge), which depends on the number of electrons trapped within the region of the storage cell 306. Each storage cell 306 may be a floating gate type storage cell (including a floating gate transistor) or a charge trapping type storage cell (including a charge trapping transistor). In one example, storage cell 306 includes a transistor with a replacement gate. A storage cell 306 with a replacement gate typically has a low-resistance gate (e.g., a tungsten gate) and a charge trapping layer between the gate and the channel, where charge is trapped or stored to represent one or more bit values. In another example, the storage cell 306 may include a transistor having a floating gate (eg, a high resistance polysilicon gate) that stores a charge indicative of one or more bit values. Other architectures are also possible.

[0067] In some implementations, each storage cell 306 is a single-level cell (SLC) with two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, while the second storage state "1" can correspond to a second voltage range. In some implementations, each storage cell 306 is a multi-level cell (MLC), which can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to have a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to have one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​into the cell. A fourth nominal storage value can be used for the erased state.

[0068] As shown in FIG3 , each NAND string 308 can include a source select gate (SSG) 310 at its source terminal and a drain select gate (DSG) 312 at its drain terminal. SSG 310 and DSG 312 are the gate electrodes of the SSG transistor and the DSG transistor, respectively, and can be configured to activate a selected NAND string 308 (column of the array) during read and program operations. In some implementations, the SSGs 310 of NAND strings 308 in the same block 304 are coupled to, for example, ground via the same source line (SL) 314 (e.g., a common SL). According to some implementations, the DSG 312 of each NAND string 308 is coupled to a corresponding bit line 316, from which data can be read via an output bus (not shown). In some implementations, each NAND string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having DSG 312) or a deselect voltage (e.g., 0 V) ​​to a corresponding DSG 312 via one or more DSG lines 313 and / or applying a select voltage (e.g., higher than the threshold voltage of a transistor having SSG 310) or a deselect voltage (e.g., 0 V) ​​to a corresponding SSG 310 via one or more SSG lines 315.

[0069] As shown in FIG3 , NAND storage strings 308 can be organized into multiple blocks 304, each of which can have a common source line 314. In some implementations, each block 304 is the basic data unit for erase operations, meaning that all storage cells 306 in the same block 304 are erased simultaneously. Storage cells 306 in adjacent NAND storage strings 308 can be coupled via word lines 318, which select which row of storage cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of storage cells 306, which is the basic data unit for programming operations. The bit size of a page 320 can correspond to the number of NAND storage strings 308 coupled by a word line 318 in a block 304. Each word line 318 can include multiple control gates (gate electrodes) at each storage cell 306 in the corresponding page 320 and a gate line coupling the control gates. In some cases, dummy word lines containing no user data can also be used in the memory array adjacent to the select gate transistors. Such dummy word lines can shield the edge data word lines from certain edge effects.

[0070] Peripheral circuitry 302 can be coupled to memory cell array 202 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. Peripheral circuitry 302 can apply voltages to bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313 to perform multi-pass programming, including the proposed NGS scheme in non-last programming passes. As described above, peripheral circuitry 302 can include any suitable circuitry to facilitate operation of memory cell array 202 by applying and sensing voltage and / or current signals to and from each target memory cell 306 via bit lines 316 via word lines 318, source lines 314, SSG lines 315, and DSG lines 313. Peripheral circuitry 302 can include various types of peripheral circuitry formed using MOS technology.

[0071] A programming sequence for a group of storage cells 306 may include programming all desired pages into the group of storage cells 306. The programming sequence may include one or more programming passes. A programming pass (which may include one or more programming loops) may program one or more pages. A programming pass may include applying one or more effective programming voltages to the cells to be programmed, followed by applying one or more verify voltages to these cells to determine which cells have been programmed (subsequent programming passes typically do not apply effective programming voltages and / or verify voltages to already programmed cells). Applying the effective programming voltage to the cells may include changing the voltage difference between the control gate and the channel of the cell to change the threshold voltage of the cell. Therefore, the voltage of a word line (coupled to the control gate of the target cell) and / or the channel of the cell may be set to enable application of the effective programming voltage. Since the term "programming voltage" is often used to refer to the voltage applied to the word line, the effective programming voltage may be the voltage difference between the control gate and the channel of the cell (which may be synonymous with the programming voltage if the channel is held at 0 V).

[0072] FIG4A illustrates a perspective view of a portion of an exemplary three-dimensional (3D) memory cell array structure 400 according to some aspects. Memory cell array structure 400 includes a substrate 430, an insulating film 431 overlying substrate 430, a layer of bottom select gates (BSG) 432 overlying insulating film 431, and multiple layers of control gates 433 (also referred to as "word lines" (WLs)) stacked atop BSG 432 to form a film stack 435 of alternating conductive and dielectric layers. For clarity, dielectric layers adjacent to the layers of control gates are not shown in FIG4 .

[0073] The control gates of each level are separated by gap structures 416-1 and 416-2 that pass through the film stack 435. The storage cell array structure 400 also includes a level of top select gates (TSGs) 434 above the stack of control gates 433. The stack of TSGs 434, control gates 433, and BSGs 432 is also referred to as a "gate electrode." The storage cell array structure 400 also includes storage strings 412 and doped source line regions 444 in portions of the substrate 430 between adjacent BSGs 432. Each storage string 412 includes a channel hole 436 that extends through the insulating film 431 and the film stack 435 of alternating conductive and dielectric layers. The storage string 412 also includes a storage film 437 on the sidewalls of the channel hole 436, a channel layer 438 above the storage film 437, and a core fill film 439 surrounded by the channel layer 438. The memory cell 440 can be formed at the intersection of the control gate 433 and the memory string 412. The portion of the channel layer 438 below the control gate 433 is also referred to as the channel of the memory cell 440. The memory cell array structure 400 also includes a plurality of bit lines (BL) 441, which are connected to the memory strings 412 above the TSG 434. The memory cell array structure 400 also includes a plurality of metal interconnect lines 443 connected to the gate electrodes through a plurality of contact structures 414. The edge of the film stack 435 is configured in a stepped shape to allow electrical connection to each level of the gate electrode.

[0074] In FIG4A , for illustrative purposes, three levels of control gates 433-1, 433-2, and 433-3 are shown along with one level of TSG 434 and one level of BSG 432. In this example, each storage string 412 may include three storage cells 440-1, 440-2, and 440-3, corresponding to the control gates 433-1, 433-2, and 433-3, respectively. The number of control gates and storage cells can be greater than three to increase storage capacity. The storage cell array structure 400 may also include other structures, such as TSG cut structures, common source contacts, and dummy storage strings. For simplicity, these structures are not shown in FIG4A .

[0075] FIG4B shows a schematic diagram of an exemplary 3D storage element 450 in a plan view according to some aspects of the present invention. The 3D storage element 450 may include multiple channel structure regions (e.g., storage planes, storage blocks, storage fingers, etc.), and one or more through array contact (TAC) structures may be formed between two adjacent channel structure regions. In some aspects as shown in FIG4B , the 3D storage element 450 may include four or more storage planes 460, each of which may include multiple storage blocks 465. Note that the arrangement of the storage planes 460 in the 3D storage element 450 and the arrangement of the storage blocks 465 in each storage plane 460 shown in FIG4B are merely examples and do not limit the scope of the present invention.

[0076] The TAC structure may include: one or more bit line (BL) TAC regions 471, which are sandwiched between two adjacent storage blocks 465 in the bit line direction (marked as "BL" in the figure) of the 3D storage element and extend along the word line direction (marked as "WL" in the figure) of the 3D storage element; one or more word line (BL) TAC regions 473, which are sandwiched between two adjacent storage blocks 465 in the word line direction (WL) and extend along the bit line direction (BL); and one or more staircase structure (SS) TAC regions 480, which are located at the edge of each storage plane 460.

[0077] In some aspects, the 3D memory element 450 may include a plurality of contact pads 490 arranged in a line at the edge of the 3D memory element 450. The interconnection contacts may be used to electrically interconnect the 3D memory element 450 to any suitable device and / or interface to provide driving power, receive control signals, send response signals, etc.

[0078] Referring to Figure 5, a schematic block diagram of an example circuit for NAND reference voltage application according to some aspects of the present invention is shown. In NAND storage devices, to improve high-speed signal integrity and save IO power, the termination method of the data line DQ[X] can be changed from center-tapped termination (CTT) (also known as series-stud terminated logic (SSTL)) to pseudo open drain (POD). In some aspects, a reference voltage Vrefq can be used to determine whether the signal on the data line DQ[X] is a 0 or a 1. This reference voltage Vrefq can be set using a mode register and must be correctly configured by the memory controller during the reference voltage DQ calibration phase.

[0079] In some aspects, NAND reference voltage DQ calibration can use two reference voltages: a reference voltage Vrefq1 for array data and characteristic parameter inputs, and a reference voltage Vrefq2 for command and address code inputs. As shown in FIG5 , a reference voltage generator 510 can generate a first reference voltage Vrefq1 and a second reference voltage Vrefq2, and send the first reference voltage Vrefq1 and the second reference voltage Vrefq2 to a first voltage comparator 522 and a second voltage comparator 524, respectively. The signal of the data line DQ[X] is also input to the first voltage comparator 522 and the second voltage comparator 524, respectively.

[0080] The output of the first voltage comparator 522 may be sent to the data path pipeline 531 and the parameter interface 533. The output of the second voltage comparator 524 may be sent to the command and address interface 535. The array data output from the data path pipeline 531 may be written into the storage cell array 542. The data parameter data output from the parameter interface 533 and the command and address data output from the command and address interface 535 may be sent to the control logic 544 to generate characteristic parameters and command and address codes.

[0081] Referring to FIG. 6 , a schematic flow chart illustrating an example method 600 for training an IO reference voltage for a NAND storage device according to aspects of the present invention is shown. In some aspects, method 600 can adjust the IO reference voltage by using a training process and performing write and read operations to verify the data eye window. Note that in method 600 , reference voltage Vrefq can be used to represent either the first reference voltage Vrefq1 or the second reference voltage Vrefq2 described above. In the following examples, reference voltage Vrefq is used to represent the first reference voltage Vrefq1.

[0082] 6 , method 600 may begin at operation 610, where a new reference voltage value may be set (e.g., setting feature 23h). In some aspects, operation 610 may be performed without previously performing an on-die termination (ODT) disable operation (e.g., command 18h) and subsequently performing an ODT enable operation (e.g., command 1h).

[0083] In some training methods, before setting a new reference voltage value, it is necessary to disable the ODT feature in order to set the first reference voltage Vrefq1 to a non-OTD state, allowing the correct input of parameter data for Vrefq1 in subsequent processes. Furthermore, after changing the reference voltage value, another operation is required to enable the ODT feature. In these conventional training methods, additional commands are required to set Vrefq1 to a specific level and to change the system terminal configuration from an ODT-on state to an ODT-off state. For non-target ODT scenarios, when the first die is used for Vrefq training and the second die provides ODT for the first die, memory and controller designs can be complex.

[0084] In the training method 600 of the present invention, the ODT disable and enable operations before and after changing the reference voltage can be omitted from the training process. Therefore, not only can the time for the ODT disable command operation and the ODT enable command operation be saved, but also the waiting time between the ODT disable command and the set feature command, the waiting time between the set feature command and the ODT enable command, and the waiting time between the ODT enable command and the subsequent write training operation can be saved.

[0085] As shown in FIG6 , method 600 may proceed to operations 620 and 630 , where a data write operation (e.g., command 63h) and a data read operation (e.g., command 64h) of a write training process may be performed. Note that operations 620 and 630 may be performed directly after operation 610 without executing an ODT enable command.

[0086] In some aspects, to perform a write training process on the transmitter side, the controller may issue Command 63h followed by a LUN address. After issuing the LUN address, the host may input a data pattern and confirm successful input by checking the NAND output in a subsequent sequence. The data size written to the DQ may be predefined by the NAND. The host may identify the data size using a Get Characteristic command (e.g., Characteristic Address = 20h, B2) and may input and output data based on this size. After writing data to the NAND using a Write Training - Data Entry command (e.g., Command 63h), the data may be read back using a subsequent Write Training - Data Output command (e.g., Command 64h) using the LUN address.

[0087] As shown in FIG6 , method 600 may then proceed to operation 640 , where a determination is made as to whether the training process is complete. In some aspects, the data read back at operation 630 may be compared to the "expected" data to determine whether further training is required. If the data read back at operation 630 substantially matches the "expected" data, it may be determined that no further training is required. In some aspects, if fewer than a predefined number of data bytes are written, unwritten registers will have undefined data when read back. If more than a predefined number of data bytes are read, the data is also undefined and invalid. If the determination at operation 640 is negative ("No" at 640 ), method 600 may return to operation 610 to begin another training loop.

[0088] If the determination at operation 640 is positive ("YES" at 640), method 600 may proceed to operation 650, where the new reference voltage value may be set to the optimized reference voltage value (e.g., setting feature 23h). After multiple cycles of changing the reference voltage value and writing training, the controller may determine the optimal reference voltage level and configure it by setting feature parameters.

[0089] Thus, method 600 can run an algorithm to align clock and data strobes at a NAND storage element, can run an algorithm and calculate the correct read and write delays to the NAND storage element, can center the data eye for reads, and can report an error when signal integrity is poor and data cannot be reliably written or read.

[0090] It should be noted that the operations described in the flowchart of FIG. 6 can be performed or executed in any order or sequence and are not limited to the order and sequence shown and described in the figure. Furthermore, some of the operations in the flowchart of FIG. 6 can be performed or executed substantially simultaneously (where appropriate) or concurrently to reduce latency and processing time. Furthermore, it should be noted that FIG. 6 is provided by way of example only. At least one of the operations shown in FIG. 6 can be performed in a different order than shown, performed concurrently, or omitted entirely.

[0091] 7, a schematic timing diagram 700 is shown of exemplary operations of the method 600 for training the first reference voltage Vrefq1 according to some aspects of the present invention. As shown in FIG7, during the first operation 710 of executing the set feature command to set the value of Vrefq1, <cmd> <addr>At time t71 after the cycle, a preset value can be set to Vrefq1 to replace the old value of the first reference voltage. During the period from time t72 to time t73, Vrefq1 with the preset value can be used during the <parameter data> period. After operation 710, the first reference voltage Vrefq1 can be set to a new value in a wait operation 720. In some aspects, the wait operation 720 can last for any suitable time (e.g., anywhere from approximately 0.1 μs to approximately 2 μs (e.g., approximately 1 μs)) until the first reference voltage Vrefq1 stabilizes at the new value. After the wait operation 720, a write training operation 730 can be performed. During the period from time t74 to time t75, Vrefq1 with the new value for write training can be used during the <data> period of write training. Note that the value of the second reference voltage Vrefq2 can remain at the same level throughout the process.

[0092] 8A , a schematic block diagram 800 of an exemplary peripheral circuit for IO reference voltage training of a NAND storage device is shown according to aspects of the present invention.

[0093] As shown in FIG. 8A , the logic control circuit 810 may generate a first trimming voltage (eg, Trim1 <n:0>) and sends the first trimming voltage to the first main voltage source 822 to control the output voltage of the first main voltage source 822 (for example, the first reference voltage generation signal Vregq1_gen). The logic control circuit 810 can also generate and send a second trimming voltage (for example, Trim2 <n:0>) and a booster enable control signal (e.g., En_bst) to control the output voltage of the voltage booster 826 (e.g., the first reference voltage boost signal Vrefq1_bst). The reference voltage pad 830 can generate a reference voltage extension signal (e.g., Vrefq_ext). Based on the received first reference voltage generation signal Vregq1_gen, the first reference voltage boost signal Vrefq1_bst, the reference voltage extension signal Vrefq_ext, and the control signal directly sent from the logic control circuit 810, the multiplexer 840 can output the first reference voltage Vrefq1. In addition, the logic control circuit 810 can generate a third trim voltage (e.g., Trim3 <n:0>) and sends the third trimmed voltage to the second main voltage source 824 to generate the second reference voltage Vrefq2. Both the first reference voltage Vrefq1 and the second reference voltage Vrefq2 can be sent to the IO circuit 850 for use.

[0094] Referring to FIG8B , a schematic timing diagram 899 is shown illustrating exemplary operations of method 600 for training first reference voltage Vrefq1 according to aspects of the present invention based on FIG8A . Comparing schematic timing diagram 899 with schematic timing diagram 700 described above, the boost enable control signal En_bst can be used to control the first reference voltage boost signal Vrefq1_bst to accelerate stabilization of the new voltage level of the first reference voltage Vrefq1 during the training process.

[0095] As shown in FIG8B , during the first operation 891 of executing the set feature command to set the first reference voltage Vrefq1 value, <cmd> <addr>At time t81 after the cycle, a preset value can be set to Vrefq1 to replace the old value of the first reference voltage. The booster enable control signal En_bst can be switched from low (e.g., a "0" level) to high (e.g., a "1" level) at time t81. Once the first reference voltage Vrefq1 is boosted and stably maintained at the preset value, the booster enable control signal En_bst can be switched from high to low at time t82. In some aspects, the duration of the first high-level booster enable control signal En_bst from time t81 to time t82 can be in a range from approximately 20 ns to approximately 100 ns, for example, approximately 50 ns.

[0096] After operation 891, the first reference voltage Vrefq1 can be set to a new value in a wait operation 892. At time t83, immediately after the <parameter data> period, a new value for write training can be set to Vrefq1 to replace the default value of the first reference voltage. The booster enable control signal En_bst can be switched from low (e.g., a "0" level) to high (e.g., a "1" level) at time t83. Once the first reference voltage Vrefq1 is lowered and stably maintained at the new value, the booster enable control signal En_bst can be switched from high to low at time t84. In some aspects, the duration of the second high-level booster enable control signal En_bst from time t83 to time t84 can be in a range from approximately 10 ns to approximately 800 ns, for example, approximately 600 ns.

[0097] 9A , a schematic block diagram 900 of an exemplary peripheral circuit for IO reference voltage training of a NAND storage device is shown according to some other aspects of the present invention.

[0098] As shown in FIG. 9A , the logic control circuit 910 may generate a first trimming voltage (eg, Trim1 <n:0>) and simultaneously transmits the first trimmed voltage to the first main voltage source 922 and the voltage booster 926. The logic control circuit 910 may also generate a booster enable control signal (e.g., En_bst) and transmit the booster enable control signal to the voltage booster 926. The logic control circuit 910 may also generate an initiation enable control signal (e.g., En_int) and transmit the initiation enable control signal to the reference voltage initiation circuit 928. Based on the first reference voltage generation signal Vrefq1_gen output from the first main voltage source 922, the first reference voltage boost signal Vrefq1_bst output from the voltage booster 926, the first reference voltage initiation signal Vrefq1_int output from the reference voltage initiation circuit 928, the reference voltage extension signal Vrefq_ext output from the reference voltage pad 930, and a control signal directly transmitted from the logic control circuit 910, the multiplexer 940 may output the first reference voltage Vrefq1. In addition, the logic control circuit 910 can generate a third trimming voltage (eg, Trim3 <n:0>) and sends the third trimmed voltage to the second main voltage source 924 to generate the second reference voltage Vrefq2. Both the first reference voltage Vrefq1 and the second reference voltage Vrefq2 can be sent to the IO circuit 950 for use.

[0099] 9B , a schematic timing diagram 999 is shown illustrating exemplary operations of the method 600 for training the first reference voltage Vrefq1 according to some other aspects of the present invention. Comparing schematic timing diagram 999 with schematic timing diagrams 700 and 899 described above, the initiation enable control signal En_int can be used to control the reference voltage initiation circuit 928 to initiate a voltage level change of the first reference voltage Vrefq1 during the training process.

[0100] As shown in FIG9B , during the first operation 991 of executing the Set Feature command to set the Vrefq1 value, <cmd> <addr>At time t91 after the cycle, the preset value can be set to Vrefq1 to replace the old value of the first reference voltage. The enable control signal En_int can be switched from low (e.g., a "0" level) to high (e.g., a "1" level) at time t91. Once the first reference voltage Vrefq1 is raised and stably maintained at the preset value, the enable control signal En_int can be switched from high to low at time t92. In some aspects, the duration of the enable control signal En_int from time t91 to time t92 can be in the range of approximately 20 ns to approximately 100 ns, for example, approximately 50 ns.

[0101] After operation 991, the first reference voltage Vrefq1 can be set to a new value in a wait operation 992. At time t93, immediately after the <parameter data> period, a new value for write training can be set to Vrefq1 to replace the default value of the first reference voltage. The booster enable control signal En_bst can be switched from low (e.g., a "0" level) to high (e.g., a "1" level) at time t93. Once the first reference voltage Vrefq1 is lowered and stably maintained at the new value, the booster enable control signal En_bst can be switched from high to low at time t94. In some aspects, the duration of the high-level booster enable control signal En_bst from time t93 to time t94 can be in a range from approximately 10 ns to approximately 800 ns, for example, approximately 600 ns.

[0102] Referring to FIG. 10A , a schematic circuit diagram of an exemplary resistor divider 1000A according to some other aspects of the present invention is shown. As shown, multiple resistors can be connected in series. Multiple interconnection points between adjacent resistor pairs can be connected to multiple input lines of a multiplexer 1040. Based on the received trim voltage Trim <n:0>The multiplexer 1040 can output the reference voltage Vrefq_out. Note that the disclosed resistor divider 1000A can be used for any of the first main voltage source, the second main voltage source, the voltage booster, and the reference voltage initiation circuit described above.

[0103] Referring to FIG. 10B , a schematic circuit diagram 1000B is shown illustrating an exemplary combination of a reference voltage generator and an analog buffer according to some further aspects of the present invention. As shown, reference voltage generator 1070 can generate a reference voltage signal Vref as a first input to analog buffer 1080. The output Vrefq_out of analog buffer 1080 can be sent back to a second input of analog buffer 1080. Note that the disclosed circuit 1000B can be used for any of the first main voltage source, second main voltage source, voltage booster, and reference voltage initiation circuits described above.

[0104] For example, various disclosed aspects can be implemented using one or more computer systems (e.g., computer system 1100 shown in FIG. 11 ). Computer system 1100 can be any known computer capable of performing the functions described herein, such as memory system 102 in FIG. Computer system 1100 includes one or more processors (also known as central processing units or CPUs), such as processor 1104. Processor 1104 is connected to a communication infrastructure 1106 (e.g., a bus). Computer system 1100 also includes user input / output devices 1103 (e.g., a monitor, keyboard, pointing device, etc.), which communicate with communication infrastructure 1106 via user input / output interface 1102. Computer system 1100 also includes main memory 1108 or primary memory, such as random access memory (RAM). Main memory 1108 can include one or more levels of cache memory. Main memory 1108 has control logic (e.g., computer software) and / or data stored therein.

[0105] The computer system 1100 may also include one or more secondary storage devices or secondary memory 1110. The secondary memory 1110 may include, for example, a hard drive 1112 and / or a removable storage device or removable storage drive 1114. The removable storage drive 1114 may be a floppy disk drive, a magnetic tape drive, a compact disk drive, an optical storage device, a tape backup device, and / or any other storage device / drive.

[0106] Removable storage drive 1114 can interact with removable storage unit 1118. Removable storage unit 1118 includes a computer-usable or computer-readable storage device on which computer software (control logic) and / or data is stored. Removable storage unit 1118 can be a floppy disk, magnetic tape, compact disk, DVD, optical storage disk, and / or any other computer data storage device. Removable storage drive 1114 reads from and / or writes to removable storage unit 1118 in a known manner.

[0107] According to some aspects, secondary memory 1110 may include other units, tools, or other means for allowing computer programs and / or other instructions and / or data to be accessed by computer system 1100. Such units, tools, or other means may include, for example, removable storage unit 1222 and interface 1220. Examples of removable storage unit 1222 and interface 1220 may include a program cartridge and cartridge interface (e.g., as found in video game devices), a removable memory chip (e.g., an EPROM or PROM) and an associated socket, a memory stick and a USB port, a memory card and an associated memory card slot, and / or any other removable storage unit and associated interface.

[0108] Computer system 1100 may also include a communication interface 1124 or network interface. Communication interface 1224 enables computer system 1100 to communicate and interact with any combination of remote devices, remote networks, remote entities, etc. (individually and collectively referenced by the diagrammatic numeral 1228). For example, communication interface 1224 may allow computer system 1100 to communicate with remote device 1228 via communication path 1226, which may be wired and / or wireless and may include any combination of a LAN, a WAN, the Internet, etc. Control logic and / or data may be transmitted to and from computer system 1100 via communication path 1226.

[0109] The operations in the aforementioned aspects can be implemented in a variety of configurations and architectures. Thus, some or all of the operations in the aforementioned aspects can be performed in hardware, software, or both. In some aspects, a tangible, non-transitory device or article of manufacture includes a tangible, non-transitory, computer-usable or readable medium having control logic (software) stored thereon, also referred to herein as a computer program product or program storage device. This includes, but is not limited to, computer system 1100, primary memory 1108, secondary memory 1110, and removable storage units 1118 and 1222, as well as tangible articles of manufacture embodying any combination of the foregoing. Such control logic, when executed by one or more data processing devices (e.g., computer system 1100), causes such data processing devices to operate as described herein.

[0110] Based on the teachings contained herein, it will be apparent to those skilled in the relevant art(s) how to make and use aspects of the present invention using data processing devices, computer systems, and / or computer architectures other than those shown in Figure 11. In particular, aspects may operate using software, hardware, and / or operating system implementations other than those described herein.

[0111] Therefore, the disclosed system, method, and medium for input / output voltage training of three-dimensional (3D) storage devices can set reference voltage values ​​without using additional ODT disable and enable commands, thereby reducing operation time, avoiding complex designs for non-ODT situations, and preventing parameter data entry errors.

[0112] One aspect of the present invention provides a method for input / output voltage training of a three-dimensional (3D) storage element. The method may include the following operations: (1) setting a reference voltage value in an on-die terminal (ODT) enabled state; (2) controlling the 3D storage element to perform a write training process; (3) determining whether a further write training process is required; (4) in response to determining that a further write training process is required, repeating operations (1), (2), and (3); and (5) in response to determining that a further write training process is not required, setting the reference voltage value to an optimized reference voltage value.

[0113] It should be noted that the operations (1)-(5) described above may be performed or executed in any order or sequence, and are not limited to following the order or sequence indicated solely to distinguish between the different operations. Furthermore, some of the operations (1)-(5) may be performed or executed substantially simultaneously (where appropriate) or concurrently to reduce latency and processing time. That is, one or more of the operations (1)-(5) may be performed in a different order than shown, performed concurrently, or omitted entirely.

[0114] In some embodiments, setting the reference voltage value is performed regardless of whether an on-die termination (ODT) is enabled or disabled.

[0115] In some embodiments, setting the reference voltage value includes: controlling a main voltage source to generate a reference voltage generating signal by using a first trimming signal.

[0116] In some embodiments, setting the reference voltage value further comprises: controlling the voltage booster to generate the reference voltage boost signal by using the second trim signal and the booster enable control signal.

[0117] In some embodiments, setting the reference voltage value further includes generating the reference voltage value based on at least a reference voltage generation signal and a reference voltage boost signal.

[0118] In some embodiments, setting the reference voltage value further includes: changing the reference voltage from an older value to a preset value during a first duration of a first high level of the boost enable control signal; and changing the reference voltage from the preset value to a new value for write training during a second duration of a second high level of the boost enable control signal.

[0119] In some embodiments, setting the reference voltage value further includes: controlling the voltage booster to generate a reference voltage boost signal by using the first trimming signal and the booster enable control signal; and controlling the reference voltage initiation circuit to generate a reference voltage initiation signal by using the first trimming signal and the initiation enable control signal.

[0120] In some embodiments, setting the reference voltage value further includes generating the reference voltage value based on at least a reference voltage generation signal, a reference voltage boost signal, and a reference voltage initiation signal.

[0121] In some embodiments, setting the reference voltage value further includes: changing the reference voltage from an older value to a preset value during a first duration of the high level of the initiation enable control signal; and changing the reference voltage from an older value to the preset value during a first duration of the high level of the boost enable control signal.

[0122] In some embodiments, performing a write training process includes performing a data write operation and a data read operation; and determining whether a further write training process is required based at least on a result of the data read operation.

[0123] Another aspect of the present invention provides a three-dimensional (3D) storage element, comprising: a storage cell array; and a peripheral circuit coupled to the storage cell array. The peripheral circuit comprises: a control circuit configured to: (1) set a reference voltage value in an on-die terminal (ODT) enabled state; (2) control the storage cell array to perform a write training process; (3) determine whether a further write training process is required; (4) in response to determining that a further write training process is required, repeat operations (1), (2), and (3); and (5) in response to determining that a further write training process is not required, set the reference voltage value to an optimized reference voltage value.

[0124] In some embodiments, the logic control circuit is further configured to set the reference voltage value regardless of whether an on-die termination (ODT) is enabled or disabled.

[0125] In some embodiments, the peripheral circuit further includes: a main voltage source configured to receive the first trimming signal from the logic control circuit and generate a reference voltage generation signal.

[0126] In some embodiments, the peripheral circuit further includes: a voltage booster configured to receive the second trimming signal and a booster enable control signal from the logic control circuit to generate a reference voltage boost signal.

[0127] In some embodiments, the peripheral circuit further includes: a multiplexer configured to generate a reference voltage value based on at least a reference voltage generation signal and a booster enable control signal.

[0128] In some embodiments, the multiplexer is configured to: change the reference voltage from an older value to a preset value during a first duration of a first high level of the booster enable control signal; and change the reference voltage from the preset value to a new value for write training during a second duration of a second high level of the booster enable control signal.

[0129] In some embodiments, the peripheral circuit further includes: a voltage booster, which is configured to receive a first trimming signal and a booster enable control signal from the logic control circuit to generate a booster enable control signal; and a reference voltage initiation circuit, which is configured to receive the first trimming signal and the initiation enable control signal from the logic control circuit to generate a reference voltage initiation signal.

[0130] In some embodiments, the peripheral circuit further includes: a multiplexer configured to generate a reference voltage value based on at least a reference voltage generation signal, a booster enable control signal, and a reference voltage initiation signal.

[0131] In some embodiments, the multiplexer is further configured to: change the reference voltage from an older value to a preset value during a first duration of the high level of the initiate enable control signal; and change the reference voltage from an older value to the preset value during a first duration of the high level of the boost enable control signal.

[0132] In some embodiments, the control circuit is further configured to: control the storage cell array to perform a data write operation and a data read operation; and determine whether a further write training process is required based at least on a result of the data read operation.

[0133] Another aspect of the present invention provides a memory system comprising: the 3D storage element described above; and a memory controller configured to control the 3D storage element.

[0134] The foregoing description of specific aspects will fully reveal the general nature of the invention, and others can readily modify and / or adapt such specific aspects for various applications by applying knowledge in the art without undue experimentation and without departing from the general concept of the invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed aspects, based on the disclosure and guidance presented herein. It should be understood that the phraseology or terminology used herein is for purposes of description and not limitation, such that the phraseology or terminology of this specification is to be interpreted by those skilled in the art in light of the disclosure and guidance.

[0135] Aspects of the present invention have been described above using functional building blocks that illustrate how specified functions and their relationships are implemented. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternate boundaries may be defined so long as the specified functions and their relationships are appropriately performed.

[0136] The Summary and Abstract sections may set forth one or more but not all exemplary aspects of the present invention as contemplated by the inventor(s), and thus, are not intended to limit the present invention and the appended claims in any way.

[0137] The breadth and scope of the present invention should not be limited by any of the above-described exemplary aspects, but should be defined only in accordance with the following claims and their equivalents.

[0138] 0,1,2,3: plane 100: System 102:Memory System 104,450: Storage components 106:Memory Controller 108:Host 112: Memory card 114: Storage card connector 116: Solid-state drive (SSD) 118:SSD connector 202: Storage cell array 204: Page Buffer 206: Column decoder / bit line driver 208: Row decoder / word line driver 210: Voltage generator 212,544: Control Logic 214: Register 216,1220:Interface 302: Peripheral circuit 304: Block 306,440,440-1,440-2,440-3: Storage unit 308,412: Storage string 310: Source Select Gate (SSG) 312: Drain select gate (DSG) 313:DSG line 314: Source line (SL) 315:SSG Line 316,441: Bit line 318: Character Line 320: Page 400: Storage cell array structure 414: Contact structure 416-1, 416-2: Gap Structure 430: substrate 431: Insulating film 432: Bottom Select Gate (BSG) 433,433-1,433-2,433-3: Control Gate 435: membrane stack 436: Channel hole 434: Top Select Gate (TSG) 437: Storage membrane 438: Channel layer 439: Core filling membrane 443:Metal Interconnect 444: Source line region 460: Storage plane 465: Storage Block 471: Bit line through array contact (TAC) area 473: Character line TAC area 480: Step structure (SS) TAC area 490: Contact pad 510,1070: Reference voltage generator 522: first voltage comparator 524: Second voltage comparator 531: Data Path Pipeline 533: Parameter interface 535: Command and Address Interface 600:Method 610,620,630,640,650,710,720,730,891,892,893,991,992,993: Operation 700,899,999: Timing diagram 800,900: Schematic block diagram of peripheral circuits 810,910:Logic control circuit 822,922: First main voltage source 824,924: Second main voltage source 826,926: Voltage Booster 830,930: Reference voltage pad 840,940,1040:Multiplexer 850,950:IO circuit 928: Reference voltage initiation circuit 1000A:Resistor voltage divider 1000B: Schematic circuit diagram of an exemplary combination of a reference voltage generator and an analog buffer 1080:Analog Buffer 1100: Computer System 1102: Input / Output Interface 1103: Input / Output Device 1104:Processor 1106: Communications Infrastructure 1108: Main memory 1110: Secondary memory 1112:Hard disk drive 1114:Removable storage drive 1118: Removable storage unit 1222: Removable storage unit 1224: Communication interface 1226: Communication path 1228: remote device, remote network, remote entity, etc. En_bst, En_int: enable control signal t71,t72,t73,t74,t75,t81,t82,t83,t84,t91,t92,t93,t94: time Trim <n:0>:Trimming voltage Trim1 <n:0>:First trimming voltage Trim2 <n:0>: Second trimming voltage Trim3 <n:0>: Third trimming voltage Vregq1_gen: first reference voltage generation signal Vrefq1_bst: first reference voltage boost signal Vrefq_ext: reference voltage extension signal Vrefq1_int: first reference voltage start signal Vrefq, Vrefq_out: reference voltage Vrefq1: first reference voltage Vrefq2: second reference voltage BL: bit line direction WL: character line direction < / addr> < / cmd> < / addr> < / cmd> < / addr> < / cmd>

Claims

1. A method for training the input / output voltage of a three-dimensional (3D) storage element, comprising: (1) Set a reference voltage value if no on-die terminal (ODT) disable operation was performed previously and no ODT enable operation was performed subsequently; (2) Control the 3D storage element to perform a write training process; (3) Determine whether a further write training process is required; (4) In response to determining that the further write training process is required, repeat operations (1), (2) and (3); and (5) In response to determining that the further write training process is not required, set the reference voltage value to an optimized reference voltage value, wherein setting the reference voltage value includes: controlling the main voltage source to generate a reference voltage generation signal by using a first trimming signal.

2. The method as described in request item 1, wherein, Setting the reference voltage value also includes: controlling the voltage booster to generate a reference voltage boost signal by using a second trimming signal and a booster enable control signal.

3. The method as described in claim 2, wherein, Setting the reference voltage value further includes: generating the reference voltage value based at least on the reference voltage generation signal and the reference voltage boost signal.

4. The method as described in request item 3, wherein, Setting the reference voltage value further includes: changing the reference voltage from an older value to a preset value during a first duration of a first high level of the boost enable control signal; and changing the reference voltage from the preset value to a new value for writing training during a second duration of a second high level of the boost enable control signal.

5. The method as described in request item 1, wherein, Setting the reference voltage value further includes: controlling a voltage booster using the first trimming signal and a booster enable control signal to generate a reference voltage boost signal; and controlling a reference voltage initiation circuit using an initiation enable control signal to generate a reference voltage initiation signal.

6. The method as described in claim 5, wherein, Setting the reference voltage value further includes generating the reference voltage value based at least on the reference voltage generation signal, the reference voltage boost signal, and the reference voltage initiation signal.

7. The method as described in request item 5, wherein, Setting the reference voltage value further includes: changing the reference voltage from an older value to a preset value during a first duration of the high level of the initiation enable control signal; and changing the reference voltage from the preset value to a new value for writing training during a second duration of the high level of the boost enable control signal.

8. The method as described in request item 1, wherein: Performing the write training process includes performing data write operations and data read operations; and determining whether the further write training process is needed based at least on the result of the data read operation.

9. A three-dimensional (3D) storage element, comprising: Storage cell array; The peripheral circuitry coupled to the memory cell array includes: a logic control circuit configured to: (1) set a reference voltage value if no on-die terminal-time (ODT) disable operation was previously performed and no ODT enable operation was subsequently performed; (2) control the memory cell array to perform a write training process; (3) determine whether a further write training process is required; (4) repeat operations (1), (2), and (3) in response to determining that the further write training process is required; and (5) set the reference voltage value to an optimized reference voltage value in response to determining that the further write training process is not required; wherein setting the reference voltage value includes: controlling a main voltage source to generate a reference voltage generation signal by using a first trimming signal.

10. The apparatus as claimed in claim 9, wherein, The peripheral circuitry further includes: the main voltage source, which is configured to receive the first trimming signal from the logic control circuit and generate a reference voltage generation signal.

11. The apparatus as claimed in claim 10, wherein, The peripheral circuitry further includes a voltage booster configured to receive a second trimming signal and a booster enable control signal from the logic control circuitry to generate a reference voltage boost signal.

12. The apparatus as claimed in claim 11, wherein, The peripheral circuitry further includes a multiplexer configured to generate the reference voltage value based at least on the reference voltage generation signal and the boost converter enable control signal.

13. The apparatus as claimed in claim 12, wherein, The multiplexer is configured to: change a reference voltage from an older value to a preset value during a first duration of a first high level of the boost enable control signal; and change the reference voltage from the preset value to a new value for writing training during a second duration of a second high level of the boost enable control signal.

14. The apparatus of claim 10, wherein the peripheral circuitry further comprises: A voltage booster, the voltage booster being configured to receive the first trimming signal and the booster enable control signal from the logic control circuit to generate a reference voltage boost signal; And a reference voltage initiation circuit, the reference voltage initiation circuit being configured to receive an initiation enable control signal from the logic control circuit to generate a reference voltage initiation signal.

15. The apparatus as claimed in claim 14, wherein, The peripheral circuitry further includes a multiplexer configured to generate the reference voltage value based at least on the reference voltage generation signal, the boost converter enable control signal, and the reference voltage initiation signal.

16. The apparatus as claimed in claim 15, wherein, The multiplexer is also configured to: change the reference voltage from an older value to a preset value during a first duration of the high level of the initiation enable control signal; and change the reference voltage from the preset value to a new value for writing training during a second duration of the high level of the boost enable control signal.

17. The apparatus as claimed in claim 9, wherein, The control circuit is also configured to: control the storage cell array to perform data write operations and data read operations; and determine, at least based on the result of the data read operation, whether the further write training process is required.

18. A memory system comprising: The 3D storage element as described in claim 9; And a memory controller configured to control the 3D storage element.

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