Error correction code circuit and semiconductor apparatus including the same

Abstract

This invention relates to an error correction code circuit and a semiconductor device including the same. The technology may include an error correction code engine configured to generate parity bits and checksum information by performing operations based on computational source data; and a data processing circuit configured to simultaneously output parity bits and first delay data generated by delaying input data for a first time during a write operation, and simultaneously output checksum information and second delay data generated by delaying input data for a second time during a read operation, and to substantially share the same signal path when generating the first delay data and when generating the second delay data.

Description

Technical Field

[0001] The various embodiments are generally related to semiconductor circuits, and more specifically, to error correction code circuits and semiconductor devices including therein. Prior Technology

[0002] In semiconductor devices (such as semiconductor memory devices), the time required for specifications related to various operations decreases due to increased operating speed, leading to an increase in bit error rate. Therefore, semiconductor devices have error correction codes (ECC) functionality to correct bit errors. Summary of the Invention

[0003] Cross-referencing of related applications: This application claims priority to Korean Application No. 10-2022-0025976, filed with the Korean Intellectual Property Office on February 28, 2022, the entire contents of which are incorporated herein by reference.

[0004] An error correction code circuit according to an embodiment of the present invention may include: an error correction code engine configured to generate parity bits and checksum information by performing operations based on computational source data; and a data processing circuit configured to simultaneously output parity bits and first delay data generated by delaying input data by a first time according to a write operation, and simultaneously output checksum information and second delay data generated by delaying input data by a second time according to a read operation, and substantially sharing the same signal path when generating the first delay data and when generating the second delay data.

[0005] A semiconductor device according to an embodiment of the present invention may include: a write path configured to write data and parity bits provided from a source outside the write path into a memory area during a write operation; a read path configured to correct errors included in data read from the memory area during a read operation based on parity information and configured to output error-corrected data; and an error correction code circuit configured to generate parity bits and parity information by performing operations on computational source data, to simultaneously output parity bits and first delay data generated by delaying input data for a first time according to the write operation to the write path, to simultaneously output parity information and second delay data generated by delaying input data for a second time according to the read operation to the read path, and to substantially share the same signal path when generating the first delay data and when generating the second delay data.

[0006] A semiconductor device according to an embodiment of the present invention may include: a write path configured to write data and parity bits provided from a source outside the write path into a memory area during a write operation; a read path configured to correct errors included in data read from the memory area during a read operation based on parity information and configured to output error-corrected data; an error correction code engine configured to generate parity bits and parity information by performing operations on computational source data; and a data processing circuit configured to simultaneously output parity bits and first delayed data generated by delaying input data for a first time according to the write operation to the write path, and simultaneously output parity information and second delayed data generated by delaying input data for a second time according to the read operation to the read path, and substantially share the same signal path when generating the first delayed data and when generating the second delayed data. Simple Explanation of the Diagram

[0007] Figure 1 is a diagram illustrating the configuration of a semiconductor device 100 according to an embodiment of the present invention. Figure 2 is a diagram illustrating the configuration of a semiconductor device 200 including an error correction code circuit according to an embodiment of the present invention. Figure 3 is a diagram showing the detailed configuration of a semiconductor device 200 including an error correction code circuit according to an embodiment of the present invention. Figure 4 is a diagram showing the configuration of the control signal generation unit 500 of Figure 3. Figure 5 is a diagram showing the configuration of the timing compensation unit 600 in Figure 3. Figure 6 is a diagram illustrating an ECC-related write operation of a semiconductor device 200 including an error correction code circuit according to an embodiment of the present invention. Figure 7 is a diagram illustrating an ECC-related read operation of a semiconductor device 200 including an error correction code circuit according to an embodiment of the present invention. Figure 8 is an operation timing diagram of a semiconductor device 200 including an error correction code circuit according to an embodiment of the present invention. Implementation

[0008] In the following description, embodiments of the invention will be described in more detail with reference to the accompanying drawings.

[0009] Various embodiments relate to providing an error correction code circuit and a semiconductor device including the same, which can improve the reliability of ECC operations and reduce current consumption caused by ECC operations.

[0010] Figure 1 is a diagram illustrating the configuration of a semiconductor device 100 according to an embodiment of the present invention.

[0011] Referring to Figure 1, the semiconductor device 100 may include a memory area 101, an address decoder 102, a pin array 103, a data input / output circuit 104, and a control circuit 105.

[0012] Memory region 101 may include multiple memory cells, and each of the multiple memory cells may include at least one of volatile memory and non-volatile memory. Examples of volatile memory may include static RAM (SRAM), dynamic RAM (SRAM), and synchronous DRAM (SDRAM), and examples of non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically erasable programmable ROM (EEPROM), electrically programmable ROM (EPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). During a read operation of semiconductor device 100, data stored in memory region 101 may be output. During a write operation of semiconductor device 100, data input from outside semiconductor device 100 may be stored in memory region 101. The memory cells of memory region 101 may be divided into multiple unit memory regions, such as multiple memory banks. Multiple memory banks may be divided into, for example, memory bank groups, and may be controlled according to the read and write operations of semiconductor device 100.

[0013] Address decoder 102 can be connected to control circuit 105 and memory area 101. Address decoder 102 can decode address signals provided by control circuit 105 and access memory area 101 based on the decoding result. Examples of address signals provided by control circuit 105 may include column address signals and row address signals. Column address signals may include addresses for selectively activating multiple memory bank groups and addresses for selectively activating multiple memory banks. Addresses for selectively activating multiple memory bank groups may be referred to as memory bank group addresses, and addresses for selectively activating multiple memory banks may be referred to as memory bank addresses.

[0014] Pin array 103 may include command and address integrated pin (CA) 103-1. Command CMD and external address signal ADD can be sequentially input through command and address integrated pin (CA) 103-1 in a predetermined timing.

[0015] Data input / output circuit 104 can be connected to memory area 101. Data input / output circuit 104 can exchange data internally with semiconductor device 100 or with external devices. Data input / output circuit 104 may include data input buffers, data output buffers, data input / output pads, etc. Data input / output circuit 104 may include error correction code circuitry (hereinafter referred to as ECC circuitry). ECC circuitry may include data processing circuitry for delaying data input during write operations and data input during read operations by using a signal path shared by write and read operations of semiconductor device 100 when performing ECC-related operations. The data processing circuitry may be connected to both the write path and read path of semiconductor device 100 and can delay data passing through the write path and data passing through the read path when performing ECC-related operations.

[0016] Control circuitry 105 can be connected to memory area 101, address decoder 102, and data input / output circuitry 104. Control circuitry 105 can perform read operations, write operations, and control operations related to address processing of semiconductor device 100. Control circuitry 105 can receive commands and external addresses from external sources via command and address integrated pins (CA).

[0017] Figure 2 is a diagram illustrating the configuration of a semiconductor device 200 including an error correction code circuit according to an embodiment of the present invention.

[0018] Referring to Figure 2, the semiconductor device 200 may include a write path 202, a read path 203, and an ECC circuit 300.

[0019] Write path 202 can be configured to write data (hereinafter referred to as write data) and parity bits provided from an external source to memory area 201 during a write operation of semiconductor device 200.

[0020] The read path 203 can be configured to correct errors included in the data (hereinafter referred to as read data) read from the memory area 201 during the read operation of the semiconductor device 100 based on the check information, and can be configured to output the error-corrected read data.

[0021] ECC circuit 300 can be configured to generate parity bits and checksum information by performing ECC operations on input data. ECC circuit 300 can be configured to delay input data during a write operation by a first time and transmit the delayed data to write path 202, and can be configured to delay input data during a read operation by a second time and transmit the delayed data to read path 203. The first time can be set to match the time required for parity bit operations, and the second time can be set to match the time required for both parity bit operations and checksum information operations. Because the second time is set to match the time including additional operations (i.e., checksum information operations), the second time can be longer than the first time.

[0022] ECC circuit 300 may include data processing circuit 400 configured to delay data input during a write operation for a first time and transmit the delayed data to write path 202, and to delay data input during a read operation for a second time and transmit the delayed data to read path 203.

[0023] Figure 3 is a diagram showing the detailed configuration of a semiconductor device 200 including an error correction code circuit according to an embodiment of the present invention.

[0024] Referring to Figure 3, the write path 202 may include a first line driver (WGIO DRV) 221, a first global line WGIO, a second line driver (WGIO DRV) 222, and a write driver (WDRV) 223.

[0025] The WGIO DRV 221 can be configured to drive write data and send driven write data to the first global line WGIO.

[0026] The first global line WGIO can be configured to send the output of WGIO DRV 221 to the ECC circuit 300.

[0027] The WGIO DRV 222 can be configured to drive and output the first delay data EIO1 and the parity bit PRT.

[0028] The WDRV 223 can be configured to drive the output of the WGIO DRV 222 and write the driven output to memory area 201.

[0029] The read path 203 may include a sense / amplifier circuit (IOSA) 231, a first line driver (RGIO DRV) 232, a second global line RGIO, a data correction circuit 233, and a second line driver (RGIO DRV) 234.

[0030] In an embodiment of the invention, a data correction circuit 233 is included in the read path. However, this is only one embodiment and the data correction circuit 233 can be configured in different circuits. For example, the data correction circuit 233 may be included as a component of the ECC circuit 300.

[0031] IOSA 231 can be configured to output read data generated by sensing and amplifying data in memory area 201 corresponding to the address associated with the read operation and the corresponding parity bit.

[0032] The RGIO DRV 232 can be configured to drive the output of the IOSA 231 and send the driven output to the second global line RGIO.

[0033] The second global line RGIO can be configured to send the output of RGIO DRV 232 to the ECC circuit 300.

[0034] Data correction circuit 233 can be configured to correct errors included in the second delayed data EIO2 according to the parity information CORR, and is configured to output error-corrected read data EIOD. Data correction circuit 233 can correct errors included in the second delayed data EIO2 by inverting the second delayed data EIO2 according to the parity information CORR. For example, when the second delayed data EIO2 includes n bits of normal data and m bits of parity, the parity information CORR can be n+m bits, corresponding to the corresponding bits of the delayed data EIO, and data correction circuit 233 can perform error correction by inverting the logic level of one (or more) bits of the second delayed data EIO2, said one (or more) bits corresponding to one (or more) bits of the n+m bits of the parity information CORR that have a logically high value. Data correction circuit 233 can output error-corrected read data EIOD in response to the output control signal CORTP. The output control signal CORTP can be generated by the data correction circuit 233 itself, and can be started by taking into account the time margin required to perform the error correction operation from the input time of the second delayed data EIO2 or the input time of the check information CORR.

[0035] In the following text, the first delay data EIO1 and the second delay data EIO2 can be collectively referred to as delay data EIO, and for ease of description, the delay data EIO during the write operation of the semiconductor device will be referred to as the first delay data EIO1, and the delay data EIO during the read operation of the semiconductor device will be referred to as the second delay data EIO2.

[0036] The RGIO DRV 234 can be configured to drive and output the data correction circuit 233.

[0037] The lengths of the first global area line WGIO and the second global area line RGIO can be longer than the lengths of other interconnects in the semiconductor device 200. Therefore, the embodiments of the present invention are merely examples, in which drivers 221, 222, 232, and 234 are connected to the first global area line WGIO and the second global area line RGIO to function as repeaters for enhancing the strength of signals transmitted through the first global area line WGIO and the second global area line RGIO so that the receiving side can identify the strength of the signal, and drivers 221, 222, 232, and 234 are not fundamental components. Drivers 221, 222, 232, and 234 can be removed based on PVT (process, voltage, temperature) conditions including the lengths of the first global area line WGIO and the second global area line RGIO and the strength of the signals transmitted through the first global area line WGIO and the second global area line RGIO. When drivers 221, 222, 232, and 234 are not included, WDRV 223 can directly drive the first delay data EIO1 and the parity bit PRT, and can write the driven first delay data EIO1 and the parity bit PRT into memory area 201. IOSA 231 can directly send the read data generated by sensing and amplifying the data in memory area 201 corresponding to the address related to the read operation and the corresponding parity bit to the second global line RGIO.

[0038] ECC circuit 300 may include an ECC engine and data processing circuit 400. The ECC engine can be configured to perform ECC operations by using low-density parity check (LDPC) codes, BCH (Bose, Chaudhri, Hocquenghem) codes, turbine codes, Reed-Solomon codes, convolutional codes, recursive hierarchical codes, or coding modulation such as trellis-coded modulation (TCM) and block-coded modulation (BCM), i.e., generating parity check bits PRT, generating check information CORR, etc.

[0039] The ECC engine may include parity check operation logic 310 and parity check sub-logic 320. In one embodiment, parity check operation logic 310 and parity check sub-logic 320 may be implemented as hardware, software, or a combination of hardware and software. Parity check operation logic 310 may be configured to generate parity bit PRT by performing ECC operations based on operation source data DD. Parity check operation logic 310 may be configured to transmit the parity bit PRT and operation source data DD to parity check sub-logic 320. Parity check sub-logic 320 may generate parity check information CORR by performing ECC operations based on the parity bit PRT and operation source data DD. In this case, the time required for the operation of the parity bit PRT will be referred to as the first time ECC_TD1, and the time required for the operation of the parity bit PRT and parity check information CORR will be referred to as the second time ECC_TD2. Because the second time ECC_TD2 requires calculating relatively more information compared to the first time ECC_TD1, the second time ECC_TD2 can be longer than the first time ECC_TD1.

[0040] Data processing circuit 400 can be configured to generate first delayed data EIO1 by delaying input data in response to write command WR, and to generate second delayed data EIO2 by delaying input data in response to read command RD. Data processing circuit 400 can be configured to simultaneously output parity bit PRT and first delayed data EIO1 in response to write command WR, wherein first delayed data EIO1 is generated by delaying input data (i.e., data loaded onto the first global line WGIO) by a first time ECC_TD1. Data processing circuit 400 can be configured to simultaneously output parity information CORR and second delayed data EIO2 by delaying input data (i.e., data loaded onto the second global line RGIO) by a second time ECC_TD2 in response to read command RD. Data processing circuit 400 can share the same signal path to generate first delayed data EIO1 and second delayed data EIO2. Data processing circuit 400 may include control signal generation unit 500 and timing compensation unit 600.

[0041] The control signal generation unit 500 can generate input control signal PIN<0:2> and output control signal POUT<0:2> in response to write command WR and read command RD.

[0042] The timing compensation unit 600 can generate a first delayed data EIO1 by delaying the input data through a pipelined processing method in response to the write command WR, based on the input control signal PIN<0:2> and the output control signal POUT<0:2>. The timing compensation unit 600 can also generate a second delayed data EIO2 by delaying the input data through a pipelined processing method in response to the read command RD, based on the input control signal PIN<0:2> and the output control signal POUT<0:2>.

[0043] The timing compensation unit 600 can be configured to transmit input data as operation source data DD to the parity check operation logic 310 during a write operation of the semiconductor device 200. The timing compensation unit 600 can also be configured to transmit input data including parity bits as operation source data DD to the parity check operation logic 310 during a read operation of the semiconductor device 100.

[0044] Figure 4 is a diagram showing the configuration of the control signal generation unit 500 of Figure 3.

[0045] Referring to Figure 4, the control signal generation unit 500 may include a first shift register 510, a second shift register 520, and a delay circuit 530.

[0046] The first shift register 510 can be configured to generate input control signals PIN<0:2> in response to write command WR and read command RD. The first shift register 510 may include a first logic gate 511 and a second logic gate 513, as well as first flip-flops 514 to third flip-flops 516. The first logic gate 511 and the second logic gate 513 can perform an OR operation on the write command WR and the read command RD, and can output the ORed command. The first flip-flops 514 to third flip-flops 516 can receive the output of the second logic gate 513 through their clock terminals, and perform a shift operation on the output terminal level whenever the clock level changes, outputting the operation result as the input control signals PIN<0:2>. The first flip-flops 514 to third flip-flops 516 can initialize the output terminal level in response to a reset signal RST. For example, when the reset signal RST is input at a high level, the first flip-flops 514 to third flip-flops 516 can initialize all input control signals PIN<0:2> to a low level.

[0047] The second shift register 520 can be configured to generate an output control signal POUT<0:2> in response to a delayed write command WRd and a delayed read command RDd. The second shift register 520 may include a first logic gate 521 and a second logic gate 523, as well as first flip-flops 524 to third flip-flops 526. The first logic gate 521 and the second logic gate 523 can perform an OR operation on the write command WR and the read command RD, and can output the ORed command. The first flip-flops 524 to third flip-flops 526 can receive the output of the second logic gate 523 through their clock terminals, and perform a shift operation on the output terminal level whenever the clock level changes, outputting the result as the input control signal PIN<0:2>. The first flip-flops 524 to third flip-flops 526 can initialize the output terminal level in response to a reset signal RST. For example, when the reset signal RST is input at a high level, the first flip-flops 524 to third flip-flops 526 can initialize all input control signals PIN<0:2> to a low level.

[0048] The delay circuit 530 can be configured to delay the write command WR and the read command RD by different set times, and can output the delayed write command WRd and read command RDd. The delay circuit 530 may include a first delay section 531 (DLY1) and a second delay section 532 (DLY2). DLY1 can output the delayed write command WRd by delaying the write command WR by a first time ECC_TD1. DLY2 can output the delayed read command RDd by delaying the read command RD by a second time ECC_TD2.

[0049] Figure 5 is a diagram showing the configuration of the timing compensation unit 600 in Figure 3.

[0050] Referring to Figure 5, the timing compensation unit 600 may include a write driver unit 610, a read driver unit 620, a pipeline register 630, a computation source data processing unit 640, and a pipeline control unit 650.

[0051] The write driver 610 can generate internal data EIOI by driving the data loaded onto the first global line WGIO in response to the write enable signal WON. The write enable signal WON can be generated based on the write command WR and can have a start-up period according to the timing specifications related to the write operation of the semiconductor device. The write driver 610 can include a plurality of logic gates 611 to 613 and drivers 614 and 615. The first logic gate 611 can perform a NAND logic operation on the logic level of the write enable signal WON and the logic level of the first global line WGIO to output a NAND-operated signal. The second logic gate 612 can invert the logic level of the write enable signal WON and output a write enable signal WON with an inverted logic level. The third logic gate 613 can perform a NOR logic operation on the output of the second logic gate 612 and the logic level of the first global line WGIO to output a NOR-operated signal. Drivers 614 and 615 can drive the internal data EIOI to the level of power supply voltage VDD or ground voltage VSS according to the output of the first logic gate 611 and the output of the third logic gate 613.

[0052] The read driver unit 620 can generate internal data EIOI by driving the data loaded onto the second global line RGIO in response to the read enable signal RON. The read enable signal RON can be generated based on the read command RD and can have a start period according to the timing specifications related to the read operation of the semiconductor device. The read driver unit 620 can include a plurality of logic gates 621 to 623 and drivers 624 and 625. The first logic gate 621 can perform NAND logic operation on the logic level of the read enable signal RON and the logic level of the second global line RGIO and output the NAND-operated signal. The second logic gate 622 can invert the logic level of the read enable signal RON and output the read enable signal RON with the inverted logic level. The third logic gate 623 can perform NOR logic operation on the output of the second logic gate 622 and the logic level of the second global line RGIO and output the NOR-operated signal. Drivers 624 and 625 can drive the internal data EIOI to the level of the power supply voltage VDD or the ground voltage VSS according to the output of the first logic gate 621 and the output of the third logic gate 623.

[0053] The pipelined register 630 can have a multi-stage pipelined structure and can pipeline internal data EIOI sequentially input in response to write command WR and read command RD in response to multiple control signals PINB<0:2>, PINT<0:2>, POUTB<0:2>, and POUTT<0:2>, and can output the pipelined data as delayed data EIO. An embodiment of the invention is an example of the pipelined register 630 configured as a three-stage pipeline 631 to 633. The first-stage pipeline 631 can respond to PINB among the multiple control signals PINB<0:2>, PINT<0:2>, POUTB<0:2>, and POUTT<0:2>. <0> and PINT <0> It receives and latches internal data EIOI, and can respond to POUTB. <0> and POUTT <0> The latched data is output as delayed data (EIO). The second-stage pipeline 632 can respond to PINB. <1> and PINT <1> It receives and latches internal data EIOI and responds to POUTB. <1> and POUTT <1> The latched data is output as delayed data (EIO). The third-stage pipeline 633 can respond to PINB. <2> and PINT <2> It receives and latches internal data EIOI, and can respond to POUTB. <2> and POUTT <2> The latched data is output as delayed data EIO. Pipeline register 630 may also include latch 634, which is used to maintain the level of delayed data EIO until a new delayed data EIO is output.

[0054] The computational source data processing unit 640 can buffer internal data EIOI and output the buffered data as computational source data DD. The computational source data processing unit 640 may include multiple logic gates 641 and 642 for buffering the internal data EIOI. The multiple logic gates 641 and 642 can output the result obtained by performing AND logic operations on the internal data EIOI and the power supply voltage VDD as the computational source data DD. The computational source data processing unit 640 may also include a latch 643, which is used to sufficiently maintain the level of the internal data EIOI until a new internal data EIOI is output.

[0055] The production line control unit 650 can generate multiple control signals PINB<0:2>, PINT<0:2>, POUTB<0:2>, and POUTT<0:2> in response to the input control signal PIN<0:2> and the output control signal POUT<0:2>. The production line control unit 650 may include a first control unit 660 and a second control unit 670. The first control unit 660 can generate multiple control signals PINB<0:2> and PINT<0:2> by inverting the input control signal PIN<0:2> through multiple inverters 661 to 666. The second control unit 670 can generate multiple control signals POUTB<0:2> and POUTT<0:2> by inverting the output control signal POUT<0:2> through multiple inverters 671 to 676.

[0056] FIG6 is a diagram illustrating an ECC-related write operation of a semiconductor device 200 including an error correction code circuit according to an embodiment of the present invention; FIG7 is a diagram illustrating an ECC-related read operation of a semiconductor device 200 including an error correction code circuit according to an embodiment of the present invention; and FIG8 is an operation timing diagram of a semiconductor device 200 including an error correction code circuit according to an embodiment of the present invention.

[0057] The write operations related to ECC operations will be described below with reference to Figures 6 and 8.

[0058] The data WDATA input from the external device in response to the write command WR can be latched as internal data EIOI of the timing compensation unit 600 via WGIO DRV 221 and the first global line WGIO, and can be provided to the parity check operation logic 310 as operation source data DD.

[0059] The parity check operation logic 310 can generate parity check bits PRT based on the operation source data DD.

[0060] Internal data EIOI can be controlled via the input control signal PIN as shown in Figure 5. <0> It is locked in node PL0 of the first-stage pipeline 631 in the pipeline register 630.

[0061] The internal data EIOI locked in node PL0 can respond to the output control signal POUT as shown in Figure 5. <0> EIO1, as the first delayed data, is output.

[0062] The first delayed data EIO1 can be based on the internal data EIOI being delayed by a first time ECC_TD1, which is the time required for the operation of the parity check bit PRT.

[0063] In fact, at the same time, the first delay data EIO1 and the parity bit PRT can be written into the memory area 201 via WGIO DRV 222 and WDRV 223.

[0064] The read operations related to ECC operations will be described below with reference to Figures 7 and 8.

[0065] An example of an input read command RD with an interval of tCCD (CAS to CAS delay) following the input write command WR will be described below.

[0066] The data output from memory area 201 in response to read command RD can be latched as internal data EIOI of timing compensation unit 600 via IOSA 231 and RGIO DRV 232, and can be provided to parity check operation logic 310 as operation source data DD.

[0067] The parity check operation logic 310 can generate parity check bits PRT based on the operation source data DD.

[0068] The parity logic 320 can generate parity information CORR based on the parity check bit PRT and the operation source data DD.

[0069] Internal data EIOI can be controlled via input control signal PIN. <1> It is then locked in node PL1 of the first-stage pipeline 631 in the pipeline temporary register 630.

[0070] The internal data EIOI locked in node PL1 can respond to the output control signal POUT. <1> EIO2, as the second delay data, is output.

[0071] The second delayed data EIO2 can be based on the internal data EIOI being delayed by a second time ECC_TD2, which is the time required for the operation of the parity bit PRT and the operation of the check information CORR.

[0072] In fact, at the same time, the second delay data EIO2 and the check information CORR can be provided to the data correction circuit 233.

[0073] The data correction circuit 233 can correct errors included in the second delayed data EIO2 based on the check information CORR, and can output the error-corrected read data EIOD in response to the output control signal CORTP.

[0074] Error-corrected read data EIOD can be output to an external device as read data RDATA via RGIO DRV 234.

[0075] It will be understood by those skilled in the art that this invention can be implemented in other specific forms without altering its technical spirit or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of this invention is defined by the claims to be described below, rather than by the specific embodiments, and should be construed as including the meaning and scope of the claims and all modifications or alterations derived from their equivalents within the scope of this invention.

[0076] 100: Semiconductor devices 101: Memory Area 102: Address Decoder 103: Pin Array 103-1: Address Integration Pin 104: Data Input / Output Circuit 105: Control Circuit 200: Semiconductor devices 201: Memory Area 202: Write path 203: Read path 221: First-line driver 222: Second-line driver 223: Write to drive 231: Sensing / Amplifier Circuit 232: First-line driver 233: Data Correction Circuit 234: Second-line driver 300: ECC circuit 310: Parity Check Logic 320: Verification Sub-Logic 400: Data processing circuit 500: Control signal generation unit 510: First shift register 511: First logic gate 513: Second logic gate 514: First trigger 515: Second trigger 516: Third trigger 520: Second shift register 521: First logic gate 523: Second logic gate 524: First trigger 525: Second trigger 526: Third trigger 530: Delay Circuit 531: First Delay Section 532: Second Delay Section 600: Timing Compensation Unit 610: Write to driver section 611: First logic gate 612: Second logic gate 613: Third logic gate 614: Driver 615: Driver 620: Read driver unit 621: First logic gate 622: Second logic gate 623: Third logic gate 624: Driver 625: Driver 630: Pipeline temporary register 631: First-stage assembly line 632: Second-stage assembly line 633: Third-stage assembly line 634: Latch 640: Data Processing Department 641: Logic gate 642: Logic gate 643: Latch 650: Assembly Line Control Department 660: First control unit 661~666: Inverters 670: Second control unit 671~676: Inverters ADD: External address signal CMD: command CORR: Checksum Information CORTP: Output control signal DD: Source data for computation ECC_TD1: First Time ECC_TD2: Second Time EIO: Delayed Data EIO1: First Delay Data EIO2: Second Delay Data EIOD: Reading data PIN<0:2>: Input control signal PINB<0:2>: Control signal PINT<0:2>: Control signal PL0: Node PL1: Node POUT<0:2>: Output control signal POUTB<0:2>: Control signal POUTT<0:2>: Control signal PRT: Parity check bit RD: Read command RDd: Read command RDATA: Read data RGIO: Second Global Line RON: Read enable signal RST: Reset signal VDD: Power supply voltage VSS: Ground voltage WDATA: Data WGIO: First Global Line WON: Write enable signal WR: Write command WRd: Write command

Claims

1. An error correction code circuit, comprising: The error correction code engine generates parity bits and checksum information by performing calculations based on the computation source data; And a data processing circuit that simultaneously outputs the parity check bit and a first delay data generated by delaying the input data by a first time according to a write operation, and simultaneously outputs the parity information and a second delay data generated by delaying the input data by a second time according to a read operation, and shares substantially the same signal path when generating the first delay data and when generating the second delay data.

2. The error correction code circuit as described in claim 1, wherein, The first time is set to match the time required for the operation of the parity bit, and the second time is set to match the time required for the operation of the parity bit and the operation of the parity information.

3. The error correction code circuit as described in claim 1, wherein, The error correction code engine includes: parity check operation logic, which generates the parity check bit by performing an operation based on the operation source data; and check sub logic, which generates the check sub information by performing an operation based on the parity check bit and the operation source data.

4. The error correction code circuit as described in claim 1, wherein, The data processing circuit includes: a control signal generation unit that generates an input control signal and an output control signal in response to a write command and a read command, respectively; and a timing compensation unit that generates first delayed data by delaying the input data according to the write operation through a pipelined processing method in response to the input control signal and the output control signal, and generates second delayed data by delaying the input data according to the read operation through a pipelined processing method in response to the input control signal and the output control signal.

5. The error correction code circuit as described in claim 4, wherein, The control signal generation unit generates the output control signal in response to delayed write commands and delayed read commands generated by delaying the write command and the read command by different times, respectively.

6. The error correction code circuit as described in claim 4, wherein, The control signal generation unit includes: a first shift register that generates the input control signal in response to the write command and the read command; a second shift register that generates the output control signal in response to a delayed write command and a delayed read command; and a delay circuit that outputs a signal obtained by delaying the write command by a first time as the delayed write command, and outputs a signal obtained by delaying the read command by a second time as the delayed read command.

7. The error correction code circuit as described in claim 4, wherein, The timing compensation unit provides the error correction code engine with the input data according to the write operation and the input data according to the read operation as the computation source data.

8. The error correction code circuit as described in claim 4, wherein, The timing compensation unit includes: a write driver that generates internal data based on the input data of the write operation in response to a write enable signal; a read driver that generates the internal data based on the input data of the read operation in response to a read enable signal; a pipelined register that pipelines the internal data based on the write operation to output the pipelined data as first delayed data, and pipelines the internal data based on the read operation to output the pipelined data as second delayed data; and a computational source data processing unit that buffers the internal data based on the write operation and the internal data based on the read operation and outputs the buffered data as the computational source data.

9. A semiconductor device, comprising: The write path, which writes data and parity bits into the memory area during the write operation; A read path that corrects errors in data read from the memory area during a read operation based on parity information and outputs error-corrected data; and an error correction code circuit that generates the parity bit and the parity information by performing operations on the source data, simultaneously outputting the parity bit and a first delay data generated by delaying the input data for a first time according to the write operation to the write path, simultaneously outputting the parity information and a second delay data generated by delaying the input data for a second time according to the read operation to the read path, and sharing substantially the same signal path when generating the first delay data and when generating the second delay data.

10. The semiconductor device as claimed in claim 9, wherein, The write path includes: a first global line that sends data provided from a source outside the write path to the error correction code circuit; a line driver that drives and outputs the first delay data and the parity bit; and a write driver that drives the output of the line driver and writes the driven output into the memory area.

11. The semiconductor device as claimed in claim 9, wherein, The read path includes: a sensing / amplifier circuit that senses and amplifies the data output from the memory area and the corresponding parity bits, and outputs the amplified data; a line driver that drives the output of the sensing / amplifier circuit and outputs the driven output; a second global line that sends the output of the line driver to the error correction code circuit; and a data correction circuit that corrects errors included in the second delayed data according to the parity information and outputs the error-corrected data.

12. The semiconductor device as claimed in claim 9, wherein, The first time is set to match the time required for the operation of the parity bit, and the second time is set to match the time required for the operation of the parity bit and the operation of the parity information.

13. The semiconductor device as claimed in claim 9, wherein, The error correction code circuit includes: an error correction code engine that generates the parity check bit and the checksum information based on the computation source data; a control signal generation unit that generates an input control signal and an output control signal in response to a write command and a read command, respectively; and a timing compensation unit that generates the first delay data by delaying the input data of the write operation through a pipelined processing method in response to the input control signal and the output control signal, and generates the second delay data by delaying the input data of the read operation through a pipelined processing method in response to the input control signal and the output control signal.

14. The semiconductor device as claimed in claim 13, wherein, The control signal generation unit generates the output control signal in response to delayed write commands and delayed read commands generated by delaying the write command and the read command by different times, respectively.

15. The semiconductor device as claimed in claim 13, wherein, The control signal generation unit includes: a first shift register that generates the input control signal in response to the write command and the read command; a second shift register that generates the output control signal in response to a delayed write command and a delayed read command; and a delay circuit that outputs a signal obtained by delaying the write command by a first time as the delayed write command, and outputs a signal obtained by delaying the read command by a second time as the delayed read command.

16. The semiconductor device as claimed in claim 13, wherein, The timing compensation unit provides the error correction code engine with the input data according to the write operation and the input data according to the read operation as the computation source data.

17. The semiconductor device as claimed in claim 13, wherein, The timing compensation unit includes: a write driver that generates internal data based on the input data of the write operation in response to a write enable signal; a read driver that generates the internal data based on the input data of the read operation in response to a read enable signal; a pipelined register that pipelines the internal data based on the write operation to output the pipelined data as first delayed data, and pipelines the internal data based on the read operation to output the pipelined data as second delayed data; and a computational source data processing unit that buffers the internal data based on the write operation and the internal data based on the read operation and outputs the buffered data as computational source data.

18. A semiconductor device, comprising: A write path that, during a write operation, writes data and parity bits provided by a source outside the write path into the memory area. A read path that corrects errors in data read from the memory area during a read operation based on parity information and outputs error-corrected data; an error correction code engine that generates the parity bit and the parity information by performing operations on the source data; and a data processing circuit that simultaneously outputs the parity bit and a first delay data generated by delaying the input data for a first time according to the write operation to the write path, simultaneously outputs the parity information and a second delay data generated by delaying the input data for a second time according to the read operation to the read path, and shares substantially the same signal path when generating the first delay data and when generating the second delay data.

19. The semiconductor device as claimed in claim 18, wherein, The data processing circuit buffers the input data according to the write operation and the input data according to the read operation, and outputs the buffered data as the computation source data.

20. The semiconductor device as claimed in claim 18, wherein, The write path includes: a first global line that sends data provided from a source outside the write path to the error correction code engine during the write operation; a line driver that drives and outputs the first delay data and the parity bit; and a write driver that drives the output of the line driver and writes the driven output into the memory area.

21. The semiconductor device as claimed in claim 18, wherein, The read path includes: a sensing / amplifier circuit that senses and amplifies the data output from the memory area and the corresponding parity bits, and outputs the amplified data; a line driver that drives the output of the sensing / amplifier circuit and outputs the driven output; a second global line that sends the output of the line driver to the error correction code engine; and a data correction circuit that corrects errors included in the second delayed data according to the parity information and outputs the error-corrected data.

22. The semiconductor device as claimed in claim 18, wherein, The data processing circuit includes: a control signal generation unit that generates input control signals in response to write commands and read commands, respectively, and generates output control signals in response to delayed write commands and delayed read commands generated by delaying the write commands and read commands by different times, wherein the pipeline register operates in response to the input control signals and the output control signals.

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