Semiconductor structure and fabrication method thereof

Abstract

A semiconductor structure includes a substrate, a first element region, and a second element region adjacent to the first element region; and a first trench isolation structure disposed in the substrate between the first element region and the second element region, wherein the first trench isolation structure includes a first bottom surface in the first element region and a second bottom surface in the second element region, wherein the first bottom surface is lower than the second bottom surface, and wherein the first trench isolation structure further includes a first top surface in the first element region and a second top surface in the second element region, wherein the first top surface and the second top surface are coplanar.

Description

Semiconductor structure and manufacturing method thereof The present invention relates to the field of semiconductor technology, and in particular to an improved semiconductor structure and a manufacturing method thereof. Semiconductor integrated circuit technology continues to advance, with each new generation featuring smaller and more complex circuit designs than the previous generation. Some products require semiconductor components with different threshold voltages and / or operating voltages within the integrated circuit, and the structures of these components can differ to achieve these different threshold voltages and / or operating voltages. For example, a thicker gate oxide layer can be used to increase the operating voltage of a semiconductor component in a higher voltage region, potentially creating a height difference between the higher voltage region and the lower voltage region. This height difference can cause problems in the manufacturing process and negatively impact manufacturing yield. The main purpose of the present invention is to provide an improved semiconductor structure and a method for manufacturing the same to address the deficiencies or shortcomings of the prior art. On the one hand, the present invention provides a semiconductor structure comprising: a substrate comprising a first element region and a second element region adjacent to the first element region; and a first trench isolation structure arranged in the substrate between the first element region and the second element region, wherein the first trench isolation structure comprises a first bottom surface in the first element region and a second bottom surface in the second element region, wherein the first bottom surface is lower than the second bottom surface, wherein the first trench isolation structure further comprises a first top surface in the first element region and a second top surface in the second element region, wherein the first top surface is coplanar with the second top surface. According to an embodiment of the present invention, the first component area is a medium voltage component area, and the second component area is an input / output (I / O) component area. According to an embodiment of the present invention, a top surface of the substrate in the first device region is lower than a top surface of the substrate in the second device region. According to an embodiment of the present invention, the semiconductor structure further includes: a first gate oxide layer located on the top surface of the substrate in the first component region; and a second gate oxide layer located on the top surface of the substrate in the second component region, wherein the first gate oxide layer is thicker than the second gate oxide layer. According to an embodiment of the present invention, the thickness of the first gate oxide layer is between 200 and 220 angstroms, and the thickness of the second gate oxide layer is between 30 and 60 angstroms. According to an embodiment of the present invention, a top surface of the second gate oxide layer is coplanar with the second top surface of the first trench isolation structure in the second device region. According to an embodiment of the present invention, the semiconductor structure further includes: a third element region adjacent to the second element region; and a second trench isolation structure arranged in the substrate between the third element region and the second element region, wherein the second trench isolation structure includes a third bottom surface in the second element region and a fourth bottom surface in the third element region, wherein the third bottom surface is coplanar with the fourth bottom surface. According to an embodiment of the present invention, the third device region is a 1.2V device region. According to an embodiment of the present invention, the semiconductor structure further includes: a fourth element region adjacent to the third element region; and a third trench isolation structure located in the substrate between the third element region and the fourth element region, wherein the third trench isolation structure includes a fifth bottom surface in the third element region and a sixth bottom surface in the fourth element region, wherein the fifth bottom surface is coplanar with the sixth bottom surface. According to an embodiment of the present invention, the fourth device region is a low voltage device region or an SRAM device region. On the other hand, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first element region and a second element region adjacent to the first element region; and forming a first trench isolation structure in the substrate between the first element region and the second element region, wherein the first trench isolation structure includes a first bottom surface in the first element region and a second bottom surface in the second element region, wherein the first bottom surface is lower than the second bottom surface, wherein the first trench isolation structure further includes a first top surface in the first element region and a second top surface in the second element region, wherein the first top surface is coplanar with the second top surface. According to an embodiment of the present invention, the first component area is a medium voltage component area, and the second component area is an input / output (I / O) component area. According to an embodiment of the present invention, a top surface of the substrate in the first device region is lower than a top surface of the substrate in the second device region. According to an embodiment of the present invention, the method further includes: forming a first gate oxide layer on the top surface of the substrate in the first component area; and forming a second gate oxide layer on the top surface of the substrate in the second component area, wherein the first gate oxide layer is thicker than the second gate oxide layer. According to an embodiment of the present invention, the thickness of the first gate oxide layer is between 200 and 220 angstroms, and the thickness of the second gate oxide layer is between 30 and 60 angstroms. According to an embodiment of the present invention, a top surface of the second gate oxide layer is coplanar with the second top surface of the first trench isolation structure in the second device region. According to an embodiment of the present invention, the method further includes: forming a third element region adjacent to the second element region; and forming a second trench isolation structure in the substrate between the third element region and the second element region, wherein the second trench isolation structure includes a third bottom surface within the second element region and a fourth bottom surface within the third element region, wherein the third bottom surface is coplanar with the fourth bottom surface. According to an embodiment of the present invention, the third device region is a 1.2V device region. According to an embodiment of the present invention, the method further includes: forming a fourth element region adjacent to the third element region; and forming a third trench isolation structure in the substrate between the third element region and the fourth element region, wherein the third trench isolation structure includes a fifth bottom surface within the third element region and a sixth bottom surface within the fourth element region, wherein the fifth bottom surface is coplanar with the sixth bottom surface. According to an embodiment of the present invention, the fourth device region is a low voltage device region or an SRAM device region. Hereinafter, the details will be described with reference to the accompanying drawings, which also constitute a part of the detailed description of the specification and are illustrated in a manner that specifically describes the embodiments that can be implemented. The following embodiments are described in sufficient detail to enable a person skilled in the art to implement them. Of course, other embodiments may be employed, and any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered limiting, and the embodiments included therein are to be defined by the appended claims. Please refer to Figures 1 to 11, which are schematic diagrams of a method for manufacturing a semiconductor structure 1 according to an embodiment of the present invention. For example, the semiconductor structure 1 can be used in a 22nm embedded high-voltage device or process platform. As shown in Figure 1, a substrate 100 is first provided, for example, a semiconductor substrate such as a silicon substrate. A silicon oxide pad layer 102 and a silicon nitride pad layer 104 are formed on the substrate 100. According to an embodiment of the present invention, the substrate 100 includes a first region RA1, a second region RA2 adjacent to the first device region RA1, a third region RA3 adjacent to the second device region RA2, and a fourth region RA4 adjacent to the third device region RA3. According to an embodiment of the present invention, for example, the first region RA1 may be a medium voltage (MV) device region, and the second device region RA2 may be an input / output (I / O) device region. According to an embodiment of the present invention, for example, the third device region RA3 may be a 1.2V device region. According to an embodiment of the present invention, for example, the fourth device region RA4 may be a low-voltage (LV) device region or a static random access memory (SRAM) device region. Next, a photoresist pattern PR1 is formed on the silicon nitride pad layer 104. The photoresist pattern PR1 has an opening OP1, exposing the silicon nitride pad layer 104 in the first device region RA1. An etching process is then used to remove the silicon nitride pad layer 104 and the silicon oxide pad layer 102 in the first device region RA1 through the opening OP1, exposing the substrate 100. As shown in FIG. 2 , the photoresist pattern PR1 is then removed. A thermal oxidation process is then performed to form a silicon oxide layer 106 on the substrate 100 within the first device area RA1. According to an embodiment of the present invention, for example, the thickness of the silicon oxide layer 106 is approximately 420 angstroms. At this point, the top surface S1 of the substrate 100 within the first device area RA1 is lower than the top surface of the surrounding substrate 100, forming a height difference H1 of approximately 210 angstroms. As shown in FIG. 3 , an etching process, such as a wet etching process, is then performed to remove the silicon oxide pad layer 102 and the silicon nitride pad layer 104 on the substrate 100 . As shown in FIG4 , after forming a silicon oxide pad layer 108 and a silicon nitride pad layer on the substrate 100, a shallow trench isolation process is immediately performed to form a first trench isolation structure TI1 in the substrate 100 between the first device area RA1 and the second device area RA2, a second trench isolation structure TI2 in the substrate 100 between the second device area RA2 and the third device area RA3, and a third trench isolation structure TI3 in the substrate 100 between the third device area RA3 and the fourth device area RA4. The silicon nitride pad layer is then removed. According to an embodiment of the present invention, the first trench isolation structure TI1 includes a first bottom surface BS1 within the first element region RA1 and a second bottom surface BS2 within the second element region RA2, wherein the first bottom surface BS1 is lower than the second bottom surface BS2, and a step H2 of approximately 210 angstroms is formed between the first element region RA1 and the second element region RA2. According to an embodiment of the present invention, the second trench isolation structure TI2 includes a third bottom surface BS3 within the second element area RA2 and a fourth bottom surface BS4 within the third element area RA3, wherein the third bottom surface BS3 and the fourth bottom surface BS4 are coplanar. According to an embodiment of the present invention, the third trench isolation structure TI3 includes a fifth bottom surface BS5 within the third element area RA3 and a sixth bottom surface BS6 within the fourth element area RA4, wherein the fifth bottom surface BS5 and the sixth bottom surface BS6 are coplanar. As shown in FIG5 , a photoresist pattern PR2 is then formed on the substrate 100. The photoresist pattern PR2 has an opening OP2, exposing the silicon oxide pad layer 108 and the first trench isolation structure TI1 within the first and second device areas RA1 and RA2, as well as the second trench isolation structure TI2 within the second device area RA2. An etching process is then performed to remove the silicon oxide pad layer 108 within the first and second device areas RA1 and RA2 through the opening OP2, exposing the substrate 100. At this point, the second trench isolation structure TI2 forms a step H3 between the second and third device areas RA2 and RA3. Subsequently, the photoresist pattern PR2 is removed. As shown in FIG. 6 , a medium voltage gate oxide layer process is then performed, such as an in-situ steam generation (ISSG) process, and a deposition process, such as an atomic layer deposition (ALD) process, to form silicon oxide layers 210-240 in the first device area RA1 to the fourth area RA4, respectively. According to an embodiment of the present invention, for example, the thickness of the silicon oxide layer 210 in the first device area RA1 and the silicon oxide layer 220 in the second device area RA2 can be approximately 210 angstroms, including an ISSG silicon oxide layer having a thickness of approximately 140 angstroms and an ALD silicon oxide layer having a thickness of approximately 70 angstroms. The silicon oxide layer 210 in the first device area RA1 serves as the medium voltage gate oxide layer. According to an embodiment of the present invention, for example, the thickness of the silicon oxide layer 230 in the third device area RA3 and the silicon oxide layer 240 in the fourth device area RA4 can be about 259 angstroms, including a silicon oxide pad layer 108 with a thickness of about 49 angstroms, an ISSG silicon oxide layer with a thickness of about 140 angstroms, and an ALD silicon oxide layer with a thickness of about 70 angstroms. At this time, the top surface S1 of the substrate 100 in the first device area RA1 is slightly lower than the top surface S2 of the substrate 100 in the second device area RA2. The top surface S2 of the substrate 100 in the second device area RA2 is slightly lower than the top surface S3 of the substrate 100 in the third device area RA3. For example, the top surface S2 is approximately 30 angstroms lower than the top surface S3. The top surface S3 of the substrate 100 in the third device area RA3 and the top surface S4 of the substrate 100 in the fourth device area RA4 are coplanar. As shown in FIG. 7 , a photoresist pattern PR3 is then formed on the substrate 100. The photoresist pattern PR3 has an opening OP3, exposing the second device area RA2, the third device area RA3, and the fourth device area RA4. An etching process, such as reactive ion etching (RIE) or chemical oxide removal (COR), is then used to etch a portion of the thickness of the silicon oxide layers 220-240 through the opening OP3. Subsequently, the photoresist pattern PR3 is removed. At this point, the silicon oxide layer 220 in the second device area RA2 remains approximately 90 angstroms thick, and the silicon oxide layer 230 in the third device area RA3 and the silicon oxide layer 240 in the fourth device area RA4 remain approximately 140 angstroms thick. As shown in FIG8 , a photoresist pattern PR4 is then formed on the substrate 100. The photoresist pattern PR4 has an opening OP4, exposing the third device area RA3 and the fourth device area RA4. An etching process, such as a wet etching process such as a buffered oxide etch (BOE), is then used to completely remove the silicon oxide layers 230-240 through the opening OP4. Subsequently, the photoresist pattern PR4 is removed. As shown in FIG. 9 , an oxidation process is then performed to form a silicon oxide layer 231 and a silicon oxide layer 241 with a thickness of approximately 15.5 angstroms on the substrate 100 in the third device region RA3 and the fourth device region RA4, respectively. As shown in FIG. 10 , a photoresist pattern PR5 is then formed on the substrate 100. The photoresist pattern PR5 has openings OP5a and OP5b, respectively exposing the second device area RA2 and the fourth device area RA4. A wet etching process, such as dilute hydrofluoric acid (DHF), is then used to etch away the silicon oxide layer 241 in the fourth device area RA4 and a portion of the silicon oxide layer 220 in the second device area RA2. At this point, the silicon oxide layer 220 in the second device area RA2 remains approximately 50 angstroms thick. Subsequently, the photoresist pattern PR5 is removed. The silicon oxide layer 220 in the second device area RA2 serves as the gate oxide layer for the input / output (I / O) device. Finally, as shown in FIG. 11 , an oxidation process is performed to form a silicon oxide layer 242 on the substrate 100 in the fourth device region RA4. According to an embodiment of the present invention, for example, the thickness of the silicon oxide layer 242 is approximately 8 angstroms. The silicon oxide layer 242 in the fourth device region RA4 serves as a gate oxide layer for a low-voltage device or an SRAM device. Referring to FIG. 12 , the top surface of the silicon oxide layer 242 in the fourth device area RA4 is indicated by a dashed line P as a horizontal reference plane to facilitate illustrating the height differences between the various regions. The first trench isolation structure TI1 further includes a first top surface TS1 in the first device area RA1 and a second top surface TS2 in the second device area RA2 . The first top surface TS1 and the second top surface TS2 are coplanar and approximately 20 angstroms above the horizontal reference plane indicated by the dashed line P. According to an embodiment of the present invention, the top surface S1 of the substrate 100 in the first element region RA1 is lower than the top surface S2 of the substrate 100 in the second element region RA2. According to an embodiment of the present invention, for example, the top surface S1 of the substrate 100 in the first element region RA1 is lower than the horizontal reference plane indicated by the dotted line P by approximately 200 angstroms. According to an embodiment of the present invention, for example, the top surface S2 of the substrate 100 in the second element region RA2 is lower than the horizontal reference plane indicated by the dotted line P by approximately 30 angstroms. According to an embodiment of the present invention, the silicon oxide layer 210 is thicker than the silicon oxide layer 220. According to an embodiment of the present invention, the thickness of the silicon oxide layer 210 is between 200-220 angstroms, and the thickness of the silicon oxide layer 220 is between 30-60 angstroms. According to an embodiment of the present invention, the top surface 220a of the silicon oxide layer 220 is coplanar with the second top surface TS2 of the first trench isolation structure TI1 in the second element region RA2. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention. 1: Semiconductor structure 100: Substrate 102: Silicon oxide pad layer 104: Silicon nitride pad layer 106: Silicon oxide layer 108: Silicon oxide pad layers 210-240, 231, 241, 242: Silicon oxide layer 220a: Top surface BS1: First bottom surface BS2: Second bottom surface BS3: Third bottom surface BS4: Fourth bottom surface BS5: Fifth bottom surface BS6: Sixth bottom surface H1, H2, H3: Step P: Dashed lines PR1, PR2, PR3, PR4: Photoresist patterns OP1, OP2, OP3, OP4, OP5a, OP5b: Opening RA1: First region RA2: Second region RA3: Third region RA4: Fourth region S1, S2, S3, S4: Top surface TI1: First trench isolation structure TI2: Second trench isolation structure TI3: Third trench isolation structure TS1: First top surface TS2: Second top surface Figures 1 through 11 are schematic diagrams illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention. Figure 12 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention, wherein the top surface of the silicon oxide layer in the fourth device region is indicated by a dotted line as a horizontal reference plane to facilitate illustrating the height difference between the various regions. 1: Semiconductor structure 100: Base 210, 220, 231, 242: Silicon oxide layer 220a: Top surface BS1: First bottom surface BS2: Second bottom surface BS3: Third bottom surface BS4: Fourth bottom surface BS5: Fifth bottom surface BS6: Sixth base P: Dashed line RA1: First Area RA2: Second Area RA3: Area 3 RA4: Region 4 S1, S2, S3, S4: top surface TI1: First trench isolation structure TI2: Second trench isolation structure TI3: Third trench isolation structure TS1: First top surface TS2: Second top surface

Claims

1. A semiconductor structure comprising: a substrate including a first element region, a second element region adjacent to the first element region, a third element region adjacent to the second element region, and a fourth element region adjacent to the third element region; and a first trench isolation structure disposed in the substrate between the first element region and the second element region, wherein, The first trench isolation structure includes a first bottom surface in the first element region and a second bottom surface in the second element region, wherein the first bottom surface is lower than the second bottom surface; the first trench isolation structure further includes a first top surface in the first element region and a second top surface in the second element region, wherein the first top surface and the second top surface are coplanar; a second trench isolation structure is disposed in the substrate between the third element region and the second element region; a third trench isolation structure is located in the substrate between the third element region and the fourth element region; a first gate oxide layer is located on the top surface of the substrate in the first element region; a second gate oxide layer is located on the top surface of the substrate in the second element region, wherein the first gate oxide layer is thicker than the second gate oxide layer; a third gate oxide layer is located on the top surface of the substrate in the third element region; and a fourth gate oxide layer is located on the top surface of the substrate in the fourth element region. In this context, an upper surface of the fourth gate oxide layer within the fourth element region is defined as a horizontal reference plane, and both the first top surface and the second top surface of the first trench isolation structure are higher than the horizontal reference plane.

2. The semiconductor structure as described in claim 1, wherein, The first component area is the medium-voltage component area, and the second component area is the input / output (I / O) component area.

3. The semiconductor structure as described in claim 1, wherein, The top surface of the substrate in the first element region is lower than the top surface of the substrate in the second element region.

4. The semiconductor structure as described in claim 1, wherein, Both the first top surface and the second top surface of the first trench isolation structure are 20 angstroms above the horizontal reference plane.

5. The semiconductor structure as described in claim 4, wherein, The thickness of the first gate oxide layer is between 200 and 220 angstroms, and the thickness of the second gate oxide layer is between 30 and 60 angstroms.

6. The semiconductor structure as described in claim 4, wherein, The top surface of the second gate oxide layer is coplanar with the second top surface of the first trench isolation structure within the second element region.

7. The semiconductor structure as described in claim 3, wherein, The second trench isolation structure includes a third bottom surface within the second element region and a fourth bottom surface within the third element region, wherein the third bottom surface and the fourth bottom surface are coplanar.

8. The semiconductor structure as described in claim 7, wherein, The third component area is the 1.2V component area.

9. The semiconductor structure as described in claim 7, wherein, The third trench isolation structure includes a fifth bottom surface in the third element region and a sixth bottom surface in the fourth element region, wherein the fifth bottom surface and the sixth bottom surface are coplanar.

10. The semiconductor structure as described in claim 9, wherein, This fourth component area is either a low-voltage component area or an SRAM component area.

11. A method of forming a semiconductor structure, comprising: providing a substrate including a first element region, a second element region adjacent to the first element region, a third element region adjacent to the second element region, and a fourth element region adjacent to the third element region; forming a first trench isolation structure in the substrate between the first element region and the second element region, wherein, The first trench isolation structure includes a first bottom surface in the first element region and a second bottom surface in the second element region, wherein the first bottom surface is lower than the second bottom surface. The first trench isolation structure further includes a first top surface in the first element region and a second top surface in the second element region, wherein the first top surface and the second top surface are coplanar. A second trench isolation structure is formed in the substrate between the third element region and the second element region. A third trench isolation structure is formed in the substrate between the third element region and the fourth element region. A first gate oxide layer is formed on the top surface of the substrate in the first element region. A second gate oxide layer is formed on the top surface of the substrate in the second element region, wherein the first gate oxide layer is thicker than the second gate oxide layer. A third gate oxide layer is formed on the top surface of the substrate in the third element region. A fourth gate oxide layer is formed on the top surface of the substrate in the fourth element region. In this context, an upper surface of the fourth gate oxide layer within the fourth element region is defined as a horizontal reference plane, and both the first top surface and the second top surface of the first trench isolation structure are higher than the horizontal reference plane.

12. The method as described in claim 11, wherein, The first component area is the medium-voltage component area, and the second component area is the input / output (I / O) component area.

13. The method as described in claim 11, wherein, The top surface of the substrate in the first element region is lower than the top surface of the substrate in the second element region.

14. The method as described in claim 11, wherein, Both the first top surface and the second top surface of the first trench isolation structure are 20 angstroms above the horizontal reference plane.

15. The method as described in claim 14, wherein, The thickness of the first gate oxide layer is between 200 and 220 angstroms, and the thickness of the second gate oxide layer is between 30 and 60 angstroms.

16. The method as described in claim 14, wherein, The top surface of the second gate oxide layer is coplanar with the second top surface of the first trench isolation structure within the second element region.

17. The method as described in claim 13, wherein, The second trench isolation structure includes a third bottom surface within the second element region and a fourth bottom surface within the third element region, wherein the third bottom surface and the fourth bottom surface are coplanar.

18. The method as described in claim 17, wherein, The third component area is the 1.2V component area.

19. The method as described in claim 17, wherein, The third trench isolation structure includes a fifth bottom surface in the third element region and a sixth bottom surface in the fourth element region, wherein the fifth bottom surface and the sixth bottom surface are coplanar.

20. The method as described in claim 19, wherein, This fourth component area is either a low-voltage component area or an SRAM component area.

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