Semiconductor device and method of manufacture

Abstract

This disclosure discloses a semiconductor device and a method for manufacturing the same, wherein the semiconductor device includes an air gap between a source / drain region and a semiconductor substrate. In one embodiment, the semiconductor device includes a semiconductor substrate, a first channel region on the semiconductor substrate, a gate structure on the first channel region, a first source / drain region adjacent to the gate structure and the first channel region, a first internal spacer layer located between the first source / drain region and the semiconductor substrate in a first direction perpendicular to the main surface of the semiconductor substrate, and a first air gap located between the first source / drain region and the first internal spacer layer in the first direction.

Description

Semiconductor devices including air spacers and methods for manufacturing the same none Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements on the semiconductor substrate. The semiconductor industry is continuously increasing the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. none To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed. Furthermore, this document may use spatial relative terms such as "below," "under," "lower," "above," "upper," etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly. Various embodiments provide methods for forming a sealing gas gap (e.g., a gas spacer) adjacent to a source / drain region in a semiconductor device, and semiconductor devices formed by such methods. The method includes depositing a multilayer stack on a semiconductor substrate, the multilayer stack including alternating first and second semiconductor materials; etching the multilayer stack and the semiconductor substrate to form a plurality of nanostructures from the multilayer stack and a first groove adjacent to the nanostructures and extending into the semiconductor substrate; etching a side surface of the nanostructure through the first groove to form a sidewall groove adjacent to the first groove; depositing two or more internal spacer layers in the first groove and filling the sidewall groove, wherein the internal spacer layers extend along the side surface of the nanostructure and along the semiconductor substrate; etching the internal spacer layers to form an internal spacer adjacent to the nanostructure and the semiconductor substrate; and forming a source / drain region adjacent to the internal spacer and the nanostructure. The source / drain region may be formed by an epitaxial deposition process and may seal a bottom gas gap vertically disposed between the source / drain region and the spacer on the semiconductor substrate. In some embodiments, the source / drain regions may also seal a side air gap horizontally disposed between the source / drain regions and spacers on the nanostructure. The side air gap may be vertically disposed between adjacent nanostructures formed of the same semiconductor material, or vertically disposed between the nanostructure and the semiconductor substrate. Providing bottom and side air gaps helps reduce parasitic capacitance in devices including air gaps and helps improve bottom isolation between the source / drain regions and the semiconductor substrate. This improves device performance, such as alternating current (AC) performance. The embodiments described below are specific to a particular context, namely, a die including a nanostructured field-effect transistor. However, various embodiments may be applied to dies including other types of transistors (e.g., fin field-effect transistors (FinFETs), planar transistors, or the like) instead of nanostructured field-effect transistors or dies combined with nanostructured field-effect transistors. According to some embodiments, Figure 1 illustrates a three-dimensional view of a nanostructured field-effect transistor (e.g., a nanowire field-effect transistor, a nanosheet field-effect transistor (Nano-FET), a multi-bridge-channel field-effect transistor (MBCFET), a gate-all-around field-effect transistor (GAA FET), a nanoribbon field-effect transistor, or the like). The nanostructured field-effect transistor includes a nanostructure 55 (e.g., a nanosheet, nanowire, nanoribbon, or the like) above fins 66 on a substrate 50 (e.g., a semiconductor substrate). The nanostructure 55 serves as a channel region of the nanostructured field-effect transistor. The nanostructure 55 may include a material suitable for forming channel regions in a p-type transistor, an n-type transistor, or the like. Isolation regions 68 are disposed between adjacent fins 66, and the fins 66 may protrude over and between adjacent isolation regions 68. Although isolation region 68 is described / illustrated as separate from substrate 50, the term "substrate" as used herein may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Additionally, although the bottom portion of fin 66 is illustrated as having a single material continuous with substrate 50, fin 66 and / or the bottom portion of substrate 50 may include a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent isolation regions 68. The gate dielectric layer 104 is located above the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 106 is located above the gate dielectric layer 104. Epitaxial source / drain regions 92 are disposed on the fin 66 on the opposite sides of the gate dielectric layer 104 and the gate electrode 106. Figure 1 further illustrates reference cross sections used in subsequent figures. Cross section A-A' is along the longitudinal axis of the gate electrode 106, and its direction is, for example, perpendicular to the current direction between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. Cross section B-B' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the fins 66 of the nanostructured field-effect transistor, and its direction is, for example, in the current direction between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. For clarity, these reference cross sections will be referenced in subsequent figures. Some embodiments discussed herein involve nanostructured field-effect transistors formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments envision states used in planar devices (such as planar field-effect transistors) or in fin field-effect transistors. According to some embodiments, Figures 2 through 22C are cross-sectional views of intermediate stages in the fabrication of nanostructured field-effect transistors. Figures 2 through 5, 6A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, and 22A illustrate the reference cross-section A-A' shown in Figure 1. Figures 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 13D, 13E, 13F, 13G, 13H, 13I, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, and 22B illustrate the reference cross-section B-B' shown in Figure 1. Figures 7A, 8A, 9A, 10A, 11A, 12A, 13A, 13C, 14C, 19C, 20C, 21C, and 22C illustrate the reference cross-section C-C' shown in Figure 1. In Figure 2, a substrate 50 is provided. Substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 can be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium arsenide phosphide) or combinations thereof. The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an N-type metal-oxide-semiconductor (NMOS) transistor with an n-type nanostructure field-effect transistor, while the p-type region 50P can be used to form a p-type device, such as a P-type metal-oxide-semiconductor (PMOS) transistor with a p-type nanostructure field-effect transistor. The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided. Further, in Figure 2, a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layers 53). For illustrative purposes and as discussed in more detail below, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region of a nanostructured field-effect transistor in the p-type region 50P. The first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form a channel region of a nanostructured field-effect transistor in the n-type region 50N. In some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanostructured field-effect transistor in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanostructured field-effect transistor in the p-type region 50P. In some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form channel regions of a nanostructured field-effect transistor in the n-type region 50N and the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form channel regions of a nanostructured field-effect transistor in the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and may be formed simultaneously. Figures 22A, 22B, and 22C illustrate the structure resulting from an embodiment where the channel regions in both the p-type region 50P and the n-type region 50N include silicon. For illustrative purposes, the multilayer stack 64 is illustrated as comprising three first semiconductor layers 51 and three second semiconductor layers 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and two semiconductor layers 53. Each layer in the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods. In some embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for p-type nanostructure field-effect transistors (such as silicon germanium or the like), and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for n-type nanostructure field-effect transistors (such as silicon, silicon carbon, or the like). For illustrative purposes, the multilayer stack 64 is illustrated as having a bottom semiconductor layer suitable for a p-type nanostructure field-effect transistor. In some embodiments, a multilayer stack 64 may be formed such that the bottom layer is a semiconductor layer suitable for n-type nanostructure field-effect transistors. The first semiconductor material and the second semiconductor material can be materials that have high etch selectivity towards each other. Therefore, the first semiconductor layer 51 of the first semiconductor material in the n-type region 50N can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type nanostructure field-effect transistor. Similarly, the second semiconductor layer 53 of the second semiconductor material in the p-type region 50P can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type nanostructure field-effect transistor. In Figure 3, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar or combinations thereof. Etching can be anisotropic. The nanostructures 55 formed by etching multilayer stack 64 can further define first nanostructures 52A to 52C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and second nanostructures 54A to 54C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be further collectively referred to as nanostructure 55. The patterned fins 66 and nanostructures 55 can be achieved using any suitable method. For example, the patterned fins 66 and nanostructures 55 can utilize one or more optical lithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine optical lithography with a self-aligning process, thereby allowing the production of patterns with, for example, smaller pitches than that achievable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66. For illustrative purposes, Figure 3 shows the fins 66 in the n-type region 50N and the p-type region 50P as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or less than the width of the fins 66 in the p-type region 50P. Furthermore, although the individual fins 66 and nanostructures 55 are shown to have uniform widths, in some embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of the individual fins 66 and / or nanostructures 55 increases continuously toward the substrate 50. In such embodiments, the individual nanostructures 55 may have different widths and may be trapezoidal in shape. In Figure 4, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The shallow trench isolation region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66 and nanostructures 55. The insulating material can be an oxide (such as silicon oxide), a nitride (such as silicon nitride), the like, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In some embodiments, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is drawn as a single layer, multiple layers can be used in some embodiments. For example, in some embodiments, a liner (not shown separately) may be formed along the surfaces of the substrate 50, fins 66, and nanostructures 55. A filler material, such as that discussed above, may be formed over the liner. A removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back process, a combination thereof, or the like, may be used. The planarization process exposes the nanostructure 55 such that the nanostructure 55, after the planarization process is completed, has a flush top surface with the insulating material. The insulating material is recessed to form shallow trench isolation regions 68. The recess in the insulating material causes the upper portions of the nanostructures 55 and fins 66 in the n-type region 50N and p-type region 50P to protrude from between adjacent shallow trench isolation regions 68. The top surface of the shallow trench isolation region 68 may have a planar, convex, concave (such as dish-shaped) or combination thereof, as shown. The flat, convex, and / or concave top surfaces of the shallow trench isolation region 68 can be formed by appropriate etching. Acceptable etching processes can be used to recess the shallow trench isolation region 68, such as etching processes selectively applied to the insulating material (e.g., etching the insulating material at a faster rate than etching the material of the fins 66 and nanostructures 55). For example, dilute hydrofluoric acid (dHF) can be used to remove oxides. The processes described above with respect to Figures 2 through 4 are merely one example of how the fins 66 and nanostructures 55 are formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structures may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structures, the epitaxial growth material may be in-situ doped during growth, thus avoiding pre- and / or post-planting. In-situ doping and planted doping can be used together. Furthermore, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are illustrated and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N, but this is for illustrative purposes only. In some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be made of different materials, or may be formed in different orders in the p-type region 50P and the n-type region 50N. Further, in Figure 4, suitable traps (not shown separately) can be formed in the fin 66, nanostructure 55, and / or shallow trench isolation region 68. In embodiments with different trap types, photoresist or other masks (not shown separately) can be used to achieve different implantation steps for the n-type region 50N and p-type region 50P. For example, photoresist can be formed over the fin 66, nanostructure 55, and shallow trench isolation region 68 in the n-type region 50N and p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by spin coating and can be patterned using acceptable optical lithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to prevent n-type impurities from implanting into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, or the like in the implantation region, with a concentration ranging from about 10 per cubic centimeter. 13 atoms (atoms / cm) 3 ) to about 10 14 atoms / cm 3 After the photoresist is applied, it is removed by, for example, an acceptable ashing process. After or before implanting the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and shallow trench isolation regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to prevent p-type impurities from implanting into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, or the like in the implantation region, with a concentration ranging from approximately 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 After the photoresist is applied, it is removed by, for example, an acceptable ashing process. After the implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which avoids the use of implantation, but in-situ doping and implantation doping can also be used together. In Figure 5, a dummy dielectric layer 70 is formed on the fin 66 and nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, combinations thereof, or similar materials, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed above the dummy dielectric layer 70, and a masking layer 74 is formed above the dummy gate layer 72. The dummy gate layer 72 can be deposited above the dummy dielectric layer 70 and then planarized by, for example, CMP. The masking layer 74 can be deposited above the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from the group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), metal nitrides, metal silicates, metal oxides, and metals. The dummy gate layer 72 can be deposited using physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques using selected materials. The dummy gate layer 72 can be made of other materials that have high etch selectivity relative to the isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, or the like. In the embodiment shown in Figure 5, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. The dummy dielectric layer 70 shown only covers the fin 66 and nanostructure 55, but this is for illustrative purposes only. In some embodiments, the deposited dummy dielectric layer 70 may cover the shallow trench isolation region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the shallow trench isolation region 68. Figures 6A through 21C illustrate various additional steps in manufacturing the apparatus of the embodiment. Figures 7A, 8A, 9A, 10A, 11A, 12A, 13A, 13C, 14A, 14C, 15A, 16A, 19C, 20C, and 21C illustrate features in the n-type region 50N or p-type region 50P. In Figures 6A and 6B, the mask layer 74 (see Figure 5) can be patterned using acceptable optical lithography and etching techniques to form a mask 78. The pattern of the mask 78 is transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers individual channel regions of the nanostructure 55. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from adjacent dummy gates 76. The dummy gates 76 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the individual fins 66 and the nanostructures 55. In Figures 7A and 7B, a first spacer layer 80 and a second spacer layer 82 are formed above the structures shown in Figures 6A and 6B, respectively. The first spacer layer 80 and the second spacer layer 82 are then patterned as spacers for forming self-aligned source / drain regions. In Figures 7A and 7B, the first spacer layer 80 is formed on the top surface of the shallow trench isolation region 68, the top and side surfaces of the nanostructure 55 and the mask 78, and the side surfaces of the fin 66, the dummy gate 76, and the dummy gate dielectric 71. The second spacer layer 82 is deposited above the first spacer layer 80. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, and deposited using techniques such as thermal oxidation or by CVD, ALD, or the like. The second spacer layer 82 may be formed of a material with a different etching rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride or the like, and may be deposited by CVD, ALD or the like. After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, a lightly doped source / drain (LDD) region (not shown separately) can be implanted. In embodiments with different device types, similar to the implantation discussed in Figure 4 above, a mask such as a photoresist can be formed over the n-type region 50N to expose the p-type region 50P. An impurity of an appropriate type (e.g., p-type) can be implanted into the fins 66 and nanostructures 55 exposed in the p-type region 50P. The mask can be removed. Subsequently, a mask such as a photoresist can be formed over the p-type region 50P to expose the n-type region 50N. An impurity of an appropriate type (e.g., n-type) can be implanted into the fins 66 and nanostructures 55 exposed in the n-type region 50N. The mask can be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. The lightly doped source / drain region can have approximately 1 x 10n 15 atoms / cm 3 To approximately 1x10 19 atoms / cm 3 The concentration of impurities within a certain range. Annealing can be used to repair implant damage and revitalize implants. In Figures 8A and 8B, a first spacer layer 80 and a second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83, respectively. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 serve to control the growth of subsequently self-aligned source / drain regions, and protect the sidewalls of the fins 66 and / or nanostructures 55 during subsequent processes. Suitable etching processes can be used to etch the first spacer layer 80 and the second spacer layer 82, such as isotropic etching processes (e.g., wet etching processes), anisotropic etching processes (e.g., dry etching processes), or the like. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, such that the first spacer layer 80 can serve as an etch stop layer when the second spacer layer 82 is patterned. When the first spacer layer 80 is patterned, the second spacer layer 82 can serve as a mask. For example, an anisotropic etching process can be used to etch the second spacer layer 82, wherein the first spacer layer 80 serves as an etch stop layer. The remaining portion of the second spacer layer 82 forms a second spacer 83, as shown in Figure 8A. As shown in Figure 8A, the second spacer 83 acts as a mask to etch the exposed portion of the first spacer layer 80, thereby forming the first spacer 81. As shown in Figure 8A, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and the nanostructure 55. As shown in Figure 8B, in some embodiments, the second spacer layer 82 can be removed from above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. In some embodiments, a portion of the second spacer layer 82 may remain above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71 (e.g., the second spacer 83 may be formed above the first spacer 81 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71). It is worth noting that the above disclosure generally describes the process for forming spacers and LDD regions, but other processes and sequences can be used. For example, fewer or more spacers can be used, different step sequences can be used (e.g., the first spacer 81 can be patterned before depositing the second spacer layer 82), additional spacers and / or the like can be formed and removed. Furthermore, different structures and steps can be used to form n-type devices and p-type devices. In Figures 9A and 9B, a first groove 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region will subsequently be formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. As shown in Figure 9A, the top surface of the shallow trench isolation region 68 may be above the bottom surface of the first groove 86 (e.g., the top surface of the fin 66). As shown in Figure 9B, the first groove 86 extends through the nanostructure 55 and into the substrate 50. The portion of the first groove 86 extending into the substrate 50 may be V-shaped (as shown in Figure 9B), U-shaped, or similar. In some embodiments, the fin 66 may be etched such that the bottom surface of the first groove 86 is flush with or above the top surface of the shallow trench isolation region 68. The first groove 86 may be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process such as RIE, NBE, or the like. During the etching process used to form the first groove 86, the first spacer 81, the second spacer 83, the mask 78, and the shallow trench isolation region 68 shield portions of the fins 66, the nanostructures 55, and the substrate 50. A single etching process or multiple etching processes can be used to etch the layers of the nanostructures 55 and / or the fins 66. A timed etching process can be used to terminate the etching of the first groove 86 after it reaches the desired depth. The first groove 86 may have a depth D1 ranging from about 30 nm to about 70 nm below the top surface of the shallow trench isolation region 68, and a depth D2 ranging from about 5 nm to about 40 nm below the top surface of the fins 66. Forming the first groove 86 to depths D1 and D2 provides sufficient space to seal the air gap beneath the subsequently formed source / drain regions without extending into the substrate 50 and damaging it. In Figures 10A and 10B, a portion of the sidewalls of the nanostructure 55 (e.g., the first nanostructure 52) exposed by the first recess 86 and formed of the first semiconductor material is etched to form a sidewall recess 88 in the n-type region 50N, and a portion of the sidewalls of the nanostructure 55 (e.g., the second nanostructure 54) exposed by the first recess 86 and formed of the second semiconductor material is etched to form a sidewall recess 88 in the p-type region 50P. Although the sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall recess 88 are shown as straight in Figure 10B, the sidewalls can be concave or convex. Isotropic etching processes such as wet etching or similar methods can be used to etch the sidewalls. When etching the first nanostructure 52 using an etchant selective for the first semiconductor material, a mask (not shown separately) can be used to protect the p-type region 50P so that the second nanostructure 54 and the substrate 50 in the n-type region 50N remain unetched compared to the first nanostructure 52. Similarly, when etching the second nanostructure 54 using an etchant selective for the second semiconductor material, a mask (not shown separately) can be used to protect the n-type region 50N, so that the first nanostructure 52 and the substrate 50 in the p-type region 50P remain unetched compared to the second nanostructure 54. In embodiments where the first nanostructure 52 includes, for example, SiGe, and the second nanostructure 54 includes, for example, Si or SiC, tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH) can be used. The sidewalls of the first nanostructure 52 in the n-type region 50N can be etched using a dry etching process of 4OH or similar, and the sidewalls of the second nanostructure 54 in the p-type region 50P can be etched using a wet or dry etching process of hydrogen fluoride, other fluorine-based etchants or similar. As shown in Figure 10B, the sidewall of the first nanostructure 52 can be recessed from the sidewall of the second nanostructure 54 in the n-type region 50N by a distance D3, which is in the range of about 3 nm to about 15 nm. The sidewall of the second nanostructure 54 can be recessed from the sidewall of the first nanostructure 52 in the p-type region 50P by a distance D4, which is in the range of about 3 nm to about 15 nm. The recesses of the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P to the aforementioned distances can provide sufficient isolation between the subsequently formed source / drain regions and the gate structure without excessively reducing the volume of the subsequently formed gate structure. In Figures 11A to 11C, a multilayer spacer 90 is formed over the structure in Figures 10A and 10B. Figure 11C shows a detailed view of regions 97a and 97b of Figure 11B. As shown in Figures 11B and 11C, the multilayer spacer 90 may fill the sidewall recesses 88 (as shown in Figure 10B). The multilayer spacer 90 is then patterned to form internal spacers, thereby serving as isolation features between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced by the corresponding gate structures. Figures 11A and 11B illustrate embodiments of the multilayer spacer 90 including a first inner spacer layer 90A and a second inner spacer layer 90B. Figure 11C illustrates an embodiment of the multilayer spacer 90 including a first inner spacer layer 90A, a second inner spacer layer 90B, a third inner spacer layer 90C, and a fourth inner spacer layer 90D. The multilayer spacer 90 may include any number of inner spacer layers, and the number of inner spacer layers, the thickness of the inner spacer layers, and the materials selected for the inner spacer layers can be chosen to control the shape and effective dielectric constant of the subsequently formed inner spacers. The internal spacer layers of the multilayer spacer film 90 can be formed of dielectric materials, such as silicon carbonitride (SiCN), silicon nitride (SiN), silicon carbonitride oxynitride (SiCON), silicon oxyoxynitride (SiOC), silicon oxynitride (SiON), or similar materials. The internal spacer layers of the multilayer spacer film 90 can be deposited by conformal deposition processes such as ALD, CVD, or similar methods. In the embodiments shown in Figures 11A and 11B, the first inner spacer layer 90A can be deposited with a thickness T1 ranging from about 1 nm to about 15 nm, and the second inner spacer layer 90B can be deposited with a thickness T2 ranging from about 3 nm to about 8 nm. The ratio of the thickness T2 of the second inner spacer layer 90B to the thickness T1 of the first inner spacer layer 90A can be in the range of about 0.5 to about 3. The first inner spacer layer 90A and the second inner spacer layer 90B fill the sidewall recess 88. The first inner spacer layer 90A can be formed of a material having relatively high etch resistance and relatively high dielectric constant, and the second inner spacer layer 90B can be formed of a material having relatively low etch resistance and relatively low dielectric constant. The material of the second inner spacer layer 90B can also have high etch selectivity relative to the material of the first inner spacer layer 90A. Therefore, the second inner spacer layer 90B can be removed without significantly removing the first inner spacer layer 90A. In some embodiments, during subsequent etching processes, the ratio of the etching rate of the material of the second inner spacer layer 90B to the etching rate of the material of the first inner spacer layer 90A (e.g., the etch selectivity of the second inner spacer layer 90B over the first inner spacer layer 90A) may be greater than about 5. The material of the first inner spacer layer 90A may also have high etch selectivity relative to the material of the second inner spacer layer 90B, so that the first inner spacer layer 90A can be removed without significantly removing the second inner spacer layer 90B. The first internal spacer layer 90A may have a dielectric constant in the range of about 4 to about 7, and the second internal spacer layer 90B may have a dielectric constant in the range of about 3 to about 6. In some embodiments, the etch selectivity and dielectric constant of the first internal spacer layer 90A and the second internal spacer layer 90B may be determined based on the oxygen, carbon, and nitrogen concentrations of the first internal spacer layer 90A and the second internal spacer layer 90B. The first internal spacer layer 90A may be formed of a material having a high carbon concentration and / or a high nitrogen concentration, and the second internal spacer layer 90B may be formed of a material having a high oxygen concentration. The first internal spacer layer 90A may have an oxygen concentration in the range of about 0 atomic percent (at.%) to about 40 at.%, a nitrogen concentration in the range of about 5 at.% to about 50 at.%, and a carbon concentration in the range of about 2 at.% to about 40 at.%. The second internal spacer layer 90B may have an oxygen concentration ranging from about 10 at.% to about 60 at.%, a nitrogen concentration ranging from about 10 at.% to about 60 at.%, and a carbon concentration ranging from about 0 at.% to about 20 at.%. Forming the first internal spacer layer 90A with the aforementioned material and having the aforementioned thickness ensures that desired portions of the first internal spacer layer 90A remain intact after subsequent etching processes (such as etching processes for removing the second internal spacer layer 90B, the first nanostructure 52 in the n-type region 50N, and the second nanostructure 54 in the p-type region 50P), whereby these portions protect the subsequently formed source / drain regions from damage. This improves device performance and reduces device defects. Forming the second internal spacer layer 90B with the aforementioned material and having the aforementioned thickness reduces the effective dielectric constant of the subsequently formed internal spacers, including residual portions of the second internal spacer layer 90B, and facilitates easy removal of the second internal spacer layer 90B, which also helps reduce the effective dielectric constant of the subsequently formed internal spacers. This improves device performance. In some embodiments, the first internal spacer layer 90A and the second internal spacer layer 90B may have a thickness in the bottom portion of the first groove 86 that is greater than the thickness of the first internal spacer layer 90A and the second internal spacer layer 90B in the sidewall groove 88, the upper portion of the first groove 86, and on the surfaces of the first spacer 81, the second spacer 83, the shallow trench isolation region 68, and the mask 78. For example, the first internal spacer layer 90A may have a thickness T3 in the bottom portion of the first groove 86 ranging from about 1 nm to about 10 nm, while the second internal spacer layer 90B may have a thickness T4 in the bottom portion of the first groove 86 ranging from about 5 nm to about 30 nm. The ratio of the thickness T3 of the first internal spacer layer 90A in the bottom portion of the first groove 86 to the thickness T1 of the first internal spacer layer 90A along the side surface of the nanostructure 55 may be in the range of about 0.2 to about 1. The ratio of the thickness T4 of the second internal spacer layer 90B in the bottom portion of the first recess 86 to the thickness T2 of the second internal spacer layer 90B along the side surface of the nanostructure 55 can be in the range of about 0.2 to about 1. Providing the first internal spacer layer 90A and the second internal spacer layer 90B with relatively large thicknesses in the bottom portion of the first recess 86 ensures that even after etching the multilayer spacer film 90 to form the internal spacer layers, the first internal spacer layer 90A and the second internal spacer layer 90B still cover portions of the substrate 50 and fin 66 adjacent to the first recess 86. This prevents the subsequent formation of source / drain regions from epitaxial growth from the substrate 50 and fin 66, thereby forming air spacers between the source / drain regions and the substrate 50 and fin 66. Air spacers can reduce capacitance and improve isolation in the finished device, improve device performance (such as AC performance), and reduce device defects. In the embodiment shown in Figure 11C, the multilayer spacer film 90 includes four internal spacer layers (e.g., a first internal spacer layer 90A, a second internal spacer layer 90B, a third internal spacer layer 90C, and a fourth internal spacer layer 90D). The first internal spacer layer 90A may be deposited to a thickness ranging from about 0.5 nm to about 2 nm, and each of the second internal spacer layer 90B, the third internal spacer layer 90C, and the fourth internal spacer layer 90D may be deposited to a thickness ranging from about 0.5 nm to about 2 nm. The first internal spacer layer 90A, the second internal spacer layer 90B, the third internal spacer layer 90C, and the fourth internal spacer layer 90D fill the sidewall recesses 88. The first inner spacer layer 90A may include the material previously described for the first inner spacer layer 90A, and each of the second inner spacer layer 90B, the third inner spacer layer 90C, and the fourth inner spacer layer 90D may include the material previously described for the second inner spacer layer 90B. In some embodiments, the first inner spacer layer 90A, the second inner spacer layer 90B, the third inner spacer layer 90C, and the fourth inner spacer layer 90D may have decreasing etch resistance and decreasing dielectric constant. Each of the first inner spacer layer 90A, the second inner spacer layer 90B, the third inner spacer layer 90C, and the fourth inner spacer layer 90D may be formed of a material with good etch selectivity to adjacent inner spacer layers, thereby selectively etching each layer of the multilayer spacer film 90. The inner spacers are subsequently formed by patterning the multilayer spacer film 90, and providing a multilayer spacer film 90 with a larger number of inner spacer layers can be used to better control the shape and effective dielectric constant of the inner spacers. In the embodiment of Figure 11C, the multilayer spacer film 90 includes four inner spacer layers, wherein the first inner spacer layer 90A formed may have a thickness less than that of the fewer inner spacer layers, which can be used to reduce the effective dielectric constant of the subsequently formed inner spacer layers. In Figures 12A through 12F, a multilayer spacer film 90 is etched to form internal spacers 91. The process for etching the multilayer spacer film 90 can be a trimming process, and may be referred to as an internal spacer trimming process. Figure 12E illustrates a detailed view of regions 97a and 97b of Figure 12B. In the various embodiments shown in Figures 12A through 12F, the remaining portion of the first internal spacer layer 90A forms the first internal spacer portion 91A, the remaining portion of the second internal spacer layer 90B forms the second internal spacer portion 91B, the remaining portion of the third internal spacer layer 90C forms the third internal spacer portion 91C, and the remaining portion of the fourth internal spacer layer 90D forms the fourth internal spacer portion 91D. The multilayer spacer film 90 can be etched by one or more etching processes, such as dry etching, wet etching, combinations thereof, or the like. The etching process for etching the multilayer spacer film 90 can be isotropic. In embodiments using a wet etching process, sulfuric acid (H2O) can be used. 2SO 4) Phosphoric acid (H) 3PO 4) Dilute hydrofluoric acid, combinations thereof, or similar substances are used to etch the multilayer spacer 90. In embodiments using a dry etching process, the multilayer spacer 90 can be etched using a gas source (including trifluoromethane (CHF)). 3) With oxygen (O 2) mixture, carbon tetrafluoride (CF) 4) Mixtures with oxygen, nitrogen trifluoride (NF-12) 3) With fluoromethane (CH4) 3F) mixtures, combinations thereof or similar with trifluoromethane, oxygen ashing, oxygen plasma or similar. As previously mentioned, compared to the etching speed of the first internal spacer layer 90A, the etching process for etching the multilayer spacer film 90 can etch the second internal spacer layer 90B, the third internal spacer layer 90C, and the fourth internal spacer layer 90D much faster, for example, at least 5 times faster than the etching speed of the first internal spacer layer 90A. Therefore, the second internal spacer layer 90B, the third internal spacer layer 90C, and the fourth internal spacer layer 90D can be etched without significantly removing the material of the first internal spacer layer 90A. Subsequently, the first internal spacer layer 90A can be etched using a selective etching process without significantly removing the material of the second internal spacer layer 90B, the third internal spacer layer 90C, and the fourth internal spacer layer 90D. This allows for good control over the final shape of the internal spacers 91. In the embodiments shown in Figures 12A and 12B, a first internal spacer portion 91A is retained in the sidewall recess 88 (see Figures 10A and 10B) and the bottom portion of the first recess 86. The first internal spacer portion 91A covers portions of the sidewall recess 88 adjacent to the nanostructure 55, particularly covering portions of the sidewall recess 88 adjacent to the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P. In the n-type region 50N, the first internal spacer portion 91A extends continuously from the sidewall recess 88 adjacent to the first nanostructure 52A to the bottom portion of the first recess 86. The first internal spacer portion 91A and the second internal spacer portion 91B may be at least partially recessed from the side surface of the second nanostructure 54 in the n-type region 50N and the side surface of the first nanostructure 52 in the p-type region 50P. The second internal spacer portion 91B is retained in the sidewall groove 88 and the bottom portion of the first groove 86. The first internal spacer portion 91A and the second internal spacer portion 91B are removed from the side surface of the second nanostructure 54 in the n-type region 50N and the side surface of the first nanostructure 52 in the p-type region 50P; the side and top surfaces of the first spacer 81, the second spacer 83 and the shallow trench isolation region 68; and the top surface of the mask 78. Providing a first internal spacer portion 91A in the sidewall recess 88 prevents subsequent etching processes from damaging the source / drain regions subsequently formed in the first recess 86, such as etching processes for removing the first nanostructure 52 from the n-type region 50N and etching processes for removing the second nanostructure 54 from the p-type region 50P. This reduces device defects and improves device performance. The second internal spacer portion 91B retained in the sidewall recess 88 has a lower dielectric constant than the first internal spacer portion 91A, which reduces the effective dielectric constant of the internal spacer 91. The second internal spacer portion 91B and the first internal spacer portion 91A are recessed relative to the sidewalls of the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thus sealing the air gap near the internal spacer 91, further reducing the effective dielectric constant of the internal spacer 91. This improves the isolation between the subsequently formed source / drain regions and the subsequently formed gate structure, reduces capacitance, and improves device performance. The first internal spacer portion 91A and the second internal spacer portion 91B are removed from the side surfaces of the first nanostructure 52 and the second nanostructure 54, so that source / drain regions can subsequently be epitaxially grown from the first nanostructure 52 and the second nanostructure 54. The first internal spacer portion 91A and the second internal spacer portion 91B, which remain in the bottom portion of the first recess 86, cover the fin 66 and the substrate 50, thus preventing the epitaxial growth of the source / drain regions from the fin 66 and the substrate 50. This seals the air gap between the source / drain regions and the internal spacer 91 in the bottom portion of the first recess 86. The air gap and the second internal spacer portion 91B, which remain in the bottom portion of the first recess 86, provide improved isolation between the source / drain regions and the underlying fin 66 and the substrate 50, provide reduced capacitance, and improve device performance. In the embodiment shown in Figure 12C, the multilayer spacer film 90 is etched such that the first internal spacer portion 91A in the n-type region 50N is discontinuous between the sidewall recess 88 adjacent to the first nanostructure 52A and the bottom portion of the first recess 86. In both the n-type region 50N and the p-type region 50P, the first internal spacer portion 91A and the second internal spacer portion 91B expose portions of the substrate 50 and fins 66. The first internal spacer portion 91A and the second internal spacer portion 91B, remaining in the bottom portion of the first recess 86, cover portions of the fins 66 and substrate 50, thus blocking the epitaxial growth of the source / drain regions from the fins 66 and substrate 50. This seals the air gap between the source / drain regions and the internal spacer 91 in the bottom portion of the first recess 86. The air gap and the second internal spacer portion 91B remaining in the bottom portion of the first recess 86 provide improved isolation between the source / drain regions and the underlying fins 66 and substrate 50, provide reduced capacitance, and improve device performance. The exposed portions of fin 66 and substrate 50 allow for the formation of larger source / drain regions, which provides improved device performance. In the embodiment shown in Figure 12D, the side surfaces of the first internal spacer portion 91A and the second internal spacer portion 91B are aligned with the side surfaces of the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P. The side profile of the internal spacer 91 can be changed by adjusting the etching process that forms the internal spacer 91 (e.g., performing a shorter etching process). In the embodiment where the side surfaces of the first internal spacer portion 91A and the second internal spacer portion 91B are aligned with the side surfaces of the second nanostructure 54 and the first nanostructure 52, the first internal spacer portion 91A and the second internal spacer portion 91B can contact the subsequently formed source / drain regions without the need to form a horizontal air gap between the internal spacer 91 and the source / drain regions. In the embodiment shown in Figure 12E, the internal spacer 91 is formed by four internal spacer layers. For example, the first internal spacer portion 91A is formed by the first internal spacer layer 90A (refer to Figure 11C), the second internal spacer portion 91B is formed by the second internal spacer layer 90B, the third internal spacer portion 91C is formed by the third internal spacer layer 90C, and the fourth internal spacer portion 91D is formed by the fourth internal spacer layer 90D. Forming the internal spacer 91 from a larger number of internal spacer layers allows for the formation of layers with higher etch resistance (such as the first internal spacer layer 90A) at a smaller thickness. This can be used to reduce the effective dielectric constant of the internal spacer, reduce capacitance, and improve device performance. Providing a larger number of internal spacer layers offers greater flexibility in terms of the shape and effective dielectric constant of the internal spacer 91. The side surfaces of the first internal spacer portion 91A, the second internal spacer portion 91B, the third internal spacer portion 91C, and the fourth internal spacer portion 91D may be at least partially recessed from the side surface of the second nanostructure 54 in the n-type region 50N and the side surface of the first nanostructure 52 in the p-type region 50P, or may be aligned with the side surfaces of the second nanostructure 54 and the first nanostructure 52, similar to the embodiments illustrated and discussed in Figures 12A to 12D. The first internal spacer portion 91A, the second internal spacer portion 91B, the third internal spacer portion 91C, and the fourth internal spacer portion 91D may be continuous or discontinuous between the bottommost sidewall groove 88 and the bottom portion of the first groove 86, similar to the embodiments discussed above in Figures 12A to 12C. In the embodiment shown in Figure 12F, the second internal spacer layer 90B is completely removed, and the internal spacer 91 includes a first internal spacer portion 91A. Removing the second internal spacer layer 90B leaves additional space to horizontally seal an air gap in the sidewall recess 88 between the internal spacer 91 and the subsequently formed source / drain region, and vertically seals an air gap in the bottom portion of the first recess 86 between the internal spacer 91 and the source / drain region. The air gap has a lower dielectric constant than the second internal spacer layer 90B. Therefore, removing the second internal spacer layer 90B reduces the effective dielectric constant of the internal spacer 91, reduces capacitance, and improves device performance. In Figures 13A to 13I, an epitaxial source / drain region 92 is formed in a first groove 86. The epitaxial source / drain region 92 horizontally seals a side air gap 94 (also referred to as a side air spacer) between the epitaxial source / drain region 92 and an internal spacer 91 in a sidewall groove 88 (see Figure 10B), wherein the internal spacer 91 is adjacent to a first nanostructure 52 in an n-type region 50N and a second nanostructure 54 in a p-type region 50P. The epitaxial source / drain region 92 vertically seals a bottom air gap 96 (also referred to as a bottom air spacer) between the epitaxial source / drain region 92 and the internal spacers 91 on the substrate 50 and fins 66 in the bottom portion of the first groove 86 (see Figure 10B). In some embodiments, the epitaxial source / drain regions 92 can apply stress to the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. As shown in Figure 13B, the epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between adjacent pairs of epitaxial source / drain regions 92. In some embodiments, the first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and the internal spacer 91 and the side air gap 94 are used to separate the epitaxial source / drain regions 92 from the nanostructure 55 to an appropriate lateral distance so that the epitaxial source / drain regions 92 do not short-circuit the gate of the subsequently formed nanostructure field-effect transistor. The internal spacer 91 and the bottom air gap 96 are used to separate the epitaxial source / drain region 92 from the substrate 50 and fins 66 to an appropriate vertical distance in order to reduce leakage current to the substrate 50 and fins 66, reduce capacitance, and improve device performance. The epitaxial source / drain region 92 in the n-type region 50N (e.g., an NMOS region) can be formed by shielding the p-type region 50P (e.g., a PMOS region). Next, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 of the n-type region 50N. The epitaxial source / drain region 92 can include any acceptable material suitable for forming a source / drain region in an n-type nanostructure field-effect transistor. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can include a material on which tensile strain is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 92 may have a surface protruding from an individual upper surface of the nanostructure 55 and may have small facets. The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by shielding the n-type region 50N (e.g., an NMOS region). Next, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 of the p-type region 50P. The epitaxial source / drain region 92 can include any acceptable material suitable for forming a source / drain region in a p-type nanostructure field-effect transistor. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 can include a material on which compressive strain is applied to the first nanostructure 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain region 92 may also have a surface protruding from an individual upper surface of the nanostructure 55 and may have small crystal faces. The source / drain regions can be formed by implanting epitaxial source / drain regions 92, first nanostructures 52, second nanostructures 54, and / or substrates 50 using dopants, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have approximately 1 x 10⁻⁶ Ω·cm. 19 atoms / cm3 and approximately 1x10 21 Impurity concentrations between atoms / cm³. The n-type and / or p-type impurities in the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth. The epitaxial process of forming epitaxial source / drain regions 92 in the n-type region 50N and p-type region 50P results in small crystal faces on the upper surface of the epitaxial source / drain regions 92 extending laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these small crystal faces cause adjacent epitaxial source / drain regions 92 of the same nanostructure field-effect transistor to merge, as shown in Figure 13A. In some embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as shown in Figure 13C. In the embodiments shown in Figures 13A and 13C, a first spacer 81 may be formed to the top surface of the shallow trench isolation region 68 to block epitaxial growth. In some embodiments, the first spacer 81 may cover a portion of the sidewalls of the nanostructure 55 to further block epitaxial growth. In some embodiments, the spacer etching process used to form the first spacer 81 may be adjusted to remove the spacer material to allow the epitaxial growth region to extend to the surface of the shallow trench isolation region 68. The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer. Any number of semiconductor material layers may be used in the epitaxial source / drain region 92. Each of the first, second, and third semiconductor material layers may be formed of different semiconductor materials and may be doped to different doping concentrations. In some embodiments, the first semiconductor material layer may have a doping concentration smaller than that of the second semiconductor material layer and greater than that of the third semiconductor material layer. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, a first semiconductor material layer may be deposited, a second semiconductor material layer may be deposited over the first semiconductor material layer, and a third semiconductor material layer may be deposited over the second semiconductor material layer. Epitaxial source / drain regions 92 are epitaxially grown from the second nanostructure 54 in the n-type region 50N, the first nanostructure 52 in the p-type region 50P, and any exposed portions of the substrate 50 and fins 66 in the n-type region 50N and p-type region 50P. Internal spacers 91 in the sidewall recesses 88 prevent the epitaxial source / drain regions 92 from epitaxially growing from the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P, thereby horizontally forming and sealing a side gap 94 between the epitaxial source / drain regions 92 and the internal spacers 91 in the sidewall recesses 88. The side gaps 94 are vertically formed in the n-type region 50N between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50 and fins 66, and vertically formed in the p-type region 50P between adjacent first nanostructures 52. The first internal spacer portion 91A in the sidewall recess 88 protects the epitaxial source / drain region 92 from subsequent etching processes, such as etching processes used to remove the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P. This reduces device defects and improves device performance. The internal spacer 91 in the bottom portion of the first recess 86 prevents the epitaxial growth of the epitaxial source / drain region 92 from the substrate 50 and fins 66 in the bottom portion of the first recess 86, thereby vertically forming and sealing a bottom air gap 96 between the epitaxial source / drain region 92 and the internal spacer 91 in the bottom portion of the first recess 86. The dielectric constant of air is approximately 1, which is less than the dielectric constant of materials commonly used for internal spacers. Therefore, the side air gap 94 reduces the effective dielectric constant between the epitaxial source / drain region 92 and the subsequently formed gate structure, reduces capacitance, and improves device performance. In addition, the internal spacers 91 and the bottom air gap 96 have low dielectric constants and provide isolation between the epitaxial source / drain regions 92 and the substrate 50 and fins 66, which reduces leakage current to the substrate 50 and fins 66, reduces capacitance, and improves device performance (such as AC performance). Figures 13A to 13C illustrate embodiments of Figures 12A and 12B, wherein a first internal spacer portion 91A, a second internal spacer portion 91B, and a side air gap 94 are formed in a sidewall groove 88, and the first internal spacer portion 91A, the second internal spacer portion 91B, and a bottom air gap 96 are formed in the bottom portion of the first groove 86, with the first internal spacer portion 91A continuous between the sidewall groove 88 and the bottom portion of the first groove 86 in the n-type region 50N. As shown in Figure 13B, the epitaxial source / drain region 92 can be separated from the first internal spacer portion 91A and the second internal spacer portion 91B in the bottom portion of the first groove 86, such that the side air gap 94 is continuous with the bottom air gap 96. Figure 13D illustrates an embodiment of Figures 12A and 12B, wherein the epitaxial source / drain region 92 is formed to a greater depth and contacts the first internal spacer portion 91A in the bottom portion of the first groove 86. The formation time of the epitaxial source / drain region 92 may be longer than that shown in Figures 13A to 13C. The epitaxial source / drain region 92 formed in the bottom portion of the first groove 86, which contacts the first internal spacer portion 91A, separates the side air gap 94 from the bottom air gap 96. Figure 13E illustrates an embodiment of Figure 12C, wherein a first internal spacer portion 91A, a second internal spacer portion 91B, and a side air gap 94 are formed in a sidewall groove 88, and the first internal spacer portion 91A, the second internal spacer portion 91B, and a bottom air gap 96 are formed in a bottom portion of the first groove 86, and the first internal spacer portion 91A is discontinuous between the sidewall groove 88 and the bottom portion of the first groove 86. As shown in Figure 13E, the epitaxial source / drain region 92 may be separated from the first internal spacer portion 91A and the second internal spacer portion 91B in the bottom portion of the first groove 86, such that the side air gap 94 is continuous with the bottom air gap 96. Figure 13F illustrates an embodiment of Figure 12C, wherein the epitaxial source / drain region 92 is formed to a greater depth and contacts the first internal spacer portion 91A and / or the second internal spacer portion 91B in the bottom portion of the first groove 86. The formation time of the epitaxial source / drain region 92 may be longer than that shown in Figure 13E. The epitaxial source / drain region 92 formed in the bottom portion of the first groove 86, which contacts the first internal spacer portion 91A and / or the second internal spacer portion 91B, can separate the side air gap 94 from the bottom air gap 96. Figure 13G illustrates an embodiment of Figure 12D, wherein the first internal spacer portion 91A and the second internal spacer portion 91B have side surfaces aligned with the nanostructure 55, and the first internal spacer portion 91A, the second internal spacer portion 91B, and the bottom air gap 96 are formed in the bottom portion of the first recess 86. As shown in Figure 13G, the bottom air gap 96 in the n-type region 50N may extend adjacent to a portion of the internal spacer 91 adjacent to the first nanostructure 52A. In some embodiments, the epitaxial source / drain region 92 in the n-type region 50N may be formed to a greater depth, such that the epitaxial source / drain region 92 physically contacts the internal spacer 91 adjacent to the first nanostructure 52A. In the embodiment of Figure 13G, the side air gap 94 is omitted, and only the bottom air gap 96 is included. Figure 13H illustrates an embodiment of Figure 12E, wherein the internal spacer 91 includes a first internal spacer portion 91A, a second internal spacer portion 91B, a third internal spacer portion 91C, and a fourth internal spacer portion 91D. As shown in Figure 13H, the first internal spacer portion 91A is physically in contact with the epitaxial source / drain region 92, and the second internal spacer portion 91B, the third internal spacer portion 91C, and the fourth internal spacer portion 91D are separable from the epitaxial source / drain region 92 by a side air gap 94. However, in some embodiments, any one of the first internal spacer portion 91A, the second internal spacer portion 91B, the third internal spacer portion 91C, and the fourth internal spacer portion 91D may be physically in contact with or separate from the epitaxial source / drain region 92. Figure 13I illustrates an embodiment of Figure 12F, wherein the second internal spacer layer 90B is removed, a first internal spacer portion 91A and a side gap 94 are formed in a sidewall recess 88, and a first internal spacer portion 91A and a bottom gap 96 are formed in a bottom portion of a first recess 86, with the first internal spacer portion 91A continuous between the sidewall recess 88 and the bottom portion of the first recess 86 in the n-type region 50N. As shown in Figure 13I, the epitaxial source / drain region 92 can be separated from the first internal spacer portion 91A and the second internal spacer portion 91B in the bottom portion of the first recess 86, such that the side gap 94 and the bottom gap 96 are continuous. In some embodiments, the epitaxial source / drain region 92 is formed to a greater depth and contacts the first internal spacer portion 91A in the bottom portion of the first recess 86. The epitaxial source / drain region 92, which contacts the first internal spacer portion 91A, is formed in the bottom portion of the first recess 86, separating the side gap 94 from the bottom gap 96. Removing the second internal spacer layer 90B will enlarge the side air gap 94 and the bottom air gap 96, further reducing the effective dielectric constant, reducing capacitance, and improving device performance. In Figures 14A through 14C, the first interlayer dielectric (ILD) 102 is deposited over the structures shown in Figures 6A, 13B, and 13A, respectively (the fabrication process in Figures 7A through 13I does not alter the cross-section shown in Figure 6A). The first interlayer dielectric 102 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 100 is disposed between the first interlayer dielectric 102 and the epitaxial source / drain region 92, the mask 78, and the first spacer 81. The contact etch stop layer 100 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and the contact etch stop layer 100 has an etch rate different from that of the overlying first interlayer dielectric 102. In Figures 15A and 15B, a planarization process such as CMP can be performed to make the top surfaces of the first interlayer dielectric 102 and the contact etch stop layer 100 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove a portion of the mask 78 on the dummy gate 76 and the first spacer 81 along the sidewall of the mask 78. After the planarization process, within process tolerances, the top surfaces of the dummy gate 76, the first spacer 81, the first interlayer dielectric 102, and the contact etch stop layer 100 are flush with each other. Therefore, the first interlayer dielectric 102 and the contact etch stop layer 100 expose the top surface of the dummy gate 76. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surfaces of the first interlayer dielectric 102 and the contact etch stop layer 100 flush with the top surfaces of the mask 78 and the first spacer 81. In Figures 16A and 16B, the dummy gate 76 and mask 78 (if present) are removed in one or more etching steps to form a recess 98. A portion of the dummy gate dielectric 71 in the recess 98 is also removed. In some embodiments, the dummy gate 76 and dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (multiple) reactive gases that selectively etch the dummy gate 76 at a faster rate than etching the first interlayer dielectric 102, the contact etch stop layer 100, or the first spacer 81. Each recess 98 exposes and / or covers portions of nanostructures 55, which serve as channel regions in the subsequently completed nanostructured field-effect transistor. The portions of the nanostructures 55 serving as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 can be used as an etch stop layer when the dummy gate 76 is etched. Next, the dummy gate dielectric 71 can be removed after the dummy gate 76 is removed. In Figures 17A and 17B, the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed, extending the groove 98. The first nanostructure 52 can be removed by forming a mask (not shown separately) over the p-type region 50P and performing an isotropic etching process (such as wet etching or the like) using an etchant selective for the material of the first nanostructure 52. The first internal spacer portion 91A, the second nanostructure 54, the substrate 50, the fin 66, the shallow trench isolation region 68, the first interlayer dielectric 102, the contact etch stop layer 100, and the first spacer 81 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructures 54A to 54C comprise, for example, Si or SiC, tetramethylammonium hydroxide, ammonium hydroxide, or the like can be used to remove the first nanostructure 52 in the n-type region 50N. Removing the second nanostructure 54 in the p-type region 50P can be achieved by forming a mask (not shown separately) over the n-type region 50N and performing an isotropic etching process (such as wet etching or the like) using an etchant selective for the material of the second nanostructure 54. The first internal spacer portion 91A, the first nanostructure 52, the substrate 50, the fin 66, the shallow trench isolation region 68, the first interlayer dielectric 102, the contact etch stop layer 100, and the first spacer 81 remain relatively unetched compared to the second nanostructure 54. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, hydrogen fluoride, another fluorine-based etchant, or the like can be used to remove the second nanostructure 54 in the p-type region 50P. In other embodiments, channel regions in both the n-type region 50N and the p-type region 50P can be formed simultaneously by, for example, removing the first nanostructure 52 from either the n-type region 50N or the p-type region 50P, or by removing the second nanostructure 54 from either the n-type region 50N or the p-type region 50P. In such embodiments, the channel regions of the n-type nanostructure field-effect transistor and the p-type nanostructure field-effect transistor may have the same material composition, such as silicon, silicon germanium, or the like. Figures 22A through 22C illustrate structures resulting from such embodiments, wherein the channel regions in both the p-type region 50P and the n-type region 50N are provided by the second nanostructure 54, and include, for example, silicon. In Figures 18A and 18B, a gate dielectric layer 104 and a gate electrode 106 are formed to replace the gate. The gate dielectric layer 104 is conformally deposited in the trench 98. In the n-type region 50N, the gate dielectric layer 104 may be formed on the top surface of the shallow trench isolation region 68, the top and side surfaces of the fin 66, the top, side, and bottom surfaces of the second nanostructure 54, and the side surfaces of the internal spacer 91 and the first spacer 81. In the p-type region 50P, the gate dielectric layer 104 may be formed on the top surface of the shallow trench isolation region 68, the side surfaces of the fin 66, the top, side, and bottom surfaces of the first nanostructure 52, and the side surfaces of the internal spacer 91 and the first spacer 81. The gate dielectric layer 104 may be deposited on the top surface of the upper internal spacer 91 and may have a stepped structure. The gate dielectric layer 104 can be deposited on the top surface of the first interlayer dielectric 102, the contact etch stop layer 100 and the first spacer 81. In some embodiments, the gate dielectric layer 104 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, the gate dielectric layer 104 may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 104 includes a high dielectric constant dielectric material, and in these embodiments, the gate dielectric layer 104 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 104 may be the same or different in the n-type region 50N and the p-type region 50P. The gate dielectric layer 104 may be formed by methods including molecular-beam deposition (MBD), ALD, PECVD, or the like. Gate electrode 106 is deposited above gate dielectric layer 104 and fills the remaining portion of groove 98. Gate electrode 106 may include metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode 106 is shown in Figures 18A and 18B, gate electrode 106 may include any number of inner liner layers, any number of work function tuning layers, and filler materials. Any combination of layers constituting gate electrode 106 may be deposited between adjacent second nanostructures 54 and between second nanostructure 54A and fin 66 in n-type region 50N, and between adjacent first nanostructures 52 in p-type region 50P. Gate dielectric layers 104 in both the n-type region 50N and the p-type region 50P can be formed simultaneously, such that the gate dielectric layers 104 in each region are formed of the same material, and gate electrodes 106 can be formed simultaneously, such that the gate electrodes 106 in each region are formed of the same material. In some embodiments, the gate dielectric layers 104 in each region can be formed by different processes, such that the gate dielectric layers 104 can be made of different materials and / or have different numbers of layers, and / or the gate electrodes 106 in each region can be formed by different processes, such that the gate electrodes 106 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate areas. After filling the groove 98, a planarization process such as CMP can be performed to remove excess material from the gate dielectric layer 104 and the gate electrode 106, which lies above the top surface of the first interlayer dielectric 102, the contact etch stop layer 100, and the first spacer 81. Thus, the remaining material of the gate electrode 106 and the gate dielectric layer 104 forms the replacement gate structure of the resulting nanostructured field-effect transistor. The gate electrode 106 and the gate dielectric layer 104 can be collectively referred to as the "gate structure". In Figures 19A to 19C, the recessed gate structures (including gate dielectric layer 104 and corresponding overlying gate electrodes 106) are formed such that the grooves are formed directly above each gate structure and between opposing portions of the first spacer 81. A gate cap 108, comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or the like), is filled into the grooves, followed by a planarization process to remove excess dielectric material extending over the first interlayer dielectric 102, the contact etch stop layer 100, and the first spacer 81. The subsequently formed gate contacts (such as gate contacts 118, see Figures 21A and 21B below) penetrate the gate cap 108 to contact the top surface of the recessed gate electrodes 106. Further, in Figures 19A to 19C, a second interlayer dielectric 110 is deposited over the first interlayer dielectric 102, the contact etch stop layer 100, the first spacer 81, and the gate cap 108. In some embodiments, the second interlayer dielectric 110 is a flowable film formed by FCVD. In some embodiments, the second interlayer dielectric 110 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable method such as CVD, PECVD, or the like. In Figures 20A to 20C, the second interlayer dielectric 110, the first interlayer dielectric 102, the contact etch stop layer 100, and the gate cap 108 are etched to form a groove 112, thereby exposing the surface of the epitaxial source / drain region 92 and / or the gate electrode 106. The groove 112 can be formed by etching using anisotropic etching processes such as RIE, NBE, or similar methods. In some embodiments, a first etching process can be used to etch the groove 112 through the second interlayer dielectric 110 and the first interlayer dielectric 102, a second etching process can be used to etch the groove 112 through the gate cap 108, and a third etching process can be used to etch the groove 112 through the contact etch stop layer 100. A mask, such as a photoresist, can be formed and patterned over the second interlayer dielectric 110 to mask portions of the second interlayer dielectric 110 in the first and second etching processes. In some embodiments, the etching process may over-etch such that the groove 112 extends into the epitaxial source / drain region 92 and / or gate electrode 106. The bottom surface of the groove 112 may be flush with the top surface of the epitaxial source / drain region 92 and / or gate electrode 106 (e.g., on the same horizontal plane or at the same distance from the substrate 50), or lower than the top surface of the epitaxial source / drain region 92 and / or gate electrode 106 (e.g., closer to the substrate 50). Although Figure 20B illustrates the groove 112 exposing the epitaxial source / drain region 92 and gate electrode 106 with the same cross-section, in some embodiments, the epitaxial source / drain region 92 and gate electrode 106 may be exposed with different cross-sections, thereby reducing the risk of short circuits in subsequently formed contacts. After the groove 112 is formed, a silicide region 114 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 114 is formed by depositing a metal (not shown separately) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium, or the like) of the epitaxial source / drain region 92 to form a silicide or germanide region. The metal may include nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal is deposited over the exposed portion of the epitaxial source / drain region 92, followed by a thermal annealing process to form the silicide region 114. Unreacted portions of the deposited metal are removed by, for example, an etching process. Although the silicate region 114 is referred to as a silicate region, the silicate region 114 may also be a germanide region or a germanide silicate region (e.g., a region including both silicate and germanide). In some embodiments, the silicate region 114 includes titanium silicate (TiSi) having a thickness in the range of about 2 nm to about 10 nm. In Figures 21A through 21C, source / drain contacts 116 and gate contacts 118 (each also referred to as contact plugs) are formed in recesses 112. Each source / drain contact 116 and gate contact 118 may include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, each source / drain contact 116 and gate contact 118 includes a barrier layer and a conductive material. Source / drain contacts 116 and gate contacts 118 are electrically coupled to underlying conductive features (e.g., gate electrode 106 and silicate region 114 in the illustrated embodiment). Gate contact 118 is electrically coupled to gate electrode 106. Source / drain contact 116 is electrically coupled to epitaxial source / drain region 92 via silicate region 114. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may include copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP can be performed to remove excess material from the surface of the second interlayer dielectric 110 for the source / drain contacts 116 and the gate contacts 118. According to some alternative embodiments, Figures 22A to 22C illustrate cross-sectional views of the device. In Figures 22A to 22C, similar reference numerals represent similar elements formed by processes similar to those in Figures 21A to 21C. In the embodiments of Figures 22A to 22C, the channel regions in the n-type region 50N and the p-type region 50P comprise the same material. For example, a second nanostructure 54 comprising silicon serves as the channel region for the p-type nanostructure field-effect transistor in the p-type region 50P and the n-type nanostructure field-effect transistor in the n-type region 50N. For example, the structures shown in Figures 22A to 22C can be formed by simultaneously removing the first nanostructure 52 from both the p-type region 50P and the n-type region 50N. A gate dielectric layer 104 and a gate electrode 106P (e.g., a gate electrode suitable for a p-type nanostructure field-effect transistor) are deposited around the second nanostructure 54 in the p-type region 50P, and a gate dielectric layer 104 and a gate electrode 106N (e.g., a gate electrode suitable for an n-type nanostructure field-effect transistor) are deposited around the second nanostructure 54 in the n-type region 50N. As described above, the materials of the epitaxial source / drain regions 92 can be different in the n-type region 50N and the p-type region 50P. These embodiments offer advantages. For example, including a side air gap 94 reduces the effective dielectric constant between the epitaxial source / drain region 92 and the gate structure (including the gate dielectric layer 104 and the gate electrode 106), reduces capacitance, and improves device performance. Including an internal spacer 91 and a bottom air gap 96 between the epitaxial source / drain region 92 and the substrate 50 improves the isolation of the epitaxial source / drain region 92, reduces leakage current, reduces capacitance, and improves device performance. Both the bottom air gap 96 and the side air gap 94 contribute to improved AC performance. According to one embodiment of this disclosure, a semiconductor device includes a semiconductor substrate, a first channel region on the semiconductor substrate, a gate structure on the first channel region, a first source / drain region adjacent to the gate structure and the first channel region, a first internal spacer layer located between the first source / drain region and the semiconductor substrate in a first direction perpendicular to the main surface of the semiconductor substrate, and a first air gap located between the first source / drain region and the first internal spacer layer in the first direction. In one embodiment, the semiconductor device further includes a second internal spacer layer located between the gate structure and the first source / drain region in a second direction parallel to the main surface of the semiconductor substrate, and a second air gap located between the first source / drain region and the second internal spacer layer in the second direction. In one embodiment, the first air gap includes air in physical contact with the surfaces of the first internal spacer layer and the first source / drain region. In one embodiment, the semiconductor device further includes a second internal spacer layer located between the first internal spacer layer and the first air gap in the first direction, the first internal spacer layer comprising a first material, and the second internal spacer layer comprising a second material different from the first material. In one embodiment, the first source / drain region is in physical contact with the semiconductor substrate. In one embodiment, the first internal spacer layer is in physical contact with the gate structure. In one embodiment, the first air gap is located between the first source / drain region and the gate structure in a second direction parallel to the main surface of the semiconductor substrate. According to another embodiment of this disclosure, a semiconductor device includes a semiconductor substrate, a plurality of channel regions on the semiconductor substrate and in a first direction perpendicular to the main surface of the semiconductor substrate, a gate structure on the plurality of channel regions, a source / drain region adjacent to the gate structure, and a first spacer structure between the source / drain region and the semiconductor substrate. The first spacer structure includes a first spacer layer having a first material, a second spacer layer on the first spacer layer having a second material different from the first material, and a bottom air gap between the second spacer layer and the source / drain region. In one embodiment, the semiconductor device further includes an internal spacer structure between the source / drain region and the gate structure. The internal spacer structure includes a first internal spacer layer having a first material, a second internal spacer layer on the first internal spacer layer having a second material, and a side air gap between the second internal spacer layer and the source / drain region. In one embodiment, the first spacer layer and the first internal spacer layer comprise continuous materials. In one embodiment, the semiconductor device further includes an internal spacer structure between the source / drain region and the gate structure. The internal spacer structure includes a first internal spacer layer having a first material and a second internal spacer layer having a second material on the first internal spacer layer. The side surfaces of the first and second internal spacer layers are aligned with the side surfaces of a plurality of channel regions. In one embodiment, the source / drain region is physically in contact with the first spacer layer. In one embodiment, the source / drain region is physically in contact with the semiconductor substrate. In one embodiment, the bottom air gap is physically in contact with the semiconductor substrate. According to another embodiment of this disclosure, a method includes the following steps: forming a gate structure on a first channel region; forming a first recess in a substrate adjacent to the gate structure; depositing a first spacer layer in the first recess; depositing a second spacer layer on the first spacer layer in the first recess; etching the first spacer layer and the second spacer layer using a first etching process to form a first internal spacer portion and a second internal spacer portion, respectively, in the first recess; forming a source / drain region in the first recess, the source / drain region and the first internal spacer portion sealing the bottom air gap. In one embodiment, the first etching process etches the second spacer layer at a rate at least five times greater than the first etching process etches the first spacer layer. In one embodiment, the first spacer layer comprises a first material, and the second spacer layer comprises a second material different from the first material. In one embodiment, the method further includes forming a multilayer stack on a substrate, the multilayer stack including alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material, a gate structure formed on the multilayer stack, a first groove passing through the multilayer stack and forming a plurality of nanostructures from the multilayer stack, and the method includes etching the sidewalls of the first semiconductor material to form a sidewall groove, depositing a first spacer layer and a second spacer layer in the sidewall groove and filling the sidewall groove, and etching the first spacer layer and the second spacer layer using a first etching process to form a third internal spacer portion and a fourth internal spacer portion in the sidewall groove, respectively. In one embodiment, the first internal spacer portion and the third internal spacer portion are continuous. In one embodiment, forming a source / drain region will form a side air gap in the sidewall groove closed by the source / drain region and the third internal spacer portion. The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure. 20: Separator 50: Substrate 50N: n-type region 50P: p-type region 51: First semiconductor layer 51A, 51B, 51C: First semiconductor layer 52: First nanostructure 52A, 52B, 52C: First nanostructure 53: Second semiconductor layer 53A, 53B, 53C: Second semiconductor layer 54: Second nanostructure 54A, 54B, 54C: Second nanostructure 55: Nanostructure 64: Multilayer stack 66: Fin 68: Isolation region / shallow trench isolation region 70: Dummy dielectric layer 71: Dummy gate dielectric 72: Dummy gate layer 74: Mask layer 76: Dummy gate 78: Mask 80: First spacer layer 81: First spacer 82: Second spacer layer 83: Second spacer 86: First groove 88: Sidewall groove 90: Multilayer spacer film 90A: First inner 90B: Second internal spacer layer; 90C: Third internal spacer layer; 90D: Fourth internal spacer layer; 91: Internal spacer; 91A: First internal spacer portion; 91B: Second internal spacer portion; 91C: Third internal spacer portion; 91D: Fourth internal spacer portion; 92: Epitaxial source / drain region; 94: Side air gap; 96: Bottom air gap; 97a, 97b: Region; 98: Groove; 100: Contact etch stop layer; 102: First interlayer dielectric; 104: Gate dielectric layer; 106: Gate electrode; 106N: Gate electrode; 106P: Gate electrode; 108: Gate cap; 110: Second interlayer dielectric; 112: Groove; 114: Silicone region; 116: Source / drain contact; 118: Gate contact; D1, D2: Depth; D3, D4: Distance; T1, T2, T3, T4: Thickness. The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 illustrates a three-dimensional view of a nanostructured field-effect transistor (FET) according to some embodiments. Figures 2, 3, 4, 5, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 11C, 12A, 12B, 12C, 12D, 12E, 12F, 13A, 13B, 13C, 13D, 13E, 13F, 13G, 13H, 1 Figures 3I, 14A, 14B, 14C, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 19C, 20A, 20B, 20C, 21A, 21B, 21C, 22A, 22B, and 22C are cross-sectional views of intermediate stages in the fabrication of nanostructured field-effect transistors according to some embodiments. Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None. 50:Substrate 50N: n-type region 50P: p-type area 54: Second nanostructure 54A, 54B, 54C: Second nanostructure 66: Fins 81: First spacer 91: Internal spacers 91A: First internal partition 91B: Second internal partition section 92: Epitaxial Source / Drain Region 94: Side air gap 96: Bottom air gap 100: Contact Etching Stop Layer 102: First interlayer dielectric 104: Gate dielectric layer 106N: Gate electrode 106P: Gate electrode 108: Gate Cap 110: Interlayer dielectric of the second layer 114: Silicone region 116: Source / Drain Contact 118: Gate Contact

Claims

1. A semiconductor device, comprising: A semiconductor substrate; A first channel region is located on the semiconductor substrate; A gate structure is located in the first channel region; A first source / drain region is adjacent to the gate structure and the first channel region; a first internal spacing portion is located between the first source / drain region and the semiconductor substrate in a first direction perpendicular to a main surface of the semiconductor substrate. A second internal spacer portion is located on the first internal spacer portion in the first direction; a bottom air gap is located in the first direction and is closed by the first source / drain region and the second internal spacer portion; a third internal spacer portion is located between the gate structure and the first source / drain region in a second direction parallel to the main surface of the semiconductor substrate; a side air gap is located between the first source / drain region and the third internal spacer portion in the second direction; and a fourth internal spacer portion is located between the third internal spacer layer and the side air gap in the second direction, and the side air gap is closed by the first source / drain region and the fourth internal spacer portion, wherein the material of the fourth internal spacer portion is different from the material of the third internal spacer portion.

2. The semiconductor device as claimed in claim 1, wherein the bottom air gap includes air in physical contact with a plurality of surfaces of the second internal spacer portion and the first source / drain region.

3. The semiconductor device as claimed in claim 1, wherein the first internal spacer portion includes a first material, and wherein the second internal spacer portion includes a second material different from the first material.

4. The semiconductor device as claimed in claim 1, wherein the second internal spacer portion is in physical contact with the gate structure.

5. The semiconductor device as claimed in claim 1, wherein the bottom air gap is located between the first source / drain region and the gate structure in the second direction parallel to the main surface of the semiconductor substrate.

6. A semiconductor device, comprising: A semiconductor substrate; A plurality of channel regions located on the semiconductor substrate and in a first direction perpendicular to a main surface of the semiconductor substrate; a gate structure located on the channel regions; a source / drain region adjacent to the gate structure; A first spacer structure is located between the source / drain region and the semiconductor substrate, wherein the first spacer structure includes: a first spacer portion including a first material; a second spacer portion located on the first spacer portion, wherein the second spacer portion includes a second material different from the first material; and a bottom air gap located between the second spacer portion and the source / drain region, and the bottom air gap is closed by the source / drain region and the second spacer portion; and an internal spacer structure is located between the source / drain region and the gate structure, wherein the internal spacer structure includes: a third internal spacer portion including the first material; a fourth internal spacer portion located on the third internal spacer portion, wherein the fourth internal spacer portion includes the second material; and a side air gap located between the fourth internal spacer portion and the source / drain region, and the side air gap is closed by the source / drain region and the fourth internal spacer portion.

7. The semiconductor device as claimed in claim 6, wherein the first spacer portion and the third internal spacer portion comprise a continuous material.

8. The semiconductor device as claimed in claim 6, wherein the plurality of side surfaces of the third internal spacer portion and the fourth internal spacer portion are aligned with the plurality of side surfaces of the channel regions.

9. A method for manufacturing a semiconductor device, comprising: A multilayer stack is formed on a substrate, the multilayer stack including alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material; a gate structure is formed on a first channel region of the multilayer stack; a first groove is formed through the multilayer stack; a sidewall of the first semiconductor material is etched to form a sidewall groove; a first spacer layer is deposited in the first groove and the sidewall groove; a second spacer layer is deposited on the first spacer layer in the first groove and the sidewall groove, wherein the material of the second spacer layer is different from the material of the first spacer layer; the first spacer layer and the second spacer layer are etched using a first etching process to form a first internal spacer portion and a second internal spacer portion on the first internal spacer portion in the first groove, and a third internal spacer portion and a fourth internal spacer portion on the third internal spacer portion in the sidewall groove; and a source / drain region is formed in the first groove, wherein a bottom air gap is closed by the source / drain region and the second internal spacer portion, and a side air gap is closed by the source / drain region and the fourth internal spacer portion.

10. A method of manufacturing a semiconductor device as claimed in claim 9, wherein the first internal spacing portion and the third internal spacing portion are continuous.

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