Inspection methods and manufacturing methods of camera elements

Abstract

The inspection method of the present invention includes: a process for preparing a device, the aforementioned device comprising: a plurality of pixel electrodes (11); a counter electrode (13) disposed opposite to the plurality of pixel electrodes (11); a photoelectric conversion layer (12) disposed between the plurality of pixel electrodes (11) and the counter electrode (13); a test electrode sandwiching the photoelectric conversion layer (12) and the counter electrode (13) and disposed between two adjacent pixel electrodes among the plurality of pixel electrodes (11); a first electrode pad electrically connected to the counter electrode (13) and exposed to the outside; and a second electrode pad electrically connected to the test electrode and exposed to the outside; and a process for measuring current, wherein a voltage is applied between the first electrode pad and the second electrode pad, and the current flowing between the first electrode pad and the second electrode pad is measured.

Description

Technical Field

[0001] The present disclosure relates to an inspection method and a method for manufacturing an imaging element. Prior Art

[0002] Background Art In recent years, imaging devices have become known that have a photoelectric conversion layer stacked above a CMOS (Complementary Metal Oxide Semiconductor) readout circuit. In such imaging devices, the quality of the photoelectric conversion layer affects the device's characteristics. During the manufacturing process of imaging devices, inspecting the quality of the photoelectric conversion layer is crucial to avoid defective products during assembly and processing after inspection.

[0003] Patent Document 1 discloses a method for inspecting a photoelectric conversion layer using a test photoelectric conversion unit disposed outside the photoelectric conversion unit.

[0004] Patent Document 2 discloses a method for inspecting a photoelectric conversion layer using a test pattern formed outside an imaging region. Prior art literature Patent Literature

[0005] [Patent Document 1] Japanese Patent No. 4783868 [Patent Document 2] Japanese Patent No. 5806635 Summary of the Invention

[0006] Summary of the Invention Problems that the invention aims to solve The present disclosure provides an inspection method capable of inspecting a photoelectric conversion layer with high precision and suppressing a decrease in the yield of an imaging element, and a method for manufacturing an imaging element using the inspection method. Means used to solve problems

[0007] An inspection method according to one aspect of the present disclosure includes: a process for preparing a device, wherein the device comprises: a plurality of pixel electrodes; a counter electrode disposed opposite the plurality of pixel electrodes; a photoelectric conversion layer disposed between the plurality of pixel electrodes and the counter electrode; a test electrode disposed opposite the counter electrode with the photoelectric conversion layer sandwiched therebetween and disposed between two adjacent pixel electrodes among the plurality of pixel electrodes; a first electrode pad electrically connected to the counter electrode and exposed to the outside; and a second electrode pad electrically connected to the test electrode and exposed to the outside; and a process for measuring current, applying a voltage between the first electrode pad and the second electrode pad, and measuring the current flowing between the first electrode pad and the second electrode pad.

[0008] One aspect of the present disclosure includes a method for manufacturing an imaging device, comprising: a plurality of pixel electrodes; a counter electrode disposed opposite the plurality of pixel electrodes; a photoelectric conversion layer disposed between the plurality of pixel electrodes and the counter electrode; a test electrode disposed opposite the counter electrode with the photoelectric conversion layer sandwiched therebetween and between two adjacent pixel electrodes; a first electrode pad electrically connected to the counter electrode and exposed to the outside; and a second electrode pad electrically connected to the test electrode and exposed to the outside; and a process for inspecting the device using the inspection method. The inspection method further includes a process for determining whether the photoelectric conversion layer is good or bad based on the current. In the manufacturing method, if the inspection determines that the photoelectric conversion layer is good, the manufacturing process of the imaging device including the device is continued; if the inspection determines that the photoelectric conversion layer is bad, the manufacturing process of the imaging device is not continued. Effects of the Invention

[0009] According to one aspect of the present disclosure, there can be provided an inspection method capable of inspecting a photoelectric conversion layer with high precision and suppressing a decrease in the yield of an imaging element, and a method for manufacturing an imaging element using the inspection method. Simple diagram description

[0010] FIG. 1 is a diagram for explaining the arrangement of an inspection structure in a wafer. FIG2 is a cross-sectional view showing a wafer according to an embodiment. FIG3 is a plan view showing an example of the planar layout of pixel electrodes and shielding electrodes according to the embodiment. FIG4 is a schematic cross-sectional view of a region corresponding to one pixel of a wafer according to an embodiment. FIG5 is a flow chart of the inspection method according to the embodiment. FIG6 is a graph showing an example of the current-voltage characteristics of the photoelectric conversion layer according to the embodiment. FIG. 7 is a graph showing current-voltage characteristics for explaining a voltage range used for global shutter operation. FIG8 is a graph showing another example of the current-voltage characteristics of the photoelectric conversion layer according to the embodiment. FIG9 is a schematic diagram showing an exemplary circuit configuration of an imaging element according to an embodiment. FIG10 is a cross-sectional view showing an exemplary device structure of a pixel according to an embodiment. FIG11 is a flowchart of a method for manufacturing an imaging element according to an embodiment. FIG12 is a cross-sectional view showing a wafer according to a modified example. FIG13 is a cross-sectional view showing an exemplary device structure of a pixel according to a modification example. Implementation Method

[0011] Mode for carrying out the invention (Process of Obtaining One Aspect of the Disclosure) In imaging devices that have a photoelectric conversion layer stacked above a CMOS readout circuit, the current-voltage characteristics, influenced by the quality of the photoelectric conversion layer, can affect the device's performance. For example, if a defect in the photoelectric conversion layer occurs, current can easily flow through the layer even when no light is applied, increasing dark current. Therefore, it is crucial to inspect the quality of the photoelectric conversion layer during the manufacturing process to avoid defective products during assembly and processing after inspection.

[0012] On the other hand, to measure the current flowing through the photoelectric conversion layer, it is necessary to apply a bias voltage to the electrodes connected to the photoelectric conversion layer and control the light irradiation state of the photoelectric conversion layer to measure the current. However, implementing a new testing structure poses the problem of reduced yield and performance of the imaging element.

[0013] FIG. 1 is a diagram for explaining the arrangement of an inspection structure in a wafer.

[0014] Previously, in the manufacturing process of imaging devices, the test structure for the process control monitor (PCM) used to confirm the quality of the photoelectric conversion layer was mostly configured in a tiny area such as the dicing area between the chips within the wafer or the edge of the chip, which is represented as a gap in Figure 1.

[0015] However, when utilizing such a tiny area for inspection, as shown in Figure 1(b), measuring the dark current and photocurrent generated in the photoelectric conversion layer presents a challenge: due to the small area of ​​the photoelectric conversion layer, the current is too small, resulting in low inspection accuracy. In particular, the dark current is much smaller than the photocurrent, making it difficult to measure.

[0016] Since the dark current and photocurrent generated in the photoelectric conversion layer increase roughly in proportion to the area of ​​the photoelectric conversion layer, inspection accuracy can be improved by increasing the area of ​​the photoelectric conversion layer under inspection. On the other hand, increasing the area of ​​the test structure used solely for inspection reduces the yield of the imaging device and increases the unit price of the wafer. Furthermore, there is the problem that the test structure placed in the dicing area can be damaged during wafer dicing. If the test structure, including the photoelectric conversion layer, is placed in the dicing area, there is a risk that the dicing machine will be contaminated by the material used for the photoelectric conversion layer.

[0017] To address the above-mentioned issues, the inventors of this application, as shown in Figure 1(a), focused on measuring the current flowing through the photoelectric conversion layer using the photoelectric conversion unit used in actual imaging. By doing so, they discovered that it was possible to increase the area of ​​the photoelectric conversion layer used for inspection, thereby increasing the amount of current measured, without reducing the yield of the imaging device due to the formation of a test structure. This led to one aspect of the present disclosure. The following describes one aspect of the present disclosure in detail.

[0018] (Summary of this disclosure) A summary of one aspect of the present disclosure is as follows.

[0019] An inspection method according to one aspect of the present disclosure includes: a process for preparing a device, wherein the device comprises: a plurality of pixel electrodes; a counter electrode disposed opposite the plurality of pixel electrodes; a photoelectric conversion layer disposed between the plurality of pixel electrodes and the counter electrode; a test electrode disposed opposite the counter electrode with the photoelectric conversion layer sandwiched therebetween and disposed between two adjacent pixel electrodes among the plurality of pixel electrodes; a first electrode pad electrically connected to the counter electrode and exposed to the outside; and a second electrode pad electrically connected to the test electrode and exposed to the outside; and a process for measuring current, applying a voltage between the first electrode pad and the second electrode pad, and measuring the current flowing between the first electrode pad and the second electrode pad.

[0020] This allows the first and second electrode pads to be used to measure the current flowing through the photoelectric conversion layer between the test electrode and the counter electrode, both positioned between the plurality of pixel electrodes. This effectively utilizes the area where the plurality of pixel electrodes are formed to measure the current in the photoelectric conversion layer. This effectively reduces the wafer size compared to a case where a separate test structure is formed, thus minimizing the yield reduction of the imaging element. Furthermore, since the current flows through the photoelectric conversion layer using the test electrode positioned between the plurality of pixel electrodes, it is easier to ensure the area of ​​the photoelectric conversion layer to be inspected. This increases the amount of current flowing through the photoelectric conversion layer, improving inspection accuracy.

[0021] Furthermore, for example, the aforementioned device may further include a charge storage unit for storing the charge obtained in the aforementioned photoelectric conversion layer; the plurality of aforementioned pixel electrodes may be electrically connected to the aforementioned charge storage unit, and the aforementioned test electrode may not be electrically connected to the aforementioned charge storage unit.

[0022] Furthermore, for example, the test electrode has the same potential in the entire region where a plurality of pixel electrodes are arranged.

[0023] In this way, since the test electrode can be connected in the area where a plurality of pixel electrodes are arranged, the area used to form the test electrode can be further reduced, and the reduction in the yield of the imaging element can be further suppressed.

[0024] Furthermore, for example, the photoelectric conversion layer may convert light incident on the photoelectric conversion layer into electric charges, the plurality of pixel electrodes may capture the electric charges, and the test electrode may function as a shield to suppress the movement of the electric charges between the plurality of pixel electrodes when the electric charges are captured by the plurality of pixel electrodes.

[0025] This allows the test electrode to be used as a shielding electrode.

[0026] Furthermore, for example, the test electrode may also surround each of a plurality of the pixel electrodes.

[0027] This allows the current flowing in the photoelectric conversion layer around the pixel electrode to be efficiently captured and measured with high sensitivity.

[0028] Furthermore, for example, the test electrodes may be arranged in a grid pattern in the region where a plurality of pixel electrodes are arranged.

[0029] In this way, the current flowing through the entire photoelectric conversion layer in the region where a plurality of pixel electrodes are arranged can be measured.

[0030] Furthermore, for example, the inspection method may further include: a process for determining whether the photoelectric conversion layer is good or bad based on the current.

[0031] In this way, the quality of the photoelectric conversion layer can be determined based on the current flowing through the layer. For example, the determination result can be used to determine whether to continue with the subsequent manufacturing process, thereby avoiding the production of defective products and the resulting increased costs.

[0032] Furthermore, for example, in the process of measuring the aforementioned current, a predetermined voltage can also be applied between the aforementioned first electrode pad and the aforementioned second electrode pad. In the process of determining whether the aforementioned photoelectric conversion layer is good or bad, when the value of the current flowing between the aforementioned first electrode pad and the aforementioned second electrode pad when the aforementioned predetermined voltage is applied is greater than the predetermined current value, the aforementioned photoelectric conversion layer can be determined to be bad; when the value of the aforementioned current is less than the aforementioned predetermined current value, the aforementioned photoelectric conversion layer can be determined to be good.

[0033] This makes it possible to easily determine a defect such as a defect in the photoelectric conversion layer or a defect in which current easily flows in the photoelectric conversion layer.

[0034] Furthermore, for example, in the process of measuring the aforementioned current, the voltage applied between the aforementioned first electrode pad and the aforementioned second electrode pad can also be scanned to measure the current-voltage characteristics between the aforementioned first electrode pad and the aforementioned second electrode pad. In the process of determining whether the aforementioned photoelectric conversion layer is good or bad, the quality of the aforementioned photoelectric conversion layer can also be determined based on the measured aforementioned current-voltage characteristics.

[0035] In this way, since the current corresponding to multiple voltages is measured, the accuracy of the inspection can be further improved.

[0036] Furthermore, for example, in a process of determining whether the photoelectric conversion layer is good or bad, the quality of the photoelectric conversion layer can be determined based on the slope of the measured current-voltage characteristic.

[0037] This can be expected to detect changes in current values ​​relative to changes in voltage with high sensitivity, thereby improving inspection accuracy.

[0038] Furthermore, a method for manufacturing an imaging element according to one aspect of the present disclosure includes: a process for manufacturing a device, wherein the device comprises: a plurality of pixel electrodes; a counter electrode arranged opposite to the plurality of pixel electrodes; a photoelectric conversion layer arranged between the plurality of pixel electrodes and the counter electrode; a test electrode sandwiching the photoelectric conversion layer and opposite to the counter electrode, and arranged between two adjacent pixel electrodes among the plurality of pixel electrodes; a first electrode pad electrically connected to the counter electrode and exposed to the outside; and a second electrode pad electrically connected to the test electrode and exposed to the outside; and a process for inspecting the device using the inspection method; if the photoelectric conversion layer is determined to be good during the inspection, the process for forming the imaging element on the device is continued, and if the photoelectric conversion layer is determined to be defective during the inspection, the process for forming the imaging element is not continued.

[0039] This allows the quality of the photoelectric conversion layer to be evaluated using the above-described inspection method during the manufacturing process of an imaging element, thereby manufacturing an imaging element. Furthermore, an imaging element having a photoelectric conversion layer judged to be good can be manufactured, thereby suppressing the occurrence of defective products.

[0040] In addition, a camera device according to one aspect of the present disclosure comprises: a plurality of pixel electrodes; a counter electrode arranged opposite to the plurality of the aforementioned pixel electrodes; a photoelectric conversion layer arranged between the plurality of the aforementioned pixel electrodes and the aforementioned counter electrode; a test electrode sandwiching the aforementioned photoelectric conversion layer and opposite to the aforementioned counter electrode, and arranged between two adjacent pixel electrodes among the plurality of the aforementioned pixel electrodes; a first electrode pad electrically connected to the aforementioned counter electrode; and a second electrode pad electrically connected to the aforementioned test electrode.

[0041] Hereinafter, the embodiment will be described with reference to the drawings.

[0042] Furthermore, the embodiments described below are all inclusive or specific examples. The numerical values, shapes, components, configurations and connection forms of the components, processes (steps), and the order of the processes (steps) shown in the following embodiments are examples and are not intended to limit the present disclosure. In addition, among the components in the following embodiments, components that are not described in the independent claims are represented as optional components. In addition, each figure is a schematic diagram and is not necessarily a precise diagram. Therefore, for example, the scales in each figure are not necessarily the same. In addition, in each figure, substantially the same components are given the same symbols, and repeated descriptions may be omitted or simplified.

[0043] In addition, in this specification, terms indicating the relationship between elements, terms indicating the shape of elements, and numerical ranges do not necessarily indicate strict meanings, but rather indicate substantially equivalent ranges, for example, including differences of several percent.

[0044] Furthermore, in this specification, the terms "above" and "below" do not refer to the absolute upward (vertically above) and downward (vertically below) directions in spatial terms. Instead, they are used to define relative positional relationships based on the stacking order of layers in a stacked structure. Specifically, the light-receiving side of the imaging element is referred to as "above," and the side opposite the light-receiving side is referred to as "below." Furthermore, the terms "above" and "below" are used solely to designate the relative placement of components and are not intended to limit the position of the imaging element during use. Furthermore, the terms "above" and "below" apply not only to situations where two components are spaced apart, i.e., when another component exists between them, but also to situations where two components are placed in close proximity, i.e., when they are in contact with each other.

[0045] (Implementation form) Hereinafter, a wafer, an inspection method, an imaging element, and a method for manufacturing the imaging element according to an embodiment will be described.

[0046] [Wafer composition] First, the overall structure of the wafer 1 of this embodiment will be described. FIG2 is a cross-sectional view of the wafer 1 of this embodiment. FIG2 also shows a cross-sectional view of a portion of the wafer 1.

[0047] As shown in Figure 2, wafer 1 includes a CMOS circuit layer 60, a plurality of pixel electrodes 11, a shielding electrode 17, an electrode pad 51, an electrode pad 52, an extraction electrode 55, a photoelectric conversion layer 12, a counter electrode 13, an electron blocking layer 15, and a hole blocking layer 16. Wafer 1 is an example of a device, and is a wafer used to form a plurality of imaging elements. Wafer 1 includes a plurality of imaging element regions A1, each corresponding to a respective imaging element, and a dicing region A2, which is an area removed by dicing when the imaging elements are singulated. The same imaging element structure is formed in the plurality of imaging element regions A1. The plurality of pixel electrodes 11, the shielding electrode 17, the electrode pad 51, the electrode pad 52, the extraction electrode 55, the photoelectric conversion layer 12, the counter electrode 13, the electron blocking layer 15, and the hole blocking layer 16 are formed in the imaging element region A1 but not in the dicing region A2.

[0048] The CMOS circuit layer 60 includes a semiconductor substrate 61 and an interlayer insulating layer 62 disposed on the semiconductor substrate 61. Although not shown in detail in FIG2 , a ROIC (Readout IC) is formed in the CMOS circuit layer 60. The CMOS circuit layer 60 includes a charge storage unit 41 and a plug 31 connecting the charge storage unit 41 to the pixel electrode 11. The CMOS circuit layer 60 is fabricated, for example, using a BEOL (Back End of Line) process and a FEOL (Front End of Line) process.

[0049] The semiconductor substrate 61 is, for example, a substrate made of silicon such as a p-type silicon substrate. The semiconductor substrate 61 is not limited to a substrate entirely made of semiconductor. The interlayer insulating layer 62 is, for example, formed of an insulating material such as silicon dioxide.

[0050] A plurality of pixel electrodes 11, a photoelectric conversion layer 12, a counter electrode 13, an electron blocking layer 15, and a hole blocking layer 16 constitute a photoelectric conversion unit 20 above a CMOS circuit layer 60. A shield electrode 17 is disposed between the photoelectric conversion unit 20 and the CMOS circuit layer 60. The photoelectric conversion unit 20 is provided in each of the plurality of imaging element areas A1.

[0051] The plurality of pixel electrodes 11 are film-shaped electrodes formed on the interlayer insulating layer 62. The pixel electrodes 11 capture signal charges generated in the photoelectric conversion layer 12. The pixel electrodes 11 are electrically connected to the charge storage unit 41 via the plug 31. The signal charges captured by the pixel electrodes 11 are stored in the charge storage unit 41. The charge storage unit 41 includes a so-called floating diffusion (FD).

[0052] The pixel electrode 11 is formed using a conductive material. For example, the conductive material is polysilicon that has been made conductive by doping with a metal such as aluminum or copper, a metal nitride, or impurities.

[0053] The photoelectric conversion layer 12 is located between the pixel electrode 11 and the counter electrode 13. The photoelectric conversion layer 12 is also located between the shielding electrode 17 and the counter electrode 13. The photoelectric conversion layer 12 receives incident light and generates hole-electron pairs as carriers.

[0054] The photoelectric conversion material constituting the photoelectric conversion layer 12 may include, for example, organic semiconductor materials, semiconductor quantum dots, semiconductor carbon nanotubes, or compound semiconductors such as InGaAs (indium gallium arsenide). Furthermore, the photoelectric conversion material may be a combination of two or more of organic semiconductor materials, semiconductor quantum dots, semiconductor carbon nanotubes, and compound semiconductors, or may include multiple types of organic semiconductor materials.

[0055] The photoelectric conversion layer 12 can also absorb, or be sensitive to, infrared wavelengths. Because it absorbs infrared wavelengths, the photoelectric conversion material has a narrower bandgap. Therefore, compared to photoelectric conversion materials that absorb visible light, it is more susceptible to generating dark current due to thermal excitation. Therefore, by measuring the dark current flowing through the photoelectric conversion layer 12, it is easy to determine whether the photoelectric conversion layer 12 is good or bad.

[0056] The counter electrode 13 is positioned opposite the plurality of pixel electrodes 11 and the shielding electrode 17, sandwiching the photoelectric conversion layer 12. The counter electrode 13 is, for example, a film-shaped transparent electrode formed from a transparent conductive material. Furthermore, the term "transparent" in this specification means transmitting at least a portion of the wavelength range of light to be detected, but not necessarily transmitting the entire visible and infrared wavelength ranges. For convenience, the entire electromagnetic spectrum, including visible and infrared light, is referred to as "light."

[0057] The counter electrode 13 is formed using a transparent conductive oxide (TCO) such as ITO, IZO, AZO, FTO, SnO 2 , TiO 2 , or ZnO.

[0058] By controlling the potential of the counter electrode 13 relative to the potential of the pixel electrode 11, either the hole or the electron in the hole-electron pairs generated by photoelectric conversion within the photoelectric conversion layer 12 can be captured by the pixel electrode 11 as signal charge. The signal charge captured by the pixel electrode 11 is accumulated in the charge accumulation unit 41 via the plug 31. More specifically, when light is incident on the photoelectric conversion layer 12 (i.e., during bright conditions), a photocurrent corresponding to the amount of light incident on the photoelectric conversion layer 12 and the sensitivity of the photoelectric conversion layer 12 flows through the pixel electrode 11. When no light is incident on the photoelectric conversion layer 12 (i.e., during dark conditions), a dark current flows through the pixel electrode 11. The pixel electrode 11 captures the charge of this current.

[0059] The signal charge accumulated in the charge storage unit 41 is read by a readout circuit connected to the charge storage unit 41. For example, when using holes as signal charge, by making the potential of the counter electrode 13 higher than that of the pixel electrode 11, the holes can be selectively captured by the pixel electrode 11. The following describes the case of using holes as signal charge. Alternatively, electrons can be used as signal charge; in this case, the potential of the counter electrode 13 can be lower than that of the pixel electrode 11.

[0060] The electron blocking layer 15 has the function of suppressing electron injection from the pixel electrode 11 into the photoelectric conversion layer 12. Furthermore, the electron blocking layer 15 transports signal charges, i.e., holes, generated in the photoelectric conversion layer 12 toward the pixel electrode 11. The upper surface of the electron blocking layer 15 is in contact with the photoelectric conversion layer 12. The lower surface of the electron blocking layer 15 is in contact with the pixel electrode 11 and the shielding electrode 17.

[0061] Hole-blocking layer 16 has the function of suppressing hole injection from counter electrode 13 into photoelectric conversion layer 12. Furthermore, hole-blocking layer 16 transports electrons, which are charges opposite to the signal charges generated by photoelectric conversion layer 12, toward counter electrode 13. The upper surface of hole-blocking layer 16 is in contact with counter electrode 13, and the lower surface of hole-blocking layer 16 is in contact with photoelectric conversion layer 12.

[0062] The materials of the electron blocking layer 15 and the hole blocking layer 16 are selected from known materials in consideration of, for example, bonding strength with adjacent layers, difference in free potential, and difference in electron affinity.

[0063] Furthermore, when electrons are used as signal charges, the wafer 1 may have a structure in which the electron blocking layer 15 and the hole blocking layer 16 are interchanged. Furthermore, the wafer 1 may not have at least one of the electron blocking layer 15 and the hole blocking layer 16.

[0064] The photoelectric conversion layer 12, electron blocking layer 15, and hole blocking layer 16 are each formed by coating methods such as spin coating or vacuum evaporation, which vaporizes the layer material by heating under vacuum and deposits it on the substrate. For example, the photoelectric conversion layer 12, electron blocking layer 15, and hole blocking layer 16 are formed on the entire CMOS circuit layer 60 of the wafer 1 and patterned into the shape of each imaging element area A1 shown in Figure 2.

[0065] Shield electrode 17 is disposed opposite counter electrode 13, sandwiching photoelectric conversion layer 12. Shield electrode 17 is formed on interlayer insulating layer 62 and disposed between a plurality of pixel electrodes 11. Shield electrode 17 is an example of a test electrode. In a plan view, shield electrode 17 overlaps photoelectric conversion unit 20.

[0066] A voltage is supplied to the shield electrode 17 from a voltage supply circuit 35 provided within the CMOS circuit layer 60. By controlling the shield electrode 17 to a predetermined potential, the shield electrode 17 functions as a shield to suppress the movement of charge between the plurality of pixel electrodes 11 when the plurality of pixel electrodes 11 capture charge, thereby suppressing so-called crosstalk. Furthermore, the voltage supply circuit 35 need not be provided within the CMOS circuit layer 60, and the voltage can be supplied to the shield electrode 17 from an external voltage supply circuit 35. The shield electrode 17 is not electrically connected to the charge storage unit 41.

[0067] The shielding electrode 17 and the pixel electrode 11 are separated from each other by a portion of the interlayer insulating layer 62. FIG3 is a plan view showing an example of the planar layout of the pixel electrode 11 and the shielding electrode 17. In FIG3 , illustration of parts other than the pixel electrode 11 and the shielding electrode 17 is omitted.

[0068] As shown in FIG3 , a plurality of pixel electrodes 11 are arranged in a two-dimensional array. A shielding electrode 17 is disposed between adjacent pixel electrodes 11 when viewed from above. The shielding electrode 17 is disposed, for example, so as to sandwich each of the plurality of pixel electrodes 11 when viewed from above. In this embodiment, the shielding electrode 17 surrounds each of the plurality of pixel electrodes 11. The shielding electrode 17 is formed, for example, in the region where the plurality of pixel electrodes 11 are disposed, and has the same potential throughout the region where the plurality of pixel electrodes 11 are disposed. The region where the plurality of pixel electrodes 11 are disposed can also be considered to be the region where the photoelectric conversion unit 20 is disposed when viewed from above, or the imaging surface formed by the pixel array PA described later.

[0069] The shielding electrode 17 extends in a grid pattern in the area where the plurality of pixel electrodes 11 are arranged. In other words, the shielding electrode 17 has a lattice-like shape when viewed from above. A pixel electrode 11 is arranged in each of the plurality of openings formed by the shielding electrode 17. Furthermore, when viewed from above, the area of ​​the plurality of pixel electrodes 11 is larger than the area of ​​the shielding electrode 17. This helps suppress a decrease in the sensitivity of the imaging element. Furthermore, the top-view shape of the shielding electrode 17 is not particularly limited, as long as it is arranged between adjacent pixel electrodes 11. For example, the shielding electrode 17 may be provided in two or more separate sections. When the shielding electrode 17 is provided in two or more separate sections, the two or more shielding electrodes 17 may have the same potential, for example, by being connected to wiring. Furthermore, the two or more shielding electrodes 17 may each be provided with an electrode pad 52 connected to the shielding electrode 17. Furthermore, when viewed from above, the area of ​​the plurality of pixel electrodes 11 may be the same as or smaller than the area of ​​the shielding electrode 17.

[0070] The shield electrode 17 is formed of a conductive material. The conductive material is, for example, polysilicon that has been made conductive by doping with a metal such as aluminum or copper, a metal nitride, or impurities.

[0071] 2 again, the configuration around the photoelectric conversion unit 20 will be described.

[0072] The electrode pad 51 is electrically connected to the counter electrode 13 via the extraction electrode 55 and the wiring within the interlayer insulating layer 62. The electrode pad 51 is formed in the interlayer insulating layer 62, and its upper surface is exposed to the outside of the wafer 1 through an opening formed in the interlayer insulating layer 62. The electrode pad 51 is an example of a first electrode pad.

[0073] The electrode pad 52 is electrically connected to the shield electrode 17 via wiring in the interlayer insulating layer 62. The electrode pad 52 is formed in the interlayer insulating layer 62, and its upper surface is exposed to the outside of the wafer 1 through an opening formed in the interlayer insulating layer 62. The electrode pad 52 is an example of a second electrode pad.

[0074] Electrode pads 51 and 52 are electrodes that contact probe terminals 201 and 202 for measuring the current flowing through photoelectric conversion layer 12. Probe terminals 201 and 202 are connected to measuring device 200, respectively. Measuring device 200 applies a voltage between electrode pads 51 and 52 via probe terminals 201 and 202 to measure the current flowing between electrode pads 51 and 52. Measuring device 200 is, for example, an ammeter.

[0075] Furthermore, the electrode pad 51 can also be used as a power supply terminal for supplying a voltage to the counter electrode 13 in the imaging element manufactured from the wafer 1 . Furthermore, the electrode pad 52 can also be used as a power supply terminal for supplying a voltage to the shielding electrode 17 in the imaging element manufactured from the wafer 1 .

[0076] Electrode pads 51 and 52 are each located within imaging element region A1 and outside photoelectric conversion unit 20 in a plan view. Electrode pads 51 and 52 are arranged so as to sandwich photoelectric conversion unit 20. The placement of electrode pads 51 and 52 is not particularly limited, as long as they are exposed to the outside of wafer 1.

[0077] The extraction electrode 55 is an electrode for supplying power to the counter electrode 13. The extraction electrode 55 is provided on the interlayer insulating layer 62. In a plan view, the extraction electrode 55 is arranged outside the region of the interlayer insulating layer 62 where the plurality of pixel electrodes 11 and the shielding electrode 17 are provided. Furthermore, in a plan view, the extraction electrode 55 is arranged around the region where the photoelectric conversion layer 12 is provided, so as not to overlap with the photoelectric conversion layer 12.

[0078] The above wafer 1 can be manufactured using a general semiconductor manufacturing process and a film forming process. In particular, when a silicon substrate is used as the semiconductor substrate 61, various silicon semiconductor processes can be used.

[0079] [Inspection method] Next, the inspection method of this embodiment using the wafer 1 will be described. In the inspection method of this embodiment, the quality of the photoelectric conversion layer 12 included in the imaging element is inspected.

[0080] Figure 4 is a schematic cross-sectional view of a region corresponding to a pixel in the imaging element region A1 of wafer 1. As shown in Figure 4 , each pixel can be considered a three-terminal element, comprising a counter electrode 13 disposed above the photoelectric conversion layer 12, a pixel electrode 11 disposed below the photoelectric conversion layer 12, and a shielding electrode 17. Counter electrode 13 is electrically connected to electrode pad 51. Shielding electrode 17 is electrically connected to electrode pad 52.

[0081] When reading signals from an imaging device manufactured from wafer 1, a bias voltage is applied between counter electrode 13 and pixel electrode 11. The pixel electrode 11 captures the signal charge generated in photoelectric conversion layer 12, which is then read by the readout circuit as the signal for each pixel. On the other hand, since shield electrode 17 operates to suppress crosstalk, signals are not read from shield electrode 17.

[0082] If the pixel electrode 11 is connected to another electrode, such as the electrode pad 51, the capacitance of the charge storage unit 41 connected to the pixel electrode 11 increases, reducing the sensitivity of the imaging device. Specifically, if the pixel electrode 11 is connected to the electrode pad 51, parasitic capacitance, such as the wiring connection to the electrode pad 51 and the capacitance of the electrode pad 51 itself, may be added to the charge storage unit 41, degrading the conversion gain, which is important for read sensitivity. Furthermore, because the pixel electrode 11 is used to separate the pixels and read the signal, the pixel electrodes 11 of each pixel are electrically isolated from each other. Therefore, when measuring the current flowing between a pixel electrode 11 and the counter electrode 13, the amount of current flowing between the pixel electrode 11 and the counter electrode 13 is also very small because the area of ​​each pixel electrode 11 itself is very small. Meanwhile, in the wafer 1 of this embodiment, the shield electrode 17 extends within the pixel array, the area where multiple pixel electrodes 11 are arranged, in the imaging device area A1, and is connected to the electrode pad 52. The shielding electrode 17 has the same potential throughout the entire pixel array. Unlike the pixel electrode 11, the shielding electrode 17 does not read signals, so even if it is directly connected to the electrode pad 51, it will not affect the sensitivity of the imaging element.

[0083] In the inspection method of this embodiment, focusing on the above viewpoint, the quality of the photoelectric conversion layer 12 provided in each imaging element area A1 is inspected by measuring the current between the electrode pad 51 electrically connected to the counter electrode 13 and the electrode pad 52 electrically connected to the shielding electrode 17.

[0084] FIG5 is a flow chart of the inspection method of this embodiment.

[0085] As shown in FIG5 , in the inspection method of this embodiment, first, a wafer 1 for inspection is prepared (step S11 ). For example, the manufactured wafer 1 is placed at an inspection location.

[0086] Next, a voltage is applied between the electrode pads 51 and 52 in each imaging element area A1 of the prepared wafer 1, and the current flowing between the electrode pads 51 and 52 is measured (step S12). For example, probe terminal 201 is brought into contact with electrode pad 51, and probe terminal 202 is brought into contact with electrode pad 52, and the current is measured using measuring instrument 200. This allows a voltage to be applied between the counter electrode 13 and the shield electrode 17 through the electrode pads 51 and 52, and the current flowing through the photoelectric conversion layer 12 between the counter electrode 13 and the shield electrode 17 can be measured. While details will be described later, by measuring the current flowing through the photoelectric conversion layer 12, it is possible to confirm whether the current value is consistent with the desired current-voltage characteristics of the photoelectric conversion layer 12, thereby inspecting the quality of the photoelectric conversion layer 12.

[0087] The probe terminals 201 and 202 can be considered to correspond to a probe card conventionally used for wafer inspection. Furthermore, the measuring device 200 can be considered to correspond to a portion of a wafer inspection circuit, or to an ammeter or voltmeter used in connection therewith.

[0088] In step S12, the current between the electrode pads 51 and 52 is measured for each of the plurality of imaging element areas A1. The current between the electrode pads 51 and 52 can be measured for each imaging element area A1, or it can be measured for two or more imaging element areas A1 simultaneously using two or more probe terminals 201 and 202.

[0089] Next, the quality of the photoelectric conversion layer 12 is determined based on the current measured in step S12 (step S13). This determination is made, for example, based on the current value when a predetermined voltage is applied between the electrode pads 51 and 52. Alternatively, the determination can be made based on the current-voltage characteristics between the electrode pads 51 and 52.

[0090] Here, the voltage applied between the electrode pad 51 and the electrode pad 52 and the determination of whether the photoelectric conversion layer 12 is good or bad will be described in detail.

[0091] For example, in step S12, a predetermined voltage is applied between the electrode pads 51 and 52. Then, in step S13, the quality of the photoelectric conversion layer 12 is determined to be good or bad based on the current value flowing between the electrode pads 51 and 52 when the predetermined voltage is applied therebetween, i.e., the current value flowing through the photoelectric conversion layer 12.

[0092] Here, the voltage applied between the electrode pad 51 and the electrode pad 52 will be described using FIG. 6 .

[0093] FIG6 is a graph showing an example of the current-voltage characteristics of the photoelectric conversion layer 12. The horizontal axis shown in FIG6 represents the bias voltage applied to the photoelectric conversion layer 12. The vertical axis shown in FIG6 represents the absolute value of the current flowing in the photoelectric conversion layer 12. FIG6 is a graph in which the vertical axis is a logarithmic semi-logarithmic representation. In FIG6, the solid line represented by "dark" represents the current-voltage characteristics in the dark when the photoelectric conversion layer 12 is not irradiated with light. In FIG6, the dotted line represented by "light" represents the current-voltage characteristics in the bright state when the photoelectric conversion layer 12 is irradiated with light of a predetermined intensity. The representation of "dark" and "light" is the same in FIG7 and FIG8 described later.

[0094] In Figure 6 , when the photoelectric conversion layer 12 is considered a photodiode, the left side of (d) represents a reverse bias voltage, and the right side of (d) represents a forward bias voltage. Furthermore, in this embodiment, a voltage where the potential of the counter electrode 13 is higher than that of the pixel electrode 11 or the shield electrode 17 represents a reverse bias voltage. On the other hand, a voltage where the potential of the counter electrode 13 is lower than that of the pixel electrode 11 or the shield electrode 17 represents a forward bias voltage.

[0095] During photoelectric conversion when capturing an image, a reverse bias voltage (e.g., approximately 5V) is applied to the photoelectric conversion layer 12, for example, at the position shown in (a). This causes a photocurrent, generated by carriers in response to the amount of incident light, to flow through the photoelectric conversion layer 12, and the signal charge is captured by the pixel electrode 11. Under the reverse bias voltage shown in (a), even if the potential of the pixel electrode 11 changes after the signal charge is captured, thereby changing the voltage applied to the photoelectric conversion layer 12, the change in photocurrent is minimal, thus suppressing fluctuations in sensitivity. Furthermore, at the voltage shown in (a), the photocurrent value flowing through the photoelectric conversion layer 12 is substantially different from the dark current value. For example, the photocurrent value is at least 10 times the dark current value.

[0096] For example, when inspecting a photoelectric conversion layer 12 having the current-voltage characteristics shown in Figure 6 , the current is measured while the voltage shown in Figure 6 (a) is applied between electrode pads 51 and 52 to confirm whether it reaches the expected current value. For example, a threshold for determining whether a product is good or bad is determined based on the known current-voltage characteristics and the area of ​​the pixel array, and the determination is made using data obtained from the measuring device 200. Specifically, a product is judged as defective when the measured current value is above a predetermined value, and as good when it is below the predetermined value. When a defect occurs in the photoelectric conversion layer 12, charge is injected from the electrodes into the photoelectric conversion layer 12 via the bias voltage, increasing the current value. Therefore, if the measured current value is above the predetermined value, the photoelectric conversion layer 12 can be considered defective. This makes it easy and highly accurate to determine whether the photoelectric conversion layer 12 is good or bad.

[0097] In a specific example, the dark current is measured while the wafer 1 is shielded from light. If the measured dark current value is greater than a predetermined value, the photoelectric conversion layer 12 is judged defective; if it is less than the predetermined value, the photoelectric conversion layer 12 is judged acceptable. Compared to measuring photocurrent, which requires adjusting the light intensity, dark current measurement enables stable inspection without adjusting the light intensity. Furthermore, when measuring a signal level that is difficult to detect simply by measuring dark current, the wafer can be illuminated with the same adjusted light and the photocurrent can be measured to determine whether the product is acceptable or not. Furthermore, both dark current and photocurrent can be measured, and the acceptable or unacceptable determination can be made based on both the photocurrent and dark current values.

[0098] Furthermore, the voltage applied between the electrode pad 51 and the electrode pad 52 is not limited to the voltage shown in FIG. 6( a ), and other voltages may be applied.

[0099] For example, the voltage shown in FIG6 (b) or (c) can be applied between electrode pad 51 and electrode pad 52. At the voltages shown in FIG6 (b) and (c), the photocurrent is quite small. For example, the photocurrent values ​​at the voltages shown in FIG6 (b) and (c) are less than one-tenth of the photocurrent value at the voltage shown in FIG6 (a). This can also be used to measure both the dark current and the photocurrent, and determine whether the photoelectric conversion layer 12 is good or bad based on the difference between the photocurrent and dark current values. For example, if the difference between the photocurrent and dark current values ​​is greater than a predetermined value, the photoelectric conversion layer 12 is determined to be bad, while if it is less than the predetermined value, the photoelectric conversion layer 12 is determined to be good. In this way, at a voltage where the photocurrent and dark current do not deviate significantly, it can be determined whether the photocurrent and dark current are consistent.

[0100] Alternatively, for example, the voltage shown in FIG6(d) can be applied between electrode pads 51 and 52. The dark current is lowest near the voltage shown in FIG6(d). Therefore, by measuring the dark current flowing when the voltage shown in FIG6(d) is applied, the lower limit of the dark current value can be determined.

[0101] Furthermore, in the voltage range shown in (c) to (e) of Figure 6, since the photocurrent and the dark current are substantially the same, by applying a voltage in this range between the electrode pad 51 and the electrode pad 52, inspection can be performed without being affected by whether or not light is irradiated toward the wafer 1.

[0102] Of the aforementioned voltages, the voltage range between (a) and (b) in Figure 6 is the voltage applied to the photoelectric conversion layer 12 during photoelectric conversion when acquiring an image. Therefore, by applying a voltage within this range between electrode pads 51 and 52, and measuring the current while the wafer 1 is shielded from light or the amount of light directed toward the wafer 1 is appropriately controlled, actual use inspections can be easily performed.

[0103] Furthermore, the voltage applied between electrode pads 51 and 52 may be multiple voltages. For example, in step S12, the voltage applied between electrode pads 51 and 52 may be scanned, and the applied voltage and the current between probe terminals 201 and 202 may be monitored to measure the current-voltage characteristics between electrode pads 51 and 52. In this case, in step S13, the quality of photoelectric conversion layer 12 is determined to be good or bad based on the measured current-voltage characteristics.

[0104] For example, multiple voltages within the voltage range represented by the current-voltage characteristic shown in FIG6 (e.g., the voltages at points (a), (b), and (c) in FIG6 ) are applied between electrode pads 51 and 52 to measure the current-voltage characteristic. The quality of the photoelectric conversion layer 12 is then determined to be good or bad based on the slope of the measured current-voltage characteristic. For example, if the slope of the measured current-voltage characteristic is not within a predetermined range, the photoelectric conversion layer 12 is determined to be bad; if it is within the predetermined range, the photoelectric conversion layer 12 is determined to be good. Alternatively, multiple slopes may be used, and if the difference between the multiple slopes is not within a predetermined range, the photoelectric conversion layer 12 is determined to be bad; if it is within the predetermined range, the photoelectric conversion layer 12 is determined to be good.

[0105] This can be expected to improve inspection accuracy by compensating for the sensitivity of the measuring device 200 and detecting abrupt changes in current value due to voltage changes with high sensitivity. The predetermined range is, for example, based on the known current-voltage characteristics of the photoelectric conversion layer 12 measured through prior testing, and is set within a range where the difference in slope from the known current-voltage characteristics is less than a predetermined value. Furthermore, the quality of the photoelectric conversion layer 12 can be determined based on the current value of the measured current-voltage characteristics. For example, within the measured voltage range, if the difference between the current values ​​of the known current-voltage characteristics and the measured current-voltage characteristics is at least a threshold value, the photoelectric conversion layer 12 is determined to be defective. Furthermore, the slope of the measured current-voltage characteristics and the current value can be combined to determine the quality of the photoelectric conversion layer 12.

[0106] In particular, when the photoelectric conversion layer 12 is irradiated with light, since the current varies greatly depending on the applied voltage, the inspection can be performed while the wafer 1 is irradiated with light while scanning the voltage applied between the electrode pad 51 and the electrode pad 52 .

[0107] Here, another example of the voltage applied between the electrode pad 51 and the electrode pad 52 will be described.

[0108] For example, in step S12, the voltage applied between electrode pad 51 and electrode pad 52 can also be determined based on the voltage range used for global shutter operation. Figure 7 shows a current-voltage characteristic diagram illustrating the voltage range used for global shutter operation. The horizontal axis in Figure 7 represents the bias voltage applied to the photoelectric conversion layer 12. Furthermore, the vertical axis in Figure 7 represents the current flowing through the photoelectric conversion layer 12. Furthermore, the current values ​​on the vertical axis in Figure 7 are not absolute values. Furthermore, the vertical axis in Figure 7 is not a logarithmic axis, but a conventional linear axis.

[0109] The photocurrent characteristics of the photoelectric conversion layer 12 in the example shown in FIG7 are broadly divided into a first voltage range, a second voltage range, and a third voltage range. The second voltage range is the reverse bias voltage range, where the absolute value of the output current density increases as the reverse bias voltage increases. The third voltage range is the forward bias voltage range, where the absolute value of the output current density increases as the forward bias voltage increases. The first voltage range is the voltage range between the second and third voltage ranges. When a voltage is applied to the photoelectric conversion layer 12, the current density flowing through the photoelectric conversion layer 12 is equal when light is incident on the photoelectric conversion layer 12 and when light is not incident on the photoelectric conversion layer 12, that is, the photocurrent and dark current are equal. The current density being equal when light is incident on the photoelectric conversion layer 12 and when light is not incident on the photoelectric conversion layer 12 means that they are substantially equal. For example, in the first voltage range, the ratio of the absolute value of the current density in the light-incident state to the absolute value of the current density in the non-light-incident state is greater than 1:10 and less than 10:1. Furthermore, the light-incident state may refer to, for example, light irradiation of 100 mW / cm². Furthermore, considering the standard indoor illuminance, the light-incident state may refer to light irradiation of 50 μW / cm² or greater.

[0110] In global shutter operation, a voltage within the second voltage range is applied to the photoelectric conversion layer 12 during the exposure period, and a voltage within the first voltage range is applied to the photoelectric conversion layer 12 during the non-exposure period, such as when signal charge is being read. When the voltage within the first voltage range is applied, the photoelectric conversion layer 12 is substantially insensitive, so no signal charge is accumulated during the reading of each pixel, enabling global shutter operation.

[0111] In step S12, the voltage applied between electrode pads 51 and 52 can be a voltage selected from any of the first, second, and third voltage ranges shown in FIG7 . For example, by applying a voltage within the first voltage range between electrode pads 51 and 52, sensitivity can be checked during the non-exposure period when signal reading is performed. Alternatively, the voltage applied between electrode pads 51 and 52 can be selected from one or more of the first, second, and third voltage ranges.

[0112] Furthermore, the photoelectric conversion layer 12 may have current-voltage characteristics different from those shown in Figures 6 and 7 . Figure 8 is a graph showing another example of the current-voltage characteristics of the photoelectric conversion layer 12. Figure 8 shows current-voltage characteristics that can be achieved, for example, when semiconductor quantum dots are used as the photoelectric conversion material. As in Figure 6 , the horizontal axis in Figure 8 represents the bias voltage applied to the photoelectric conversion layer 12. Furthermore, the vertical axis in Figure 8 represents the absolute value of the current flowing through the photoelectric conversion layer 12. Furthermore, Figure 8 is a semi-logarithmic graph with a logarithmic vertical axis.

[0113] In the current-voltage characteristics shown in Figure 8 , the difference between the photocurrent and dark current is significant, and there is essentially no voltage range where the photocurrent and dark current values ​​are equal. Therefore, it is also possible to apply a predetermined voltage between electrode pads 51 and 52 and measure both the photocurrent and dark current values. This improves inspection accuracy. Furthermore, it is possible to measure only the dark current value, shortening inspection time.

[0114] Furthermore, although the current-voltage characteristics of the photoelectric conversion layer 12 are described using FIG. 6 to FIG. 8 , the current-voltage characteristics shown in FIG. 6 to FIG. 8 may also be characteristics of the entire photoelectric conversion section 20 .

[0115] Furthermore, when measuring either the photocurrent or the dark current in step S12, the decision on which to measure can be based on the sensitivity wavelength of the photoelectric conversion layer 12. In particular, the longer the sensitivity wavelength of the photoelectric conversion layer 12, the more likely the dark current is to increase. This is because the inherent band gap of the material of the photoelectric conversion layer 12 is relatively narrow, so thermal excitation in the photoelectric conversion layer 12 generates carriers that contribute to the dark current. Therefore, if the photoelectric conversion layer 12 is sensitive to wavelengths from near-infrared to short-wave infrared, the dark current can be measured. On the other hand, if the photoelectric conversion layer 12 is sensitive only to wavelengths below the visible wavelength, the photocurrent can be measured.

[0116] As described above, the inspection method of this embodiment includes a process for preparing wafer 1 and a process for measuring current. A voltage is applied between electrode pads 51 and 52 in wafer 1, and the current flowing between electrode pads 51 and 52 is measured. Because electrode pads 51 are electrically connected to counter electrode 13 and electrode pads 52 are electrically connected to shield electrode 17, the current flowing through photoelectric conversion layer 12 between counter electrode 13 and shield electrode 17 can be measured, thereby inspecting the quality of photoelectric conversion layer 12.

[0117] In this embodiment, the quality inspection of the photoelectric conversion layer 12 is performed on a large scale for the following purposes: for example, to detect variations within the wafer 1 plane and to sort good and bad products within each imaging element area A1 within the wafer 1. Meanwhile, variations within each pixel within the same imaging element area A1 can be detected through image scanning and other methods. Furthermore, if there are localized white spots or excessive dark current in each pixel, these defects can be corrected through image processing at a specific scale. Therefore, the necessity for inspection during the manufacturing process is considered low.

[0118] When forming the photoelectric conversion layer 12 on the surface of the wafer 1 using a film-forming method such as spin coating, uneven film thickness and coating, as well as cracks, may occur. The quality of the photoelectric conversion layer 12 due to these problems can be determined by measuring the current flowing through the photoelectric conversion layer 12 using the inspection method of this embodiment. Furthermore, after the photoelectric conversion portion 20 is formed on the entire surface of the wafer 1, patterning is performed based on the shape of the area where the plurality of pixel electrodes 11 are formed, and openings are performed in the electrode pad area. Damage to the photoelectric conversion layer 12 caused by these patterning and opening processes can also be detected using the inspection method of this embodiment.

[0119] By detecting defects in the photoelectric conversion layer 12 early in the manufacturing process, defective products can be removed in the subsequent imaging element manufacturing process before dicing and packaging, thereby reducing increases in packaging assembly costs and packaging costs. Similarly, increases in costs associated with the camera module manufacturing process after the packaging of the imaging element can also be reduced.

[0120] Alternatively, inspection can be performed by outputting an image while the wafer 1 is illuminated or shielded from light. However, this presents challenges such as the need to construct an inspection program for outputting the image, a complex inspection sequence for connecting a probe card, and increased inspection time due to the signal accumulation required for imaging. Therefore, the inspection method of this embodiment, which connects inspection probe terminals 201 and 202 to electrode pads 51 and 52 to measure the current between them, is very simple. For example, there is no need to replace the probe card required for inspection or add a new inspection structure. Therefore, the method is highly effective in that it can be applied to any product type and part number.

[0121] Furthermore, the inspection method of this embodiment can measure the current flowing through the photoelectric conversion layer 12 between the shield electrode 17 and the counter electrode 13, which are arranged between the plurality of pixel electrodes 11. Therefore, compared to inspection methods in which a test pattern including the photoelectric conversion layer 12 is formed separately from the photoelectric conversion portion 20 on the wafer 1, there is no need to provide an inspection area on the wafer 1, thereby improving the yield of imaging devices. Furthermore, since the photoelectric conversion layer 12 in the imaging area can be directly inspected over a large area, inspection accuracy can be improved.

[0122] [Image Sensor Configuration] Next, the configuration of the imaging element 100 manufactured from the wafer 1 will be described. In the following description of the imaging element 100, the description of points common to the wafer 1 will be omitted or simplified.

[0123] FIG9 is a schematic diagram showing an exemplary circuit configuration of an imaging device 100 according to this embodiment. The imaging device 100 shown in FIG9 includes a pixel array PA comprising a plurality of pixels 10 arranged two-dimensionally. The pixel array PA forms, for example, the imaging surface of the imaging device 100. FIG9 schematically illustrates an example in which the pixels 10 are arranged in a matrix of two columns and two rows. The number and arrangement of the pixels 10 in the imaging device 100 are not limited to the example shown in FIG9 .

[0124] Each pixel 10 includes a photoelectric converter 20 , a signal detection circuit 22 , a reset transistor 28 , a charge storage unit 41 , and a shield electrode 17 .

[0125] The photoelectric conversion section 20 includes a pixel electrode 11, a photoelectric conversion layer 12, a counter electrode 13, an electron blocking layer 15, and a hole blocking layer 16, disposed in the imaging element region A1 of the wafer 1. The photoelectric conversion section 20 receives incident light and generates signal charges. The entire photoelectric conversion section 20 need not be a separate element for each pixel 10; for example, a portion of the photoelectric conversion section 20 may encompass multiple pixels 10.

[0126] The signal detection circuit 22 detects the signal charge generated by the photoelectric conversion unit 20. In this example, the signal detection circuit 22 includes a signal detection transistor 24 and an address transistor 26. The signal detection transistor 24 and the address transistor 26 are, for example, field-effect transistors (FETs), with N-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) being used as examples. Each transistor, including the signal detection transistor 24 and the address transistor 26, as well as the reset transistor 28 described later, has a control terminal, an input terminal, and an output terminal. The control terminal is, for example, a gate. The input terminal is one of a drain and a source, for example, a drain. The output terminal is the other of a drain and a source, for example, a source.

[0127] As schematically shown in FIG9 , the control terminal of the signal detection transistor 24 is electrically connected to the photoelectric converter 20. Signal charge generated by the photoelectric converter 20 is accumulated in the charge accumulation section 41. The charge accumulation section 41 extends to include the region between the gate of the signal detection transistor 24 and the photoelectric converter 20. Signal charge is positive or negative charge, such as holes or electrons.

[0128] The imaging element 100 includes peripheral circuits directly or indirectly connected to the photoelectric conversion section 20. For example, the peripheral circuits drive the pixel array PA and capture images based on the signal charges generated in the photoelectric conversion section 20. The peripheral circuits include, for example, a voltage supply circuit 32, a voltage supply circuit 35, a reset voltage source 34, a vertical scanning circuit 36, a row signal processing circuit 37, a horizontal signal reading circuit 38, and a pixel drive signal generating circuit 39. Each of the peripheral circuits may be entirely disposed within the CMOS circuit layer 60, or at least one circuit may be disposed outside the CMOS circuit layer 60. For example, the voltage supply circuit 32 and the voltage supply circuit 35 may be disposed on a printed circuit board or a power supply board, for example, outside the CMOS circuit layer 60. In this case, the electrode pads 51 and 52 function as terminals connected to the voltage supply circuit 32 and the voltage supply circuit 35, which are disposed on a printed circuit board or a power supply board, for example, outside the CMOS circuit layer 60.

[0129] The photoelectric converter 20 of each pixel 10 is connected to a sensitivity control line 42. In the configuration shown in FIG9 , the sensitivity control line 42 is connected to a voltage supply circuit 32. The voltage supply circuit 32 supplies a voltage to the counter electrode 13 of the photoelectric converter 20.

[0130] 9 , the shielding electrode 17 is connected to the sensitivity control line 45. The sensitivity control line 45 is connected to the voltage supply circuit 35. The voltage supply circuit 35 supplies a voltage to the shielding electrode 17. The shielding electrode 17 is electrically isolated from the pixel electrode 11.

[0131] The voltage supply circuit 32 and the voltage supply circuit 35 are not limited to specific power supply circuits, and may be a circuit that generates a predetermined voltage or a circuit that converts a voltage supplied from another power supply into a predetermined voltage.

[0132] Each pixel 10 is connected to a power line 40 that supplies a power supply voltage VDD. As shown in the figure, the input terminal of the signal detection transistor 24 is connected to the power line 40. With the power line 40 functioning as a source-follower power supply, the signal detection transistor 24 amplifies the signal charge generated by the photoelectric converter 20 and outputs it. Specifically, a voltage corresponding to the amount of signal charge accumulated in the charge storage unit 41 is applied to the control terminal of the signal detection transistor 24. The signal detection transistor 24 amplifies this voltage.

[0133] The output terminal of the signal detection transistor 24 is connected to the input terminal of the address transistor 26. The output terminal of the address transistor 26 is connected to one of the plurality of vertical signal lines 47 arranged in each row of the pixel array PA. The control terminal of the address transistor 26 is connected to the address control line 46. By controlling the potential of the address control line 46, the output of the signal detection transistor 24 can be selectively read to the corresponding vertical signal line 47. Specifically, the voltage amplified by the signal detection transistor 24 is converted into a signal voltage and selectively read as a pixel signal by the address transistor 26.

[0134] In the example shown, the address control line 46 is connected to the vertical scanning circuit 36. The vertical scanning circuit 36 ​​is also called a "column scanning circuit." The vertical scanning circuit 36 ​​selects a plurality of pixels 10 arranged in each column by applying a predetermined voltage to the address control line 46. This reads the signal of the selected pixel 10 and resets the potential of the charge storage unit 41.

[0135] Furthermore, a pixel drive signal generating circuit 39 is connected to the vertical scanning circuit 36. In the illustrated example, the pixel drive signal generating circuit 39 generates a signal for driving the pixels 10 arranged in each column of the pixel array PA. The generated pixel drive signal is supplied to the pixels 10 in the column selected by the vertical scanning circuit 36.

[0136] Vertical signal lines 47 are main signal lines that transmit pixel signals from the pixel array PA to peripheral circuits. Connected to vertical signal lines 47 are row signal processing circuits 37. Row signal processing circuits 37 are also called "column signal storage circuits." Row signal processing circuits 37 perform noise suppression signal processing, typified by correlated double sampling, and analog-to-digital conversion (AD conversion). As shown in the figure, row signal processing circuits 37 are provided corresponding to each row of pixels 10 in the pixel array PA. Connected to these row signal processing circuits 37 are horizontal signal readout circuits 38. Horizontal signal readout circuits 38 are also called "row scanning circuits." Horizontal signal readout circuits 38 sequentially read signals from multiple row signal processing circuits 37 and transmit them to horizontal common signal lines 49.

[0137] The imaging device 100 can be driven using either a global shutter or rolling shutter method. When driven using the global shutter method, the voltage supply circuit 32 applies a bias voltage within the second voltage range to the counter electrode 13 during the exposure period and a bias voltage within the first voltage range during the non-exposure period. During the non-exposure period, signals are read from each pixel column.

[0138] In the configuration illustrated in FIG9 , the pixel 10 includes a reset transistor 28. The reset transistor 28, like the signal detection transistor 24 and the address transistor 26, can be a field-effect transistor. Unless otherwise specified, the following description uses an N-channel MOSFET as the reset transistor 28. As shown, the reset transistor 28 is connected between a reset voltage line 44 that supplies a reset voltage Vr and the charge accumulation unit 41. The control terminal of the reset transistor 28 is connected to a reset control line 48. By controlling the potential of the reset control line 48, the potential of the pixel electrode 11 and the charge accumulation unit 41 can be reset to the reset voltage Vr. In this example, the reset control line 48 is connected to the vertical scanning circuit 36. Therefore, the vertical scanning circuit 36 ​​applies a predetermined voltage to the reset control line 48, thereby resetting the plurality of pixels 10 arranged in each column.

[0139] In this example, a reset voltage line 44, which supplies a reset voltage Vr to the reset transistor 28, is connected to a reset voltage source 34. The reset voltage source 34 is also referred to as a "reset voltage supply circuit." The reset voltage source 34, like the voltage supply circuit 32 described above, can be configured to supply a predetermined reset voltage Vr to the reset voltage line 44 during operation of the imaging element 100. It is not limited to a specific power supply circuit. The voltage supply circuit 32, the voltage supply circuit 35, and the reset voltage source 34 can each be part of a single voltage supply circuit or separate voltage supply circuits. Furthermore, at least one of the voltage supply circuit 32, the voltage supply circuit 35, and the reset voltage source 34 can also be part of the vertical scanning circuit 36. Alternatively, the sensitivity control voltage from the voltage supply circuit 32, the sensitivity control voltage from the voltage supply circuit 35, and / or the reset voltage Vr from the reset voltage source 34 can be supplied to each pixel 10 via the vertical scanning circuit 36.

[0140] Furthermore, the imaging element 100 may also include circuits other than those described above that are used in known image sensors.

[0141] Next, the device structure of the pixel 10 of the image sensor 100 will be described. Fig. 10 is a cross-sectional view showing an exemplary device structure of the pixel 10 of this embodiment.

[0142] As shown in FIG10 , pixel 10 includes a CMOS circuit layer 60, a photoelectric conversion unit 20 located above CMOS circuit layer 60, a sealing layer 21 located above photoelectric conversion unit 20, a shielding electrode 17, and a charge storage unit 41. Pixel 10 may further include an optical filter, a microlens, and the like above sealing layer 21. Light enters pixel 10 from above sealing layer 21.

[0143] The photoelectric conversion section 20 includes a pixel electrode 11 electrically connected to the charge storage section 41; a counter electrode 13 located above and opposite the pixel electrode 11; a photoelectric conversion layer 12 located between the pixel electrode 11 and the counter electrode 13; an electron blocking layer 15 located between the pixel electrode 11 and the photoelectric conversion layer 12; and a hole blocking layer 16 located between the counter electrode 13 and the photoelectric conversion layer 12. In the example shown in FIG10 , the counter electrode 13, the photoelectric conversion layer 12, the electron blocking layer 15, and the hole blocking layer 16 are formed to cover a plurality of pixels 10.

[0144] Although partially omitted in FIG10 , the CMOS circuit layer 60 in each pixel 10 includes various transistors, such as the signal detection circuit 22 and reset transistor 28 described with reference to FIG9 , wiring such as signal lines, control lines, and power lines, and a charge storage unit 41. Furthermore, a plug 31 is provided in the interlayer insulating layer 62 of the CMOS circuit layer 60 to connect the charge storage unit 41 and the pixel electrode 11. The plug 31 is formed of a conductive material.

[0145] FIG10 schematically shows the signal detection circuit 22 and the reset transistor 28, as well as the control lines and signal lines connected thereto. The gate of the reset transistor 28 is connected to the reset control line en_rst of each column. The signal detection circuit 22 outputs a pixel signal to the vertical signal line Vsig of each row. The reset control line en_rst corresponds to the reset control line 48 in FIG9 . The vertical signal line Vsig corresponds to the vertical signal line 47 in FIG9 . The pixel array PA is, for example, an array of n columns × m rows. FIG10 illustrates the pixel 10 in the i-th column and j-th row of the pixel array PA. Therefore, the reset control line en_rst Indicates the reset control line en_rst of the i-th column, the vertical signal line Vsig <j>Indicates the vertical signal line Vsig of the j-th row.

[0146] The pixel electrode 11 is an electrode for capturing signal charges generated in the photoelectric conversion layer 12. At least one pixel electrode 11 is present in each pixel 10. The signal charges captured by the pixel electrode 11 are accumulated in the charge accumulation unit 41 via the plug 31. The voltage corresponding to the signal charges accumulated in the charge accumulation unit 41 is read by the signal detection circuit 22.

[0147] The photoelectric conversion layer 12 is located between the pixel electrode 11 and the counter electrode 13 . The photoelectric conversion layer 12 is also located between the shielding electrode 17 and the counter electrode 13 .

[0148] The counter electrode 13 is disposed on the side of the photoelectric conversion layer 12 for incident light. Therefore, light passing through the counter electrode 13 is incident on the photoelectric conversion layer 12.

[0149] A voltage is applied to the counter electrode 13 from the voltage supply circuit 32. By adjusting the voltage applied to the counter electrode 13 by the voltage supply circuit 32, a bias voltage, which is the potential difference between the counter electrode 13 and the pixel electrode 11, can be set and maintained at a desired value.

[0150] Furthermore, the counter electrode 13 is formed, for example, to cover a plurality of pixels 10. Therefore, a desired voltage can be applied simultaneously to the plurality of pixels 10 from the voltage supply circuit 32. By varying the voltage applied to the counter electrode 13, the sensitivity of the photoelectric conversion unit 20 can be adjusted. Furthermore, as long as the desired voltage can be applied from the voltage supply circuit 32, the counter electrode 13 can be provided separately for each pixel 10. Similarly, the photoelectric conversion layer 12, the electron blocking layer 15, and the hole blocking layer 16 can each be formed to cover a plurality of pixels 10, or they can be provided separately for each pixel 10.

[0151] The voltage applied to the photoelectric conversion layer 12 is the difference between the potential Vito of the counter electrode 13 and the potential Vfd of the charge storage unit 41. The potential Vfd of the charge storage unit 41 varies according to the amount of signal charge stored in response to the amount of light incident on the photoelectric conversion layer 12.

[0152] The shield electrode 17 is arranged opposite the counter electrode 13, sandwiching the photoelectric conversion layer 12. The shield electrode 17 is located below the photoelectric conversion section 20. The shield electrode 17 is in contact with the lower surface of the photoelectric conversion section 20. Furthermore, although not shown in FIG10 , as described above, the shield electrode 17 is connected to the sensitivity control line 45 and receives a voltage from the voltage supply circuit 35 via the sensitivity control line 45. Furthermore, a portion of the interlayer insulating layer 62 may be disposed between the shield electrode 17 and the photoelectric conversion section 20. In other words, the shield electrode 17 and the photoelectric conversion section 20 do not need to be in contact.

[0153] The shield electrode 17 is formed of a conductive material. The conductive material is, for example, polysilicon that has been made conductive by doping with a metal such as aluminum or copper, a metal nitride, or impurities.

[0154] The voltage applied to the shielding electrode 17 can be used to suppress the movement of signal charges between pixels 10, or so-called crosstalk. Therefore, color mixing can be suppressed even without physically separating the photoelectric conversion layer 12. The voltage applied to the shielding electrode 17 is set, for example, to a higher potential than that of the pixel electrodes 11. For example, a voltage higher than the reset voltage Vr is applied to the shielding electrode 17. This makes it easier for holes to migrate to the pixel electrodes 11 surrounded by the shielding electrode 17 when viewed from above, thus suppressing the migration of holes to the pixel electrodes 11 of adjacent pixels 10 beyond the shielding electrode 17.

[0155] Furthermore, the voltage applied to the shielding electrode 17 can be set to a lower potential than that of the pixel electrode 11. For example, a voltage lower than the reset voltage Vr can be applied to the shielding electrode 17. This allows holes that attempt to migrate beyond the shielding electrode 17 to the pixel electrode 11 of an adjacent pixel 10 in a plan view to be captured by the shielding electrode 17, thereby preventing the holes from migrating beyond the shielding electrode 17 to the pixel electrode 11 of the adjacent pixel 10.

[0156] Furthermore, the imaging element 100 may not include the sensitivity control line 45 and the voltage supply circuit 35, and the shield electrode 17 may be connected to the ground of the imaging element 100. This can also suppress crosstalk.

[0157] [Method for manufacturing an imaging element] Next, a method for manufacturing the image sensor 100 of this embodiment will be described. FIG11 is a flow chart of the method for manufacturing the image sensor 100 of this embodiment.

[0158] As shown in FIG11 , in the manufacturing method of the imaging element 100 , a wafer 1 is first manufactured (step S21 ). For example, the wafer 1 shown in FIG2 can be manufactured using a general semiconductor manufacturing process and a film forming process.

[0159] Next, the wafer 1 is inspected (step S22). In step S22, for example, the inspection method described in steps S11 and S12 is used for inspection.

[0160] Next, the inspection results of step S22 are compared with the judgment criteria (step S23). Specifically, by comparing the inspection results of step S22 with the judgment criteria, the quality of the photoelectric conversion layer 12 is determined to be good or bad. In step S23, the same method as step S13 is used.

[0161] Next, the subsequent manufacturing process continues (step S24) for the imaging element region A1 containing the photoelectric conversion layer 12 determined to be good in step S23. That is, if the photoelectric conversion layer 12 is determined to be good in step S23, the subsequent manufacturing process continues. Subsequent manufacturing processes include, for example, dicing the wafer 1 into individual imaging element regions A1, connecting the wafers corresponding to the imaging element regions A1 to an external substrate having peripheral circuits formed thereon, and packaging. This allows the manufacturing of the imaging element 100. In step S24, for example, the wafers corresponding to the imaging element regions A1 containing the photoelectric conversion layer 12 determined to be good are used to manufacture the imaging element 100. On the other hand, for example, the wafers corresponding to the imaging element regions A1 containing the photoelectric conversion layer 12 determined to be defective are removed and not used in the manufacturing of the imaging element 100.

[0162] Furthermore, other inspections other than the inspection of the photoelectric conversion layer 12 in step S22 may be performed on the wafer 1. In this case, the results of the other inspections are also compared with the judgment criteria, and the subsequent manufacturing process may be continued for the imaging element area A1 of the photoelectric conversion layer 12 that is also judged as good by the results of the other inspections.

[0163] By using the above-described method for manufacturing the imaging element 100, the imaging element 100 can be manufactured after the wafer including the photoelectric conversion layer 12 determined to be defective is removed. This can avoid manufacturing defective imaging elements 100 before the final process, thereby suppressing cost increases.

[0164] [Modification] Furthermore, the configuration of wafer 1 and imaging element 100 is not limited to the above example; they may have the configuration of a known multilayer image sensor. Below, a description will be given of a wafer 1a having a photoelectric conversion layer 12a formed of a compound semiconductor such as InGaAs, and an imaging element manufactured from wafer 1a. In the following description of the modified examples, the description of points common to the embodiment will be omitted or simplified.

[0165] Figure 12 is a cross-sectional view of wafer 1a according to this variation. Figure 13 is a cross-sectional view of an exemplary device structure of pixel 10a according to this variation. Figure 12 illustrates a portion of wafer 1a corresponding to imaging element region A1 shown in Figure 2 . Furthermore, detailed configurations within the CMOS circuit layer are omitted in Figures 12 and 13 . Wafer 1a differs primarily from wafer 1 according to the embodiment in that it includes a photoelectric conversion unit 20a, replacing photoelectric conversion unit 20. The imaging element manufactured from wafer 1a has the configuration of pixel 10a shown in Figure 13 , replacing pixel 10 of imaging element 100 according to the embodiment.

[0166] Wafer 1a includes: CMOS circuit layer 60, insulating layer 63, insulating layer 64, multiple pixel electrodes 11, shielding electrode 17, electrode pad 51, electrode pad 52, extraction electrode 55, photoelectric conversion layer 12a, counter electrode 13, carrier transport layer 18, carrier transport layer 19, impurity diffusion region 9, and impurity diffusion region 9a. FIG. 12 shows only the pixel electrode 11 and shielding electrode 17 corresponding to one pixel 10a in the pixel array.

[0167] Insulation layer 63 and insulation layer 64 are sequentially stacked above CMOS circuit layer 60. Insulation layer 63 and interlayer insulation layer 62 of CMOS circuit layer 60 are bonded by hybrid bonding, which includes metal-metal bonding and dielectric-dielectric bonding.

[0168] A plurality of pixel electrodes 11, a photoelectric conversion layer 12a, a counter electrode 13, a carrier transport layer 18, a carrier transport layer 19, and an impurity diffusion region 9 constitute a photoelectric conversion portion 20a above a CMOS circuit layer 60. A portion of an insulating layer 63 is positioned between the photoelectric conversion portion 20a and the CMOS circuit layer 60. A shield electrode 17 and an impurity diffusion region 9a are positioned between the photoelectric conversion portion 20a and the CMOS circuit layer 60.

[0169] The photoelectric conversion layer 12 a is made of, for example, a compound semiconductor such as n-type InGaAs.

[0170] The impurity diffusion region 9 is positioned between the pixel electrode 11 and the photoelectric conversion layer 12a, and is in contact with the pixel electrode 11 and the photoelectric conversion layer 12a. The impurity diffusion region 9a is positioned between the shield electrode 17 and the photoelectric conversion layer 12a, and is in contact with the shield electrode 17 and the photoelectric conversion layer 12a. The impurity diffusion region 9 and the impurity diffusion region 9a are p-type impurity diffusion regions doped with p-type impurities such as Zn, and are responsible for capturing signal charges. Signal charges generated by photoelectric conversion in the photoelectric conversion layer 12a are collected by the impurity diffusion region 9 and the impurity diffusion region 9a due to diffusion caused by the bias voltage between the counter electrode 13 and the pixel electrode 11 and the difference in signal charge concentration. The signal charges collected by the impurity diffusion region 9 are captured by the pixel electrode 11 and stored in the charge storage unit 41 via the plugs 31a and 31. The signal charges collected by the impurity diffusion region 9a are captured by the shield electrode 17.

[0171] Carrier transport layer 18 transports holes, the signal charges generated in photoelectric conversion layer 12a, toward pixel electrode 11 while suppressing electron injection from pixel electrode 11 into photoelectric conversion layer 12a. Furthermore, carrier transport layer 19 transports electrons, charges opposite to the signal charges generated in photoelectric conversion layer 12a, toward counter electrode 13 while suppressing hole injection from counter electrode 13 into photoelectric conversion layer 12a. Carrier transport layers 18 and 19 are each composed of, for example, n-type InP.

[0172] The photoelectric conversion layer 12a, composed of n-type InGaAs, is grown on another InP substrate, for example. The carrier transport layers 18 and 19 also function as buffer layers, which help to maintain a uniform lattice constant and grow the n-type InGaAs layer with low defects during the formation of the photoelectric conversion layer 12a.

[0173] Plug 31a is provided at the lower end of insulating layer 63, connecting pixel electrode 11 and plug 31. A metal-metal bond is formed at the interface between plug 31a and plug 31. When plug 31a and plug 31 are made of copper (Cu), a Cu-Cu bond is formed at the interface between plug 31a and plug 31.

[0174] Plug 31d is disposed at the lower end of insulating layer 63, connecting shield electrode 17 to plug 31c disposed in interlayer insulating layer 62. A metal-to-metal bond, such as a Cu-Cu bond, is formed at the interface between plugs 31d and 31c. Shield electrode 17 is electrically connected to electrode pad 52 via plugs 31d and 31c.

[0175] Lead-out electrode 55a is disposed at the lower end of insulating layer 63 and contacts counter electrode 13 and lead-out electrode 55. A metal-to-metal bond, such as a Cu-Cu bond, is formed at the interface between lead-out electrode 55a and lead-out electrode 55. Counter electrode 13 is electrically connected to electrode pad 51 via lead-out electrode 55a and lead-out electrode 55.

[0176] Electrode pads 51 and 52 are formed on the CMOS circuit layer 60. Openings are formed in the insulating layers 63 and 64 to expose the electrode pads 51 and 52. Furthermore, the electrode pad 51 can be formed on or in the insulating layer 63, or on or in the insulating layer 64, as long as it is electrically connected to the counter electrode 13. Similarly, the electrode pad 52 can be formed on or in the insulating layer 63, or on or in the insulating layer 64, as long as it is electrically connected to the shielding electrode 17.

[0177] Similar to wafer 1 in the embodiment, probe terminals 201 and 202 can be used to apply a voltage between electrode pads 51 and 52, and the current flowing between electrode pads 51 and 52 can be measured. Specifically, the quality of photoelectric conversion layer 12a of wafer 1a can be inspected using the inspection method described in FIG. 5 . Furthermore, an imaging device can be manufactured from wafer 1a using the manufacturing method described in FIG. 11 .

[0178] (Other embodiments) The wafer, inspection method, imaging element, and imaging element manufacturing method of the present disclosure have been described above based on the embodiments, but the present disclosure is not limited to these embodiments.

[0179] For example, in the inspection method of the above-described embodiment, a voltage is applied between electrode pads 51 and 52 on wafer 1 or 1a, and the current flowing between electrode pads 51 and 52 is measured. However, this is not limiting. The inspection method disclosed herein can also be performed on devices formed by singulating wafer 1 or 1a. Furthermore, the inspection method disclosed herein can also be performed on imaging elements incorporated into a camera system or sensor system. In this case, the imaging element is an example of a device. Thus, the term "device" in this disclosure encompasses not only completed devices but also intermediate components in various states produced during the manufacturing process.

[0180] Furthermore, for example, in the inspection method of the above embodiment, the quality of the photoelectric conversion layer 12 is determined to be good or bad, but this is not limiting. The inspection method of the present disclosure may not determine the quality of the photoelectric conversion layer 12. For example, the inspection method of the present disclosure may also record the current measured in step S12.

[0181] Furthermore, the wafer and imaging element disclosed herein may not include all of the components described in the above embodiments, and may be composed of only components for performing the target operation.

[0182] Furthermore, the overall or specific aspects of the present disclosure may be implemented by an inspection apparatus that performs the inspection method of the above-mentioned embodiment, or may be implemented by a manufacturing apparatus that performs the manufacturing method of the imaging element of the above-mentioned embodiment.

[0183] In addition, without departing from the scope of the present disclosure, various modifications that can be conceived by those skilled in the art to implement the embodiments and examples, as well as other forms constructed by combining some of the constituent elements of the embodiments and examples are also included in the scope of the present disclosure.

[0184] Industrial applicability The inspection method and imaging element manufacturing method disclosed herein can be used in imaging elements suitable for various camera systems and sensor systems for mobile devices, medical applications, monitoring applications, vehicle applications, measurement applications including distance measurement, drones, robots, and the like.

[0185] 1,1a: Wafer 9,9a: Impurity diffusion region 10,10a: pixels 11: Pixel electrode 12,12a: Photoelectric conversion layer 13: Counter electrode 15:Electron blocking layer 16: Hole blocking layer 17: Shielding electrode 18,19: Carrier transport layer 20,20a: Photoelectric conversion unit 21: Sealing layer 22: Signal detection circuit 24: Signal detection transistor 26: Address transistor 28: Reset transistor 31,31a,31c,31d: plug 32,35: Voltage supply circuit 34: Reset voltage source 36: Vertical scanning circuit 37: Line signal processing circuit 38: Horizontal signal reading circuit 39: Pixel drive signal generating circuit 40: Power cord 41: Charge storage unit 42,45: Sensitivity control line 44: Reset voltage line 46: Address control line 47: Vertical signal line 48: Reset control line 49: horizontal common signal line 51,52: Electrode pads 55,55a: Lead-out electrode 60:CMOS circuit layer 61:Semiconductor substrate 62: Interlayer insulation layer 63,64: Insulation layer 100: Camera element 200: Measuring device 201,202: Probe terminals A1: Camera component area A2: Cutting area FD: Floating Diffusion PA: Pixel Array S11~S13: Steps S21~S24: Steps VDD: power supply voltage Vfd: potential Vito: Potential Vr: reset voltage Vsig: vertical signal line en_rst: reset control line Vsig <j>: Vertical signal line of row j en_rst : Reset control line for column i < / j> < / j>

Claims

1. A method for inspection, comprising: a process for preparing a device, the device comprising: a plurality of pixel electrodes; a counter electrode disposed opposite to the plurality of pixel electrodes; a photoelectric conversion layer disposed between the plurality of pixel electrodes and the counter electrode; a test electrode sandwiching the photoelectric conversion layer and opposing the counter electrode, and disposed between two adjacent pixel electrodes among the plurality of pixel electrodes; a first electrode pad electrically connected to the counter electrode and exposed to the outside; and a second electrode pad electrically connected to the test electrode and exposed to the outside; and a process for measuring current, wherein a voltage is applied between the first electrode pad and the second electrode pad, and the current flowing between the first electrode pad and the second electrode pad is measured.

2. The inspection method of claim 1, wherein the aforementioned device further includes a charge storage section, the aforementioned charge storage section stores the charge obtained from the aforementioned photoelectric conversion layer, a plurality of the aforementioned pixel electrodes are electrically connected to the aforementioned charge storage section, and the aforementioned test electrodes are not electrically connected to the aforementioned charge storage section.

3. The inspection method as requested in claim 1, wherein the aforementioned test electrodes have the same potential throughout the entire area where a plurality of the aforementioned pixel electrodes are disposed.

4. The inspection method as claimed in claim 3, wherein the aforementioned photoelectric conversion layer converts light incident on the aforementioned photoelectric conversion layer into charge, and a plurality of the aforementioned pixel electrodes capture the aforementioned charge, and when the aforementioned charge is captured by the plurality of the aforementioned pixel electrodes, the aforementioned test electrode functions as a shield to suppress the movement of the aforementioned charge between the plurality of the aforementioned pixel electrodes.

5. The inspection method as requested in item 1, wherein the aforementioned test electrode surrounds each of the plurality of the aforementioned pixel electrodes.

6. The inspection method as described in claim 5, wherein the aforementioned test electrodes are arranged in a grid pattern in the area where a plurality of the aforementioned pixel electrodes are disposed.

7. The inspection method of any one of claims 1 to 6 further includes determining the good or bad of the aforementioned photoelectric conversion layer based on the aforementioned current.

8. The inspection method of claim 7, wherein in the process of measuring the aforementioned current, a predetermined voltage is applied between the aforementioned first electrode pad and the aforementioned second electrode pad; in the process of determining whether the aforementioned photoelectric conversion layer is good or bad, when the value of the aforementioned current flowing between the aforementioned first electrode pad and the aforementioned second electrode pad when the aforementioned predetermined voltage is applied is greater than or equal to a predetermined current value, the aforementioned photoelectric conversion layer is determined to be bad; when the value of the aforementioned current is less than the aforementioned predetermined current value, the aforementioned photoelectric conversion layer is determined to be good.

9. The inspection method of claim 7, wherein in the process of measuring the aforementioned current, the voltage applied between the aforementioned first electrode pad and the aforementioned second electrode pad is scanned to measure the current-voltage characteristics between the aforementioned first electrode pad and the aforementioned second electrode pad, and in the process of determining whether the aforementioned photoelectric conversion layer is good or bad, the aforementioned photoelectric conversion layer is determined to be good or bad based on the aforementioned current-voltage characteristics.

10. The inspection method as claimed in claim 9, wherein in the process of determining whether the aforementioned photoelectric conversion layer is good or bad, the determination of whether the aforementioned photoelectric conversion layer is good or bad is based on the slope in the aforementioned current-voltage characteristics.

11. A method for manufacturing a camera element, comprising: a process for fabricating a device, the device comprising: a plurality of pixel electrodes; a counter electrode disposed opposite to the plurality of pixel electrodes; a photoelectric conversion layer disposed between the plurality of pixel electrodes and the counter electrode; a test electrode sandwiching the photoelectric conversion layer and opposing the counter electrode, and disposed between two adjacent pixel electrodes among the plurality of pixel electrodes; a first electrode pad electrically connected to the counter electrode and exposed to the outside; and a second electrode pad electrically connected to the test electrode and exposed to the outside; and a process for inspecting the device by means of the inspection method of claim 7; if the photoelectric conversion layer is determined to be good during the inspection, the process of forming a camera element in the device continues; if the photoelectric conversion layer is determined to be defective during the inspection, the process of forming the camera element is not continued.

12. An imaging device comprising: a plurality of pixel electrodes; a counter electrode disposed opposite to the plurality of pixel electrodes; a photoelectric conversion layer disposed between the plurality of pixel electrodes and the counter electrode; a test electrode sandwiching the photoelectric conversion layer and opposing the counter electrode, and disposed between two adjacent pixel electrodes among the plurality of pixel electrodes; a first electrode pad electrically connected to the counter electrode; and a second electrode pad electrically connected to the test electrode.

Images