Semiconductor structure and forming method thereof

Abstract

The present invention provides a semiconductor structure comprising a plurality of MTJ (Magnetic tunnel junctions) elements. From a top view, the plurality of MTJ elements are arranged in an array. At least one second contact structure is located in the array of MTJ elements. At least one first masking layer covers a top surface and two sidewalls of each MTJ element. From a cross-sectional view, a cross-sectional sidewall of the first masking layer is flush with a sidewall of a second metal layer below the second contact structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to an arrangement pattern of magnetic tunneling junction (MTJ) elements and contact structures and a method for forming the same. Prior Art

[0002] The magnetoresistance (MR) effect is known to occur when a material's electrical resistance changes with an applied magnetic field. Its physical quantity is defined as the difference in resistance in the presence and absence of a magnetic field divided by the initial resistance, representing the rate of change. Currently, the MR effect has been successfully applied in hard drive production and holds significant commercial value. Furthermore, by exploiting the characteristic of giant magnetoresistance materials exhibiting varying resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can be fabricated. This advantage allows the material to retain stored data even when power is off.

[0003] The magnetoresistance effect is also used in magnetic field sensing. For example, electronic compass components used in mobile phones with global positioning systems (GPS) provide information such as the user's location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistance (AMR) sensors, giant magnetoresistance (GMR) sensors, and magnetic tunneling junction (MTJ) sensors. However, these prior technologies often suffer from drawbacks such as increased chip area, more expensive manufacturing processes, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvement. Summary of the Invention

[0004] The present invention provides a semiconductor structure comprising a plurality of MTJ (Magnetic Tunnel Junction) elements. From a top view, the plurality of MTJ elements are arranged in an array. At least one second contact structure is located within the array of MTJ elements. At least one first mask layer covers a top surface and two side walls of each MTJ element. From a cross-sectional view, a cross-sectional sidewall of the first mask layer is aligned with a sidewall of a second metal layer below the second contact structure.

[0005] The present invention further provides a method for forming a semiconductor structure, comprising forming a plurality of MTJ (Magnetic Tunnel Junction) elements. From a top view, the plurality of MTJ elements are arranged in an array, forming at least one second metal layer located within the array of MTJ elements, forming a first mask layer covering each MTJ element and covering each MTJ element and a top surface of the second metal layer, forming a second mask layer covering the first mask layer, performing a first etching step to remove the second mask layer above the second metal layer, and performing a second etching step to remove the first mask layer above the second metal layer and expose the top surface of the second metal layer.

[0006] To achieve closer alignment between the MTJ elements and the second contact structures, the present invention designs a unique pattern for the MTJ element array and the second contact structures. The second contact structures are arranged within the lateral gaps between the MTJ elements, without altering the original dimensions of the MTJ element array. However, the small spacing of this pattern can easily lead to exposure defects during the manufacturing process. Therefore, the present invention also proposes a double exposure and dicing method. This method can form a tightly spaced MTJ element array and contact structures without causing device exposure defects. Simple diagram description

[0007] FIG. 1 is a top view schematically illustrating the arrangement of an MTJ element, a second metal layer, and a contact structure according to a first embodiment of the present invention. FIG. 2 is a top view schematically illustrating the arrangement of an MTJ element, a second metal layer, and a contact structure according to a second embodiment of the present invention. FIG3 is a schematic cross-sectional view of the structure taken along section line AA′ and section line BB′ of FIG2 . FIG4 is a top view schematically illustrating the semiconductor structure after forming the first photoresist layer according to the present invention. FIG5 is a schematic diagram illustrating a cross-sectional structure after forming a first photoresist layer based on the cross-sectional structure of FIG3. FIG6 is a schematic diagram showing the cross-sectional structure of FIG5 after a portion of the second mask layer is removed. FIG. 7 is a top view schematically illustrating the semiconductor structure after forming the second photoresist layer according to the present invention. FIG8 is a schematic diagram illustrating a cross-sectional structure after forming a second photoresist layer based on the cross-sectional structure of FIG6. FIG9 is a schematic diagram illustrating the cross-sectional structure of FIG8 after partially removing the first mask layer and the second photoresist layer. FIG10 is a schematic diagram illustrating the cross-sectional structure of FIG9 after the second mask layer is completely removed and the second contact structure is formed. Implementation Method

[0008] In order to enable those skilled in the art to further understand the present invention, the following lists preferred embodiments of the present invention and describes in detail the components and intended effects of the present invention in conjunction with the accompanying drawings.

[0009] For ease of explanation, the various figures of the present invention are merely illustrative to facilitate understanding of the present invention. The detailed proportions may be adjusted based on design requirements. Those skilled in the art will readily understand that the upper and lower relationships between components depicted in the figures refer to the relative positions of the objects. Therefore, the figures can be reversed to present the same components, and this is fully within the scope of this specification. This is further clarified.

[0010] Please refer to Figure 1, which illustrates a top view schematically illustrating the arrangement of an MTJ element, a second metal layer, and a contact structure according to a first embodiment of the present invention. First, a plurality of magnetic tunnel junctions (MTJ) elements 10 are formed on one layer of a semiconductor stack structure, each MTJ element being arranged in an array. Furthermore, a plurality of second contact structures V2 are arranged adjacent to the MTJ elements 10. In this embodiment, the MTJ elements 10 and the second contact structures are both formed on one of the metal layers in the semiconductor structure, such as the second lateral metal conductor layer from bottom to top during the manufacturing process, often referred to as the second metal layer (M2). However, the present invention is not limited thereto. In practice, the MTJ elements 10 and the second contact structures V2 can be formed on other metal layers in the semiconductor structure, such as the first metal layer (M1) or the third metal layer (M3), and are thus within the scope of the present invention.

[0011] The second contact structure V2 can connect to other electronic components, such as word lines, transistors, and other electronic components within the logic area, but is not limited thereto. In this embodiment, the second contact structure V2 is inserted between the array of MTJ elements 10. Because the second contact structure V2 must be formed, the spacing of the original array of MTJ elements 10 needs to be adjusted to accommodate the second contact structure V2. For example, as shown in Figure 1, the original MTJ elements 10 have a horizontal spacing of X1 and a vertical spacing of Y1 (along the X and Y directions of Figure 1, respectively). However, due to the insertion of multiple second contact structures V2 into the array of MTJ elements 10, the spacing between some MTJ elements 10 is extended to Y1', where Y1' is greater than Y1. This, because a certain amount of space must be reserved to accommodate the second contact structure V2, is not conducive to device miniaturization.

[0012] In another embodiment of the present invention, the position of the second contact structure V2 is adjusted to allow for a tighter arrangement within the array of MTJ elements 10. Unlike the first embodiment, the second contact structure V2 is located in the lateral gap between adjacent MTJ elements 10. Therefore, the arrangement shown in FIG2 does not increase the gap between the MTJ elements 10 due to the insertion of the second contact structure V2. Specifically, the MTJ elements 10 in FIG2 can be defined as MTJ element 10A, MTJ element 10B, MTJ element 10C, and MTJ element 10D. MTJ elements 10A and 10C are located in the same row (aligned along the Y axis), MTJ elements 10B and 10D are located in the same row (aligned along the Y axis), MTJ elements 10A and 10B are located in the same column (aligned along the X axis), and MTJ elements 10C and 10D are located in the same column (aligned along the X axis). In this embodiment, the second contact structure V2 is located, for example, between the MTJ element 10A and the MTJ element 10B in the lateral direction (X direction). However, the second contact structure V2 is not located between the MTJ element 10C and the MTJ element 10D in the lateral direction. Therefore, the lateral distance between the MTJ element 10A and the MTJ element 10B is equal to the pitch X1 described in the first embodiment, and the lateral distance between the MTJ element 10C and the MTJ element 10D is also equal to the pitch X1 described in the first embodiment. Furthermore, in this embodiment, the longitudinal spacing between all adjacent MTJ elements 10 is Y1, unlike the spacing between some adjacent MTJ elements 10 in FIG. 1, where the spacing is extended to Y1'.

[0013] The arrangement shown in FIG. 2 facilitates reducing the overall size of the components. However, in actual manufacturing, due to the closer arrangement of components, some difficulties may be encountered during the fabrication process. For example, when the component spacing is small, such as when the distance D1 between the MTJ element 10 and the second contact structure V2 in FIG. 2 is less than approximately 50 nanometers, the current process technology is more likely to encounter exposure issues when forming the pattern of the second contact structure V2. For example, when removing the mask (not shown) on the surface of the second contact structure V2, it may also affect the surrounding MTJ elements, causing process contamination. Alternatively, the exposure range set during the formation of the second contact structure V2 is small, which can easily lead to exposure failures or pattern deformation.

[0014] To achieve a closer alignment between the MTJ element and the second contact structure while simultaneously addressing the aforementioned exposure issues, the present invention provides a double exposure method for forming a specially arranged element pattern, as shown in FIG2 . This method offers advantages such as improved element quality and reduced element size. Details are provided in the following paragraphs.

[0015] FIG3 illustrates a schematic cross-sectional view of the structure taken along section lines AA' and BB' of FIG2. As shown in FIG3, the structure first includes a substrate 100, such as a substrate 100 made of a semiconductor material. The semiconductor material may be selected from the group consisting of silicon, germanium, a silicon-germanium composite, silicon carbide, gallium arsenide, and the like.

[0016] The substrate 100 may include active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and dielectric layers such as interlayer dielectrics (ILDs) covering the substrate 100. More specifically, the substrate 100 may include a planar or non-planar MOS transistor T (e.g., a fin-structured transistor). The MOS transistor T may include transistor elements such as a gate structure (e.g., a metal gate), source / drain regions, sidewalls, an epitaxial layer, and a contact etch stop layer. An interlayer dielectric (ILD) may be disposed on the substrate 100 and cover the MOS transistor T. The ILD may have a plurality of contact plugs (CT) electrically connected to the gate and / or source / drain regions of the MOS transistor T. Since the processes associated with planar or non-planar transistors and interlayer dielectrics are well known in the art, they will not be further described here.

[0017] An intermetallic dielectric (IMD) layer is then formed on the interlayer dielectric (ILD) layer. A first metal layer M1, a first contact structure V1, and a second metal layer M2 are sequentially formed in the IMD layer to electrically connect to the aforementioned contact plugs CT. In this embodiment, the first contact structure V1 can be embedded in the IMD layer IMD using either a single damascene process or a dual damascene process and electrically connected to each other. For example, the first contact structure V1 may further comprise a barrier layer (not shown) and a metal layer. The barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer may be selected from the group consisting of, but not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene or dual damascene processes are well known in the art, they will not be further described here. In this embodiment, the metals of the first metal layer M1, the second metal layer M2, or the subsequently formed third metal layer M3 preferably include a highly conductive metal such as copper or tungsten. The interlayer dielectric layer ILD and the intermetallic dielectric layer IMD preferably include silicon oxide or an ultra-low-k dielectric layer, but are not limited thereto.

[0018] A contact structure WV can then be formed on a portion of the second metal layer M2. The contact structure may be made of, for example, but not limited to, tungsten. A bottom electrode BE, an MTJ element 10, and a top electrode TE are then sequentially formed on the contact structure WV. The bottom electrode layer BE and the top electrode TE preferably comprise a conductive material, such as, but not limited to, tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or a combination thereof. The MTJ element 10 described herein is equivalent to the MTJ element 10 described in Figures 1-2. The MTJ element 10 may be a stacked structure consisting of a pinned layer, a barrier layer, and a free layer located between the bottom electrode BE and the top electrode TE. The pinned layer may comprise a ferromagnetic material, such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), or cobalt (Co), to pin or constrain the magnetic moment direction of adjacent layers. The barrier layer can be made of an insulating material containing an oxide, such as aluminum oxide (AlOx) or magnesium oxide (MgO), but is not limited thereto. The free layers, including the first and second free layers, can be made of ferromagnetic materials, such as iron, cobalt, nickel, or alloys thereof, such as cobalt-iron-boron (CoFeB) and nickel-iron (NiFe), but are not limited thereto. The magnetization direction of the free layer is "free" to change in response to an external magnetic field. Other materials and fabrication methods for the contact structure WV and the MTJ element 10 are well known in the art and will not be elaborated upon here.

[0019] As shown in FIG3 , a first mask layer HM1 and a second mask layer HM2 are further formed to completely cover the second metal layer M2 and the MTJ element 10. The first mask layer HM1 and the second mask layer HM2 are made of different materials. For example, the first mask layer HM1 is made of silicon nitride, and the second mask layer HM2 is made of titanium nitride (TiN), but the present invention is not limited to this. In subsequent steps, a second contact structure (equivalent to the second contact structure V2 in FIG2 ) will be formed on the top surface of the second metal layer M2 located adjacent to the MTJ element 10 in the X direction. To allow the second contact structure to electrically connect to the second metal layer M2, the first mask layer HM1 and the second mask layer HM2 on the top surface of the second metal layer M2 are removed without affecting the MTJ element 10.

[0020] FIG4 illustrates a top view of the semiconductor structure after forming the first photoresist layer according to the present invention. FIG5 illustrates a cross-sectional view of the structure after forming the first photoresist layer based on the cross-sectional structure of FIG3. Referring to FIG4 and FIG5 together, a first patterned photoresist layer PR1 is formed to cover each MTJ element 10. It is noteworthy that the first patterned photoresist layer PR1 comprises a plurality of parallel stripes, for example, along the Y direction, covering each MTJ element 10, but not covering the location where the second contact structure V2 is intended to be formed (the dotted line in FIG4 indicates the location where the second contact structure V2 is intended to be formed, but it is understood that the second contact structure V2 has not yet been formed).

[0021] FIG6 illustrates a cross-sectional view of the structure of FIG5 after a portion of the second mask layer has been removed. As shown in FIG6 , a first etching step E1 is performed using the first patterned photoresist layer PR1 as a mask to remove the second mask layer HM2 not covered by the first patterned photoresist layer PR1. Subsequently, the first patterned photoresist layer PR1 is removed. The etching step described herein may include various dry or wet etching processes. The etching step and the method for removing the photoresist are well known in the art and will not be described in detail here.

[0022] FIG7 illustrates a top view of the semiconductor structure after forming the second photoresist layer according to the present invention. FIG8 illustrates a cross-sectional view of the structure after forming the second photoresist layer based on the cross-sectional structure of FIG6 . Referring to FIG7 and FIG8 together, a second patterned photoresist layer PR2 is formed to cover a portion of the MTJ element 10. The second patterned photoresist layer PR2 includes an opening OP along the X-direction, exposing a portion of the MTJ element 10, the second metal layer M2, and the location where the second contact structure V2 is to be formed.

[0023] Next, please refer to FIG. 9 , which illustrates a cross-sectional structure after portions of the first mask layer and the second photoresist layer have been removed based on the cross-sectional structure of FIG. A second etching step E2 is performed to remove portions of the first mask layer HM1 not covered by the second mask layer HM2. At this point, all mask layers on top of the second metal layer M2 adjacent to the MTJ element 10 in the X direction in FIG. 9 have been removed, exposing the surface of the second metal layer M2.

[0024] It is noteworthy that in this embodiment, when the first mask layer HM1 on the surface of the second metal layer M2 is removed, the sidewalls of the surrounding MTJ element 10 are still covered by the first mask layer HM1 and the second mask layer HM2, effectively protecting the MTJ element 10 from etching. Furthermore, in this embodiment, preferably, after the second etching step, the first mask layer HM1 and the second mask layer HM2 form a sidewall S1 that is flush with the sidewall S2 of the second metal layer M2.

[0025] Figure 10 illustrates the cross-sectional structure of Figure 9 after the second mask layer is completely removed and the second contact structure is formed. As shown in Figure 10 , the second mask layer HM2 is completely removed, and a dielectric layer (not shown) is formed overlying the intermetallic dielectric layer IMD. A second contact structure V2 is then formed within the dielectric layer and electrically connected to the second metal layer M2. A third metal layer M3 is then formed to connect to the second contact structure V2. The second contact structure V2 described here is equivalent to the second contact structure V2 shown in Figures 1 or 2 above. The method of the present invention allows for the formation of tightly spaced MTJ device arrays and contact structures using a double exposure and dicing method without causing device exposure defects.

[0026] In summary, the present invention provides a semiconductor structure comprising a plurality of MTJ (Magnetic Tunnel Junction) elements 10. From a top view, the plurality of MTJ elements 10 are arranged in an array. At least one second contact structure V2 is located within the array of MTJ elements 10. At least one first mask layer HM1 covers a top surface and two sidewalls of each MTJ element 10. From a cross-sectional view, a cross-sectional sidewall S1 of the first mask layer HM1 is aligned with a sidewall S2 of the second metal layer M2 below the second contact structure V2.

[0027] In some embodiments of the present invention, when viewed from above, the array of MTJ elements 10 includes multiple rows, each row is arranged along a longitudinal direction (Y direction), the multiple rows include a first row and a second row adjacent to each other, and the second contact structure V2 is located between the first row and the second row (see Figure 2).

[0028] In some embodiments of the present invention, the first row includes a first MTJ element 10A and a third MTJ element 10C, and the second row includes a second MTJ element 10B and a fourth MTJ element 10D. When viewed from above, the distance X1 between the first MTJ element 10A and the second MTJ element 10B along a lateral direction (X direction) is equal to the distance between the third MTJ element 10C and the fourth MTJ element 10D along the lateral direction.

[0029] In some embodiments of the present invention, along the lateral direction, a connection line L1 between the first MTJ element 10A and the second MTJ element 10B passes through the second contact structure V2, but a connection line L2 between the third MTJ element 10C and the fourth MTJ element 10D does not pass through the second contact structure (as shown in FIG. 2 ).

[0030] Some embodiments of the present invention further include a plurality of contact structures WV, each of which is located below one of the MTJ elements and electrically connected to the MTJ element.

[0031] In some embodiments of the present invention, a bottom surface of the first mask layer HM1 is flush with a top surface of the second metal layer M2.

[0032] In some embodiments of the present invention, each MTJ element is not located on the second metal layer M2.

[0033] The present invention further provides a method for forming a semiconductor structure, comprising forming a plurality of MTJ (Magnetic Tunnel Junctions) elements 10. From a top view, the plurality of MTJ elements 10 are arranged in an array to form at least one second metal layer M2 located within the array of the MTJ elements 10. A first mask layer HM1 is formed to cover each MTJ element 10 and a top surface of the second metal layer M2. A second mask layer HM2 is formed to cover the first mask layer HM1. A first etching step E1 is performed to remove the second mask layer HM2 above the second metal layer M2. A second etching step E2 is performed to remove the first mask layer HM1 above the second metal layer M2 and expose the top surface of the second metal layer M2.

[0034] In some embodiments of the present invention, performing the first etching step E1 further includes: forming a first patterned photoresist layer PR1, the first patterned photoresist layer PR1 including a plurality of strip patterns arranged along a longitudinal direction and covering each MTJ element 10; performing the first etching step E1 to etch the area not covered by the first patterned photoresist layer PR1, removing the second mask layer HM2 above the second metal layer M2, and removing the first patterned photoresist layer PR1.

[0035] In some embodiments of the present invention, the second etching step E2 further includes: forming a second patterned photoresist layer PR2 to cover a portion of the plurality of MTJ elements 10, the second patterned photoresist layer PR2 including an opening OP extending along a lateral direction, the opening exposing another portion of the MTJ element 10 and the second metal layer M2, performing the second etching step E2 to etch the area not covered by the second patterned photoresist layer PR2, removing the first mask layer HM1 above the second metal layer M2, and removing the second patterned photoresist layer PR2.

[0036] In some embodiments of the present invention, after the second etching step E2 is performed, the second mask layer HM2 still covers the first mask layer HM1, and a cross-sectional sidewall of the first mask layer HM1, a cross-sectional sidewall (sidewall S1) of the second mask layer HM2, and a sidewall S2 of the second metal layer M2 are aligned.

[0037] In some embodiments of the present invention, after the second etching step E2, the first mask layer HM1 is further removed.

[0038] In summary, the present invention features a unique pattern of MTJ element arrays and second contact structures designed to achieve closer alignment between the MTJ elements and the second contact structures. The second contact structures are arranged within the lateral gaps between the MTJ elements, without altering the original dimensions of the MTJ element array. However, the small spacing of this pattern can easily lead to exposure defects during the manufacturing process. Therefore, the present invention also proposes a double exposure and dicing method. This method can form a tightly spaced MTJ element array and contact structures without causing exposure defects. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0039] 10: Magnetic Tunneling Junction (MTJ) Device 10A:MTJ element 10B:MTJ element 10C:MTJ element 10D:MTJ components 100: Base BE: Bottom electrode CT: Contact plug D1: Distance E1: First etching step E2: Second etching step HM1: First mask layer HM2: Second mask layer ILD: Interlayer Dielectric Layer IMD: Intermetal Dielectric OP: Opening PR1: first patterned photoresist layer PR2: Second patterned photoresist layer L1: Connection L2: Connection M1: First metal layer M2: Second metal layer M3: The third metal layer S1: Sidewall S2: Sidewall T: Metal Oxide Semiconductor Transistor TE: Upper electrode V1: first contact structure V2: Second contact structure WV: Contact structure X1: horizontal spacing Y1: vertical spacing Y1': vertical spacing

Claims

1. A semiconductor structure comprising: a plurality of MTJ (Magnetic tunnel junctions) elements, which, in a top view, are arranged in an array; at least one second contact structure located within the array of the MTJ elements; and at least one first masking layer covering a top surface and two sidewalls of each of the MTJ elements, wherein, in a cross-sectional view, a cross-sectional sidewall of the first masking layer is flush with a sidewall of a second metal layer beneath the second contact structure.

2. The semiconductor structure as described in claim 1, wherein, viewed from the top view, the array of the MTJ elements comprises multiple rows, each row being arranged along a longitudinal direction, the multiple rows comprising an adjacent first row and a second row, and the second contact structure being located between the first row and the second row.

3. The semiconductor structure as described in claim 2, wherein the first row includes a first MTJ element and a third MTJ element, the second row includes a second MTJ element and a fourth MTJ element, wherein, viewed from the top view, the distance between the first MTJ element and the second MTJ element along a lateral direction is equal to the distance between the third MTJ element and the fourth MTJ element along the lateral direction.

4. The semiconductor structure as described in claim 3, wherein along the lateral direction, a line connecting the first MTJ element and the second MTJ element passes through the second contact structure, but a line connecting the third MTJ element and the fourth MTJ element does not pass through the second contact structure.

5. The semiconductor structure as described in claim 1, further comprising a plurality of contact structures, each of which is located below one of the MTJ elements and is electrically connected to the MTJ element.

6. The semiconductor structure as described in claim 1, wherein a bottom surface of the first masking layer is flush with a top surface of the second metal layer.

7. The semiconductor structure as described in claim 1, wherein each of the MTJ elements is not located on the second metal layer.

8. A method for forming a semiconductor structure, comprising: forming a plurality of MTJ (Magnetic tunnel junctions) elements, wherein, from a top view, the plurality of MTJ elements are arranged in an array; forming at least one second metal layer located in the array of the MTJ elements; forming a first masking layer covering a top surface and sidewalls of each of the MTJ elements and a top surface of the second metal layer; forming a second masking layer covering the first masking layer; performing a first etching step to remove the second masking layer above the second metal layer; and performing a second etching step to remove the first masking layer above the second metal layer and expose the top surface of the second metal layer, wherein, after the second etching step, from a cross-sectional view, a cross-sectional sidewall of the first masking layer is flush with a sidewall of the second metal layer.

9. The method for forming a semiconductor structure as described in claim 8, wherein the first etching step further comprises: forming a first patterned photoresist layer, the first patterned photoresist layer comprising a plurality of strip patterns arranged along a longitudinal direction and covering each of the MTJ elements; performing the first etching step to etch the area not covered by the first patterned photoresist layer and remove the second masking layer above the second metal layer; and removing the first patterned photoresist layer.

10. The method for forming a semiconductor structure as described in claim 9, wherein the second etching step further comprises: forming a second patterned photoresist layer covering a portion of the plurality of MTJ elements, the second patterned photoresist layer including an opening extending in a lateral direction, the opening exposing another portion of the MTJ elements and the second metal layer; performing the second etching step to etch the area not covered by the second patterned photoresist layer and remove the first masking layer above the second metal layer; and removing the second patterned photoresist layer.

11. The method for forming a semiconductor structure as described in claim 10, wherein after the second etching step, the second masking layer still covers the first masking layer.

12. The method for forming a semiconductor structure as described in claim 8, wherein after the second etching step, the method further includes removing the second masking layer.

13. The method of forming a semiconductor structure as described in claim 8, further comprising forming a second contact structure on the second metal layer, and, as viewed from the top view, the array of MTJ elements comprises multiple rows, each row being arranged along a longitudinal direction, the multiple rows comprising an adjacent first row and a second row, and the second contact structure being located between the first row and the second row.

14. The method for forming a semiconductor structure as described in claim 13, wherein the first row includes a first MTJ element and a third MTJ element, the second row includes a second MTJ element and a fourth MTJ element, wherein, viewed from the top view, the distance between the first MTJ element and the second MTJ element along a lateral direction is equal to the distance between the third MTJ element and the fourth MTJ element along the lateral direction.

15. The method of forming a semiconductor structure as described in claim 14, wherein along the lateral direction, a line connecting the first MTJ element and the second MTJ element passes through the second contact structure, but a line connecting the third MTJ element and the fourth MTJ element does not pass through the second contact structure.

16. The method of forming a semiconductor structure as described in claim 8, further comprising forming a plurality of contact structures, each of the contact structures being located below one of the MTJ elements and electrically connected to the MTJ element.

17. The method for forming a semiconductor structure as described in claim 8, wherein a bottom surface of the first masking layer is flush with a top surface of the second metal layer.

18. The method of forming a semiconductor structure as described in claim 8, wherein each of the MTJ elements is not located on the second metal layer.

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