Memory device

Abstract

A memory device, a method of operating the memory device, and a test system including the memory device are disclosed. The memory device may include: a decoder group configured to receive a plurality of codewords including a plurality of symbols from outside the memory device and decode the plurality of codewords into a data pattern; a memory cell array configured to store the data pattern received from the decoder group and including a plurality of memory cells; and an encoder configured to encode the data pattern into the plurality of codewords including the plurality of symbols. The plurality of codewords may include illegal codewords and normal codewords, and the decoder group may be further configured to convert illegal codewords among the plurality of codewords into a fixed pattern, and the encoder may be configured to output the plurality of codewords to outside the memory device.

Description

Technical Field

[0001] The present inventive concept relates to a memory device, and more particularly, to a memory device capable of detecting an illegal codeword and outputting the detected codeword in a fixed pattern, a method of operating the memory device, and a test system including the memory device. [Cross - reference to Related Applications]

[0002] This application is based on and claims the priority of both Korean Patent Application No. 10 - 2022 - 0061654, filed on May 19, 2022, and Korean Patent Application No. 10 - 2022 - 0115178, filed on September 13, 2022, with the Korean Intellectual Property Office, and the entire contents of the above - mentioned applications are incorporated herein by reference. Prior Art

[0003] There is an increasing demand for dynamic random access memories (DRAMs) with high capacities (e.g., for stable and fast real - time processing of large amounts of data). However, the performance characteristics of DRAMs change over time. Memory systems may require DRAMs with reliability availability serviceability (RAS) functions.

[0004] Semiconductor wafers can be manufactured in a semiconductor manufacturing process and then tested by test equipment in a wafer state, a die state, or a packaged state. As the fine - process continues, the possibility of errors occurring in semiconductor wafers such as DRAMs during the manufacturing process increases. In addition, even if no errors are detected in the initial test step, errors may occur during the operation of the wafer. Summary of the Invention

[0005] The present inventive concept provides a memory device in which an illegal codeword is detected, the illegal codeword is output in a fixed pattern, and the illegal codeword is compared with input data, thereby enabling checking whether the memory device is counterfeit or not operating properly. The present inventive concept also provides a method of operating the memory device and a test system including the memory device.

[0006] According to some aspects of the present invention concept, a memory device may include a decoder group configured to receive a plurality of codewords including a plurality of symbols from an external device outside the memory device. The decoder group may be configured to decode the plurality of codewords into a data pattern. The memory device may include a memory cell array configured to store the data pattern received from the decoder group and may include a plurality of memory cells, and the memory device may include an encoder configured to encode the data pattern into the plurality of codewords including the plurality of symbols. The plurality of codewords may include illegal codewords and normal codewords, and the decoder group may be further configured to convert the illegal codewords among the plurality of codewords into a fixed pattern. The encoder may be further configured to output the plurality of codewords to the outside.

[0007] According to another aspect of the present invention concept, a method of operating a memory device may include: receiving a plurality of first codewords including a plurality of symbols from a device outside the memory device, decoding the plurality of first codewords into a data pattern, storing the decoded data pattern in a memory cell array, and reading the stored data pattern from the memory cell array and encoding the plurality of first codewords, wherein the plurality of first codewords include illegal codewords and normal codewords, and the decoding further includes converting the illegal codewords among the plurality of first codewords into a fixed pattern.

[0008] According to another aspect of the present invention concept, a test system may include a memory device and a test device, wherein the memory device includes: a decoder group configured to receive a plurality of first codewords including a plurality of symbols from outside the memory device and decode the plurality of first codewords into a data pattern; a memory cell array configured to store the data pattern received from the decoder group and including a plurality of memory cells; and an encoder configured to encode the data pattern into a plurality of second codewords, and the decoder group is further configured to convert the illegal codewords among the plurality of first codewords into a fixed pattern, and the encoder is further configured to output the plurality of second codewords to the outside of the memory device, and the test device includes test logic configured to compare the plurality of second codewords received from the memory device with the plurality of second codewords. Brief Description of the Drawings

[0009] The embodiments will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram of a test system according to some embodiments. FIG. 2 is a block diagram of the decoder group shown in FIG. 1. FIG. 3 shows a mapping table of a decoder according to some embodiments. FIG. 4 is a structural diagram of test design (DFT) logic according to some embodiments. FIG. 5 is a flowchart showing an operation method of a memory device according to some embodiments. FIG. 6 shows a table for converting illegal codewords into a fixed pattern according to some embodiments. FIG. 7 is a flowchart showing a test operation method according to some embodiments. FIG. 8 shows a data table input to a decoder group according to some embodiments. FIG. 9 shows a data table in the memory cells of a memory cell array input to a decoder group according to some embodiments. FIG. 10 shows an encoded data table according to some embodiments. FIG. 11 is a block diagram showing a system including a memory device according to some embodiments. Embodiments

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0011] FIG. 1 is a block diagram of a test system according to some embodiments.

[0012] Referring to FIG. 1, a test system 10 for testing different types of semiconductor devices (e.g., memory devices) may include a test device 200 and one or more memory devices 100 on which tests will be performed. The test device 200 may include test logic 210, and the memory device 100 may include an input / output (I / O) circuit 110, a decoder group 120, an encoder 140, and a memory cell array 130.

[0013] Although not shown in FIG. 1, the test device 100 may further include various components, such as a communication device for communicating with an external host or external device to request tests and / or report test results, a memory for temporarily storing various information related to various tests, and a power supply circuit for supplying power to the memory device 100. In addition, the test system 10 according to the exemplary embodiments of the present disclosure may perform various definitions.

[0014] According to some embodiments, the test device 200 may include a semiconductor chip, such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), an application processor (AP), or a similar semiconductor chip, and when a plurality of memory devices 100 are installed, test operations may be performed on the plurality of memory devices in parallel. Additionally, when testing one memory device 100, the test device 200 may provide test data to the memory device 100 in parallel via a plurality of test channels, and may receive test results from one memory device 100 in parallel via the plurality of test channels.

[0015] In addition, the memory device 100 may be various types of semiconductor devices, and in an example, may be a memory device including a semiconductor memory cell array. For example, the memory device may be a dynamic random access memory (DRAM), such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LP DDR) SDRAM, a graphics double data rate (GDDR) SDRAM, or a rambus dynamic random access memory (RDRAM).

[0016] The memory device 100 may receive data from the test device 100, and may store the received test data in the memory cell array 130. Additionally, the memory device 100 may read the data stored in the memory cell array 130, and may provide the read data to the test device 200 as a test result.

[0017] According to some exemplary embodiments, the memory device 100 may be a memory device for transmitting / receiving signals modulated by an N-level pulse amplitude modulation (hereinafter referred to as pulse amplitude modulation (PAM)-N, where N is a natural number greater than or equal to 3) method. For example, the memory device 100 may use the PAM-3 method to transmit / receive signals. The PAM-N method is a modulation method for transmitting multiple bits during a unit interval. Here, the unit interval may correspond to the symbol period of the signal used to transmit one symbol. For example, when data is modulated by the PAM-N method, multiple data bit information may be included in one symbol. Hereinafter, embodiments of the present disclosure will be described based on the PAM-3 method.

[0018] As an example of a test operation, the test logic 210 may transmit codewords CW0 to CW23 including PAM-3 symbols to the memory device 100 as test data. The memory device 100 may decode or convert the codewords including PAM-3 symbols into a data pattern and store the converted data pattern in the memory cell array 130. The memory device 100 may read the data pattern stored in the memory cell array 130, encode the read data pattern, convert the data pattern into a codeword including PAM-3 symbols, and output the codeword to the test logic 210. The test logic 210 may compare whether the codewords CW0 to CW23 transmitted as test data are the same as the codewords CW0 to CW23 received from the memory device 100. For example, the test logic 210 may compare the first codeword with the second codeword. Here, the first codeword may be test data composed of PAM-3 symbols transmitted by the test logic 210 to the memory device 100, and the second codeword may be data composed of PAM-3 symbols transmitted to the test logic 210, and the memory device 100 encodes the data pattern. For example, when the codewords CW0 to CW23 received from the memory device 100 are illegal codewords and are converted into a specific fixed pattern, the test logic 210 may compare the fixed pattern with the test data. For example, when the codewords received from the memory device 100 are data patterns representing normal codewords, the test logic 210 may compare the data pattern with the test data. The test logic 210 may test whether the test data is the same as the codewords decoded and encoded by the memory device 100. For example, the codeword may include m bits, and the data pattern and the fixed pattern may include n bits. Here, m and n may be different positive integers, and m may be greater than n. For example, the codeword may include 14 bits, and the data pattern and the fixed pattern may include 11 bits.

[0019] The multiple codewords CW0 to CW23 output from the memory device 100 can be provided to the test device 200 via multiple test channels. For example, the memory device 100 can decode and encode codewords including PAM-3 symbols.

[0020] The I / O circuit 110 can input data from the outside and output data to the outside. The I / O circuit 110 can input the multiple codewords CW0 to CW23 from the test logic 210 of the test device 200 / output the multiple codewords CW0 to CW23 to the test logic 210 of the test device 200 or transmit the multiple codewords CW0 to CW23 to the test logic 210 of the test device 200 / receive the multiple codewords CW0 to CW23 from the test logic 210 of the test device 200. The decoder group 120 can include design for testing (DFT) logic 125. Hereinafter, the decoder group 120 and the DFT logic 125 will be described in detail with reference to FIG. 2. The encoder 140 can encode a data pattern into multiple codewords including multiple symbols. The encoder 140 can include a mapping table representing the mapping relationship between the multiple symbols S0 to S15 and the multiple codewords CW0 to CW23. The memory cell array 130 can include multiple memory cells. The memory cell array 130 can store the data pattern received from the decoder group 120 and / or a fixed pattern. The memory cell array 130 can store test data received from the decoder group 120. The test data can include a data pattern and a fixed pattern.

[0021] The test device 200 can determine the logical state of the received codeword. For example, when the received codeword is different from the test data, a defect of the memory device can be detected. For example, errors may occur when the test data undergoes the decoding operation of the decoder group 120 of the memory device 100, during the operation stored in the memory cell array 130, and / or during the encoding operation of the encoder 140. Therefore, when the received codeword is different from the test data, the test device 200 can detect a defect of the memory device, and then can check whether the memory device is counterfeit or not operating correctly.

[0022] According to the present disclosure, the memory device can detect an illegal codeword and convert the illegal codeword into a fixed pattern (non-random pattern) using an unused symbol, so that the memory device can test a memory device based on a PAM-3 interface, the implementation area and power consumption of the test device can be reduced, and the manufacturing cost of the test device can be reduced.

[0023] FIG. 2 is a block diagram of the PAM-3 decoder shown in FIG. 1.

[0024] Referring to FIG. 2, the decoder group 120 may include a first decoder 121, a second decoder 122, a third decoder 123, a fourth decoder 124, and DFT logic 125. The decoder group 120 may receive a plurality of codewords including a plurality of symbols from outside the memory device (e.g., an external device). For example, the plurality of symbols S0 to S15 may include 7 symbols, and one codeword may include 7 symbols. One symbol may include 2 bits, and one codeword may include 14 bits. That is, the decoder group 120 may receive the plurality of codewords, where each codeword in the plurality of codewords includes 14 bits. The plurality of codewords may include illegal codewords and normal codewords.

[0025] The first decoder 121, the second decoder 122, the third decoder 123, and the fourth decoder 124 may include a plurality of codewords CW0 to CW23 including a plurality of symbols S0 to S15. The first decoder 121, the second decoder 122, the third decoder 123, and the fourth decoder 124 may include a mapping table representing the mapping relationship between the plurality of symbols S0 to S15 and the plurality of codewords CW0 to CW23. The mapping table may be implemented using a register (or storage element) for storing the mapping relationship between the plurality of symbols S0 to S15 and the plurality of codewords CW0 to CW23. The first decoder 121, the second decoder 122, the third decoder 123, and the fourth decoder 124 may use the mapping table to decode a plurality of codewords including a plurality of symbols. The first decoder 121, the second decoder 122, the third decoder 123, and the fourth decoder 124 may receive a codeword including 14 bits and decode a codeword including 14 bits.

[0026] The first decoder 121 may include a mapping table on which a codeword including 14 bits can be mapped with 1 symbol per 2 bits. The mapping table of the first decoder 121 may include 1 symbol per 2 bits and invalid symbols. The second decoder 122 may include a mapping table on which a codeword including 14 bits can be mapped with 2 symbols per 3 bits. The mapping table of the second decoder 122 may include unused symbols among 2 symbols per 3 bits. The third decoder 123 may include a mapping table on which a codeword including 14 bits can be mapped with 2 symbols per 3 bits. The mapping table of the third decoder 123 may include unused symbols among 2 symbols per 3 bits. The fourth decoder 124 may include a mapping table on which a codeword including 14 bits can be mapped with 2 symbols per 3 bits. The mapping table of the fourth decoder 124 may include unused symbols among 2 symbols per 3 bits.

[0027] That is, the first decoder 121 may include a mapping table on which a codeword including 14 bits can be mapped with 1 symbol per 2 bits, and the second decoder 122, the third decoder 123, and the fourth decoder 124 may include mapping tables on which a codeword including 14 bits can be mapped with 2 symbols per 3 bits. The first to fourth decoders 121, 122, 123, and 124 may decode a codeword including 14 bits into a data pattern. The data pattern may include a mapping of 7 symbols per 11 bits. The test pattern may include the data pattern and a fixed pattern. The mapping table will be described in detail with reference to FIG. 3 below.

[0028] The DFT logic 125 may receive a plurality of mapped symbols from the first to fourth decoders 124. When an invalid symbol and / or an unused symbol among the plurality of mapped symbols is received, the DFT logic 125 may detect an illegal codeword. The illegal codeword may include an invalid symbol and / or an unused symbol. The DFT logic 125 may detect the illegal codeword and convert the illegal codeword into a fixed pattern FP. In other words, the DFT logic 125 may decode the illegal codeword into the fixed pattern FP. The DFT logic 125 may decode a normal codeword into a data pattern.

[0029] According to some embodiments of the present disclosure, when the DFT logic 125 includes an invalid symbol and / or an unused symbol, the DFT logic 125 may detect the illegal codeword and convert the illegal codeword into a fixed pattern. The memory device may convert the illegal codeword into a fixed pattern and output the codeword, and may test the memory device based on the PAM-3 interface, thereby checking whether the memory device is counterfeit or not operating properly.

[0030] FIG. 3 shows a mapping table of a decoder according to some embodiments.

[0031] Referring to FIG. 3, (a) illustrates the mapping table of the first decoder 121, and (b) illustrates the mapping tables of the second decoder 122 to the fourth decoder 124.

[0032] The mapping table of the first decoder 121 may include 2 bits, 1 symbol, and an invalid symbol. The 2 bits may correspond to [x0:x1]. For example, the 2 bits may include [0,0], [1,0], and [1,1]. The 1 symbol may include a least significant bit (LSB) and a most significant bit (MSB) and may correspond to [y0:y1]. For example, the 1 symbol may include [0:0], [1:0], and [1:1]. One symbol having one of three levels during the unit interval may be generated, and one symbol may correspond to 2 bits. One symbol may include the invalid symbol of the mapping table of the first decoder 121. For example, the invalid symbol may be [0:1].

[0033] The mapping table of the second decoder 122 may include 3 bits and 2 symbols. The mapping table of the second decoder 122 may include unused symbols for 3 bits and 2 symbols. The 3 bits may correspond to [x0:x1:x2]. For example, the 3 bits may include [0:0:0], [0:0:1], [0:1:0], [0:1:1], [1:0:0], [1:0:1], [1:1:0], and [1:1:1]. Each of the 2 symbols may include an LSB and an MSB, and the 2 symbols may correspond to [y0:y1:y2:y3]. For example, the 2 symbols may include [0:0:1:0], [0:0:0:0], [0:0:1:1], [1:0:1:1], [1:1:1:0], [1:0:0:1], [1:1:1:0], and [1:1:1:1]. The 2 symbols may include the unused symbols of the mapping table of the second decoder 122. For example, the unused symbol may be [1:0:1:0].

[0034] The mapping tables of the third decoder 123 and the fourth decoder 124 are the same as the mapping table of the second decoder 122, and thus will not be described herein again.

[0035] The first decoder 121, the second decoder 122, the third decoder 123, and the fourth decoder 124 can receive a plurality of codewords including a plurality of symbols and can map and / or decode the codewords according to each mapping table.

[0036] The invalid symbols of the mapping table of the first decoder 121 and the unused symbols of the mapping tables of the second decoder 122 to the fourth decoder 124 are not limited to the symbols provided in this disclosure.

[0037] FIG. 4 is a structural diagram of DFT logic according to some embodiments.

[0038] Referring to FIG. 4, the DFT logic 125 can include a first OR circuit OR1, a second OR circuit OR2, and a third OR circuit OR3.

[0039] The first OR circuit OR1 can receive invalid symbols mapped by the first decoder 121 to the fourth decoder 124. For example, when the first OR circuit OR1 receives an invalid symbol, the first OR circuit OR1 can output 1, and when the first OR circuit OR1 receives a valid symbol, the first OR circuit OR1 can output 0. When the first decoder 121 maps an invalid symbol, the second OR circuit OR2 can receive unused symbols mapped by at least one or more of the second decoder 122, the third decoder 123, and the fourth decoder 124. For example, when the second OR circuit OR2 receives an unused symbol, the second OR circuit OR1 can output 1, and when the second OR circuit OR2 receives a used symbol, the second OR circuit OR2 can output 0. The third OR circuit OR3 can receive the output value of the first OR circuit OR1 and the output value of the second OR circuit OR2. The third OR circuit OR3 can output an illegal codeword or a normal codeword based on the received output value of the first OR circuit OR1 and the received output value of the second OR circuit OR2. For example, in the case of an illegal codeword, the third OR circuit OR3 can output 1, and in the case of a normal codeword, the third OR circuit OR3 can output 0.

[0040] When the third OR circuit OR3 outputs 1 indicating an illegal codeword, the DFT logic 125 can convert the illegal codeword into a fixed pattern. When the third OR circuit OR3 outputs 0 indicating a normal codeword, the DFT logic 125 can convert the normal codeword into a data pattern.

[0041] For example, referring to FIG. 4, for the codewords received by the decoder group 120, each column DQ[i] represents a serial data line, and each row [S0:S15] represents a serial symbol line. Each symbol may include 2 bits. For example, [S0:S6] of DQ[0] may include 7 symbols containing 14 bits, and this may be presented as codeword 0 (CW0) as a codeword. For example, [S7:S13] of DQ[0] may include 7 symbols containing 14 bits, and this may be presented as codeword 1 (CW1). For example, [S13:S15] of DQ[1] to DQ[3] may include 7 symbols containing 14 bits, and this may be presented as codeword 20 (CW20).

[0042] In addition, referring to FIGS. 3 and 4, it is described that the DFT logic 125 can be configured to detect illegal codewords. Among them, [S0:S6] of DQ[9] may include 7 symbols containing 14 bits, and the example provided herein is based on the assumption that codeword 18 (CW18) is an illegal codeword.

[0043] The codeword 18 (CW18) can be received via the first decoder 121 to the fourth decoder 124 of the decoder group 120 shown in FIG. 2. The codeword 18 (CW18) may include 7 symbols [S0:S6]. The 7 symbols may include invalid symbols and / or unused symbols. When the invalid symbol of each of the symbols is [0:1], the invalid symbol can be provided to the first OR circuit OR1. When the first decoder 121 maps [0:1] as the invalid symbol [y0:y1], one of the second decoder 122 to the fourth decoder 124 can provide the unused symbol [1:0:1:0] of the symbol to the second OR circuit OR2. The third OR circuit OR3 can receive the output value of the first OR circuit OR1 and the output value of the second OR circuit OR2. The third OR circuit OR3 can output an illegal codeword based on the received output value of the first OR circuit OR1 and the received output value of the second OR circuit OR2. That is, the DFT logic 125 can detect the codeword 18 (CW18) as an illegal codeword.

[0044] FIG. 5 is a flowchart showing an operation method of a memory device according to an embodiment.

[0045] Referring to FIG. 5, decoder group 120 can receive multiple codewords (S110) including multiple symbols from the outside (e.g., from an external device). For example, the multiple symbols S0 to S15 can include 7 symbols, and one codeword can include 7 symbols. One symbol can include 2 bits, and one codeword can include 14 bits. That is, decoder group 120 can receive a codeword including 14 bits. The multiple codewords can include illegal codewords and normal codewords.

[0046] Decoder group 120 can decode the received multiple codewords into a data pattern (S120). For example, the first decoder 121 can include a mapping table on which one codeword including 14 bits can be mapped with 2 bits for 1 symbol, and the second decoder 122 and the third decoder 123 can include a mapping table on which one codeword including 14 bits can be mapped with 3 bits for 2 symbols. The first decoder to the fourth decoder 124 can decode a codeword including 14 bits into a data pattern.

[0047] Decoder group 120 can check whether there are invalid symbols (S130). For example, the first OR circuit OR1 can receive invalid symbols from the multiple symbols mapped by the first decoder 121 to the fourth decoder 124.

[0048] When there are invalid symbols (the "YES" branch of operation S130), unused symbols can be used to detect illegal codewords (S140). When the first decoder 121 maps [0:1] as the invalid symbol [y0:y1], one of the second decoder 122 to the fourth decoder 124 can provide the unused symbol [1:0:1:0] in the symbol to the second OR circuit OR2.

[0049] When there are no invalid symbols (the "NO" branch of operation S130), that is, when there are only valid symbols, decoder group 120 can decode the multiple codewords including multiple symbols into a data pattern and thus can end the operation.

[0050] The illegal codewords can be converted into a fixed pattern and the illegal codewords can be output (S150). For example, the third OR circuit OR3 can output illegal codewords based on the received output value of the first OR circuit OR1 and the received output value of the second OR circuit OR2. The fixed pattern FP can use [1:0:1:0] as the unused symbol. The DFT logic 125 can detect the illegal codewords, convert the illegal codewords into a fixed pattern, and can output the codewords.

[0051] FIG. 6 shows a table for converting illegal codewords into a fixed pattern according to some embodiments.

[0052] Referring to FIGS. 4 and 6, assume that codeword 18 (CW18) is an illegal codeword, and the illegal codeword is converted into a fixed pattern.

[0053] Codeword 18 (CW18) can be provided to the first decoder 121 to the fourth decoder 124. The first decoder 121 to the fourth decoder 124 can receive codeword 18 (CW18). Codeword 18 (CW18) can include 7 symbols [S0:S6]. The 7 symbols can include invalid symbols and / or unused symbols. When the invalid symbol in the symbols is [0:1], the invalid symbol can be provided to the first OR circuit OR1. When the first decoder 121 maps [0:1] as the invalid symbol [y0:y1], one of the second decoder 122 to the fourth decoder 124 can provide the unused symbol [1:0:1:0] in the symbols to the second OR circuit OR2. The third OR circuit OR3 can receive the output value of the first OR circuit OR1 and the output value of the second OR circuit OR2. The third OR circuit OR3 can output the illegal codeword based on the received output value of the first OR circuit OR1 and the received output value of the second OR circuit OR2. That is, the DFT logic 125 can detect codeword 18 (CW18) as an illegal codeword.

[0054] The DFT logic 125 can output the illegal codeword. The third OR circuit OR3 can output the illegal codeword. For example, the third OR circuit OR3 can output the illegal codeword as 1, while the third OR circuit OR3 can output the normal codeword as 0. The DFT logic 125 can convert the illegal codeword into a fixed pattern FP. The DFT logic 125 can detect the illegal codeword and can use the unused symbol to convert the illegal codeword into a fixed pattern FP.

[0055] For example, when the first decoder 121 maps [0:1] as the invalid symbol [y0:y1], the third decoder 123 can use [1:0:1:0] as the unused symbol [y10:y11:y12:y13] to convert [0:1] into a fixed pattern. Therefore, the fixed pattern can be [0:0:1] as 3 bits [x8:x9:x10].

[0056] In another example, when the first decoder 121 maps [0:1] as the invalid symbol [y0:y1], the second decoder 122 can use [1:0:1:0] as the unused symbol [y2:y3:y4:y5] to convert [0:1] into a fixed pattern, and the third decoder 123 can use [1:0:1:0] as the unused symbol [y6:y7:y8:y9] to convert [0:1] into a fixed pattern. Therefore, the fixed patterns can be [0:0:1] as three bits [x2:x3:x4] and [0:0:1] as three bits [x5:x6:x7], respectively.

[0057] In another example, when the first decoder 121 maps [0:1] as the invalid symbol [y0:y1], the third decoder 123 can use [1:0:1:0] as the unused symbol [y6:y7:y8:y9] to convert [0:1] into a fixed pattern, and the fourth decoder 124 can use [1:0:1:0] as the unused symbol [y10:y11:y12:y13] to convert [0:1] into a fixed pattern. Therefore, the fixed patterns can be [0:0:1] as three bits [x5:x6:x7] and [0:0:1] as three bits [x8:x9:x10], respectively.

[0058] In another example, when the first decoder 121 maps [0:1] as the invalid symbol [y0:y1], the second decoder 122 can use [1:0:1:0] as the unused symbol [y2:y3:y4:y5] to convert [0:1] into a fixed pattern, and the fourth decoder 124 can use [1:0:1:0] as the unused symbol [y10:y11:y12:y13] to convert [0:1] into a fixed pattern. Therefore, the fixed patterns can be [0:0:1] as three bits [x2:x3:x4] and [0:0:1] as three bits [x8:x9:x10], respectively.

[0059] By detecting an illegal codeword, the DFT logic 125 can use the unused symbols of the second decoder 122 to the fourth decoder 124 to convert the illegal codeword into a fixed pattern. For example, the fixed pattern can be represented by 11 bits, and [x0:x1] can be represented as [0:0:1], [x5:x6:x7] can be represented as [0:0:1], and [x8:x9:x10] can be represented as [0:0:1].

[0060] According to some embodiments of the present disclosure, when the DFT logic 125 includes invalid symbols and / or unused symbols, the DFT logic 125 can detect an illegal codeword and convert the illegal codeword into a fixed pattern. The memory device can convert the illegal codeword into a fixed pattern and output the codeword, and can test the memory device based on the PAM-3 interface, thereby checking whether the memory device is counterfeited or not operating properly.

[0061] FIG. 7 is a flowchart showing a method of a test operation according to some embodiments.

[0062] Referring to FIG. 7, the memory device 100 can receive a plurality of codewords including a plurality of symbols from the outside (S120). For example, the plurality of symbols S0 to S15 can include 7 symbols, and one codeword can include 7 symbols. One symbol can include 2 bits, and one codeword can include 14 bits. That is, the decoder group 120 can receive one codeword including 14 bits. The plurality of codewords can include illegal codewords and normal codewords.

[0063] The memory device 100 can determine whether the received codeword is an illegal codeword (S121). For example, when the DFT logic 125 detects an illegal codeword, the DFT logic 125 can use the unused symbols of the decoder group 120 to convert the illegal codeword into a fixed pattern and output the codeword. When a normal codeword (not an illegal codeword) is detected, the DFT logic 125 may not convert the normal codeword into a fixed pattern, but can immediately output the data pattern.

[0064] The test device 200 can check whether the test data and the fixed pattern are the same as each other (S122). For example, the test logic 210 can compare whether the plurality of codewords CW0 to CW23 received from the memory device 100 are the same as the test data. For example, when the codeword received from the memory device 100 is an illegal codeword and is converted into a specific fixed pattern, the test logic 210 can compare the fixed pattern with the test data. For example, when the codewords CW0 to CW23 received from the memory device 100 are data patterns representing normal codewords, the test logic 210 can compare the data patterns with the test data. The test logic 210 can test whether the thing in which the data pattern is encoded and converted into a codeword is the same as the test data.

[0065] When the codeword obtained by encoding the data pattern is different from the test data, the test logic 210 can detect a defect in the memory device (S123). For example, since the data pattern undergoes decoding operations by the decoder group 120 of the memory device 100, storage operations in the memory cell array 130, and / or encoding operations by the encoder 140, errors may occur during the above operations. Therefore, when the codeword obtained by encoding the data pattern is different from the test data, the test logic 210 can detect a defect in the memory device, and then can check whether the memory device is counterfeit or not operating properly.

[0066] However, since there is no defect in the memory device when the codeword obtained by encoding the data pattern is different from the test data, the test logic 210 can end the test. Additionally, since there is no defect in the memory device when the codeword obtained by encoding the fixed pattern is different from the test data, the test logic 210 can end the test.

[0067] FIG. 8 shows a data table input to the decoder group according to some embodiments. FIG. 9 shows a data table in the memory cells of the memory cell array input to the decoder group according to some embodiments.

[0068] Referring to FIG. 8, the decoder group 120 can receive multiple codewords including multiple symbols input to the decoder group 120. For example, one codeword can include 7 symbols. One symbol can include 2 bits, and one codeword can include 14 bits. That is, the decoder group 120 can receive multiple codewords including 14 bits. The multiple codewords can include illegal codewords and normal codewords.

[0069] For the codewords received by decoder group 120, each column DQ[i] represents a serial data line, and each row [S0:S15] represents a serial symbol line. Each symbol may include 2 bits. As shown in FIG. 8, decoder group 120 may receive 23 codewords. The illegal codewords among the 23 codewords may be codeword 1, codeword 2, codeword 4, codeword 7, codeword 9, codeword 10, codeword 12, codeword 16, codeword 19, codeword 22 (e.g., CW1, CW2, CW4, CW7, CW9, CW10, CW12, CW16, CW19, CW22), and the normal codewords among the 23 codewords may be codeword 0, codeword 3, codeword 5, codeword 6, codeword 8, codeword 11, codeword 13, codeword 14, codeword 15, codeword 17, codeword 18, codeword 20, codeword 21 (e.g., CW0, CW3, CW5, CW6, CW8, CW11, CW13, CW14, CW15, CW17, CW18, CW20, CW21).

[0070] Referring to FIG. 9, decoder group 120 may detect an illegal codeword, and decoder group 120 may convert the illegal codeword into a fixed pattern and provide the fixed pattern to memory cell array 130. Memory cell array 130 may store a data pattern and / or a fixed pattern. The data pattern and the fixed pattern may be 11 bits. Hereinafter, referring to FIG. 9, the illegal codeword detected in FIG. 8 is converted into a fixed pattern.

[0071] For the decoded data pattern and fixed pattern, each column DQ[i] represents a serial data line, and each row [0T:31T] represents the burst length of a data burst.

[0072] As shown in FIGS. 4 and 6, illegal codewords can be converted into a fixed pattern. For example, codeword 16 (CW16) can be provided to the first decoder 121 to the fourth decoder 124. The first decoder 121 to the fourth decoder 124 can receive codeword 16 (CW16). Codeword 16 (CW16) can include 7 symbols [S0:S6]. The 7 symbols can include invalid symbols and / or unused symbols. When the invalid symbol in the symbols is [0:1], the invalid symbol can be provided to the first OR circuit OR1. When the first decoder 121 maps [0:1] as the invalid symbol [y0:y1], one of the second decoder 122 to the fourth decoder 124 can provide the unused symbol [1:0:1:0] in the symbols to the second OR circuit OR2. The third OR circuit OR3 can receive the output value of the first OR circuit OR1 and the output value of the second OR circuit OR2. The third OR circuit OR3 can output an illegal codeword based on the received output value of the first OR circuit OR1 and the received output value of the second OR circuit OR2. That is, the DFT logic 125 can detect codeword 16 (CW16) as an illegal codeword. The DFT logic 125 can output an illegal codeword. The third OR circuit OR3 can output an illegal codeword. The DFT logic 125 can detect an illegal codeword and can convert the illegal codeword into a fixed pattern using the unused symbols.

[0073] For example, when the first decoder 121 maps [0:1] as the invalid symbol [y0:y1], the third decoder 123 can use [1:0:1:0] as the unused symbol [y10:y11:y12:y13] to convert [0:1] into a fixed pattern. Therefore, the fixed pattern can be [0:0:1] as 3 bits [x8:x9:x10].

[0074] In another example, when the first decoder 121 maps [0:1] as the invalid symbol [y0:y1], the second decoder 122 can use [1:0:1:0] as the unused symbol [y2:y3:y4:y5] to convert [0:1] into a fixed pattern, and the third decoder 123 can use [1:0:1:0] as the unused symbol [y6:y7:y8:y9] to convert [0:1] into a fixed pattern. Therefore, the fixed patterns can be [0:0:1] as 3 bits [x2:x3:x4] and [0:0:1] as 3 bits [x5:x6:x7], respectively.

[0075] In another example, when the first decoder 121 maps [0:1] as the invalid symbol [y0:y1], the third decoder 123 can convert [0:1] into a fixed pattern using [1:0:1:0] as the unused symbol [y6:y7:y8:y9], and the fourth decoder 124 can convert [0:1] into a fixed pattern using [1:0:1:0] as the unused symbol [y10:y11:y12:y13]. Therefore, the fixed patterns can be [0:0:1] as three bits [x5:x6:x7] and [0:0:1] as three bits [x8:x9:x10], respectively.

[0076] In another example, when the first decoder 121 maps [0:1] as the invalid symbol [y0:y1], the second decoder 122 can convert [0:1] into a fixed pattern using [1:0:1:0] as the unused symbol [y2:y3:y4:y5], and the fourth decoder 124 can convert [0:1] into a fixed pattern using [1:0:1:0] as the unused symbol [y10:y11:y12:y13]. Therefore, the fixed patterns can be [0:0:1] as three bits [x2:x3:x4] and [0:0:1] as three bits [x8:x9:x10], respectively.

[0077] By detecting an illegal codeword, the DFT logic 125 can convert the illegal codeword into a fixed pattern using the unused symbols of the second decoder 122 to the fourth decoder 124. For example, the fixed pattern can be represented by 11 bits, and [x0:x1] can be represented as [0:0:1], [x5:x6:x7] can be represented as [0:0:1], and [x8:x9:x10] can be represented as [0:0:1].

[0078] According to some embodiments of the present disclosure, when the DFT logic 125 includes invalid symbols and / or unused symbols, the DFT logic 125 can detect an illegal codeword and convert the illegal codeword into a fixed pattern. The memory device can convert the illegal codeword into a fixed pattern and output the codeword, and can test the memory device based on the PAM-3 interface, thereby checking whether the memory device is counterfeit or not operating properly.

[0079] FIG. 10 shows an encoded data table according to some embodiments.

[0080] Referring to FIG. 10, data is shown in which the encoder 140 encodes data patterns and fixed patterns stored in the memory cell array 130.

[0081] For an encoded codeword, each column DQ[i] represents a serial data line, and each row [S0:S15] represents a serial symbol line.

[0082] When a normal codeword is decoded into a data pattern, the encoder 140 can encode the data pattern into a codeword. When an illegal codeword is decoded into a fixed pattern, the encoder 140 can encode the fixed pattern into a codeword including 14 bits, each of the 14 bits being 0.

[0083] The encoded codeword can be provided to the test logic 210 of the test device 200. For example, when the codeword received from the memory device 100 is a data pattern representing a normal codeword, the test logic 210 can compare the data pattern with test data. The test logic 210 can test whether the thing in which the data pattern is encoded and converted into a codeword is the same as the input data.

[0084] When the codeword obtained by encoding the data pattern is different from the input data, the test logic 210 can detect a defect in the memory device. For example, since the data pattern undergoes decoding operations of the decoder group 120 of the memory device 100, operations stored in the memory cell array 130, and / or encoding operations of the encoder 140, errors may occur in the above operations. Therefore, when the codeword obtained by encoding the data pattern is different from the input data, a defect in the memory device can be detected, and thus it can be checked whether the memory device is counterfeit or not operating properly. However, since there is no defect in the memory device when the codeword obtained by encoding the data pattern is different from the input data, the test logic 210 can end the test. Additionally, since there is no defect in the memory device when the codeword obtained by encoding the data pattern is different from the input data, the test logic 210 can end the test.

[0085] FIG. 11 is a block diagram showing a system including a memory device according to some embodiments.

[0086] Referring to FIG. 11, the system 1000 may include a camera 1100, a display 1200, an audio processor 1300, a modem 1400, DRAMs 1500a and 1500b, flash memory devices 1600a and 1600b, I / O devices 1700a and 1700b, and an application processor (AP) 1800. The system 1000 may be implemented as a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, an Internet of Things (IoT) device, or a similar device, or may be implemented using a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, an IoT device, or a similar device. Additionally, the system 1000 may also be implemented as a server or a personal computer, or may be implemented using a server or a personal computer.

[0087] The camera 1100 may capture still images or moving images according to the user's control, may store the captured image / video data, or may transmit the image / video data to the display 1200. The audio processor 1300 may process audio data or network content included in the flash memory devices 1600a and 1600b.

[0088] The modem 1400 may modulate and transmit signals for wired / wireless data transmission / reception, and may demodulate the signals to restore the signals to their original signals. The I / O devices 1700a and 1700b may include devices for providing digital input functions and / or digital output functions, such as a universal serial bus (USB) or a memory, a digital camera, a secure digital (SD) card, a digital versatile disc (DVD), a network adapter, a touch screen, and similar devices.

[0089] The AP 1800 can control the overall operation of the system 1000. The AP 1800 can control the display 1200, such that some parts of the content stored in the flash memory devices 1600a and 1600b can be displayed on the display 1200. When user inputs are received via the I / O devices 1700a and 1700b, the AP 1800 can perform control operations corresponding to the user inputs. The AP 1800 can include an accelerator block as a dedicated circuit for artificial intelligence (AI) data operations, or the system 1000 can include an accelerator chip 1820 separated from the AP 1800. The DRAM 1500b can be additionally installed on the accelerator block or the accelerator chip 1820. The accelerator can be a functional block for performing specific functions of the AP 1800, and can include a graphic processing unit (GPU) as a functional block for performing graphic data processing, a neural processing unit (NPU) as a functional block for performing AI calculations and inferences, and a data processing unit (DPU) as a functional block for performing data transmission.

[0090] The system 1000 can include multiple DRAMs 1500a and 1500b. The AP 1800 can control the DRAMs 1500a and 1500b via commands and mode register settings (MRS) suitable for the Joint Electron Device Engineering Council (JEDEC) standard specifications, or can set and convey DRAM interface protocols to use company-specific functions, such as low voltage / high speed / reliability, and cyclic redundancy check (CRC) / error correction code (ECC) functions. For example, the AP 1800 can communicate with the DRAM 1500a using an interface suitable for the JEDEC standard specifications, and the accelerator block or the accelerator chip 1820 can set and convey a new DRAM interface protocol to use the DRAM 1500b for an accelerator with a higher bandwidth than the DRAM 1500a.

[0091] Although only DRAMs 1500a and 1500b are shown in FIG. 11, any memory such as phase-change random access memory (PRAM), static RAM (SRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), or hybrid ferroelectric RAM can be used based on considerations of the bandwidth, response speed, and voltage conditions of the AP 1800 or the accelerator chip 1820. Compared with the latency and bandwidth of the I / O devices 1700a and 1700b or the flash memories 1600a and 1600b, the DRAMs 1500a and 1500b may have relatively small latency and bandwidth. The DRAMs 1500a and 1500b can be initialized when the system 1000 is powered on, and the operating system and application data can be loaded to use them as a temporary storage location for the operating system and application data, or as an execution space for various software codes.

[0092] Addition / subtraction / multiplication / division operations, vector operations, address operations, or fast Fourier transform (FFT) operations can be performed in the DRAMs 1500a and 1500b. In addition, functions used during inference can be performed in the DRAMs 1500a and 1500b. Here, inference can be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm can include a training operation for learning a model using various data and an inference operation for discriminating data using the learned model. According to some embodiments, the image captured by the user through the camera 1100 can be signal-processed and stored in the DRAM 1500b, and the accelerator block or the accelerator chip 1820 can perform AI data operations for discriminating data using the data stored in the DRAM 1500b and the functions for inference.

[0093] System 1000 may include multiple memories (e.g., multiple storage devices) or multiple flash memory devices 1600a and 1600b with a capacity larger than that of DRAMs 1500a and 1500b. The accelerator block or accelerator chip 1820 may perform training operations and AI data operations using flash memory devices 1600a and 1600b. In some embodiments, flash memory devices 1600a and 1600b may perform training operations and inference AI data operations performed by AP 1800 and / or accelerator chip 1820 using the operating devices provided in memory controller 1610. Flash memory devices 1600a and 1600b may store the photos taken by camera 1100 and / or may store the data transmitted via the data network. For example, flash memory devices 1600a and 1600b may store augmented reality (AR) / virtual reality (VR), high definition (HD) content, or ultra high definition (UHD) content.

[0094] In system 1000, DRAMs 1500a and 1500b may include DFT logic (125 shown in FIG. 1). When DFT logic 125 includes invalid symbols and / or unused symbols, DFT logic 125 may detect illegal codewords and convert the illegal codewords into a fixed pattern. The memory device may convert the illegal codewords into a fixed pattern and output the codewords, and may test the memory device based on the PAM-3 interface, and thus may check whether the memory device is counterfeit.

[0095] As described above, some exemplary embodiments are disclosed in the drawings and the specification. Although specific terms have been used in the specification to describe the embodiments, this is only for the purpose of illustrating the technical idea of the present disclosure, rather than for limiting the scope of the present disclosure set forth in the claims.

[0096] Although the present inventive concept has been specifically shown and described with reference to embodiments of the present inventive concept, it should be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the following claims.

[0097] 10: Test system 100: Memory device 110: Input / output (I / O) circuit 120: Decoder group 121: First decoder 122: Second decoder 123: Third decoder 124: Fourth decoder 125: Test design (DFT) logic 130: Memory cell array 140: Encoder 200: Test device 210: Test logic 1000: System 1100: Camera 1200: Display 1300: Audio processor 1400: Modem 1500a, 1500b: DRAM 1600a, 1600b: Flash memory device / Flash memory 1610, 1620: Memory controller 1700a, 1700b: I / O device 1800: Application processor (AP) 1810: Controller 1820: Accelerator, accelerator chip 1830: Interface CW0, CW1, CW2, CW3, CW4, CW5, CW6, CW7, CW8, CW9, CW10, CW11, CW12, CW13, CW14, CW15, CW16, CW17, CW18, CW19, CW20, CW21, CW22, CW23: Codeword DO0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7, DQ8, DQ9, DQE: Serial data line FP: Fixed pattern OR1: First OR circuit OR2: Second OR circuit OR3: Third OR circuit S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15: Symbol S110, S120, S121, S122, S123, S130, S140, S150: Operation <h2 style=";text-align:left;direction:ltr">x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, y12, y13:

Claims

1. A memory device, comprising: A decoder group is configured to receive a plurality of codewords from an external device outside the memory device, each of the plurality of codewords including a plurality of symbols, the plurality of codewords including a plurality of normal codewords and a plurality of illegal codewords that are different from each other, and the decoder group is configured to decode the plurality of normal codewords into a plurality of data patterns and decode the plurality of illegal codewords into a plurality of fixed patterns having the same value; a memory cell array is configured to receive the plurality of data patterns and the plurality of fixed patterns from the decoder group and is configured to store the plurality of data patterns and the plurality of fixed patterns, the memory cell array including a plurality of memory cells; and an encoder is configured to encode the plurality of data patterns read from the memory cell array into a plurality of first codewords and encode the plurality of fixed patterns read from the memory cell array into a plurality of second codewords having the same value, and output the plurality of first codewords and the plurality of second codewords to an external device outside the memory device.

2. The memory device as claimed in claim 1, wherein the plurality of symbols comprises 7 symbols, and each of the plurality of codewords is data comprising m bits, and each of the plurality of data patterns and the plurality of fixed patterns is data comprising n bits.

3. The memory device as claimed in claim 2, wherein m and n are different positive integers, and m is greater than n.

4. The memory device as claimed in claim 2, wherein the decoder group and the encoder are each configured to generate a third-order pulse amplitude modulation (PAM) signal.

5. The memory device of claim 1, wherein the decoder group includes a first decoder, a second decoder, a third decoder, a fourth decoder and test design (DFT) logic, and the first decoder is configured to map each of the plurality of codewords with 2 bits and 1 symbol, and the second to fourth decoders are configured to map each of the plurality of codewords with 3 bits and 2 symbols, and the first to fourth decoders are further configured to decode each of the plurality of codewords into one of the plurality of data patterns and the plurality of fixed patterns, wherein the data pattern includes an 11-bit, 7-symbol mapping.

6. The memory device as claimed in claim 5, wherein the test design logic is configured to convert the plurality of illegal codewords among the plurality of codewords into the plurality of fixed patterns.

7. The memory device as claimed in claim 5, wherein the mapping table of the first decoder includes 2 bits, 1 symbol, and an invalid symbol, and the mapping tables of the second decoder to the fourth decoder include 3 bits, 2 symbols, and an unused symbol.

8. The memory device as claimed in claim 7, wherein the test design logic includes: A first OR circuit is configured to receive the invalid symbol contained in each of the plurality of codewords and mapped by the first decoder to the fourth decoder from among the plurality of symbols, to output a first value indicating whether each of the plurality of codewords includes the invalid symbol; a second OR circuit is configured to receive the unused symbol mapped by at least one of the second decoder, the third decoder, and the fourth decoder when the first decoder maps the invalid symbol, and to output a second value indicating whether each of the plurality of codewords includes the unused symbol; And a third OR circuit, configured to receive the first value from the first OR circuit and the second value from the second OR circuit, and output a third value indicating whether each of the plurality of codewords is an illegal codeword.

9. The memory device as claimed in claim 8, wherein the test design logic is further configured to convert the illegal codeword into the fixed pattern when the third OR circuit output indicates that each of the plurality of codewords is the third value of the illegal codeword.

Images