Semiconductor device and methods of making and using thermally advanced semiconductor packages

Abstract

A semiconductor device includes a substrate. A semiconductor die is disposed above the substrate. An encapsulant is deposited on the substrate and above the semiconductor die. A first trench is formed in the encapsulant above the semiconductor die. A conductor layer is formed above the encapsulant and into the first trench.

Description

Semiconductor devices and methods for making and using thermally advanced semiconductor packages The present invention relates generally to semiconductor devices, and more particularly, to semiconductor devices and methods of making and using thermally advanced semiconductor packages. As semiconductor devices become faster and more densely packed, the amount of heat they generate grows. Managing the heat emitted by semiconductor dies, while requiring increasingly advanced semiconductor packaging, is a never-ending race. As power dissipation levels and the complexity of package architectures increase, thermal management becomes critical and presents a design challenge. Integrated thermal management is needed to ensure the performance and reliability of high-power components. Currently available methods and package structures are reaching their limits and becoming insufficient. Therefore, a need exists for a thermally advanced semiconductor package. According to one aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising providing a substrate; disposing a semiconductor die above the substrate; depositing an encapsulant over the substrate and the semiconductor die; forming a first trench in the encapsulant above the semiconductor die; and forming a conductive layer over the encapsulant and into the first trench. According to another aspect of the present invention, a semiconductor device is provided, comprising a substrate, a semiconductor die, an encapsulant, a first trench, and a conductive layer. The semiconductor die is disposed above the substrate. The encapsulant is disposed above the substrate and the semiconductor die. The first trench is formed in the encapsulant above the semiconductor die. The conductive layer is formed above the encapsulant and extends into the first trench. According to another aspect of the present invention, a semiconductor device is provided, comprising a semiconductor package, a trench, and a conductive layer. The trench is formed in the semiconductor package. The conductive layer is formed above the semiconductor package and extends into the trench. The present invention is described in one or more embodiments with reference to the drawings below, wherein like reference numerals represent like or similar elements. Although the present invention is described in terms of the best mode for carrying out the purposes of the present invention, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word and thus can refer to both a single semiconductor device and a plurality of semiconductor devices. The terms "semiconductor die" and "die" are used interchangeably. Semiconductor devices are typically fabricated using two complex processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create the relationship between voltage and current necessary for circuit function. Back-end manufacturing refers to the dicing or singulation of the completed wafer into individual semiconductor dies and the packaging of the semiconductor dies for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor dies, the wafer is scribed and cut along non-functional areas of the wafer (called dicing streets or dicing lines). The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are mounted on a packaging substrate that includes pins or contact pads for interconnection with other system components. The contact pads formed above the semiconductor dies are then connected to contact pads within the package. The electrical connections can be made using a conductive layer, bumps, stub bumps, conductive paste, or wire bonding. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, and the functionality of the semiconductor device is made available to other system components. FIG1 a shows a semiconductor wafer 100 having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or devices 104 are formed on wafer 100. The semiconductor dies 104 are separated by inactive inter-die wafer regions or scribe lines 106. The scribe lines 106 provide dicing areas for singulating the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, semiconductor wafer 100 has a width or diameter of 100 to 450 millimeters (mm). Figure 1b shows a cross-sectional view of a portion of semiconductor wafer 100. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110 that includes analog or digital circuitry implemented as active components, passive components, conductors, and dielectric layers formed within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within active surface 110 to implement analog or digital circuitry, such as a digital signal processor (DSP), application-specific integrated circuit (ASIC), memory, or other signal processing circuitry. Semiconductor die 104 may also include integrated passive devices (IPDs) such as inductors, capacitors, and resistors for radio frequency (RF) signal processing. An electrically conductive layer 112 is formed over the active surface 110 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as a contact pad electrically connected to the circuitry on the active surface 110. Conductive bump material is deposited over the conductive layer 112 using evaporation, electrolytic plating, electroless plating, shot drop, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, or a combination thereof, along with an optional fluxing solvent. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 114. In one embodiment, the bumps 114 are formed over an under bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesion layer. The bumps 114 can also be press-bonded or thermocompressed to the conductive layer 112. The bumps 114 represent one type of interconnect structure that can be formed over the conductive layer 112. The interconnect structure can also use bonding wires, conductive paste, stub bumps, micro bumps or other electrical interconnects. In FIG1c , the semiconductor wafer 100 is singulated through scribe lines 106 into individual semiconductor dies 104 using a saw or laser cutting tool 118. The individual semiconductor dies 104 can be inspected and electrically tested for identification of known good dies or known good units (KGDs / KGUs) after singulation. Figures 2a through 2c illustrate the fabrication of a semiconductor package 150 having a semiconductor die 104 and an advanced cooling structure. Figure 2a shows semiconductor package 150 formed on a substrate 152. While only a single substrate 152 is shown, hundreds or thousands of substrates are typically processed on a common carrier using the same steps described herein for a single unit, but performed as a whole. Substrate 152 may also begin as a single large substrate with multiple units that are singulated from one another during or after the manufacturing process. Substrate 152 includes one or more insulating layers 154 interleaved with one or more conductive layers 156. In one embodiment, insulating layer 154 is a core insulating board with conductive layers 156 patterned on the top and bottom surfaces, such as a copper-clad laminate. Conductive layers 156 also include conductive vias electrically coupled through insulating layer 154. Substrate 152 can include any number of conductive and insulating layers interleaved with one another. A solder mask or passivation layer can be formed on either side of substrate 152. In other embodiments, any suitable type of substrate or lead frame can be used for substrate 152. Forming semiconductor package 150 begins by mounting semiconductor die 104, discrete components 160, die stack 162, other discrete active or passive components, additional semiconductor die, and any other desired components to substrate 152. Any number, type, and combination of semiconductor die and other electrical components can be used to make package 150. Solder bumps 114 are reflowed between semiconductor die 104 and substrate 152 to mechanically and electrically connect the semiconductor die to the substrate. A molded underfill 164 is dispensed onto substrate 152 or semiconductor die 104 before mounting the semiconductor die. In other embodiments, molded underfill 164 is dispensed between semiconductor die 104 and substrate 152 after mounting. Semiconductor die 104 is connected to discrete components 160 and die stack 162 via conductive layer 156. Solder paste or a plurality of solder bumps are used to electrically and mechanically couple the discrete components 160 and the die stack 162 to the conductive layer 156. Any combination of discrete active and passive components can be mounted as desired. Any type and number of components can also be mounted to the top surface, bottom surface, or both of the substrate 152 and embedded within the substrate in any suitable order and configuration. Solder bumps 166 or another suitable interconnect structure are mounted to the bottom of substrate 152 for subsequent integration of semiconductor package 150 into a larger electrical system. Solder bumps 166 can be applied at any stage of the manufacturing process. After semiconductor die 104 and any other desired electrical components are mounted on substrate 152, they are encapsulated with an encapsulant or molding compound 170. Encapsulant 170 is deposited over substrate 152 and semiconductor die 104 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or another suitable application device. Encapsulant 170 can be a polymer composite material such as epoxy, epoxy acrylate, or a polymer with or without fillers. Encapsulant 170 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. Encapsulant 170 completely covers the side surfaces of semiconductor die 104 and fills any gaps between substrate 152 and semiconductor die 104 without the use of a separate molded underfill 164. In some embodiments, the encapsulant 170 is deposited while the substrate 152 remains as a wafer or strip, wherein multiple packages are formed simultaneously, and then the substrate 152 along with the encapsulant are singulated. In FIG2 b , a plurality of recesses, cavities, slots, or trenches 176 are formed in encapsulant 170 by laser ablation using a laser 178. In other embodiments, trenches 176 are formed by sawing, plasma etching, chemical etching, or other suitable techniques. Trenches 176 selectively thin encapsulant 170 above semiconductor die 104, thereby reducing the thickness of the encapsulant above the semiconductor die where the trenches are formed. In one embodiment, trenches 176 are formed completely through encapsulant 170 to expose the backside of semiconductor die 104. Trenches 176 can also be formed partially into semiconductor die 104 or completely through semiconductor die 104. 2b , the trenches 176 are formed as elongated slots extending the length or width of the semiconductor die 104, or the entire length or width of the package 150. In other embodiments, the trenches 176 are circular, square, or other smaller shapes formed in a grid or other pattern over and across the footprint of the semiconductor die 104. In FIG2 c , a conductive material is sputtered over package 150 to form a conductive shielding layer 180 . Shielding layer 180 is formed using any suitable metal deposition technique (e.g., PVD, CVD, other sputtering methods, spraying, or electroplating). The sputtered material can be copper, steel, aluminum, gold, combinations thereof, or any other suitable conductive material. In some embodiments, shielding layer 180 can be fabricated by sputtering multiple layers of different materials (e.g., stainless steel-copper-stainless steel or titanium-copper). Shielding layer 180 is a conformal layer having a substantially uniform thickness on all exposed surfaces of encapsulant 170. The bottom surface and vertical sidewalls within trench 176 are coated with shielding layer 180, while the remainder of the trench remains free of significant solid matter. In some embodiments, trench 176 is formed completely through encapsulant 170 to expose the top surface of semiconductor die 104. In this case, shielding layer 180 is formed downwardly and in direct physical contact with the semiconductor die. Shielding layer 180 reduces EMI between components of package 150 and other nearby electronic devices. Shielding layer 180 is optionally connected to a ground voltage node through conductive layer 156 to further reduce EMI. Shielding layer 180 can be connected to conductive layer 156 by sputtering the shielding layer onto the exposed side surfaces of the exposed conductive layer of substrate 152. In addition to shielding against EMI radiation, shielding layer 180 also serves to reduce thermal resistance vertically along the walls of trench 176 between semiconductor die 104 and the top surface of encapsulant 170. Shielding layer 180 is thermally conductive and efficiently transfers thermal energy from semiconductor die 104. The semiconductor package 150 having the grooves 176 and the shielding layer 180 can be used as a conventional heat sink. The grooves 176 increase the exposed surface area for heat dissipation, similar to a heat sink. In addition, the depth of the grooves 176 brings the shielding layer 180 physically closer to the semiconductor die 104, which reduces the thermal resistance between the semiconductor die and the shielding layer. The additional surface area and the reduced encapsulant thickness both increase thermal conductivity, which is desirable for adequate cooling of the semiconductor die 104. Furthermore, the shielding layer 180 is close to or in contact with the semiconductor die 104, eliminating the need for a special molding process such as film-assisted molding to expose the semiconductor die or back grinding to reduce the thickness of the encapsulant. The semiconductor package 150 can be used in the form shown in FIG. 2 c, with the grooves 176 and the shielding layer 180 operating as heat sinks, which reduces the cost and manufacturing complexity of creating a package structure with a separate heat sink that must be applied. FIG2 d illustrates another embodiment in which trenches 176 outside the footprint of semiconductor die 104 are formed deeper into encapsulant 170. Trenches 176 are formed close to or touching the side surfaces of semiconductor die 104, thereby increasing the surface area of ​​shielding layer 180 immediately adjacent to the semiconductor die. Deep trenches 176 around semiconductor die 104 increase the efficiency of heat transfer between the semiconductor die and shielding layer 180 by increasing this surface area. In another embodiment, trenches 176 are formed completely into substrate 152. Semiconductor package 150 also provides additional cooling options, as illustrated in Figures 3a and 3b. Figure 3a shows heat sink 200 mounted to package 150 with thermal interface material (TIM) 202. TIM 202 physically contacts shielding layer 180 and heat sink 200 to enhance thermal coupling therebetween. TIM 202 penetrates and fills trench 176, providing a good thermal interface between shielding layer 180 and heat sink 200. In some embodiments, TIM 202 also serves as the adhesive that physically couples heat sink 200 to semiconductor package 150. Any suitable thermal interface material can be used. By allowing for a larger footprint in all directions, higher fins, more options for fin density and shape, and more surface area for heat dissipation than trench 176 alone, heat sink 200 allows for greater surface area for heat dissipation than trench 176 alone. In some embodiments, the footprint of heat sink 200 is larger than the footprint of package 150. FIG3 b illustrates an embodiment of water cooling. A watertight chamber 210 is formed above the package 150, with the shielding layer 180 forming part of the chamber. The chamber 210 is formed or provided with a seal against the shielding layer 180 to prevent water contained in the chamber from escaping and flowing onto nearby electronic devices. Water 212 or another suitable coolant is pumped into an inlet 214 and then exits through an outlet 216 in the circuit. An optional protective layer can be formed over the EMI shield 180. The protective layer protects the shielding layer 180 from corrosion caused by the water 212. The protective layer can be a polymer material, a different metal that is not susceptible to corrosion, or another suitable material. The protective layer can be sputtered in a manner similar to the shielding layer 180. Water 212 flows across the shield 180, including into the grooves 176, and absorbs heat energy from the semiconductor die 104. The grooves 176 increase the total thermal interface surface area between the water 212 and the shield 180. The water 212 exiting the outlet 216 carries the absorbed heat energy away from the package 150. The water flow loop between the outlet 216 and the inlet 214 includes a pump to keep the water 212 flowing and a heat sink to allow the heat energy in the water to be discharged to the ambient air. FIG5 below shows one embodiment of a complete loop in various embodiments, which can also be used with the chamber 210. Any suitable water cooling device or technology can be used with the package 150. The water 212 can flow across the back of the package 150 parallel or perpendicular to the grooves 176. In some embodiments, a spray plate is used to direct the water 212 downward into the grooves 176. Figures 4a-4c illustrate the formation of a second embodiment of a package 230. Similar to the above description, trench 176 is formed in encapsulant 170 above semiconductor die 104. In addition, trench 232 is formed completely through encapsulant 170 and substrate 152 to form a fluid path that extends completely through package 230 from the top surface to the bottom surface of the package. Trench 232 can expose the side surface of semiconductor die 104, including a peripheral portion of the semiconductor die that can be removed, or a portion of encapsulant 170 can remain between the semiconductor die and trench 232. In one embodiment, each trench 232 is formed along the length or width of the semiconductor die 104, as shown in FIG4b. Each trench 232 has a length substantially equal to the length or width of the semiconductor die 104 and is spaced apart from the semiconductor die such that the trenches do not physically contact one another. In other embodiments, the trenches 232 are formed longer or shorter than the sides of the semiconductor die 104. Multiple trenches 232 can be formed along a single side of the semiconductor die 104, as desired. Shielding layer 180 is conformally sputtered into trench 232, along with trench 176 in FIG4c. Shielding layer 180 coats the inner surface of trench 232 while still allowing water or another fluid to flow between the top and bottom sides of package 230, as shown in FIG4d. Arrows 234 indicate the flow of water 212 along the bottom surface of package 230. Water 212 flows downward along one trench 232 and upward along the other, circulating between the top and bottom sides of package 230. The trenches 232 improve cooling by allowing more surface area of ​​the shield layer 180 near the semiconductor die 104 to absorb thermal energy. The trenches 232 also provide increased surface area of ​​the water 212 for absorbing thermal energy by routing the water close to the side and bottom surfaces of the semiconductor die 104. In some embodiments, the substrate 152 includes a pattern of the conductor layer 156 designed to enhance heat transfer from the semiconductor die 104 to the water 212 in a manner similar to the shield layer 180, e.g., a stack of conductor layers and conductor vias extending completely through the substrate. FIG5 illustrates an immersion cooling embodiment, in which enclosure 230 is immersed in a coolant liquid or fluid. Server racks 250 are located in a reservoir 252 and immersed in liquid coolant 254. Coolant 254 is a thermally conductive but electrically insulating dielectric fluid, such as mineral oil or a fluorocarbon. Each server rack 250 contains a wide range of computer and electrical equipment designed to operate while immersed in coolant 254, including enclosure 230. Reservoir 252 includes an outlet conduit 256, from which coolant 254 is drawn, and an inlet conduit 258, from which coolant 254 is returned to the reservoir. A pump 260 creates a pressure differential to circulate fluid through reservoir 252 and radiator 262. Radiator 262 includes a plurality of metal fins that absorb heat energy from coolant 254, and one or more fans that blow ambient air over the fins, transferring the heat energy to the ambient air. As coolant 254 flows through reservoir 252 from inlet conduit 258 to outlet conduit 256, the fluid flows over and through package 230, including through grooves 232. Thermal energy from semiconductor die 104 is absorbed by coolant 254 and carried to heat sink 262 for exhaust to ambient air. In some embodiments, package 230 is mounted on a printed circuit board (PCB) or other substrate having openings or slots aligned with grooves 232 to allow coolant 254 to flow without significant additional resistance from the PCB. Figures 6a-6c illustrate additional water cooling embodiments with grooves 232 for liquid circulation cooling. Figure 6a shows a horizontal flow embodiment, in which coolant 254 or water 212 flows horizontally across package 230. Package 230 is placed in a fluid chamber 270, which contains coolant 254 and channels it horizontally across the package. As part of this flow, coolant 254 naturally flows into and out of grooves 232. Package 230 is mounted on a substrate 272 that forms part of chamber 270. In other embodiments, substrate 272 is placed within chamber 270 along with package 230. Coolant 254 flows to the right in Figure 6a, passing through the pump and radiator, and then returns to the left across package 230. Thermal energy from semiconductor die 104 is continuously absorbed by coolant 254, and then released to the ambient air through the radiator. In FIG6 b , an underfill 274 is added between package 230 and substrate 272 . Underfill 274 protects bumps 166 from coolant 254 , which can corrode or damage the bumps over time. Underfill 274 can be used with any of the above or below embodiments. Any suitable molding compound, underfill, adhesive, or epoxy compound can be used for underfill 274 . FIG6 c illustrates a vertically oriented liquid cooling embodiment. Coolant 254 or water 212 flows from inlet 280 onto package 230 and returns to the pump and radiator through outlet 282. Coolant 254 flows in parallel between inlet 280 and outlet 282, above and below package 230. The fluid path wall 284 is sized and shaped to allow for approximately equal water flow between the two paths. In some embodiments, the top of path wall 284 is divided into a sealing cover glued to the top of package 230 above groove 232, and the bottom of path wall 284 below package 230 is divided into an adhesive barrier formed between the package and substrate 272. The coolant 254 or water 212 flowing across the top of the package and into groove 176, flowing in parallel through groove 232 and below package 230, absorbs thermal energy from the semiconductor die 104 and removes the heat through outlet 282. Other embodiments include a plurality of stacked packages 230 , with the coolant 254 flowing vertically through each of the packages in series or parallel. While one or more embodiments of the present invention have been described in detail, it will be apparent to those skilled in the art that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims. 100: Wafer 102: Base Substrate Material 104: Semiconductor Die / Component 106: Slice Street 108: Inactive Surface 110: Active Surface 112: Conductive Layer 114: Bump 118: Laser Slicing Tool 150: Package 152: Substrate 154: Insulating Layer 156: Conductive Layer 160: Discrete Component 162: Die Stack 164: Molded Underfill 166: Bump 170: Encapsulant / Mold Compound 176: Groove 178: Laser 180: Shielding Layer / EMI Shield 200: Heat Sink 202: TIM 210: Chamber 212: Water 214: Inlet 216: Outlet 230: Enclosure 232: Groove 234: Arrow 250: Server Rack 252: Reservoir 254: Coolant 256: Outlet Duct 258: Inlet Duct 260: Pump 262: Radiator 270: Chamber 272: Substrate 274: Bottom Filler 280: Inlet 282: Outlet 284: Path Wall [Figures 1a] to 1c] illustrate a semiconductor wafer having a plurality of semiconductor dies separated by dicing lines; [Figures 2a] to 2d] illustrate the formation of a thermal advanced semiconductor package; [Figures 3a] and 3b] illustrate cooling options for the thermal advanced semiconductor package; [Figures 4a] to 4d] illustrate a second embodiment for the thermal advanced semiconductor package; [Figure 5] illustrates the use of the thermal advanced semiconductor package in immersion cooling; and [Figures 6a] to 6c] illustrate options for liquid circulation cooling. 104:Semiconductor chips / components 152:Substrate 154: Insulation layer 156: conductor layer 160: Discrete Components 162: Die stacking 166: Bump 170: Encapsulant / Molding Compound 176: Groove 180: Shielding layer / EMI shielding 230:Package 232: Groove 234: Arrow

Claims

1. A method for manufacturing a semiconductor device, comprising: Provide substrate; Semiconductor chips are disposed above the substrate; An encapsulating agent is deposited on the substrate and the semiconductor die; A first trench is formed in the encapsulant above the semiconductor die; a second trench is formed that extends completely through the encapsulant and the substrate, wherein the encapsulant extends completely around the second trench in a plan view, and wherein the side surface of the semiconductor die is exposed; a conductor layer is formed above the encapsulant and into the first trench and the second trench, wherein the conductor layer completely covers the encapsulant, and covering the encapsulant includes covering each outer surface of the encapsulant and extending continuously from the first trench to the side surface of the substrate, and wherein the conductor layer is formed directly on the side surface of the semiconductor die; and coolant fluid is guided into the first trench and the second trench while the conductor layer remains completely covering the encapsulant.

2. The method of claim 1, further comprising immersing the semiconductor device in a liquid coolant.

3. A method for manufacturing a semiconductor device, comprising: The method includes a semiconductor die and an encapsulant deposited on the semiconductor die; forming a trench in the encapsulant, wherein the trench exposes a side surface of the semiconductor die, and wherein the trench is completely outside the occupied area of ​​the semiconductor die; forming a conductor layer on the encapsulant and in the trench, wherein the conductor layer completely covers the encapsulant, and covering the encapsulant includes covering each outer surface of the encapsulant and extending continuously from the trench to a side surface of the semiconductor package, and wherein the conductor layer is formed directly on the side surface of the semiconductor die in the trench; and guiding the flow of coolant into the trench while the conductor layer remains completely covering the encapsulant.

4. The method of claim 3, further comprising: forming a trench that extends completely through the semiconductor package, wherein the encapsulant remains fully extended around the trench in a plan view.

5. The method of claim 3 further comprises pumping the liquid coolant through the radiator.

6. The method of claim 3, further comprising immersing the semiconductor package in the liquid coolant.

7. A method for manufacturing a semiconductor device, comprising: A semiconductor package is provided, comprising: a substrate; a semiconductor die disposed above the substrate; an encapsulant deposited above the semiconductor die and the substrate; and a trench formed in the encapsulant above the semiconductor die, wherein a side surface of the semiconductor die is exposed in the trench; forming a conductor layer above the semiconductor package and in the trench, wherein the conductor layer extends continuously from within the trench to a side surface of the semiconductor package, and wherein the conductor layer is formed directly on the side surface of the semiconductor die; and guiding a coolant fluid into the trench.

8. The method of claim 7, further comprising disposing the semiconductor package over the second substrate; and applying an underfill to the space between the semiconductor package and the second substrate.

9. The method of claim 7, wherein the trench extends completely through the semiconductor package.

10. The method of claim 7, further comprising: coupling a pump to the trench; and coupling a heat sink to the trench and the pump, wherein the coolant is configured to circulate from the semiconductor package to the heat sink by the pump.

11. The method of claim 7, further comprising immersing the semiconductor package in the liquid coolant.

12. A method for manufacturing a semiconductor device, comprising: A semiconductor package is provided, comprising: a semiconductor die; a trench formed in the semiconductor package, wherein a surface of the semiconductor die is exposed in the trench; a conductor layer formed above the semiconductor package and into the trench, wherein the conductor layer extends continuously from within the trench to a side surface of the semiconductor package, and wherein the conductor layer is formed on the surface of the semiconductor die; and a fluid for guiding coolant into the trench.

13. The method of claim 12 further comprises: disposing the semiconductor package over the second substrate; and applying an underfill material between the semiconductor package and the second substrate.

14. The method of claim 12, wherein the trench extends completely through the semiconductor package.

15. The method of claim 12, further comprising: coupling a pump to the trench; and coupling a heat sink to the trench and the pump, wherein the coolant is configured to circulate from the semiconductor package to the heat sink by the pump.

16. The method of claim 12, further comprising immersing the semiconductor package in the liquid coolant.

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