Semiconductor device

Abstract

The objective of this invention is to stabilize the electrical properties of a transistor constructed using an oxide semiconductor, thereby improving the reliability of the transistor. In an oxide semiconductor film, regions with a higher crystalline content and regions with a higher amorphous content are formed. The regions with a higher crystalline content are configured to function as channel formation regions, while other regions are configured to contain a higher amorphous content. Preferably, the oxide semiconductor film is formed in a self-aligned manner, mixing the regions with a higher crystalline content and the regions with a higher amorphous content. To form regions with different crystallinities within an oxide semiconductor film, after forming an oxide semiconductor film containing a higher crystalline content, a process is first performed to amorphize a portion of the oxide semiconductor film.

Description

Semiconductor devices and electronic equipment This invention relates to a transistor and a method for manufacturing the same. In particular, this invention relates to a transistor forming a channel in an oxide semiconductor layer and a method for manufacturing the same. Furthermore, this invention relates to a semiconductor device having the transistor. Furthermore, in the invention disclosed in this specification, in addition to elements made of silicon semiconductors, elements made of compound semiconductors are also included as components constituting semiconductor integrated circuits, and wide bandgap semiconductors are disclosed as an example. Note that in this specification, a semiconductor device refers to any device that can operate by utilizing the characteristics of semiconductors. Therefore, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. Electronic or optical devices are formed using silicon-based transistors. In recent years, in addition to silicon-based transistors, the technology of manufacturing transistors using oxide semiconductors and applying these transistors to electronic or optical devices has attracted attention. In active-matrix liquid crystal displays, transistors are disposed in each pixel. In many cases, these transistors are made of amorphous silicon, polycrystalline silicon, or similar materials. Note that while transistors made of amorphous silicon have low field-effect mobility, they can handle large-area glass substrates. On the other hand, while transistors made of polycrystalline silicon have high field-effect mobility, they are less suitable for large-area glass substrates. Oxide semiconductors have attracted attention as a constituent material for transistors, replacing silicon-based materials. This is because transistors made of oxide semiconductors have higher field-effect mobility than transistors made of amorphous silicon, and can cope with the large-area development of liquid crystal display devices. For example, Patent Documents 1 and 2 disclose technologies for manufacturing transistors using zinc oxide and In-Ga-Zn-O oxides as oxide semiconductors, and using them as switching elements for pixels in display devices. Furthermore, Patent Document 3 discloses a transistor having a stack of oxide semiconductor films that leave amorphous components at the interface with the base. However, controlling the critical voltage is difficult in transistors made of oxide semiconductors. Specifically, in oxide semiconductors, some of the hydrogen becomes donors and releases electrons as charge carriers. Furthermore, as the carrier concentration in the oxide semiconductor increases, a channel forms within it even without a voltage applied between the gate and source. That is, the critical voltage of the transistor drifts in the negative direction. Even when the field-effect mobility is high, the critical voltage of the transistor is also high or negative, making it difficult to control the circuit including the transistor. When a transistor has a high critical voltage and a large absolute value of that critical voltage, it cannot function as a switch when the drive voltage is low, and may even become a load. Furthermore, when the critical voltage is negative, it easily becomes a so-called normally conducting state, in which current is generated between the source and drain electrodes even when the gate voltage is 0V. When using an n-channel transistor, it is preferable to use a transistor that forms a channel only when a positive voltage is applied to the gate electrode, and the drain current begins to flow. The following transistors are unsuitable for use in circuits: transistors that do not form a channel unless the drive voltage is increased; and transistors that form a channel and allow the drain current to flow even under negative voltage conditions. Furthermore, completely removing hydrogen contained in oxide semiconductors is difficult. Therefore, transistors made of oxide semiconductors are more difficult to control the critical voltage compared to transistors made of silicon-based materials. [Patent Document 1] Japanese Patent Application Publication No. 2007-123861 [Patent Document 2] Japanese Patent Application Publication No. 2007-96055 [Patent Document 3] Japanese Patent Application Publication No. 2011-135066 In view of the above-mentioned problems, one objective of the present invention is to suppress and stabilize the variations in the electrical characteristics of transistors made of oxide semiconductors. Furthermore, one objective of the present invention is to improve the reliability of semiconductor devices. One aspect of the present invention is characterized by using an oxide semiconductor layer comprising regions with distinct crystallinity to construct the transistor. Specifically, the transistor is constructed using an oxide semiconductor layer in which the proportion of crystalline regions in the channel-forming region is higher than the proportion of crystalline regions in other regions. For example, one aspect of the present invention is a transistor comprising: a gate layer; a gate insulating layer disposed on the gate layer; an oxide semiconductor layer disposed on the gate insulating layer; a source electrode layer and a drain electrode layer disposed and isolated on the oxide semiconductor layer; and an etch stop layer disposed on the oxide semiconductor layer in a region between the source electrode layer and the drain electrode layer, wherein in the oxide semiconductor layer, the proportion of a crystalline region overlapping the interface with the etch stop layer is higher than the proportion of a crystalline region overlapping the interface with the source electrode layer or the drain layer. In the transistor with the above-described structure, the proportion of crystalline regions in the first region (channel forming region) is higher than that in the second region (other regions). In other words, the defect density in the first region is lower than that in the second region. Furthermore, defects included in the oxide semiconductor layer easily become trap sites for impurities contained in that oxide semiconductor layer. Therefore, in a transistor according to one aspect of the present invention, impurities such as hydrogen easily diffuse from the first region to the second region, while they do not easily diffuse in the opposite direction (from the second region to the first region). As a result, in a transistor according to one aspect of the present invention, the concentration of impurities such as hydrogen in the channel forming region is suppressed, thereby achieving stabilization of electrical characteristics and improvement of reliability. Furthermore, one other structure of the present invention is a semiconductor device including an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode layer on the gate insulating film, wherein the oxide semiconductor layer has a first region, a second region, and a third region, wherein the first region overlaps the gate electrode layer and is located between the second region and the third region, and the proportion of crystalline component is higher than that of amorphous component, the proportion of amorphous component is higher than that of crystalline component in the second region and the third region, and the hydrogen concentration in the second region and the third region is higher than that in the first region. In the above structure, regions with a higher crystalline content and regions with a higher amorphous content are formed within the pattern of an oxide semiconductor layer. The regions with a higher crystalline content are configured to function as channel formation regions, while the other regions are configured to contain a higher proportion of amorphous content. Preferably, the oxide semiconductor film is formed in a self-aligned manner, mixing the regions with a higher crystalline content and the regions with a higher amorphous content. Furthermore, in the above structure, the second or third region is electrically connected to the source electrode layer or the drain electrode layer and has a higher conductivity than the first region used as the channel forming region. The oxide semiconductor film used as the channel formation region contains a higher degree of crystalline composition, and in this crystalline composition, the preferred c-axis is aligned in the direction parallel to the normal vector of the formed surface of the oxide semiconductor film. By containing a higher degree of crystalline composition in the oxide semiconductor film, the bonding state of metal atoms and oxygen atoms in the region used as the channel formation region is serialized, thereby suppressing the generation of oxygen defects. Furthermore, it is known that in oxide semiconductor films, in addition to oxygen defects, electrons are also generated as charge carriers due to hydrogen. Therefore, it is preferable to also reduce the amount of hydrogen in the oxide semiconductor film used as the channel formation region. At least a portion of an oxide semiconductor film containing crystalline components is formed into a region with a higher amorphous content. Hydrogen is attracted to and trapped in this region (a process also known as intrinsic gettering) to reduce the hydrogen concentration in the region used as the channel formation region to a level lower than that in the region with a higher amorphous content. Hydrogen diffuses into the region with a higher amorphous content, is trapped there, and is stabilized. Transistors using oxide semiconductor films with extremely low minority carrier density and reduced carrier generation sources such as oxygen vacancies and hydrogen in the channel formation region can have extremely small off-state currents. Note that in this specification, “hydrogen” refers to a hydrogen atom, and when it is described as “containing hydrogen”, it also includes hydrogen contained in hydrogen molecules, hydrocarbons, hydroxyl groups, and water. Furthermore, the conductivity is improved when hydrogen is added to the oxide semiconductor film. Therefore, the region with more amorphous components contains more hydrogen than the region with more crystalline components, and the conductivity of the region with more amorphous components is higher than that of the region with more crystalline components. In order to form regions with more crystalline components and regions with more amorphous components in an oxide semiconductor film, a process is first performed to amorphize a portion of the oxide semiconductor film after forming an oxide semiconductor film containing more crystalline components. For example, when the temperature of the substrate to be formed is set to 200°C or higher, an oxide semiconductor film containing more crystalline components can be obtained. Furthermore, even if the temperature of the substrate to be formed is below 200°C, an oxide semiconductor film containing more crystalline components can also be obtained by performing a heat treatment at 200°C or higher after forming the oxide semiconductor film. Moreover, immediately after film formation, the oxide semiconductor film is preferably in a supersaturated state containing more oxygen than its stoichiometric composition. Therefore, it is preferable to form the oxide semiconductor film under conditions where the proportion of oxygen in the sputtering gas is high, and more preferably, to form the oxide semiconductor film in an oxygen atmosphere (100% oxygen gas). Furthermore, when forming an oxide semiconductor film with a high degree of crystallization, it is preferable to appropriately select a process that prevents impurities such as copper, aluminum, and chlorine from being mixed in or adhering to the surface of the oxide semiconductor film. If these impurities adhere to the surface of the oxide semiconductor film, it is preferable to remove the impurities by exposing the surface of the oxide semiconductor film to oxalic acid or dilute hydrofluoric acid, or by performing plasma treatment (such as N2O plasma treatment). In addition, a method for manufacturing a semiconductor device is also an aspect of the present invention, which includes the following steps: forming an oxide semiconductor layer having a crystalline composition having a c-axis that is substantially perpendicular to the top surface of the oxide semiconductor layer; forming a gate insulating film on the oxide semiconductor layer; forming a gate electrode layer on the gate insulating film; using the gate electrode layer as a mask to amorphize a portion of the oxide semiconductor layer; and forming a source electrode layer or a drain electrode layer in contact with the amorphized region. As one of the processes used to amorphize a portion of an oxide semiconductor film, elements can be added using an ion implantation device or an ion plasma device. Specifically, rare gases such as argon, oxygen, or dopants can be added. By using an ion implantation device or an ion plasma device, even if an insulating layer or the like covers the oxide semiconductor film, argon, oxygen, or dopants can be added to the oxide semiconductor film through the insulating layer to amorphize a portion of the oxide semiconductor film. Furthermore, as one of the processes used to amorphize a portion of the oxide semiconductor film, a portion of the oxide semiconductor film can also be exposed to argon plasma or oxygen plasma. Another aspect of the invention is a method for manufacturing a semiconductor device, comprising the steps of: forming an oxide semiconductor layer containing a crystalline composition having a c-axis substantially perpendicular to the top surface of the oxide semiconductor layer; forming a gate insulating film on the oxide semiconductor layer; forming a gate electrode layer on the gate insulating film; exposing a portion of a region in the oxide semiconductor layer overlapping the gate insulating film, amorphizing the exposed region of the oxide semiconductor layer; and forming a source electrode layer and a drain electrode layer in contact with the amorphized region. When a portion of an oxide semiconductor film is exposed to argon or oxygen plasma to amorphize it, amorphization occurs only near the surface of the exposed oxide semiconductor film, leaving crystalline portions below. When the oxide semiconductor film is thin, the exposed area becomes a region with a higher proportion of amorphous components. However, when the amorphized area is thin and the oxide semiconductor film is thick, amorphization occurs only on the surface, while other areas form regions with a higher proportion of crystalline components. Note that the proportion of amorphous components is higher in the plasma-exposed regions than in the unexposed regions (e.g., channel formation regions), and the proportion of crystalline components is lower. Therefore, the plasma-exposed regions can be used as source or drain regions. Furthermore, when heat treatment is performed after a process used to amorphize a portion of the oxide semiconductor film, the amorphized region is recrystallized, thus increasing its crystallinity. However, the crystallinity of the recrystallized region is lower than that of the channel-forming region. This feature is also one aspect of the present invention, which is a semiconductor device comprising an oxide semiconductor layer, a gate insulating film on the oxide semiconductor layer, and a gate electrode layer on the gate insulating film. The oxide semiconductor layer has a first region, a second region, and a third region, wherein the first region overlaps the gate electrode layer, is located between the second and third regions, and has higher crystallinity than the second and third regions. One of the features of the above structure is that the second or third region is electrically connected to the source electrode layer or the drain electrode layer, the interface near the second or third region that contacts the source electrode layer or the drain electrode layer is amorphous, and the hydrogen concentration near the interface is higher than the hydrogen concentration in the first region. Furthermore, sputtering with high power can also be used as one of the processes for amorphizing a portion of an oxide semiconductor film. For example, sputtering is performed when a conductive film for forming wiring is formed on a region contacting a portion of the oxide semiconductor film, causing the portion of the oxide semiconductor film to become amorphous. In this case, depending on the film formation conditions of the conductive film, the portion of the oxide semiconductor film becomes amorphous, thus amorphization of the portion of the oxide semiconductor film can be achieved without increasing the number of processes. Furthermore, by performing a process to amorphize a portion of the oxide semiconductor film, oxygen defects increase in the region with a higher amorphous content compared to the region with a higher crystalline content. These oxygen defects are suppressed by placing an oxygen-excess insulating layer above or below the oxide semiconductor film and by using heat treatment or similar methods to diffuse oxygen into the oxide semiconductor film. Furthermore, the density in regions of the aforementioned oxide semiconductor film with a higher proportion of crystalline components is higher than 6.0 g / cm³. 3 And below 6.375 g / cm 3 When the membrane density is low, the diffusion of oxygen and hydrogen increases. In addition, 6.375 g / cm 3 The density value is that its composition is In 2O 3: Ga 2O 3. The theoretical density value of the In-Ga-Zn-O compound with a molar ratio of 1:1:2 (In:Ga:Zn = 1:1:1 [atomic ratio]). Furthermore, the composition of the oxide semiconductor film can be determined using X-ray photoelectron spectroscopy (XPS). In addition, the film density of oxide semiconductor films can be determined using methods such as Rutherford backscattering spectrometry (RBS) or X-ray reflection (XRR). In addition, as materials for oxide semiconductor films, the following can be used: indium oxide, tin oxide, zinc oxide; binary metal oxides such as In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, and In-Ga oxides; ternary metal oxides such as In-Ga-Zn oxides (also known as IGZO), In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides, and In... Oxides of the following types: -Hf-Zn, In-La-Zn, In-Ce-Zn, In-Pr-Zn, In-Nd-Zn, In-Sm-Zn, In-Eu-Zn, In-Gd-Zn, In-Tb-Zn, In-Dy-Zn, In-Ho-Zn, In-Er-Zn, In-Tm-Zn, In-Yb-Zn, In-Lu-Zn; Quaternary metal oxides such as In-Sn-Ga-Zn, In-Hf-Ga-Zn, In-Al-Ga-Zn, In-Sn-Al-Zn, In-Sn-Hf-Zn, In-Hf-Al-Zn, etc. Additionally, here, for example, In-Ga-Zn oxides refer to oxides containing In, Ga, and Zn, with no limitation on the proportions of In, Ga, and Zn. Furthermore, it is also possible to include metallic elements other than In, Ga, and Zn. For example, In-Ga-Zn oxides with an atomic ratio of In:Ga:Zn = 1:1:1 (= 1 / 3: 1 / 3: 1 / 3) or In:Ga:Zn = 2:2:1 (= 2 / 5: 2 / 5: 1 / 5), or oxides with a similar composition, can be used. Alternatively, In-Sn-Zn oxides with an atomic ratio of In:Sn:Zn = 1:1:1 (= 1 / 3: 1 / 3: 1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3: 1 / 6: 1 / 2), or In:Sn:Zn = 2:1:5 (= 1 / 4: 1 / 8: 5 / 8), or oxides with a similar composition, can also be used. However, this is not a limitation. There are no particular restrictions on the structure of transistors that use regions with higher crystalline content as channel formation regions; for example, top-gate transistors and bottom-gate transistors can be appropriately applied. Additionally, a back-gate electrode can be provided, and the transistor can be reliably kept normally off by applying a voltage to the back-gate electrode. One aspect of the present invention relates to a semiconductor device comprising a transistor or a circuit comprising a transistor. For example, one aspect of the present invention relates to a semiconductor device comprising a transistor having a channel forming region formed by an oxide semiconductor film or a circuit comprising a transistor. For example, one aspect of the present invention relates to: an LSI; a CPU; a power device installed in a power supply circuit; a semiconductor integrated circuit including memory, thyristors, converters, image sensors, etc.; an electro-optical device, exemplified by a liquid crystal display panel; a light-emitting display device having a light-emitting element; and an electronic device in which the aforementioned circuits or devices are mounted as components. In oxide semiconductor films, hydrogen in the channel-forming region is attracted and fixed in areas with higher amorphous content, thus minimizing hydrogen removal from the channel-forming region. This allows the channel-forming region to become a highly purified type I (intrinsic semiconductor) or close to a highly purified type I. By making the channel-forming region type I, the critical voltage of the transistor can be made positive, enabling the realization of a so-called normally off switching element. If a normally off switching element can be implemented, then using this element can provide a semiconductor device with low power consumption. 1: Gate layer 2: Gate insulation layer 3: Oxide semiconductor layer 4: Source electrode layer 5: Drain electrode layer 6: Etching stop layer 7: Area 8: Area 100:Substrate 106: Component isolation insulation layer 108: Gate insulating film 110: Gate electrode 116: Channel Formation Area 120: Impurity Zone 124: Intermetallic compound region 128: Insulation layer 130: Insulation layer 142a: Electrode layer 142b: Electrode layer 144: Oxide semiconductor layer 146: Gate insulating film 148a: Gate electrode 148b: Conductive layer 150: Insulation layer 152: Insulation layer 156: Wiring 160: Transistor 162: Transistor 164: Capacitor Components 185:Substrate 400:Substrate 401: Gate electrode layer 402: Gate insulating film 403: Oxide semiconductor film 404a: Low resistance region 404b: Low resistance region 405a: Source electrode layer 405b: Drain electrode layer 406: Insulating film 407: Insulating film 409: Channel Formation Area 410: Transistor 413: Insulating film 414a: Sidewall insulation layer 414b: Sidewall insulation layer 415: Interlayer insulating film 417a: Insulating film 417b: Insulating film 420: Transistor 436: Substrate insulation layer 440a: Transistor 440b: Transistor 440c: Transistor 440d: Transistor 440e: Transistor 440F: Transistor 440g: Transistor 442: Gate insulating film 445a: Amorphous region 445b: Amorphous region 448: Insulating film 450: Capacitor wiring 451: Capacitor 500:Substrate 502: Gate insulation layer 504: Interlayer insulation layer 505: Color Filter Layer 506: Insulation layer 507: Next door 510: Transistor 511: Gate layer 512: Oxide semiconductor layer 513a: Conductive layer 513b: Conductive layer 520: Capacitor Component 521: Conductive layer 522: Oxide semiconductor layer 523: Conductive layer 530: Crossover of wiring layer 533: Conductive layer 540: Light-emitting element 541: Electrode layer 542: Electroluminescent layer 543: Electrode layer 601:Substrate 602: Photodiode 606a: Semiconductor film 606b: Semiconductor film 606c: Semiconductor film 608: Adhesive layer 613:Substrate 622: Light 631: Insulation layer 633: Interlayer insulation layer 634: Interlayer insulation layer 640: Transistor 641a: Electrode layer 641b: Electrode layer 642: Electrode layer 643: Conductive layer 645: Conductive layer 656: Transistor 658: Reinstallation of signal line for photodiode 659: Gate signal line 671: Photoelectric sensor output signal line 672: Photodetector reference signal line 1141: Switching element 1142: Memory Unit 1143: Memory Unit Group 1189: ROM Interface 1190:Substrate 1191:ALU 1192: ALU controller 1193: Instruction Decoder 1194: Interrupt controller 1195: Timer Controller 1196: Temporary Register 1197: Register Controller 1198: Bus Interface 1199:ROM 3000:Substrate 3001: Transistor 3003a: Electrode 3003b: Electrode 3003c: Electrode 3004: Logic Circuits 3021: Main Body 3022: Fixing part 3023: Display Section 3024: Operation button 3025: External storage slot 3100a: Wiring 3100b: Wiring 3100c: Wiring 3100d: Wiring 3106: Component isolation insulation layer 3140a: Insulating film 3140b: Insulating film 3141a: Insulating film 3141b: Insulating film 3142a: Insulating film 3142b: Insulating film 3170a: Memory Unit 3170b: Memory Unit 3171a: Transistor 3171b: Transistor 3200: Transistor 3202: Transistor 3204: Capacitor Component 3208: Electrode 3210a: Conductive layer 3210b: Conductive layer 3212: Electrode 3214: Electrode 3216: Wiring 3220: Insulation layer 3222: Insulation layer 3224: Insulation layer 3303: Electrode 3400a: Memory Cell Array 3400b: Memory Cell Array 3400n: Memory Cell Array 3501a: Electrode 3501b: Electrode 3501c: Electrode 3502a: Electrode 3502b: Electrode 3502c: Electrode 3503a: Electrode 3503b: Electrode 3505: Electrode 4001:Substrate 4002: Pixel section 4003: Signal line drive circuit 4004: Scan line drive circuit 4005: Sealing material 4006:Substrate 4008: Liquid Crystal Layer 4010: Transistor 4011: Transistor 4013: Liquid Crystal Components 4015: Connecting terminal electrode 4016: Terminal electrode 4018:FPC 4018a: FPC (Flexible Printed Circuit) 4018b: FPC (Flexible Printed Circuit) 4019: Anisotropic conductive layer 4020: Insulation layer 4021: Insulation layer 4030: Electrode layer 4031: Electrode layer 4032: Insulation layer 4033: Insulation layer 4035: Spacer 4510: Next door 4511: Electroluminescent layer 4513: Light-emitting element 4514: Filler material 8000: Television 8001: Casing 8002: Display Unit 8003: Speaker Section 8200: Indoor unit 8201: Outer casing 8202: Air outlet 8203: CPU 8204: Outdoor unit 8300: Electric Refrigeration and Freezing Box 8301: Outer casing 8302: Refrigerator door 8303: Freezer door 8304: CPU 9000: Table 9001: Outer casing 9002: Legs 9003: Display Unit 9004: Display button 9005: Power Supply Cable 9033: Card 9034: Switch 9035: Power switch 9036: Switch 9038: Operation switch 9201: Main Body 9202: Outer shell 9203: Display Unit 9204: Keyboard 9205: External connection port 9206: Pointing device 9630: Outer casing 9631: Display Unit 9631a: Display Unit 9631b: Display Unit 9632a: Area 9632b: Area 9633: Solar Cell 9634: Charge / Discharge Control Circuit 9635: Battery 9636: DC-DC converter 9637: Converter 9638: Operation Key 9639: Button 9700: Electric vehicle 9701: Secondary battery 9702: Control Circuit 9703: Drive unit 9704: Processing device In the diagram: Figure 1A is a top view showing a structural example of a transistor, and Figure 1B is a cross-sectional view showing a structural example of a transistor. Figures 2A to 2C are cross-sectional views illustrating examples of transistor manufacturing processes; Figures 3A to 3C are cross-sectional views illustrating examples of transistor manufacturing processes; Figures 4A to 4C are diagrams illustrating an example of a display device; Figures 5A and 5B are diagrams illustrating an example of a display device; Figures 6A and 6B are diagrams illustrating an example of a display device; Figures 7A and 7B are diagrams illustrating an example of an image sensor; Figures 8A and 8B are diagrams illustrating an example of a memory device; Figures 9A to 9C are model diagrams used to calculate the movement of excess oxygen; Figure 10 shows the calculation results of the model diagrams in Figures 9A to 9C; Figures 11A to 11C are model diagrams used to calculate oxygen defect movement; Figure 12 shows the calculation results of the model diagrams in Figures 11A to 11C; Figures 13A to 13E are cross-sectional and top views illustrating one aspect of the present invention. Figures 14A to 14E are cross-sectional views illustrating one aspect of the present invention; Figures 15A to 15D are cross-sectional views illustrating one aspect of the present invention; Figures 16A and 16B are cross-sectional views illustrating one aspect of the present invention; Figures 17A and 17B are cross-sectional views illustrating one aspect of the present invention; Figures 18A to 18C are cross-sectional views, top views, and circuit diagrams illustrating one embodiment of a semiconductor device; Figure 19 is a perspective view showing one embodiment of a semiconductor device; Figure 20 is a cross-sectional view showing one embodiment of a semiconductor device; Figures 21A to 21C are block diagrams illustrating one embodiment of a semiconductor device and circuit diagrams of a portion thereof. Figures 22A to 22C are diagrams illustrating the electronic device; Figures 23A to 23C are diagrams illustrating the electronic device; Figures 24A to 24C are diagrams illustrating electronic devices. However, the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in various forms. Furthermore, the present invention should not be construed as being limited solely to the embodiments described below. Implementation Method 1 The following describes one aspect of the present invention in detail. <1. Transistor> Referring to Figures 1A to 3C, examples of the structure and manufacturing process of a transistor according to one aspect of the present invention are described. <1-1. Examples of Transistor Structures> Figures 1A and 1B are diagrams illustrating a structural example of a transistor according to one aspect of the present invention. Specifically, Figure 1A is a top view of the transistor, and Figure 1B is a cross-sectional view of the transistor along AB shown in Figure 1A. The transistors shown in Figures 1A and 1B have: a gate layer 1 disposed on a substrate 100; a gate insulating layer 2 disposed on the gate layer 1; an oxide semiconductor layer 3 disposed on the gate insulating layer 2; a source electrode layer 4 and a drain electrode layer 5 disposed and isolated on the oxide semiconductor layer 3; and an etch stop layer 6 disposed on the oxide semiconductor layer 3 in the region between the source electrode layer 4 and the drain electrode layer 5. In simple terms, the transistors shown in Figures 1A and 1B are anti-interlaced type (etch stop type, channel stop type) transistors with the etch stop layer 6. Note that in the transistors shown in Figures 1A and 1B, the etch stop layer 6 is disposed not only on the oxide semiconductor layer 3 in the region between the source electrode layer 4 and the drain electrode layer 5, but also between the end of the oxide semiconductor layer 3 and the source electrode layer 4 and the drain electrode layer 5. In other words, the source electrode layer 4 and the drain electrode layer 5 are in contact with the oxide semiconductor layer 3 through the openings provided in the etch stop layer 6. Furthermore, in the oxide semiconductor 3 of the transistor shown in Figures 1A and 1B, the crystallinity of region 7, which overlaps with the interface to the etch stop layer 6, and region 8, which overlaps with the interface to the source electrode layer 4 or the drain electrode layer 5, differs. Specifically, the proportion of crystalline regions in region 7 is higher than that in region 8. Moreover, region 7 comprises all or most of the region where a channel is formed according to the voltage between the gate layer 1 and the source electrode layer 4. In other words, in the transistors shown in Figures 1A and 1B, the defect density in region 7, where channels are formed, is lower than that in region 8. Here, defects in the oxide semiconductor layer 3 easily become trap sites for impurities such as hydrogen contained in the oxide semiconductor layer 3. Therefore, in the transistors shown in Figures 1A and 1B, impurities such as hydrogen easily diffuse from region 8 to region 7, while they do not easily diffuse from region 7 to region 8. As a result, in the transistors shown in Figures 1A and 1B, the concentration of impurities such as hydrogen in region 7 is suppressed, thereby achieving stabilization of electrical characteristics and improved reliability. Furthermore, improvements in switching characteristics can be achieved in the transistors shown in Figures 1A and 1B. These improvements will be explained in detail below. The electrical properties of transistors forming channels in oxide semiconductors can sometimes change depending on the processing or heat treatment conditions. This change is caused by the introduction of impurities (such as chlorine, fluorine, boron, or hydrogen) during the formation process of the oxide semiconductor, or by the removal of oxygen from the oxide semiconductor. These introductions or removals are easily noticeable at the ends of the oxide semiconductor. That is, in transistors forming channels in oxide semiconductors, the ends of the oxide semiconductor become low-resistance regions, and parasitic channels of the transistor are easily formed in these low-resistance regions. Note that in this transistor, it is possible to form two types of channels: a channel formed in the shortest path between the source and drain based on the voltage between the gate and source regions of the oxide semiconductor (also called the former channel), and the parasitic channel (also called the latter channel). In transistors that can potentially form two types of channels, the critical voltage between the gate and source differs for each channel. Typically, the critical voltage for the channel with the former type of channel is higher than that for the channel with the latter type of channel. Furthermore, the current-driving capability of the channel with the former type of channel is higher than that of the channel with the latter type of channel. Therefore, when the gate-source voltage of the transistor rises in the off state, the current between the source and drain undergoes a two-stage change. Specifically, a first-stage change (an increase in the current between the source and drain) is observed near the critical voltage of the channel with the latter type of channel, and a second-stage change (an increase in the current between the source and drain) is observed near the critical voltage of the channel with the former type of channel. In the transistors shown in Figures 1A and 1B, the etch stop layer 6 is disposed between the end of the oxide semiconductor layer 3 and the source electrode layer 4 and drain electrode layer 5. Therefore, if the region at the end of the oxide semiconductor layer 3 is a low-resistance region, no parasitic channels are formed in the transistors shown in Figures 1A and 1B. That is to say, improved switching characteristics can be achieved in the transistors shown in Figures 1A and 1B. Furthermore, the structure capable of improving switching characteristics is not limited to the structures shown in Figures 1A and 1B. Since the source and drain electrodes of the transistor are electrically connected to this end, a parasitic channel is formed at the end of the oxide semiconductor layer. Therefore, the switching characteristics of the transistor can be improved as long as at least one of the source electrode layer 4 and the drain electrode layer 5 is not electrically connected to the end of the oxide semiconductor layer 3. For example, when a transistor with a structure in which at least one of the source electrode layer 4 and the drain electrode layer 5 does not contact the side surface of the oxide semiconductor layer 3, the switching characteristics can be improved. <1-1-1. Specific example of substrate 100> As the substrate 100, any substrate can be used as long as it has heat resistance sufficient to withstand the heat treatment during the transistor manufacturing process. For example, substrates such as glass substrates, ceramic substrates, quartz substrates, and sapphire substrates can be used. Furthermore, a flexible substrate can also be used as the substrate 100. Additionally, to prevent impurities contained in the substrate 100 from being incorporated into the oxide semiconductor layer formed subsequently, an insulating layer can be formed on the substrate 100. <1-1-2. Specific Examples of Gate Layer 1> As the gate layer 1, a film composed of elements selected from aluminum, copper, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium, or alloys composed of these elements, can be used. Alternatively, stacks of these films can also be used. Furthermore, nitrogen-containing metal oxides can also be used as gate layer 1, specifically nitrogen-containing In-Ga-Zn-O films, nitrogen-containing In-Sn-O films, nitrogen-containing In-Ga-O films, nitrogen-containing In-Zn-O films, nitrogen-containing Sn-O films, nitrogen-containing In-O films, or metal nitride films (InN, SnN, etc.). These films have a work function of 5 eV or higher, preferably 5.5 eV or higher. When these films are used as gates, the critical voltage of the transistor can be made positive, thus enabling a so-called normally-off switching element. <1-1-3. Specific examples of gate insulation layer 2> As the gate insulating layer 2, silicon oxide films, silicon nitride films, silicon oxynitride films, silicon oxynitride films, aluminum oxide films, aluminum oxynitride films, or gallium oxide films can be used. Furthermore, stacks of these materials can also be used. Note that "silicon oxynitride" and "aluminum oxynitride" refer to substances in which the oxygen content is greater than the nitrogen content. Note that "silicon oxynitride" refers to substances in which the nitrogen content is greater than the oxygen content. In particular, the gate insulating layer 2 is preferably a layer including an alumina film. The alumina film has a high blocking effect, that is, it prevents both impurities such as hydrogen and oxygen from passing through the film. Therefore, by using a layer including an alumina film as the gate insulating layer 2, oxygen can be prevented from detaching from the oxide semiconductor layer 3, and impurities such as hydrogen can be prevented from mixing into the oxide semiconductor layer 3. In addition, hafnium oxide film, yttrium oxide film, and hafnium silicate (HfSi) film can be used as the gate insulating layer 2. x O y (x>0, y>0) membrane, hafnium silicate membrane with added nitrogen, hafnium aluminate (HfAl) membrane x O y (x>0, y>0) membranes or lanthanum oxide membranes (membranes made of so-called high-k materials). By using such membranes, gate leakage current can be reduced. <1-1-4. Specific examples of oxide semiconductor layer 3> <(1) Materials> As the oxide semiconductor layer 3, a film containing at least indium can be used. In particular, a film containing both indium and zinc is preferred. In addition, as a stabilizer to reduce the inhomogeneity of the electrical properties of the transistor, a film containing gallium is also preferred in addition to the aforementioned film. Furthermore, as the oxide semiconductor layer 3, a film containing tin; hafnium; aluminum; zirconium; or one or more of the lanthanide elements lanthanum, cerium, tungsten, neodymium, samarium, europium, thorium, tungsten, dysprosium, thulium, erbium, thium, ytterbium, and ruthenium can be used as a stabilizer. For example, as the oxide semiconductor layer 3, the following can be applied: indium oxide films; In-Zn type oxide films, In-Mg type oxide films, and In-Ga type oxide films of binary metal oxides; In-Ga-Zn type oxide films, In-Al-Zn type oxide films, In-Sn-Zn type oxide films, In-Hf-Zn type oxide films, In-La-Zn type oxide films, In-Ce-Zn type oxide films, In-Pr-Zn type oxide films, and In-Nd-Zn type oxide films. In-Sm-Zn oxide films, In-Eu-Zn oxide films, In-Gd-Zn oxide films, In-Tb-Zn oxide films, In-Dy-Zn oxide films, In-Ho-Zn oxide films, In-Er-Zn oxide films, In-Tm-Zn oxide films, In-Yb-Zn oxide films, In-Lu-Zn ​​oxide films; quaternary metal oxide films, In-Sn-Ga-Zn oxide films, In-Hf-Ga-Zn oxide films, In-Al-Ga-Zn oxide films, In-Sn-Al-Zn oxide films, In-Sn-Hf-Zn oxide films, In-Hf-Al-Zn oxide films. For example, "In-Ga-Zn oxides" refers to oxides with In, Ga, and Zn as the main components, without any restrictions on the proportions of In, Ga, and Zn. Furthermore, it may also include metallic elements other than In, Ga, and Zn. In addition, a portion of the oxygen constituting the oxide semiconductor layer 3 can also be replaced with nitrogen. <(2) Crystal structure> As described above, the oxide semiconductor layer 3 is a film in which the proportion of crystalline regions varies, for example, an oxide semiconductor film containing both amorphous and crystalline regions. Within this crystalline region, the crystalline structure of the oxide semiconductor is not limited to a specific structure. The crystalline region of an oxide semiconductor film is composed of at least one of c-axis aligned crystal (CAAC), polycrystalline, or microcrystalline. The defect state density of microcrystalline is higher than that of CAAC. Note that oxide semiconductors including CAAC are referred to as CAAC-OS (c-axis aligned crystalline oxide semiconductor). For example, the crystalline regions of an oxide semiconductor film may include CAAC-OS. In CAAC-OS, for example, the c-axis is aligned and the a-axis and / or b-axis are not macroscopically aligned. For example, the crystalline regions of an oxide semiconductor film may include microcrystals. Note that an oxide semiconductor comprising microcrystals is referred to as a microcrystalline oxide semiconductor. The crystalline regions of an oxide semiconductor film comprising microcrystalline oxide semiconductors may, for example, include microcrystals (also called nanocrystals) with a size greater than or equal to 1 nm and less than 10 nm. Alternatively, the crystalline regions of an oxide semiconductor film comprising microcrystalline oxide semiconductors may, for example, include a crystalline-amorphous mixed phase structure with crystalline portions (each greater than or equal to 1 nm and less than 10 nm) distributed. The amorphous region of an oxide semiconductor film includes at least an amorphous portion. For example, the amorphous region of an oxide semiconductor film may include microcrystals. Note that an oxide semiconductor including an amorphous portion is referred to as an amorphous oxide semiconductor. The defect state density of the amorphous portion is higher than that of microcrystals or CAAC. The amorphous region of an oxide semiconductor film including an amorphous oxide semiconductor may, for example, have a disordered atomic arrangement and lack crystalline components. Alternatively, the amorphous region of an oxide semiconductor film including an amorphous oxide semiconductor may, for example, be completely amorphous and lack crystalline portions. Alternatively, the oxide semiconductor film can be a hybrid film comprising any one of CAAC-OS, microcrystalline oxide semiconductor, and amorphous oxide semiconductor. For example, the hybrid film may include regions of amorphous oxide semiconductor, regions of microcrystalline oxide semiconductor, and regions of CAAC-OS. In addition, the crystalline region of the oxide semiconductor film can be in a single-crystal state, for example. The oxide semiconductor film preferably comprises multiple crystalline regions. In each crystalline region, the c-axis is preferably aligned in a direction parallel to the normal vector of the surface on which the oxide semiconductor film is formed. Note that, between crystalline regions, the directions of the a-axis and b-axis of one crystalline region may differ from those of another. An example of such an oxide semiconductor film is the CAAC-OS film. The CAAC-OS film can be used in the crystalline regions of an oxide semiconductor film. The CAAC-OS film will be described in detail below. CAAC-OS films are not completely amorphous. CAAC-OS films, for example, comprise oxide semiconductors with a mixed crystalline-amorphous phase structure, exhibiting a mixture of crystalline and amorphous portions. Furthermore, in most cases, the crystalline portions are preferably located within a cube with a side length less than 100 nm. In images obtained using transmission electron microscopy (TEM), the boundaries between amorphous and crystalline portions, as well as the boundaries between crystalline portions themselves, are not clearly observable in CAAC-OS films. Additionally, grain boundaries are not clearly observable in CAAC-OS films using TEM. Therefore, the reduction in electron mobility due to grain boundaries is suppressed in CAAC-OS films. In each of the crystalline portions included in the CAAC-OS film, for example, the c-axis is aligned in a direction parallel to the normal vector of the surface on which the CAAC-OS film is formed or the normal vector of the surface of the CAAC-OS film. Furthermore, in each crystalline portion, when viewed from a direction perpendicular to the ab plane, the metal atoms are arranged in a triangular or hexagonal structure, and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or in a layered arrangement of metal and oxygen atoms. Note that the directions of the a-axis and b-axis of one crystalline portion may differ from those of another crystalline portion. In this specification, the term "perpendicular" includes a range from 80° to 100°, preferably from 85° to 95°. And the term "parallel" includes a range from -10° to 10°, preferably from -5° to 5°. In CAAC-OS films, the distribution of crystals is not necessarily uniform. For example, in the formation process of CAAC-OS films, when crystal growth occurs from the surface side of the oxide semiconductor film, sometimes the proportion of crystals near the surface of the oxide semiconductor film is higher than that near the surface where the oxide semiconductor film is formed. Because the c-axis of the crystalline portion included in the CAAC-OS film is parallel to either the normal vector of the surface on which the CAAC-OS film is formed or the normal vector of the surface of the CAAC-OS film, the direction of the c-axis can sometimes differ depending on the shape of the CAAC-OS film (the cross-sectional shape of the surface on which the CAAC-OS film is formed or the cross-sectional shape of the surface of the CAAC-OS film). Furthermore, crystalline portions are formed during film formation or after film formation via crystallization treatments such as heat treatment. Therefore, the c-axis of the crystalline portion is parallel to either the normal vector of the surface on which the CAAC-OS film is formed or the normal vector of the surface of the CAAC-OS film. Transistors using CAAC-OS films exhibit minimal changes in electrical properties due to exposure to visible or ultraviolet light. Therefore, these transistors possess high reliability. Note that oxygen removal from the CAAC-OS film tends to occur from the side (end face) of the film (this will be explained in detail in the "Supplementary Explanation: Oxygen Removal from the Oxide Semiconductor Layer" section below). Therefore, when using a CAAC-OS film as the oxide semiconductor layer 3, it is preferable to use a transistor with an etch stop layer 6 disposed between the end of the oxide semiconductor layer 3 and the source electrode layer 4 and drain electrode layer 5, as shown in Figures 1A and 1B. This is because the formation of parasitic channels in the transistor can be prevented. <(3) Layer structure> As the oxide semiconductor layer 3, not only can a single oxide semiconductor film be used, but also a stack of multiple oxide semiconductor films can be used. For example, at least two of the following layers can be used as the oxide semiconductor layer 3: amorphous oxide semiconductor film, polycrystalline oxide semiconductor film, and CAAC-OS film. Alternatively, a layer composed of stacks of oxide semiconductor films with different compositions can be used as oxide semiconductor layer 3. Specifically, a layer comprising a first oxide semiconductor film (hereinafter also referred to as the lower layer) in contact with the gate insulating layer 2 and a second oxide semiconductor film (hereinafter also referred to as the upper layer) in contact with the source electrode layer 4, the drain electrode layer 5 and the etch stop layer 6, the composition of which is different from that of the first oxide semiconductor film, can be used as oxide semiconductor layer 3. For example, when both the lower and upper layers contain indium, gallium, and zinc, it is preferable to set the indium concentration in the lower layer to be higher than the indium concentration in the upper layer, and set the gallium concentration in the upper layer to be higher than the gallium concentration in the lower layer, or / and set the indium concentration in the lower layer to be higher than the gallium concentration in the lower layer, and set the gallium concentration in the upper layer to be the same as the indium concentration in the upper layer. Therefore, it is possible to improve the mobility of the transistor with oxide semiconductor layer 3 and suppress the formation of parasitic channels. Specifically, the improved mobility of the transistor can be achieved by setting a high indium concentration in the lower layer. This is because the s-orbitals of heavy metals in oxide semiconductors mainly contribute to carrier conduction, and the overlap of s-orbitals increases when the In content is increased. Furthermore, by setting a high gallium concentration in the upper layer, oxygen desorption can be suppressed, thereby suppressing the formation of parasitic channels in the upper layer. This is because Ga has a higher oxygen defect formation energy than In, making it less prone to oxygen defect formation. <1-1-4. Specific examples of source electrode layer 4 and drain electrode layer 5> The source electrode layer 4 and the drain electrode layer 5 can be composed of films made of elements selected from aluminum, copper, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium, alloys containing these elements, or nitrides containing these elements. Alternatively, stacks of these films can also be used. Furthermore, transparent conductive films can also be used as the source electrode layer 4 and the drain electrode layer 5. For example, indium tin oxide (In₂O₃) can be used. 2O 3-SnO 2) Membrane, indium oxide and zinc oxide (In 2O 3-ZnO) membranes or membranes that contain silicon oxide. <1-1-5. Specific example of etch stop layer 6> As the etch stop layer 6, silicon oxide film, silicon nitride film, silicon oxynitride film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film, or gallium oxide film can be used. Alternatively, a stack of these materials can also be used. In particular, it is preferable to use a layer including an aluminum oxide film as the etch stop layer 6. This is because by using a layer including an aluminum oxide film as the etch stop layer 6, oxygen can be prevented from detaching from the oxide semiconductor layer 3, and impurities such as hydrogen can be prevented from mixing into the oxide semiconductor layer 3. <1-2. Examples of Transistor Manufacturing Processes> Figures 2A to 2C and 3A to 3C are diagrams illustrating examples of the manufacturing process of the transistors shown in Figures 1A and 1B. Specifically, Figures 2A to 2C and 3A to 3C are cross-sectional views illustrating the manufacturing process of the transistor. <(1) Formation of gate layer 1 (Fig. 2A)> First, a conductive film is formed on the substrate 100. Next, a mask is formed on the conductive film using photolithography. Then, the portions of the conductive film not covered by the mask are removed by etching. As a result, a gate layer 1 is formed. The conductive film can be formed by sputtering or similar methods. Alternatively, heat treatment can be performed before, after, or after the formation of the gate layer 1. For example, a GRTA (Gas Rapid Thermal Anneal) apparatus using high-temperature gas can be used, with heat treatment at 650°C for 1 to 5 minutes. Furthermore, rare gases such as argon or inert gases such as nitrogen can be used as the high-temperature gas in the GRTA. Alternatively, an electric furnace can be used, with heat treatment at 500°C for 30 minutes to 1 hour. <(2) Formation of gate insulation layer 2 (Fig. 2B)> Next, a gate insulating layer 2 is formed on the substrate 100 and the gate layer 1. The gate insulating layer 2 can be formed by plasma CVD, sputtering, or other methods. Furthermore, after forming the gate insulating layer 2, a heat treatment aimed at reducing the water or hydrogen content can be performed. For example, a heat treatment at 300°C or higher and 700°C or lower for no more than 1 hour under reduced pressure or an inert atmosphere can be performed. This suppresses hydrogen incorporation into the subsequently formed oxide semiconductor layer 3. Furthermore, when the gate insulating layer 2 includes an aluminum oxide film, the aluminum oxide film can be formed by directly forming the film using a sputtering method or by performing an oxidation treatment after forming the aluminum film. Examples of such oxidation treatments include oxygen plasma treatment or oxygen doping treatment. Furthermore, the alumina film possesses high barrier properties. Therefore, when forming the gate insulating layer 2 including the alumina film, it is preferable to perform a heat treatment aimed at reducing the water or hydrogen content before forming the alumina film. Specifically, it is preferable to perform this heat treatment after forming the insulating film other than the alumina film constituting the gate insulating layer 2 and before forming the alumina film, or after forming the aluminum film and before performing the oxidation treatment on the aluminum film. This allows for efficient reduction of the water or hydrogen content in the formed gate insulating layer 2. <(3) Formation of oxide semiconductor layer 3 (Fig. 2C)> Next, an oxide semiconductor film is formed on the gate insulating layer 2. Then, a mask is formed on the oxide semiconductor film using photolithography. Finally, the portions of the oxide semiconductor film not covered by the mask are removed by etching. As a result, an oxide semiconductor layer 3 is formed. The oxide semiconductor film can be formed by sputtering or the like. Furthermore, it is preferable to form the oxide semiconductor film under conditions where the oxide semiconductor film contains a relatively high amount of oxygen (e.g., film formation by sputtering in an atmosphere with 100% oxygen). This increases the amount of oxygen contained in the oxide semiconductor film (preferably including regions with an excess of oxygen compared to the stoichiometric composition of the oxide semiconductor in its crystalline state). Additionally, to improve the crystallinity of the oxide semiconductor film, the film formation can be performed while the substrate 100 is heated. Furthermore, a heat treatment aimed at reducing the water or hydrogen content can be performed after the formation of the oxide semiconductor film or the formation of the oxide semiconductor layer 3. For example, a heat treatment at a temperature of 300°C or higher and 700°C or lower for no more than 1 hour can be performed under reduced pressure or an inert atmosphere. Moreover, when the gate insulating layer 2 is an oxygen-containing insulating layer, the oxygen contained in the gate insulating layer 2 due to this heat treatment may be supplied to the oxide semiconductor film or the oxide semiconductor layer 3. Therefore, even if an oxygen defect occurs in the oxide semiconductor film or the oxide semiconductor layer 3 due to this heat treatment, the oxygen defect can be filled by the oxygen supply from the gate insulating layer 2. <(4) Formation of etch stop layer 6 (Fig. 3A)> Next, an insulating film is formed on the gate insulating layer 2 and the oxide semiconductor layer 3. Then, a mask is formed on the insulating film using photolithography. Finally, the portion of the insulating film not covered by the mask is removed by etching. As a result, an etch stop layer 6 is formed. The insulating film can be formed by plasma CVD, sputtering, or other methods. Furthermore, after forming the etch stop layer 6, a heat treatment aimed at reducing the water or hydrogen content can be performed. For example, a heat treatment at 300°C or higher and 700°C or lower for no more than 1 hour under reduced pressure or an inert atmosphere can be performed. This suppresses hydrogen incorporation into the oxide semiconductor layer 3. Furthermore, when the etch stop layer 6 includes an aluminum oxide film, the aluminum oxide film can be formed by directly depositing the film using a sputtering method or by performing an oxidation process after forming the aluminum film. Examples of such oxidation processes include oxygen plasma treatment or oxygen doping treatment. Furthermore, the alumina film possesses high barrier properties. Therefore, when forming the etch stop layer 6, which includes the alumina film, it is preferable to perform a heat treatment aimed at reducing the water or hydrogen content before forming the alumina film. Specifically, it is preferable to perform this heat treatment after forming the insulating film other than the alumina film constituting the etch stop layer 6 and before forming the alumina film, or after forming the aluminum film and before performing the oxidation treatment on the aluminum film. This allows for efficient reduction of the water or hydrogen content in the formed etch stop layer 6. <(5) Crystallinity control of oxide semiconductor layer 3 (Figure 3B)> Next, plasma treatment is performed. Furthermore, in this plasma, inert gases such as argon and nitrogen, or oxygen gas, are used as the gas. As a result, crystallization occurs in specific regions of the oxide semiconductor layer 3. Specifically, crystallization occurs in regions 8 that are not covered by the etch stop layer 6. Consequently, the proportion of crystalline regions in regions 7 covered by the etch stop layer 6 is higher than the proportion of crystalline regions in regions 8. <(6) Formation of source electrode layer 4 and drain electrode layer 5 (Fig. 3C)> Next, a conductive film is formed on the oxide semiconductor layer 3 and the etch stop layer 6. Then, a mask is formed on the conductive film using photolithography. Next, the portions of the conductive film not covered by the mask are removed by etching. As a result, the source electrode layer 4 and the drain electrode layer 5 are formed. The conductive film can be formed by sputtering or the like. Furthermore, when the conductive film is formed by sputtering, the crystals contained in region 8 of the oxide semiconductor layer 3 can be made amorphous by setting certain conditions. For example, increasing the sputtering power can promote the amorphization of region 8. In this case, the process of <(5) control of crystallinity of oxide semiconductor layer 3> can be omitted. <2. Semiconductor Devices> Hereinafter, specific examples of semiconductor devices constructed using the above-described transistors will be described with reference to Figures 4A to 8B. <2-1. Display Device> Figures 4A to 4C are diagrams illustrating an example of a display device constructed using the aforementioned transistor. Specifically, the display devices shown in Figures 4A to 4C are display devices in which all or part of the driving circuit and the pixel section are disposed on the same substrate (so-called system-on-panel display devices). Furthermore, the aforementioned transistor can be used as the transistor disposed in both the driving circuit and the pixel section. In Figure 4A, a sealing material 4005 is provided around a pixel portion 4002 disposed on a substrate 4001, and a substrate 4006 is used for sealing. In Figure 4A, a scan line driving circuit 4004 and a signal line driving circuit 4003 formed on an IC wafer or a separately prepared substrate using a single-crystal semiconductor film or a polycrystalline semiconductor film are mounted in an area on the substrate 4001 that is different from the area surrounded by the sealing material 4005. Furthermore, various signals and potentials supplied to the separately formed signal line driving circuit 4003, scan line driving circuit 4004, or pixel portion 4002 are supplied from FPCs (Flexible printed circuits) 4018a and 4018b. In Figures 4B and 4C, a sealing material 4005 is provided around the pixel portion 4002 and the scan line driving circuit 4004 disposed on the substrate 4001. Furthermore, a substrate 4006 is disposed on the pixel portion 4002 and the scan line driving circuit 4004. Therefore, the pixel portion 4002, the scan line driving circuit 4004, and the display element are sealed together by the substrate 4001, the sealing material 4005, and the substrate 4006. In Figures 4B and 4C, a signal line driving circuit 4003 formed on an IC wafer or a separately prepared substrate using a single-crystal semiconductor film or a polycrystalline semiconductor film is mounted in an area on the substrate 4001 different from the area surrounded by the sealing material 4005. In Figures 4B and 4C, various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scan line driving circuit 4004, or the pixel portion 4002 are supplied from the FPC 4018. Furthermore, Figures 4B and 4C show examples of separately forming a signal line driving circuit 4003 and mounting the signal line driving circuit 4003 onto the substrate 4001, but the structure is not limited to this. Alternatively, a separate scan line driving circuit can be formed and mounted, or only a portion of the signal line driving circuit or a portion of the scan line driving circuit can be separately formed and mounted. Furthermore, there are no particular restrictions on the connection method for the separately formed drive circuit, and methods such as COG (Chip On Glass), wire bonding, or TAB (Tape Automated Bonding) can be used. Figure 4A shows an example of mounting the signal line drive circuit 4003 and the scan line drive circuit 4004 using the COG method, Figure 4B shows an example of mounting the signal line drive circuit 4003 using the COG method, and Figure 4C shows an example of mounting the signal line drive circuit 4003 using the TAB method. In addition, the display device includes a panel in which the display element is sealed and a module in which an IC including a controller is installed. Note that the display device in this specification refers to an image display device, a display apparatus, or a light source (including lighting equipment). Additionally, the display device also includes: modules with connectors such as FPCs or TCPs; modules with printed circuit boards at the ends of the TCPs; or modules in which ICs (integrated circuits) are directly mounted to the display element via COG (Chip-on-Glass) mounting. Furthermore, the pixel section and scan line driving circuit provided on the substrate have multiple transistors, and the transistors shown in Embodiment 1 can be used. As display elements installed in a display device, liquid crystal elements (also known as liquid crystal display elements) and light-emitting elements (also known as light-emitting display elements) can be used. Light-emitting elements include those whose brightness is controlled by current or voltage; specifically, they include inorganic EL (Electro-luminescence) and organic EL. In addition, display media such as electronic ink, which change contrast due to electrical effects, can also be used. Furthermore, one embodiment of the display device will be described using Figures 4A to 4C, as well as Figures 6A and 6B. Figure 6A corresponds to a cross-sectional view along line MN, which is cut off in Figure 4B. As shown in Figures 4A to 4C and Figures 6A and 6B, the display device includes a connection terminal electrode 4015 and a terminal electrode 4016, which are electrically connected to the terminals of the FPC 4018 via an anisotropic conductive layer 4019. The terminal electrode 4015 is formed of the same conductive layer as the first electrode layer 4030, and the terminal electrode 4016 is formed of the same conductive layer as the source electrode layer and drain electrode layer of transistors 4010 and 4011. Furthermore, the pixel portion 4002 and the scan line driving circuit 4004 disposed on the substrate 4001 have multiple transistors. Figures 4A to 4C, and Figures 6A and 6B illustrate the transistor 4010 included in the pixel portion 4002 and the transistor 4011 included in the scan line driving circuit 4004. In Figure 6A, an insulating layer 4020 is disposed on the transistors 4010 and 4011, and in Figure 6B, an insulating layer 4021 is also disposed. The aforementioned transistors 4010 and 4011 can be used. Furthermore, Figures 6A and 6B show transistors with a structure having an oxide semiconductor layer extending to the outer side of the ends of the source and drain electrode layers. In transistors with such a structure, the formation of parasitic channels in the transistor can be suppressed without providing an etch stop layer between the ends of the oxide semiconductor layer and the source and drain electrode layers. Furthermore, a conductive layer may be provided at a location overlapping the oxide semiconductor layer of the transistor 4011 used in the driving circuit. The potential of the conductive layer may be the same as or different from the potential of the gate electrode layer of the transistor 4011, and it may also serve as a second gate electrode layer. Furthermore, the potential of the conductive layer may be GND, 0V, or a floating state. This conductive layer has the function of shielding external electric fields, that is, preventing external electric fields from acting on the interior (including the circuit section of the transistor) (especially, the electrostatic shielding function of shielding against static electricity). By utilizing the shielding function of the conductive layer, the electrical characteristics of the transistor can be prevented from changing due to the influence of external electric fields such as static electricity. The transistor 4010 disposed in the pixel section 4002 is electrically connected to the display element, thereby constituting a display panel. There are no particular limitations on the display element as long as it can perform display, and a variety of display elements can be used. <2-1-1. Liquid Crystal Display Device> Figure 6A shows an example of a liquid crystal display device using a liquid crystal element as a display element. In Figure 6A, the liquid crystal element 4013, which serves as the display element, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Additionally, insulating layers 4032 and 4033, serving as alignment films, are provided to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is disposed on one side of the substrate 4006, and the first electrode layer 4030 and the second electrode layer 4031 are stacked with the liquid crystal layer 4008 in between. Furthermore, the spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and it is provided to control the thickness of the liquid crystal layer 4008 (cell gap). Alternatively, spherical spacers can also be used. When liquid crystal elements are used as display elements, thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, high-molecular-weight dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc., can be used. The above-mentioned liquid crystal materials (liquid crystal components) exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, homogeneous phase, etc., depending on the conditions. Alternatively, a liquid crystal composition that displays a blue phase can be used as the liquid crystal layer 4008 without an alignment film. In this case, the liquid crystal layer 4008 is in contact with the first electrode layer 4030 and the second electrode layer 4031. The blue phase is a type of liquid crystal phase, referring to the phase that appears just before the cholesterol phase liquid crystal transitions to a homogeneous phase when the temperature is raised. The blue phase can be displayed using a liquid crystal composition that mixes liquid crystals and chiral reagents. Furthermore, to broaden the temperature range for displaying the blue phase, polymerizable monomers and polymerization initiators are added to the liquid crystal composition that displays the blue phase, and polymer stabilization treatment is performed to form a liquid crystal layer. Because the liquid crystal composition that displays the blue phase has a short response time and is optically isotropic, alignment treatment is not required, and viewing angle dependence is low. In addition, since no alignment film is required and friction treatment is not necessary, electrostatic damage caused by friction treatment can be prevented, and malfunctions and breakages of the liquid crystal display device during the manufacturing process can be reduced. Thus, the productivity of the liquid crystal display device can be improved. In transistors using oxide semiconductor layers, the electrical characteristics of the transistor may change significantly due to the influence of electrostatics, exceeding the design range. Therefore, it is more effective to use liquid crystal components that exhibit a blue phase in liquid crystal display devices that have transistors using oxide semiconductor layers. Furthermore, the resistivity of liquid crystal materials is 1×10⁻⁶. 9 Ω·cm or higher, preferably 1×10⁻⁶. 11 Ω·cm or higher, preferably 1×10⁻⁶ 12 Ω·cm or higher. Furthermore, the resistivity values ​​in this specification are measured at 20°C. The size of the storage capacitor installed in the liquid crystal display device is set to account for factors such as leakage current of the transistors disposed in the pixel section, so that the charge can be maintained for a predetermined period of time. The size of the storage capacitor can be set to account for factors such as the off-state current of the transistors. By using a transistor having an oxide semiconductor layer disclosed in this specification, it is sufficient to set a storage capacitor with a capacitance of 1 / 3 or less, preferably 1 / 5 or less, of the capacitance of the liquid crystal in each pixel. Using the oxide semiconductor layer transistor disclosed in this specification, the current value in the off-state (off-state current value) can be controlled to be low. Therefore, the hold time of electrical signals such as image signals can be extended, and the write interval can also be extended when the power is on. Thus, the frequency of update operations can be reduced, thereby suppressing power consumption. Furthermore, transistors using the oxide semiconductor layer disclosed in this specification can achieve higher field-effect mobility, thus enabling high-speed driving. For example, by using such high-speed driving transistors in a liquid crystal display device, switching transistors for the pixel section and driving transistors for the driving circuit section can be formed on the same substrate. In other words, since a separate semiconductor device formed from silicon wafers or the like is not required for the driving circuit, the number of components in the semiconductor device can be reduced. In addition, by using high-speed driving transistors in the pixel section, high-quality images can be provided. Liquid crystal display devices can employ TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, etc. In addition, normally black liquid crystal display devices can also be used, such as transmissive liquid crystal display devices employing vertical alignment (VA) mode. Examples of vertical alignment modes include MVA (Multi-Domain Vertical Alignment), PVA (Patterned Vertical Alignment), and ASV (Advanced Super View). VA-type liquid crystal display devices can also be used. A VA-type liquid crystal display device controls the alignment of liquid crystal molecules in the liquid crystal display panel. In a VA-type liquid crystal display device, the liquid crystal molecules are aligned perpendicular to the panel when no voltage is applied. Furthermore, a method called multi-domain design, which divides a pixel into several regions (sub-pixels) and orients the molecules in different directions, can also be used. Furthermore, optical components (optical substrates), such as a black matrix (light-shielding layer), polarizing components, phase difference components, and anti-reflection components, are appropriately provided in the display device. For example, circular polarization utilizing polarizing substrates and phase difference substrates can also be used. Additionally, backlights, sidelights, etc., can be used as light sources. Furthermore, the display method within the pixel unit can employ progressive scan or interlaced scan, among others. Moreover, the color factors controlled within the pixel during color display are not limited to the three colors RGB (R for red, G for green, and B for blue). For example, RGBW (W for white) or colors with one or more of the following added to RGB: yellow, cyan, magenta, etc., can also be used. Additionally, the size of the display area can vary for each color factor point. However, the disclosed invention is not limited to color display devices but can also be applied to monochrome display devices. <2-1-2. EL Display Device> As display elements included in a display device, electroluminescent light-emitting elements can be used. Electroluminescent light-emitting elements are distinguished based on whether the light-emitting material is an organic compound or an inorganic compound; generally, the former is called an organic EL element, and the latter is called an inorganic EL element. In organic light-emitting diode (EL) devices, by applying a voltage to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer comprising a light-emitting organic compound, allowing current to flow. Furthermore, through the recombination of these charge carriers (electrons and holes), the light-emitting organic compound forms an excited state, emitting light when it returns to the ground state from this excited state. Due to this mechanism, such light-emitting elements are called current-excited light-emitting elements (LEEs). Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices based on their device structure. Dispersed inorganic EL devices have a light-emitting layer in which luminescent material particles are dispersed in a binder, and their light emission mechanism is donor-acceptor recombination luminescence utilizing donor and acceptor energy levels. Thin-film inorganic EL devices have a structure in which the light-emitting layer is sandwiched between dielectric layers, and these dielectric layers are held in place by electrodes; their light emission mechanism is localized type light emission utilizing inner-shell electron transitions of metal ions. Organic EL devices will be used as the light-emitting element in this description. To extract light, at least one of the pair of electrodes of the light-emitting element needs to be transparent. Furthermore, a transistor and a light-emitting element are formed on the substrate. As a light-emitting element, there are: a top-emitting element that extracts light from the surface opposite to the substrate; a bottom-emitting element that extracts light from the surface on one side of the substrate; and a double-sided emitting element that extracts light from both the surface on one side of the substrate and the surface opposite to the substrate. Any of the above-mentioned emitting structures can be used. Figures 5A, 5B, and 6B show examples of light-emitting devices that use light-emitting elements as display elements. Figure 5A is a plan view of the light-emitting device. The cross-sections taken along the chain lines S1-T1, S2-T2, and S3-T3 in Figure 5A correspond to Figure 5B. Furthermore, in the plan view of Figure 5A, the electroluminescent layer 542 and the second electrode layer 543 are omitted and not shown. In the light-emitting devices shown in Figures 5A and 5B, a transistor 510, a capacitor element 520, and a wiring layer intersection 530 are included on the substrate 500, and the transistor 510 is electrically connected to the light-emitting element 540. Furthermore, Figures 5A and 5B are light-emitting devices with a bottom-emitting structure that extracts light from the light-emitting element 540 through the substrate 500. The transistor described above can be used as transistor 510. The transistor 510 includes a gate layer 511, a gate insulating layer 502, an oxide semiconductor layer 512, and conductive layers 513a and 513b that serve as source electrode layers or drain electrode layers. The capacitor element 520 includes a conductive layer 521, a gate insulating layer 502, an oxide semiconductor layer 522, and a conductive layer 523, and the gate insulating layer 502 and the oxide semiconductor layer 522 are sandwiched between the conductive layer 521 and the conductive layer 523 to form a capacitor. The wiring layer intersection 530 is the intersection of the gate layer 511 and the conductive layer 533, and the gate layer 511 and the conductive layer 533 intersect through the gate insulating layer 502. An interlayer insulating layer 504 is formed on the junction of the transistor 510, capacitor element 520, and wiring layer 530, and a color filter layer 505 is disposed on the interlayer insulating layer 504 in a region overlapping with the light-emitting element 540. An insulating layer 506 serving as a planarization insulating layer is disposed on the interlayer insulating layer 504 and the color filter layer 505. The insulating layer 506 overlaps with the transistor 510, and the insulating layer 506 includes a region in which the thickness of the insulating layer 506 is greater than the thickness of the color filter layer 505. A light-emitting element 540, comprising a stacked structure of a first electrode layer 541, an electroluminescent layer 542, and a second electrode layer 543, is disposed on an insulating layer 506. The first electrode layer 541 contacts the conductive layer 513a through an opening formed in the insulating layer 506 and the interlayer insulating layer 504, thus electrically connecting the light-emitting element 540 to the transistor 510. Furthermore, a partition wall 507 is provided to cover a portion of the first electrode layer 541 and the opening. As the insulating layer 506, a 1500nm thick photosensitive acrylic film can be used, and as the partition 507, a 1500nm thick photosensitive polyimide film can be used. As the color filter layer 505, a colored light-transmitting resin can be used, for example. The colored light-transmitting resin can be a photosensitive organic resin or a non-photosensitive organic resin. Using a photosensitive organic resin layer reduces the number of photoresist masks and simplifies the manufacturing process, making it preferable. Color refers to colors other than achromatic colors such as black, gray, and white. A color filter layer is formed of a material that allows only the colored light to pass through. As for the color, red, green, and blue can be used. Additionally, cyan, magenta, and yellow can also be used. Allowing only the colored light to pass through means that the light passing through the color filter layer has a peak in the wavelength of its color. The thickness of the color filter layer can be appropriately controlled by considering the relationship between the concentration of the colored material and the light transmittance. For example, the thickness of the color filter layer 505 can be set to be above 1500 nm and below 2000 nm. In the light-emitting device shown in FIG6B, the light-emitting element 4513, which serves as a display element, is electrically connected to the transistor 4010 disposed in the pixel section 4002. Furthermore, the structure of the light-emitting element 4513 is a stacked structure of a first electrode layer 4030, an electroluminescent layer 4511, and a second electrode layer 4031; however, it is not limited to the structure shown. The structure of the light-emitting element 4513 can be appropriately modified according to the direction of the light emitted from it. The partitions 4510 (Fig. 6B) and 507 (Fig. 5B) are formed using organic or inorganic insulating materials. In particular, it is preferred to use a photosensitive resin material to form openings in the first electrode layer 4030 (Fig. 6B) and the first electrode layer 541 (Fig. 5B), and the sidewalls of the openings are formed as inclined surfaces with continuous curvature. Electroluminescent layer 4511 (Fig. 6B) and electroluminescent layer 542 (Fig. 5B) can be constructed as a single layer or as a stack of multiple layers. To prevent oxygen, hydrogen, water, carbon dioxide, etc., from penetrating into the light-emitting element 4513 (Fig. 6B) and the light-emitting element 540 (Fig. 5B), a protective film can be formed on the second electrode layer 4031 (Fig. 6B), the second electrode layer 543 (Fig. 5B), and the partition walls 4510 (Fig. 6B) and 507 (Fig. 5B). Silicon nitride films, silicon oxynitride films, diamond-like carbon (DLC) films, etc., can be formed as protective films. In addition, in order to prevent oxygen, hydrogen, water, carbon dioxide and other substances from penetrating the light-emitting element 4513 (Fig. 6B) and the light-emitting element 540 (Fig. 5B), a layer containing organic compounds can be formed covering the light-emitting element 4513 (Fig. 6B) and the light-emitting element 540 (Fig. 5B) by vapor deposition. Furthermore, a filling material 4514 is provided and sealed in the space sealed by the substrate 4001, the substrate 4006, and the sealing material 4005. Thus, in order to avoid exposure to external gases, it is preferable to use a protective film (adhesive film, UV-curable resin film, etc.) with high airtightness and low degassing for encapsulation (sealing). As a filler material 4514, in addition to inert gases such as nitrogen or argon, ultraviolet-cured resins and thermosetting resins can also be used, such as PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate). For example, nitrogen can be used as a filler material. Additionally, if necessary, optical films such as polarizing plates or circular polarizing plates (including elliptical polarizing plates), chromatic aberration plates (λ / 4 plates, λ / 2 plates), and color filters can be appropriately disposed on the emitting surface of the light-emitting element. Furthermore, anti-reflective films can be disposed on the polarizing plates or circular polarizing plates. For example, anti-glare treatment can be performed, which utilizes the surface irregularities to diffuse reflected light and reduce glare. <2-1-3. Electrophoresis Display Device> As a display device, electronic paper that drives electronic ink can also be provided. Electronic paper is also called an electrophoretic display device (electrophoretic display) and has the following advantages: the same readability as paper; its power consumption is lower than that of other display devices; and it is thin and light. Various forms can be conceived of electrophoretic display devices, but it generally comprises multiple microcapsules consisting of a first particle with a positive charge and a second particle with a negative charge dispersed in a solvent or solute. By applying an electric field to the microcapsules, the particles within them move relative to each other, thus displaying only the color of the particles aggregated on one side. Additionally, the first or second particle may contain a dye that does not move when there is no electric field. Furthermore, the color of the first particle may differ from the color of the second particle (including colorless). Thus, electrophoretic display devices utilize the phenomenon of materials with high dielectric constants moving into regions with high electric fields, a phenomenon known as the dielectrophoretic effect. The solvent in which the aforementioned microcapsules are dispersed is called electronic ink, and this electronic ink can be printed onto surfaces such as glass, plastic, cloth, and paper. Furthermore, color displays can be achieved by using color filters and pigmented particles. Furthermore, the first and second particles in the microcapsules can be made of a material selected from conductive materials, insulating materials, semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electrochromic materials, magnetophoretic materials, or composite materials of these materials. Furthermore, electronic paper can also be used in display devices employing a rotating ball display method. The rotating ball display method involves placing spherical particles, painted white and black respectively, between a first electrode layer and a second electrode layer, which serve as display elements. A potential difference is generated between the first and second electrode layers to control the orientation of the spherical particles for display purposes. <2-2. Image Sensor> Figure 7A shows an example of an image sensor. Figure 7A is the equivalent circuit of a photoelectric sensor, and Figure 7B is a cross-sectional view showing a portion of a photoelectric sensor. One electrode of photodiode 602 is electrically connected to photodiode reset signal line 658, while the other electrode of photodiode 602 is electrically connected to the gate of transistor 640. One of the source and drain terminals of transistor 640 is electrically connected to photosensor reference signal line 672, while the other of the source and drain terminals of transistor 640 is electrically connected to one of the source and drain terminals of transistor 656. The gate of transistor 656 is electrically connected to gate signal line 659, and the other of the source and drain terminals of transistor 656 is electrically connected to photosensor output signal line 671. Note that in the circuit diagrams of this specification, to make the transistors using oxide semiconductor layers readily apparent, the symbol for transistors using oxide semiconductor layers is represented as "OS". In Figure 7A, transistors 640 and 656 can be applied using the aforementioned transistors. Furthermore, Figure 7B shows a transistor with a structure where the oxide semiconductor layer extends to the outside of the source and drain electrode layers. In transistors with such a structure, the formation of parasitic channels in the transistor can be suppressed without providing an etch stop layer between the end of the oxide semiconductor layer and the source and drain electrode layers. Figure 7B is a cross-sectional view showing the photodiode 602 and transistor 640 in the photoelectric sensor, wherein the photodiode 602 and transistor 640, which serve as the sensor, are disposed on a substrate 601 (element substrate) having an insulating surface. A substrate 613 is disposed on the photodiode 602 and transistor 640 by using an adhesive layer 608. An insulating layer 631, an interlayer insulating layer 633, and an interlayer insulating layer 634 are provided on the transistor 640. The photodiode 602 has: an electrode layer 641b disposed on the interlayer insulating layer 633; ​​a first semiconductor film 606a, a second semiconductor film 606b, and a third semiconductor film 606c sequentially stacked on the electrode layer 641b; an electrode layer 642 disposed on the interlayer insulating layer 634 and electrically connected to the electrode layer 641b via the first to third semiconductor films; and an electrode layer 641a disposed on the same layer as the electrode layer 641b and electrically connected to the electrode layer 642. Electrode layer 641b is electrically connected to conductive layer 643 formed on interlayer insulating layer 634, and electrode layer 642 is electrically connected to conductive layer 645 via electrode layer 641a. Conductive layer 645 is electrically connected to gate electrode layer of transistor 640, and photodiode 602 is electrically connected to transistor 640. Here, a pin-type photodiode is illustrated, wherein a semiconductor film having p-type conductivity is stacked as a first semiconductor film 606a, a high-resistance semiconductor film (I-type semiconductor film) is stacked as a second semiconductor film 606b, and a semiconductor film having n-type conductivity is stacked as a third semiconductor film 606c. The first semiconductor film 606a is a p-type semiconductor film and can be formed from an amorphous silicon film containing impurity elements that impart p-type properties. The first semiconductor film 606a is formed by plasma CVD using a semiconductor material gas containing an impurity element belonging to Group 13 of the periodic table (e.g., boron (B)). Silane (SiH₂) can be used as the semiconductor material gas. 4). Alternatively, Si can be used. 2H 6. SiH 2Cl 2. SiHCl 3. SiCl 4. SiF 4. Alternatively, after forming an amorphous silicon film free of impurity elements, impurity elements can be introduced into the amorphous silicon film using diffusion or ion implantation. Preferably, after introducing impurity elements using ion implantation or similar methods, heating or similar methods is performed to diffuse the impurity elements. In this case, LPCVD, vapor phase growth, or sputtering can be used as methods for forming the amorphous silicon film. Preferably, the thickness of the first semiconductor film 606a is set to be 10 nm or more and 50 nm or less. The second semiconductor film 606b is a type I semiconductor film (intrinsically semiconductor film) formed from an amorphous silicon film. To form the second semiconductor film 606b, an amorphous silicon film is formed using a semiconductor material gas via plasma CVD. Silanes (SiH₂) can be used as the semiconductor material gas. 4). Alternatively, Si can be used. 2H 6. SiH 2Cl 2. SiHCl 3. SiCl 4 or SiF 4. The second semiconductor film 606b can also be formed by LPCVD, vapor deposition, sputtering, etc. Preferably, the thickness of the second semiconductor film 606b is set to be 200 nm or more and 1000 nm or less. The third semiconductor film 606c is an n-type semiconductor film, formed from an amorphous silicon film containing impurity elements that impart n-type properties. The third semiconductor film 606c is formed by plasma CVD using a semiconductor material gas containing impurity elements belonging to Group 15 of the periodic table (e.g., phosphorus (P)). Silane (SiH₂) can be used as the semiconductor material gas. 4). Alternatively, Si can be used. 2H 6. SiH 2Cl 2. SiHCl 3. SiCl 4 or SiF 4. Alternatively, after forming an amorphous silicon film free of impurity elements, impurity elements can be introduced into the amorphous silicon film using diffusion or ion implantation. Preferably, after introducing impurity elements using ion implantation or similar methods, heating or similar methods is performed to diffuse the impurity elements. In this case, LPCVD, vapor phase growth, or sputtering can be used as methods for forming the amorphous silicon film. Preferably, the thickness of the third semiconductor film 606c is set to be 20 nm or more and 200 nm or less. In addition, the first semiconductor film 606a, the second semiconductor film 606b and the third semiconductor film 606c may also be formed using polycrystalline semiconductors or microcrystalline semiconductors (SAS) instead of amorphous semiconductors. Furthermore, since the mobility of holes generated by the photoelectric effect is lower than that of electrons, pin-type photodiodes exhibit better characteristics when the surface of the p-type semiconductor film is used as a light-receiving surface. An example is shown here where light received by photodiode 602 from the surface of substrate 601 on which the pin-type photodiode is formed is converted into an electrical signal. Additionally, light from the side of the semiconductor film whose conductivity is opposite to that of the side used as the light-receiving surface is interfering light; therefore, it is preferable to use a conductive layer with light-shielding properties as the electrode layer. Alternatively, the surface of the n-type semiconductor film can also be used as the light-receiving surface. By using insulating materials and employing methods such as sputtering, plasma CVD, spin coating, impregnation, spraying, droplet jetting (inkjet), screen printing, and offset printing, insulating layers 631, 633, and 634 can be formed. The insulating layer 631 is formed using an inorganic insulating material, such as a single layer or stack of silicon oxynitride, silicon oxynitride, aluminum oxide, etc. To reduce surface unevenness, interlayer insulating layers 633 and 634 are preferably planarizing insulating layers. For example, heat-resistant organic insulating materials such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, or epoxy resin can be used as interlayer insulating layers 633 and 634. In addition to the above-mentioned organic insulating materials, single layers or stacks of low-dielectric-constant materials (low-k materials), silicate resins, PSG (silicon phosphate glass), BPSG (borosilicate glass), etc., can also be used. Information about the target can be read by detecting the light 622 incident on the photodiode 602. Alternatively, a light source such as a backlight can be used when reading the target's information. <2-3. Memory Devices> Hereinafter, an example of a memory device is described with reference to the illustrations. This memory device uses the transistors shown in this specification and is able to retain stored data even without a power supply, and there is no limit to the number of writes. Figures 8A and 8B are examples of the structure of a memory device. Figure 8A shows a cross-sectional view of the memory device, and Figure 8B shows a circuit diagram of the memory device. The memory device shown in Figures 8A and 8B has a transistor 3200 using a semiconductor material other than oxide semiconductor at its lower part, and a transistor 3202 using oxide semiconductor and a capacitor element 3204 at its upper part. The transistor 3202 is an example of the structure of the transistor 420 shown in Embodiment 4. Here, by using polycrystalline silicon or monocrystalline silicon as semiconductor materials other than oxide semiconductors, the transistor 3200 can operate at high speed. On the other hand, by using oxide semiconductors, the transistor 3200 can become a transistor that can maintain its charge for a long time. Furthermore, although the above-described transistors are all n-channel transistors, p-channel transistors can of course be used. In addition to using the above-described transistors as transistor 3202, the specific structure of the memory device, such as the materials used in the memory device or the structure of the memory device, is not limited to the structure shown here. The transistor 3200 in Figure 8A includes: a channel forming region disposed in a substrate 3000 containing a semiconductor material (e.g., silicon); an impurity region disposed in a manner sandwiching the channel forming region; an intermetallic compound region contacting the impurity region; a gate insulating film disposed on the channel forming region; and a gate electrode layer disposed on the gate insulating film. Note that although the presence of a source electrode layer or a drain electrode layer is not always explicitly shown in the figures, this state is sometimes referred to as a transistor for convenience. Furthermore, in this case, for the purpose of illustrating the interconnection of the transistor, the source region or drain region is sometimes also referred to as a source electrode layer or a drain electrode layer. That is, in this specification, the source electrode layer may include the source region. A device isolation insulating layer 3106 is provided on the substrate 3000 in a manner surrounding the transistor 3200, and an insulating layer 3220 is provided in a manner covering the transistor 3200. In addition, the device isolation insulating layer 3106 is formed using device separation techniques such as LOCOS (Local Oxidation of Silicon) or STI (shallow trench isolation). By using a single-crystal semiconductor substrate as substrate 3000, high-speed operation of transistor 3200 can be achieved. Therefore, by using this transistor as a readout transistor, information can be read out at high speed. As a process before forming transistor 3202 and capacitor element 3204, CMP processing is performed on the insulating layer 3220 covering transistor 3200 to planarize it, while exposing the top surface of the gate electrode layer of transistor 3200. Because the 3202 transistor has a low off-state current, it is possible to retain stored data for a long time. In other words, since a memory device that does not require updating or has an extremely low update frequency can be formed, power consumption can be significantly reduced. One of the source electrode layer and drain electrode layer of transistor 3202 is electrically connected to electrode 3208 through an opening provided in the gate insulating layer and oxide semiconductor layer, and is electrically connected to the gate electrode layer of transistor 3200 through electrode 3208. Electrode 3208 can be formed by the same process as the gate electrode layer of transistor 3202. A single layer or a stack of insulating layers 3222 is provided on the transistor 3202. Furthermore, a conductive layer 3210a is provided in the region that overlaps one of the source electrode layer and the drain electrode layer of the transistor 3202, separated by the insulating layer 3222. The capacitor element 3204 is constituted by one of the source electrode layer and the drain electrode layer of the transistor 3202, the insulating layer 3222, and the conductive layer 3210a. That is, one of the source electrode layer and the drain electrode layer of the transistor 3202 serves as one electrode of the capacitor element 3204, and the conductive layer 3210a serves as the other electrode of the capacitor element 3204. Note that if a capacitor is not required, a structure without the capacitor element 3204 can be used. Alternatively, the capacitor element 3204 can be separately disposed above the transistor 3202. An insulating layer 3224 is provided on the capacitor element 3204. Furthermore, a wiring 3216 is provided on the insulating layer 3224 for connecting the transistor 3202 to other transistors. The wiring 3216 is electrically connected to the other of the source electrode layer and drain electrode layer of the transistor 3202 via an electrode 3214 provided in an opening formed in the insulating layer 3224, a conductive layer 3210b provided in the same layer as the conductive layer 3210a, and an electrode 3212 provided in an opening formed in the insulating layer 3222. In Figure 8A, preferably, transistors 3200 and 3202 are arranged such that at least a portion of them overlap, and the source or drain region of transistor 3200 overlaps with a portion of the oxide semiconductor layer included in transistor 3202. Additionally, transistor 3202 and capacitor element 3204 are arranged such that at least a portion overlaps with transistor 3200. For example, the conductive layer 3210a of capacitor element 3204 is arranged such that at least a portion overlaps with the gate electrode layer of transistor 3200. By adopting this planar layout, the area occupied by the memory device can be reduced, thereby achieving high integration. Next, Figure 8B shows an example of the circuit structure corresponding to Figure 8A. In Figure 8B, the first wiring (1st Line) is electrically connected to the source electrode layer of transistor 3200, and the second wiring (2nd Line) is electrically connected to the drain electrode layer of transistor 3200. Furthermore, the third wiring (3rd Line) is electrically connected to one of the source electrode layer and the drain electrode layer of transistor 3202, and the fourth wiring (4th Line) is electrically connected to the gate electrode layer of transistor 3202. Additionally, the other of the gate electrode layer of transistor 3200 and the source electrode layer and the drain electrode layer of transistor 3202 is electrically connected to one electrode of capacitor element 3204, and the fifth wiring (5th Line) is electrically connected to the other electrode of capacitor element 3204. In the memory device shown in Figure 8B, by effectively utilizing the characteristics of maintaining the potential of the gate electrode layer of transistor 3200, information can be written, stored, and read as shown below. The writing and holding of information are explained. First, the potential of the fourth wiring is set to a potential that turns on transistor 3202, thus turning on transistor 3202. As a result, the potential of the third wiring is applied to the gate electrode layer of transistor 3200 and capacitor element 3204. That is, a predetermined charge (writing) is applied to the gate electrode layer of transistor 3200. Here, either a charge at two different potential levels (hereinafter referred to as Low level charge and High level charge) is applied. Then, by setting the potential of the fourth wiring to a potential that turns off transistor 3202, transistor 3202 is turned off, and the charge applied to the gate electrode layer of transistor 3200 is held (holding). Because the off-state current of transistor 3202 is extremely small, the charge on the gate electrode layer of transistor 3200 is maintained for a long time. Next, the information readout will be explained. When a predetermined potential (constant potential) is applied to the first wiring, and an appropriate potential (readout potential) is applied to the fifth wiring, the second wiring has a different potential depending on the amount of charge held in the gate electrode layer of the transistor 3200. This is because, generally speaking, in the case of an n-channel transistor 3200, the apparent critical value V when a High quasi-charge is applied to the gate electrode layer of the transistor 3200 is... th_H The apparent critical value V is below the low quasi-charge applied to the gate electrode layer of transistor 3200. th_L Here, the apparent critical voltage refers to the potential of the fifth wiring required for transistor 3200 to be in the "conducting state". Therefore, by setting the potential of the fifth wiring to V... th_H and V th_L Potential V between 0, which can distinguish the charge applied to the gate electrode layer of transistor 3200. For example, during writing, when a High level charge is supplied, if the potential of the fifth wiring is V 0(>V th_H If the transistor 3200 is in the "conducting state", it will become "conducting" when supplied with a low quasi-charge. Even if the potential of the fifth wiring is V... 0( <V th_LThe transistor 3200 also remains in a "cut-off state". Therefore, the held information can be read by identifying the potential of the second wiring. Note that when configuring memory cells in an array, it is necessary to read out the information of the desired memory cells. Thus, when not reading out information, a potential less than V is applied to the fifth wiring that keeps transistor 3200 in a "cut-off state" regardless of the state of the gate electrode layer. th_H The potential is sufficient. Alternatively, a potential greater than V can be applied to the fifth wiring to make the transistor 3200 "conducting" regardless of the state of the gate electrode layer. th_L The potential is sufficient. In the aforementioned memory devices, by using oxide semiconductor transistors, stored data can be retained for an extremely long time. That is, because no update work is required, or the frequency of update work can be reduced to an extremely low level, power consumption can be significantly reduced. Furthermore, stored data can be retained for a long time even in the absence of a power supply (note that the preferred voltage is fixed). Furthermore, in the aforementioned memory device, information writing does not require high voltage, and there is no issue of component degradation. For example, unlike conventional non-volatile memory, there is no need to inject or extract electrons from the floating gate, thus eliminating problems such as gate insulation film degradation. In other words, in the aforementioned memory device, there is no limit to the number of times it can be rewritten, addressing the problems inherent in conventional non-volatile memory, thereby significantly improving reliability. Moreover, by writing information based on the transistor's on or off state, high-speed operation can be easily achieved. Note that the memory device constructed using the transistors shown in this specification is not limited to the memory devices shown in Figures 8A and 8B. For example, this transistor can also be used as a transistor disposed in a memory cell of DRAM. <Supplementary Explanation: Oxygen Desorption from the Oxide Semiconductor Layer> The following details how oxygen can easily detach from the side (end face) of the CAAC-OS membrane. Here, with reference to scientific and technological calculation results, the mobility of excess oxygen (oxygen atoms existing in excess of stoichiometry) and oxygen defects in In-Ga-Zn type oxide (hereinafter referred to as IGZO) films of ternary metal oxides, which are examples of oxide semiconductor films, is explained. Furthermore, in the calculations, a model with an excess oxygen or oxygen defect in an In-O surface of IGZO with an atomic ratio of In:Ga:Zn=3:1:2 was formed by structural optimization (refer to Figures 9A to 9C and Figures 11A to 11C). The energy of the intermediate structure along the minimum energy path was calculated using the NEB (Nudged Elastic Band) method. The calculations were performed using the density functional theory (DFT) based software "OpenMX". The parameters are described below. Pseudoatomic local basis functions are used as basis functions. These basis functions are divided into polarized basis classes (STOs, Slater Type Orbitals). As a functional, GGA / PBE (Generalized Gradient Approximation / Perdew-Burke-Ernzerhof) is used. Set the cut-off energy to 200Ry. Set the sampling k-points to 5×5×3. In the calculation of the mobility of excess oxygen, there are 85 atoms present in the computational model, and in the calculation of the mobility of oxygen vacancies, there are 83 atoms present in the computational model. The mobility of excess oxygen and oxygen defects is evaluated by calculating the height Eb of the energy barrier that must be crossed to move to their respective locations. That is, the higher the height Eb of the energy barrier that must be crossed during movement, the more difficult the movement is; the lower the height Eb of the energy barrier that must be crossed during movement, the easier the movement is. First, the movement of excess oxygen is explained. Figures 9A to 9C show the models used for calculating the movement of excess oxygen. Calculations are performed for the following two migration modes. Figure 10 shows the calculation results. In Figure 10, the horizontal axis represents the path length (of the excess oxygen movement), and the vertical axis represents the energy (required for the movement) for state A in model 9A. Regarding the movement of excess oxygen, in the two migration modes mentioned above, the first migration is from model A to model B. The second migration is from model A to model C. Note that the oxygen atom represented by "1" in Figures 9A to 9C is called the first oxygen atom of Model A. The oxygen atom represented by "2" in Figures 9A to 9C is called the second oxygen atom of Model A. The oxygen atom represented by "3" in Figures 9A to 9C is called the third oxygen atom of Model A. As shown in Figure 10, the maximum value of the barrier height Eb for the first migration (Eb) max The maximum value of the energy barrier height Eb for the second migration is 0.53 eV. max The value is 2.38 eV. Therefore, the maximum value of the barrier height Eb during the first migration (Eb) is... max The energy required for the first migration is lower than that required for the second migration. Therefore, it can be said that the energy required for the first migration is less than that required for the second migration, and the first migration is easier to occur than the second migration. In other words, it can be said that the first oxygen atom in model A is easier to move than the direction that pushes out the third oxygen atom in model A, compared to the direction that pushes out the second oxygen atom in model A. Therefore, it can be said that oxygen atoms are easier to move along the indium atom layer than to move through the indium atom layer. Next, the movement of oxygen vacancies will be explained. Figures 11A to 11C show the models used for calculating the movement of oxygen vacancies. Calculations were performed for the following two migration modes. Figure 12 shows the calculation results. In Figure 12, the horizontal axis represents the path length (for the movement of oxygen vacancies), and the vertical axis represents the energy required for the movement to state A in model 11A. Regarding the movement of oxygen vacancies, in the two migration modes mentioned above, the first migration is from model A to model B. The second migration is from model A to model C. Note that the circles depicted by dashed lines in Figures 11A to 11C represent oxygen defects. As shown in Figure 12, the maximum value of the barrier height Eb for the first migration (Eb) max The maximum value of the energy barrier height Eb for the second migration is 1.81 eV. max The value is 4.10 eV. Therefore, the maximum value of the barrier height Eb during the first migration (Eb) is... max The energy required for the first migration is lower than that required for the second migration. Therefore, it can be said that the energy required for the first migration is less than that required for the second migration, and the first migration is easier to occur than the second migration. In other words, it can be said that oxygen vacancies in model A are easier to move to the location of oxygen vacancies in model B than oxygen vacancies in model C. Therefore, it can also be said that oxygen vacancies are easier to move along the indium atom layer than to move through the indium atom layer. Next, in order to compare the probability of occurrence of the above four migration modes from another perspective, the temperature dependence of these migrations will be explained. The above four migrations include the following migrations: (1) the first migration of excess oxygen; (2) the second migration of excess oxygen; (3) the first migration of oxygen deficiency; and (4) the second migration of oxygen deficiency. The temperature dependence of these migrations is compared based on the migration frequency per unit time. Here, the migration frequency Z ( / second) at a certain temperature T (K) is expressed by the oscillation number Zo ( / second) of the oxygen atom in the chemically stable position as follows (1). Note that in formula (1), Eb max This represents the maximum value of the energy barrier height Eb during each migration, and k represents the Boltzmann constant. Furthermore, Zo = 1.0 × 10⁻⁶. 13 ( / second) is used for calculation. When excess oxygen or oxygen deficiency exceeds the maximum value of the energy barrier height Eb only once per second (Eb... max When moving (Z=1 ( / second)), when T is obtained using formula (1), the following result can be obtained: (1) First migration of excess oxygen: when Z=1, T=206K (-67 ℃); (2) Second migration of excess oxygen: When Z=1, T=923K (650℃); (3) First migration of oxygen defects: When Z=1, T=701K (428℃); (4) Second migration of oxygen defects: When Z=1, T=1590K (1317℃). On the other hand, Z at T=300K (27℃) is as follows: (1) First migration of excess oxygen: at T=300K, Z=1.2×10 4 ( / Second); (2) Second migration of excess oxygen: at T=300K, Z=1.0×10 -27 ( / Second); (3) First migration of oxygen vacancies: at T=300K, Z=4.3×10 -18 ( / Second); (4) Second migration of oxygen vacancies: at T=300K, Z=1.4×10 -56 ( / Second). Furthermore, Z at T=723K (450℃) is as follows: (1) First migration of excess oxygen: at T=723K, Z=2.0×10 9 ( / Second); (2) Second migration of excess oxygen: at T=723K, Z=2.5×10 -4 ( / Second); (3) First migration of oxygen vacancies: at T=723K, Z=2.5 ( / s); (4) Second migration of oxygen vacancies: at T=723K, Z=2.5×10 -16 ( / Second). Based on the calculation results, it can be said that at T=300K and T=723K, excess oxygen moves more easily along the indium atom layer than through it. Furthermore, it can be said that at T=300K and T=723K, oxygen vacancies move more easily along the indium atom layer than through it. Furthermore, at T=300K, the movement of excess oxygen along the indium atom layer is very easy, but other migration mechanisms are not easy to occur. At T=723K, not only the movement of excess oxygen along the indium atom layer, but also the movement of oxygen defects along the indium atom layer is easy to occur, but both excess oxygen and oxygen defects have difficulty penetrating the indium atom layer. Therefore, as with CAAC-OS films, when a layer of indium atoms exists on a surface parallel to the surface to which the film is formed, it can be said that excess oxygen and oxygen defects are easily moved along the surface to which the film is formed. As explained above, in CAAC-OS films, both excess oxygen and oxygen defects readily migrate along the formed surface or base of the film. This leads to the problem of oxygen detachment from the sides of the film. Oxygen detachment results in a reduction of excess oxygen atoms, making it difficult to fill oxygen defects. When oxygen defects are present, the conductivity of the CAAC-OS film can potentially increase to a level unsuitable for use as a switching element. Note that the above description describes the case where excess oxygen or oxygen defects penetrate the layer of indium atoms, but the same description can also be applied to the case where the oxide semiconductor film contains metals other than indium. Implementation Method 2 In this embodiment, FIG13A and FIG13B are used to illustrate one method of manufacturing a semiconductor device, and FIG13C, FIG13D and FIG13E are used to illustrate one method of manufacturing a semiconductor device. Figures 13C, 13D, and 13E show a plan view and a cross-sectional view of transistor 410 as an example of a semiconductor device. Figure 13E is a plan view of transistor 410, Figure 13C is a cross-sectional view along line X1-X2 in Figure 13E, and Figure 13D is a cross-sectional view along line Y1-Y2 in Figure 13E. The transistor 410 shown in Figures 13C, 13D, and 13E includes: a substrate insulating layer 436 on a substrate 400; an oxide semiconductor film 403 on the substrate insulating layer 436; a gate insulating film 402 disposed on the oxide semiconductor film 403; a gate electrode layer 401 disposed on the oxide semiconductor film 403 through the gate insulating film 402; an insulating film 406 disposed on the gate electrode layer 401; a source electrode layer 405a or a drain electrode layer 405b electrically connected to the oxide semiconductor film 403 through openings in the gate insulating film 402 and the insulating film 406; and an insulating film 407 disposed on the source electrode layer 405a and the drain electrode layer 405b. Furthermore, in transistor 410, the oxide semiconductor film 403 includes: a channel forming region 409 overlapping the gate electrode layer 401; and low-resistance regions 404a and 404b sandwiched therebetween, the resistance of which is lower than that of the channel forming region 409 and contains a dopant. A dopant is an element that alters the conductivity of the oxide semiconductor film. As a dopant, any one or more elements selected from Group 15 elements (typically nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb)), boron (B), aluminum (Al), tungsten (W), molybdenum (Mo), indium (In), gallium (Ga), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn) can be used. The oxide semiconductor film 403 may be in a single crystal, polycrystalline (also known as polycrystal), or amorphous state. In this embodiment, the low-resistance regions 404a and 404b, to which dopant has been added, are made to be mostly amorphous or regions where the proportion of amorphous component is higher than that of crystalline component. Figure 13A shows a cross-sectional view of the fabrication process before the introduction of the impurity element used as a dopant. The oxide semiconductor film 403 before the introduction of the impurity element used as a dopant is a single-crystal film, a polycrystalline film (also known as a polycrystal), or a CAAC-OS film. The thickness of the oxide semiconductor film 403 is set to be 1 nm or more and 30 nm or less (preferably 5 nm or more and 10 nm or less), and can be appropriately achieved using sputtering, MBE (Molecular Beam Epitaxy), CVD, pulsed laser deposition, ALD (Atomic Layer Deposition), etc. Furthermore, the oxide semiconductor film 403 can be formed using a sputtering apparatus in which multiple substrate surfaces are arranged approximately perpendicular to the surface of the sputtering target. Monocrystalline films, polycrystalline films, or CAAC-OS films can be obtained by changing the film formation conditions of the film formation method, increasing the substrate temperature during film formation, or performing appropriate heat treatment after film formation. Furthermore, as shown in FIG13B, after the gate electrode layer 401 is formed, low-resistance regions 404a and 404b are self-aligned by using the gate electrode layer 401 as a mask and introducing impurity elements. Ion implantation or ion doping is used as the method for introducing impurity elements. Additionally, this region can be used as the source or drain region of the transistor 410. By providing low-resistance regions 404a and 404b, the electric field applied to the channel forming region 409 disposed between the pair of low-resistance regions can be mitigated. Furthermore, by contacting the source electrode layer 405a and drain electrode layer 405b with the low-resistance regions 404a and 404b respectively, the contact resistance between the oxide semiconductor film 403 and the source electrode layer 405a and drain electrode layer 405b can be reduced. Furthermore, in this embodiment, the proportion of crystalline components in the channel forming region 409 is higher than that of amorphous components compared to low-resistance regions 404a and 404b. Additionally, hydrogen is attracted in the direction indicated by the dashed arrow in FIG13B, therefore the hydrogen concentration in the channel forming region 409 is lower than that in low-resistance regions 404a and 404b. Here, it is preferable to achieve high purification by sufficiently removing impurities such as hydrogen or supplying sufficient oxygen to bring the oxide semiconductor film 403 into an oxygen supersaturated state. Specifically, the hydrogen concentration in the oxide semiconductor layer is 5 × 10⁻⁶. 19 atoms / cm 3 The preferred value is 5×10. 18 atoms / cm 3 The following is preferred: 5×10 17 atoms / cm 3 The following describes the hydrogen concentration in the oxide semiconductor layer. Furthermore, secondary ion mass spectrometry (SIMS) is used to measure the hydrogen concentration in the oxide semiconductor layer. Additionally, to ensure sufficient oxygen supply to the oxide semiconductor film 403, resulting in an oxygen supersaturated state, an insulating layer (SiOx, etc.) containing excess oxygen is disposed in contact with the oxide semiconductor film 403 in a manner that covers the oxide semiconductor film 403. The insulating layer containing excess oxygen is a substrate insulating layer 436 and a gate insulating film 402, which are disposed in contact with the ground in a manner that covers an oxide semiconductor film 403. The substrate insulating layer 436 and the gate insulating film 402 are SiOx films or silicon oxynitride films containing a large amount of oxygen by appropriately setting the film formation conditions in the PCVD or sputtering process. In addition, when the insulating layer contains a large amount of excess oxygen, oxygen is added by oxygen doping treatment using ion implantation, ion doping, or plasma treatment. Note that the term "oxygen doping" as used above refers to the process of adding oxygen (including at least one of oxygen radicals, oxygen atoms, oxygen molecules, ozone, oxygen ions (oxygen molecular ions), and / or oxygen cluster ions) into a block. Note that the term "block" is used to indicate that oxygen is added not only to the surface of the film but also to its interior. Additionally, "oxygen doping" includes "oxygen plasma doping," which involves adding plasma-enhanced oxygen into the block. In oxygen doping, oxygen-containing gases can be used. Examples of oxygen-containing gases include oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, and carbon monoxide. Furthermore, in oxygen doping, the oxygen-containing gas can also contain rare gases. Due to the oxygen doping treatment described above, at the interface between the insulating layer and the oxide semiconductor film, or within the block of the insulating layer, at least one region with an oxygen excess exceeding the stoichiometry of the film can be provided. Furthermore, an insulating film 406 is provided on the oxide semiconductor film 403, the gate insulating film 402, and the gate electrode layer 401. The insulating film 406 can be a planarization insulating film used to reduce the surface unevenness caused by the transistor. As a planarization insulating film, organic materials such as polyimide resin, acrylic resin, and benzocyclobutene resin can be used. In addition to the above-mentioned organic materials, low dielectric constant materials (low-k materials) can also be used. Alternatively, multiple insulating films formed from the above-mentioned materials can be stacked to form a planarization insulating film. Alternatively, it is preferable to provide a barrier layer (AlOx, etc.) to suppress the release of oxygen from the oxide semiconductor film in such a way that it covers the oxide semiconductor film and is disposed on the outside of the insulating layer containing excess oxygen. The insulating film 407 acts as a barrier layer. Preferably, an aluminum film is stacked on the insulating layer containing excess oxygen, and oxygen doping is performed on both the insulating layer and the aluminum film from a position on the aluminum film to form regions in the insulating layer containing excess oxygen beyond the stoichiometric composition, while simultaneously oxidizing the aluminum film to form an aluminum oxide film. Alternatively, preferably, a titanium oxide film, tungsten oxide film, nickel oxide film, molybdenum oxide film, or magnesium oxide film is stacked on the aluminum oxide film, and the resistivity of the titanium oxide film, tungsten oxide film, nickel oxide film, molybdenum oxide film, or magnesium oxide film is set to 1×10⁻⁶. 10 Ωm or more and 1×10 19 Below Ωm (preferably 1×10) 10 Ωm or more and 1×10 18 For Ωm and below, 1×10 is preferred. 11 Ωm or more and 1×10 15 (Ωm or less). By providing a film with the above resistivity, electrostatic damage to semiconductor devices can be prevented. By covering an oxide semiconductor film with an insulating or barrier layer containing excess oxygen, it is possible to achieve a state in which the amount of oxygen in the oxide semiconductor layer is approximately consistent with the stoichiometric composition, or a supersaturated state in which oxygen is more abundant than the stoichiometric composition. For example, when the oxide semiconductor film is IGZO, an example of a stoichiometric composition is In:Ga:Zn:O = 1:1:1:4 [atomic ratio], therefore the atomic ratio of oxygen in the oxide semiconductor film is 4 or more. Furthermore, although an example of a stack of insulating film 406 and insulating film 407 is shown in this embodiment, there are no particular limitations, and insulating film 406 may also be omitted. In transistor 410, an oxide semiconductor film 403 is self-aligned with regions containing more crystalline components (i.e., channel formation region 409) and more amorphous components (i.e., low-resistance regions 404a and 404b), and the hydrogen concentration in channel formation region 409 is lower than that in the regions with more amorphous components. Therefore, by removing as much hydrogen as possible from the channel formation region of transistor 410 and supplying oxygen, the channel formation region can be made into a highly purified type I or close to a highly purified type I. By making the channel formation region type I, the critical voltage value of the transistor can be made positive, and a so-called normally off switching element can be realized. Furthermore, in the channel formation region of transistor 410, the minority carrier density is extremely low and the sources of carrier generation such as oxygen vacancies and hydrogen are reduced, thus the off-state current can be minimized. Implementation Method 3 In this embodiment, Figures 14A to 14E illustrate an example of a method for manufacturing a semiconductor device having sidewalls on the side of the gate electrode layer. First, a base insulating layer 436 is formed on a substrate 400 having an insulating surface. There are no particular limitations on the substrate that can be used as the substrate 400 with an insulating surface, but the substrate 400 needs to have heat resistance sufficient to withstand subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminum borosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc., can be used. In addition, as the substrate 400, single-crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates made of silicon or silicon carbide, SOI substrates, etc., can also be used, and substrates on which semiconductor elements are disposed can also be used. Alternatively, a flexible substrate can be used as the substrate 400 to manufacture the semiconductor device. To manufacture a flexible semiconductor device, a transistor 440a including an oxide semiconductor film 403 can be directly manufactured on the flexible substrate, or the transistor 440a including an oxide semiconductor film 403 can be manufactured on another manufacturing substrate, and then the transistor is peeled off and transferred onto the flexible substrate. Furthermore, for peeling and transferring from the manufacturing substrate to the flexible substrate, it is preferable to provide a release layer between the manufacturing substrate and the transistor 440a including the oxide semiconductor film 403. A substrate insulating layer 436 can be formed by means of plasma CVD or sputtering, using silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide or a mixture thereof. The substrate insulating layer 436 can be a single layer or a stacked layer. For example, a silicon oxide film, an In-Hf-Zn oxide film, and an oxide semiconductor film 403 can be sequentially stacked on the substrate 400. Alternatively, an In-Zr-Zn oxide film with an atomic ratio of In:Zr:Zn=1:1:1 and an oxide semiconductor film 403 can be sequentially stacked on the substrate 400. Furthermore, an In-Gd-Zn oxide film with an atomic ratio of In:Gd:Zn=1:1:1 and an oxide semiconductor film 403 can be sequentially stacked on the substrate 400. In this embodiment, a silicon oxide film is formed as the substrate insulating layer 436 by sputtering. Alternatively, a nitride insulating film may be provided between the substrate insulating layer 436 and the substrate 400. The nitride insulating film may be formed by plasma CVD or sputtering and using silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, or a mixture thereof. Since the substrate insulating layer 436 is in contact with the oxide semiconductor film 403, it is preferable that there is at least an amount of oxygen in the film (bulk) exceeding the stoichiometric ratio. For example, when a silicon oxide film is used as the substrate insulating layer 436, SiO2 is used. 2+α(Note that α>0) This is a film. By using this substrate insulating layer 436, oxygen can be supplied to the oxide semiconductor film 403, thereby improving its properties. By supplying oxygen to the oxide semiconductor film 403, oxygen defects in the film can be filled. For example, oxygen can be supplied to the oxide semiconductor film 403 by providing a substrate insulating layer 436 containing a large amount (excess) of oxygen as an oxygen supply source in a manner that contacts the oxide semiconductor film 403. Oxygen can also be supplied to the oxide semiconductor film 403 by performing a heat treatment while at least a portion of the oxide semiconductor film 403 is in contact with the substrate insulating layer 436. The region formed in the substrate insulating layer 436 in contact with the oxide semiconductor film 403 can also be planarized. There are no particular limitations on the planarization process, and polishing (e.g., chemical mechanical polishing (CMP)), dry etching, and plasma processing can be used as planarization processes. As a plasma treatment, backsputtering can be performed, for example, by introducing argon gas to generate plasma. Backsputtering refers to a method of using an RF power supply to apply voltage to one side of the substrate in an argon atmosphere to form plasma near the substrate for surface modification. Alternatively, nitrogen, helium, oxygen, etc., can be used instead of an argon atmosphere. By performing backsputtering, powdery substances (also known as particles or dust) adhering to the surface of the substrate insulating layer 436 can be removed. As a planarization process, multiple polishing, dry etching, and plasma processing can be performed, or these processes can be combined. Furthermore, when these processes are combined, there are no particular restrictions on the process sequence, which can be appropriately set according to the unevenness of the surface of the substrate insulating layer 436. As a planarization process, for example, the surface of the silicon oxide film used as the substrate insulating layer 436 can be polished by chemical mechanical polishing (polishing conditions: polyurethane-based polishing cloth, silicon-based slurry, slurry temperature at room temperature, polishing pressure of 0.001 MPa, polishing rotation speed (table / spindle) of 60 rpm / 56 rpm, polishing time of 0.5 minutes), setting the average surface roughness (Ra) of the silicon oxide film surface to about 0.15 nm. Next, an oxide semiconductor film 403 is formed on the substrate insulating layer 436. In the process of forming the oxide semiconductor film 403, in order to minimize the presence of hydrogen or water in the oxide semiconductor film 403, it is preferable to preheat the substrate on which the substrate insulating layer 436 is formed in the preheating chamber of the sputtering apparatus as a pretreatment for forming the oxide semiconductor film 403, so that impurities such as hydrogen or water adhering to the substrate and the substrate insulating layer 436 are removed and discharged. In addition, a cryogenic pump is preferably used as the exhaust unit provided in the preheating chamber. Furthermore, in order to ensure that the substrate insulating layer 436 is in a state where impurities such as hydrogen (including water and hydroxyl groups) are reduced and excess oxygen is present, the substrate insulating layer 436 may be subjected to a heat treatment (dehydration or dehydrogenation treatment) and / or an oxygen doping treatment to remove hydrogen (including water and hydroxyl groups) (dehydration or dehydrogenation). The dehydration or dehydrogenation treatment and the oxygen doping treatment can be performed multiple times, or they can be combined and repeated. Furthermore, immediately after film formation, the oxide semiconductor film 403 is preferably in a supersaturated state containing more oxygen than its stoichiometric composition. For example, when forming the oxide semiconductor film 403 using sputtering, it is preferable to perform film formation under conditions where the proportion of oxygen in the film-forming gas is high, and in particular, it is preferable to perform film formation in an oxygen atmosphere (100% oxygen gas). When film formation is performed under conditions where the proportion of oxygen in the film-forming gas is high, and in particular, in an atmosphere where the oxygen gas is 100%, even if the film formation temperature is set to, for example, 300°C or higher, the release of Zn from the film can be suppressed. Furthermore, since the oxide semiconductor film 403 is supplied with sufficient oxygen and is in an oxygen supersaturated state, the insulating film (a plurality of insulating films disposed in such a manner as to cover the oxide semiconductor film 403) in contact with the oxide semiconductor film 403 is preferably an insulating film containing excess oxygen. In addition, in this embodiment, as the target material for forming the oxide semiconductor film 403 by sputtering, an oxide target material with a composition of In:Ga:Zn=3:1:2 [atomic percentage] is used to form an In-Ga-Zn type oxide film (IGZO film). Furthermore, the relative density (fill rate) of the metal oxide target is 90% or higher and 100% or lower, preferably 95% or higher and 99.9% or lower. By using a metal oxide target with high relative density, a dense oxide semiconductor film can be formed. The sputtering gas used in forming the oxide semiconductor film 403 is preferably a high-purity gas that has had impurities such as hydrogen, water, hydroxyl groups or hydrides removed. The substrate is held in a deposition chamber under reduced pressure. Then, while removing residual moisture from the deposition chamber, a sputtering gas, from which hydrogen and moisture have been removed, is introduced, and an oxide semiconductor film 403 is formed on the substrate 400 using the aforementioned target material. To remove residual moisture from the deposition chamber, an adsorption-type vacuum pump, such as a cryogenic pump, ion pump, or titanium sublimation pump, is preferably used. Alternatively, a turbomolecular pump with an added cold trap can be used as the exhaust unit. This is because in a deposition chamber where a cryogenic pump is used for exhaust, for example, hydrogen atoms and water (H+) are removed. By venting compounds containing hydrogen atoms, such as 2O (and more preferably, compounds containing carbon atoms), the concentration of impurities contained in the oxide semiconductor film 403 formed in the deposition chamber can be reduced. Furthermore, it is preferable to form the substrate insulating layer 436 and the oxide semiconductor film 403 continuously without exposing them to the atmosphere. By continuously forming the substrate insulating layer 436 and the oxide semiconductor film 403 without exposing them to the atmosphere, impurities such as hydrogen or moisture can be prevented from adhering to the surface of the substrate insulating layer 436. The oxide semiconductor film 403 can be formed by processing the film-shaped oxide semiconductor film into an island-shaped oxide semiconductor film through photolithography. Alternatively, a photoresist mask for forming the island-shaped oxide semiconductor film 403 can be formed using inkjet printing. Since a photomask is not required when forming the photoresist mask using inkjet printing, manufacturing costs can be reduced. Furthermore, etching of oxide semiconductor films can be performed using either dry etching or wet etching, or both. For example, as an etchant for wet etching of oxide semiconductor films, a solution mixed with phosphoric acid, acetic acid, and nitric acid can be used. Alternatively, ITO-07N (manufactured by Kanto Chemical Co., Ltd., Japan) can also be used. Alternatively, etching can be performed using dry etching via ICP (Inductively Coupled Plasma) etching. For example, IGZO films can be etched using ICP etching (etching conditions: etching gas (BCl₂)). 3: Cl 2=60sccm:20sccm), power supply is 450W, bias power is 100W, pressure is 1.9Pa), and it is processed into an island shape. The oxide semiconductor film 403 is preferably a highly purified oxide semiconductor film that is virtually free of impurities such as copper, aluminum, and chlorine. In the fabrication process of the transistor 440a, it is preferable to appropriately select a process in which these impurities will not be introduced into or adhere to the surface of the oxide semiconductor film 403. If these impurities adhere to the surface of the oxide semiconductor film 403, it is preferable to perform a treatment that exposes the surface of the oxide semiconductor film 403 to oxalic acid or dilute hydrofluoric acid, or to perform plasma treatment (N... Impurities on the surface of the oxide semiconductor film 403 are removed by methods such as plasma treatment. Specifically, the copper concentration of the oxide semiconductor film 403 is 1 × 10⁻⁶. 18 atoms / cm 3 The preferred value is 1×10. 17 atoms / cm 3 Below. Additionally, the aluminum concentration of the oxide semiconductor film 403 is 1×10⁻⁶. 18 atoms / cm 3 The following is an explanation of the process. Furthermore, the chlorine concentration of the oxide semiconductor film 403 is 2 × 10⁻⁶. 18 atoms / cm 3 the following. Alternatively, the oxide semiconductor film 403 can be subjected to a heat treatment to remove excess hydrogen (including water or hydroxyl groups) (dehydration or dehydrogenation). The heat treatment temperature is set to 300°C or higher and 700°C or lower than the strain point of the substrate. The heat treatment can be performed under reduced pressure or in a nitrogen atmosphere. For example, the substrate is placed in an electric furnace, one of the heat treatment apparatuses, and the oxide semiconductor film 403 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. Furthermore, the heat treatment apparatus is not limited to electric furnaces; devices that use heat conduction or thermal radiation generated by heating elements such as resistance heating elements can also be used to heat the workpiece. For example, GRTA (Gas Rapid Thermal Anneal) apparatus and LRTA (Lamp Rapid Thermal Anneal) apparatus, etc., can be used. LRTA apparatus heats the workpiece by utilizing the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps. GRTA apparatus uses high-temperature gas for heat treatment. The high-temperature gas used is a rare gas such as argon or an inert gas such as nitrogen that does not react with the workpiece during heat treatment. For example, as a heat treatment, GRTA can also be performed by placing the substrate in an inert gas heated to a high temperature of 650°C to 700°C, and after heating for a few minutes, removing the substrate from the inert gas. In addition, during heat treatment, nitrogen or rare gases such as helium, neon, and argon are preferably free of water, hydrogen, etc. Alternatively, it is preferable to set the purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment apparatus to 6N (99.9999%) or higher, more preferably to 7N (99.99999%) or higher (i.e., to set the impurity concentration to 1 ppm or less, preferably to 0.1 ppm or less). Alternatively, after heating the oxide semiconductor film 403 by heat treatment, high-purity oxygen gas, high-purity nitrous oxide gas, or ultra-dry air (air with a moisture content of less than 20 ppm (dew point converted to -55°C), preferably less than 1 ppm, and more preferably less than 10 ppb, when measured using a dew point meter using CRDS (cavity ring-down laser spectroscopy) method) can be introduced into the same furnace. The oxygen gas or nitrous oxide gas is preferably free of water, hydrogen, etc. Alternatively, it is preferable to set the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment apparatus to 6N or higher, preferably 7N or higher (i.e., setting the impurity concentration in the oxygen gas or nitrous oxide gas to less than 1 ppm, preferably less than 0.1 ppm). By utilizing oxygen gas or nitrous oxide gas to supply oxygen to the main component material of oxide semiconductors during the impurity removal process using dehydration or dehydrogenation treatment, the oxide semiconductor film 403 can be highly purified and electrically type I (intrinsically) purified. Furthermore, the heat treatment for dehydration or dehydrogenation can be performed either after the formation of the film-like oxide semiconductor film or after the formation of the island-like oxide semiconductor film 403. In addition, it can be subjected to multiple heat treatments for dehydration or dehydrogenation, and can also be used for other heat treatments. By performing a heat treatment for dehydration or dehydrogenation on the film-shaped oxide semiconductor film 403 before it is processed into an island shape, i.e. while the film-shaped oxide semiconductor film 403 is covered with the substrate insulating layer 436, it is preferable to prevent the release of oxygen contained in the substrate insulating layer 436 due to the heat treatment. Next, a gate insulating film 442 covering the oxide semiconductor film 403 is formed. Furthermore, to improve the coverage of the gate insulating film 442, the surface of the oxide semiconductor film 403 may also undergo the aforementioned planarization treatment. In particular, when a thin insulating film is used as the gate insulating film 442, the surface of the oxide semiconductor film 403 preferably has good planarity. The thickness of the gate insulating film 442 is set to be above 1 nm and below 20 nm. Sputtering, MBE, CVD, pulsed laser deposition, ALD and other methods can be used appropriately. As the material for the gate insulating film 442, silicon oxide film, gallium oxide film, aluminum oxide film, silicon nitride film, silicon oxynitride film, aluminum oxynitride film, or silicon oxynitride film can be used. The portion of the gate insulating film 442 that contacts the oxide semiconductor film 403 preferably contains oxygen. In particular, the gate insulating film 442 preferably contains oxygen in its film (bulk) in an amount exceeding the stoichiometric ratio; for example, when using a silicon oxide film as the gate insulating film 442, SiO₂ is used. 2α (Note that α>0) film. In this embodiment, SiO2 is used as the gate insulating film 442. 2α (Note that α>0) A silicon oxide film. By using this silicon oxide film as the gate insulating film 442, oxygen can be supplied to the oxide semiconductor film 403, thereby improving its properties. Furthermore, the gate insulating film 442 is preferably formed with consideration for the size of the manufactured transistor and the step coverage of the gate insulating film 442. Furthermore, hafnium oxide, yttrium oxide, and hafnium silicate (HfSi) are used as materials for the gate insulating film 442. x O y (x>0, y>0)), hafnium silicate with added nitrogen, hafnium aluminate (HfAl) x O y High-k materials such as lanthanum oxide (x>0, y>0) can reduce gate leakage current. Moreover, the gate insulating film 442 can be either a single-layer structure or a multilayer structure. Furthermore, in order to ensure that the gate insulating film 442 is in a state where impurities such as hydrogen (including water and hydroxyl groups) are reduced and that it contains excess oxygen, the gate insulating film 442 can also be subjected to a heat treatment (dehydration or dehydrogenation) and / or an oxygen doping treatment to remove hydrogen (including water and hydroxyl groups) (dehydration or dehydrogenation treatment). The dehydration or dehydrogenation treatment and the oxygen doping treatment can be performed multiple times, or they can be combined and repeated. In this embodiment, the gate insulating film 442 is subjected to microwave-assisted oxygen plasma treatment while being heated at a temperature of 200°C or higher and 400°C or lower. This treatment results in a high-density gate insulating film 442, and allows for dehydration, dehydrogenation, and oxygen doping of the gate insulating film 442. Next, a stack of conductive film and insulating film is formed on the gate insulating film 442, and the conductive film and insulating film are etched to form a stack of gate electrode layer 401 and insulating film 413. The gate electrode layer 401 can be formed from metals such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or alloys with these as the main components. Alternatively, the gate electrode layer 401 can be a semiconductor film, such as a polycrystalline silicon film doped with impurity elements like phosphorus, or a silicide film such as nickel silicate. The gate electrode layer 401 can be either a single-layer structure or a multilayer structure. Alternatively, the gate electrode layer 401 can also be made of conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with added silicon oxide. Furthermore, a multilayer structure of the above-mentioned conductive materials and the above-mentioned metal materials can also be used. Furthermore, a nitrogen-containing metal oxide can be used as a layer of the gate electrode layer 401 that contacts the gate insulating film 442. Specifically, nitrogen-containing In-Ga-Zn-O films, nitrogen-containing In-Sn-O films, nitrogen-containing In-Ga-O films, nitrogen-containing In-Zn-O films, nitrogen-containing Sn-O films, nitrogen-containing In-O films, and metal nitride films (InN, SnN, etc.) can be used. These films have a work function of 5 eV or higher, preferably 5.5 eV or higher. When these films are used as gate electrode layers, the threshold voltage of the transistor can be made positive, thus enabling a so-called normally-off switching element. Inorganic insulating films such as silicon nitride film, aluminum nitride film, silicon oxynitride film, aluminum oxynitride film, silicon oxide film, silicon oxynitride film, aluminum oxide film, aluminum oxide film, and aluminum oxynitride film can typically be used as the insulating film 413. The insulating film 413 can be formed by plasma CVD or sputtering methods. Next, using the gate electrode layer 401 and the insulating film 413 as a mask, the dopant is introduced into the oxide semiconductor film 403 to form low resistance regions 404a and 404b (see Figure 14A). The dopant implantation process can be controlled by appropriately setting implantation conditions such as accelerating voltage and dosage, or by adjusting the thickness of the film through which the dopant permeates. In this embodiment, phosphorus is used as the dopant, and phosphorus ions are implanted using an ion implantation method. Furthermore, the dopant dosage can be set to 1 × 10⁻⁶. 13 ions / cm 2 Above and 5×10 16 ions / cm 2 the following. The preferred dopant concentration in the low resistance region is 5 × 10⁻⁶. 18 / cm 3 Above and 1×10 22 / cm 3 the following. The substrate 400 can also be heated while the dopant is being introduced. Alternatively, the process of introducing dopant into the oxide semiconductor film 403 can be performed multiple times, and a variety of dopant can be used. Alternatively, heat treatment can be performed after the dopant introduction process. Preferred heating conditions are: a temperature of 300°C or higher and 700°C or lower, more preferably 300°C or higher and 450°C or lower; in an oxygen atmosphere; for 1 hour. Alternatively, heat treatment can be performed in a nitrogen atmosphere, under reduced pressure, or in atmospheric (ultra-dry air). In this embodiment, phosphorus (P) ions are implanted into the oxide semiconductor film 403 using an ion implantation method. Furthermore, the following conditions are used for phosphorus (P) ion implantation: accelerating voltage of 30 kV; dose of 1.0 × 10⁻⁶ kV. 15 ions / cm 2 . The oxide semiconductor film 403 is a CAAC-OS film, a polycrystalline film, or a single-crystal film. Depending on the dopant introduction processing conditions or the type of dopant, sometimes a portion of the oxide semiconductor film 403 becomes amorphous due to the introduction of a dopant. For example, sometimes due to dopant introduction processing, in an oxide semiconductor film that does not overlap with the gate electrode layer 401, the upper layer becomes amorphous, but the lower layer remains crystalline without the addition of a dopant. Therefore, when a portion of the oxide semiconductor film 403 becomes amorphous, it is preferable to perform the aforementioned heat treatment to recrystallize the amorphous region, thereby improving the crystallinity of the oxide semiconductor film 403. As a result of the above-mentioned process, a low-resistance region 404a and a low-resistance region 404b are provided between the channel forming region 409, and a highly crystalline oxide semiconductor film 403 is formed. Next, in order to form a sidewall insulating layer (hereinafter also referred to as sidewall), an insulating film 448 is formed (see Figure 14B). As the insulating film 448, inorganic insulating films such as silicon oxide films, silicon oxynitride films, aluminum oxide films, aluminum oxynitride films, silicon nitride films, aluminum nitride films, silicon oxynitride films, and aluminum oxynitride films can typically be used, and they can be used as single layers or stacked layers. The insulating film 448 can be formed using plasma CVD, sputtering, or CVD using a film-forming gas. As the CVD method, LPCVD, plasma CVD, etc., can be used, and other methods such as coating can also be used. Then, the insulating film 448 is anisotropically etched to form sidewall insulating layers 414a and 414b. Furthermore, the gate insulating film 442 is etched using the gate electrode layer 401, the insulating film 413, the sidewall insulating layer 414a, and the sidewall insulating layer 414b as masks to form the gate insulating film 402 (see Figure 14C). In addition, by etching the gate insulating film 442, a portion of the low resistance regions 404a and 404b is exposed. Next, a process is performed to amorphize a portion of the exposed low-resistance regions 404a and 404b. As one amorphization process, a portion of the exposed low-resistance regions 404a and 404b may be exposed to argon plasma or oxygen plasma. Alternatively, they may be exposed to a plasma containing dopants. When the thickness of the oxide semiconductor film 403 is sufficiently thick compared to the depth of the surface to which oxygen, argon, or dopants are added to the plasma, only the surface layer of the exposed low-resistance regions 404a and 404b becomes amorphous regions 445a and 445b, while other regions retain a crystalline composition (see Figure 14D). By setting amorphous regions 445a and 445b, hydrogen is attracted in the direction indicated by the dashed arrow in Figure 14D, and the attracted and fixed hydrogen in the amorphous regions 445a and 445b can be removed as much as possible from the channel formation region. Furthermore, when a process is performed to amorphize a portion of the exposed low-resistance regions 404a and 404b, it is important to protect the gate electrode layer 401 from exposure to plasma. In addition, as one of the other methods to produce amorphization of part of the exposed low-resistance regions 404a and 404b, argon, oxygen and dopants can also be added using an ion implantation device or an ion plasma device. Next, an insulating film 407 is formed on the oxide semiconductor film 403, the gate insulating film 402, and the gate electrode layer 401 as a highly dense inorganic insulating film (typically an alumina film) used as a protective insulating film. The insulating film 407 may be a single layer or a multilayer, and preferably includes at least an aluminum oxide film. By setting the alumina film density to a high density (film density of 3.2 g / cm³), 3 The preferred value is 3.6 g / cm³. 3 The above (the above) can impart stable electrical properties to transistor 440a. The film density can be determined using Rutherford backscattering analysis or X-ray reflectance. Furthermore, it is preferable that the alumina film (in a bulk medium) contains at least an amount of oxygen exceeding the stoichiometric ratio. For example, when using an alumina film, its composition is AlO₂. x (Note that x>1.5) is sufficient. The alumina film used as insulating film 407 has a high blocking effect, that is, it prevents impurities such as hydrogen and moisture and oxygen from passing through the film. Therefore, the insulating film 407 serves as a protective film that prevents impurities such as hydrogen and moisture, which cause changes in electrical properties during and after the manufacturing process, from entering the oxide semiconductor film 403, and prevents the release of oxygen, the main constituent material of the oxide semiconductor, from the oxide semiconductor film 403. Furthermore, the aluminum oxide film can supply oxygen to the oxide semiconductor film 403 in contact with it. The insulating film 407 can be formed using methods such as plasma CVD, sputtering, or vapor deposition. Alternatively, a metal oxide film obtained by oxidizing a metal film can be used as the insulating film 407. In this embodiment, an aluminum oxide film obtained by oxygen doping an aluminum film is used. As the insulating film 407, in addition to aluminum oxide films, inorganic insulating films such as silicon oxide films, silicon oxynitride films, aluminum oxynitride films, or gallium oxide films can typically be used. Alternatively, hafnium oxide films, magnesium oxide films, zirconium oxide films, lanthanum oxide films, barium oxide films, or metal nitride films (e.g., aluminum nitride films) can also be used. An interlayer insulating film 415 is formed on the insulating film 407. The interlayer insulating film 415 can be formed using the same material and method as the insulating film 407. In this embodiment, the interlayer insulating film 415 is formed to a thickness that can flatten the unevenness produced by the transistor 440a. The interlayer insulating film 415 can be a silicon oxynitride film formed by CVD or a silicon oxide film formed by sputtering. As the interlayer insulating film 415, a planarization insulating film can be formed to reduce the surface roughness caused by transistors. Organic materials such as polyimide resins, acrylic resins, and benzocyclobutene resins can be used as the planarization insulating film. In addition to the aforementioned organic materials, low-dielectric-constant materials (low-k materials) can also be used. An opening is formed in the interlayer insulating film 415 and the insulating film 407 to reach the oxide semiconductor film 403, and a source electrode layer 405a and a drain electrode layer 405b are formed in the opening. The source electrode layer 405a and the drain electrode layer 405b can be used to connect transistors to other transistors or components to form various circuits. As conductive films for the source electrode layer 405a and drain electrode layer 405b, for example, metal films containing elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or metal nitride films (titanium nitride films, molybdenum nitride films, tungsten nitride films) composed of the aforementioned elements can be used. Alternatively, high-melting-point metal films such as Ti, Mo, and W, or their metal nitride films (titanium nitride films, molybdenum nitride films, tungsten nitride films), can be laminated on one or both the underside and the upper side of metal films such as Al and Cu. Furthermore, the conductive films for the source electrode layer and drain electrode layer can be formed of conductive metal oxides. Indium oxide (In) can be used as a conductive metal oxide. 2O 3) Tin oxide (SnO) 2) Zinc oxide (ZnO), indium oxide-tin oxide (In) 2O 3-SnO 2) Indium oxide-zinc oxide (In 2O 3-ZnO) or metal oxides that make these metal oxide materials contain silicon oxide. For example, the source electrode layer 405a and the drain electrode layer 405b can be a single layer of molybdenum film, a stack of tantalum nitride film and copper film, or a stack of tantalum nitride film and tungsten film. Furthermore, to reduce the number of process steps, as another method for amorphizing a portion of the exposed low-resistance regions 404a and 404b, a formation process can be employed where high-power sputtering is performed when forming the conductive films for the source electrode layer 405a and drain electrode layer 405b. In this case, depending on the film formation conditions of the conductive film, a portion of the exposed low-resistance regions 404a and 404b becomes amorphous, thus amorphizing a portion of the oxide semiconductor film without increasing the number of process steps. By means of the above process, a semiconductor device having the transistor 440a of this embodiment can be manufactured (see FIG14E). Figures 15A to 15D, 16A and 16B show transistors 440b, 440c, 440d, 440e, 440f and 440g, which have other structures different from transistor 440a. In transistors 440b, 440c, 440d, and 440e, the source electrode layer 405a and the drain electrode layer 405b are disposed in contact with the exposed top surface of the oxide semiconductor film 403 and the sidewall insulating layers 414a and 414b. Therefore, the distance between the source electrode layer 405a or the drain electrode layer 405b in contact with the amorphous region 445a of the oxide semiconductor film 403, and between the amorphous region 445b and the gate electrode layer 401, is equal to the width of the channel length direction of the sidewall insulating layer. This not only enables further miniaturization but also further suppresses process deviations. Thus, because the distance between the amorphous regions 445a and 445b of the source electrode layer 405a or drain electrode layer 405b in contact with the oxide semiconductor film 403 and the gate electrode layer 401 can be shortened, the resistance between the regions (amorphous regions 445a and 445b) of the source electrode layer 405a or drain electrode layer 405b in contact with the oxide semiconductor film 403 and the gate electrode layer 401 is reduced, thereby improving the conduction characteristics of transistors 440b, 440c, 440d, and 440e. Additionally, in Figures 15A and 15B, the insulating film 407 is disposed in contact with the interlayer insulating film 415, the source electrode layer 405a, the drain electrode layer 405b, the sidewall insulating layer 414a, the sidewall insulating layer 414b, and the insulating film 413. In transistors 440b and 440c, the conductive films disposed on the gate electrode layer 401, insulating film 413, and sidewall insulating layers 414a and 414b are removed by cutting (grinding, polishing) during the manufacturing process to separate the conductive films and form the source electrode layer 405a and drain electrode layer 405b. As a cutting (grinding, polishing) method, chemical mechanical polishing (CMP) can be appropriately used. In the process of transistor 440d, a photoresist mask formed by photolithography is used to etch the conductive film disposed on gate electrode layer 401, insulating film 413 and sidewall insulating layer 414a and sidewall insulating layer 414b to form source electrode layer 405a and drain electrode layer 405b. In the process of manufacturing transistor 440e, the source electrode layer 405a and the drain electrode layer 405b are formed by etching the conductive film disposed on the gate electrode layer 401, the insulating film 413 and the sidewall insulating layers 414a and 414b by gradually shrinking the photoresist mask formed by photolithography. In transistor 440f, the source electrode layer and drain electrode layer are disposed in regions of the oxide semiconductor film 403 that do not overlap with the gate insulating film 402. A metal film (aluminum film, titanium film, etc.) is formed by high-power sputtering on the oxide semiconductor film 403, resulting in amorphization. Metal elements are diffused into the oxide semiconductor film 403 through heat treatment, thereby reducing the resistivity of the oxide semiconductor film 403 and forming an amorphous region 445a for the source electrode layer and an amorphous region 445b for the drain electrode layer. Note that after forming the amorphous regions 445a and 445b, the metal film is removed. In transistor 440g, an insulating film serving as a barrier film is formed by covering sidewall insulating layers 414a and 414b with a sidewall insulating layer. After forming insulating film 448, anisotropic etching is performed on insulating film 448 to form sidewall insulating layers 414a and 414b, and then an insulating film serving as a barrier film is formed. This barrier film is then anisotropically etched to form insulating films 417a and 417b. For example, as the barrier film, an aluminum film can be formed and oxygen-doped to form an aluminum oxide film. By anisotropically etching insulating film 448 and performing a second anisotropic etching on the barrier film, the sidewall insulating layer shown in transistor 440g, consisting of sidewall insulating layers 414a, 414b, insulating film 417a, and insulating film 417b, can be formed. As described above, in semiconductor devices having an oxide semiconductor film including a channel forming region containing a crystalline component and an amorphous region containing a greater amount of amorphous component, stable electrical characteristics and high reliability can be achieved. Therefore, a structure and a method for manufacturing a semiconductor device having a transistor including an oxide semiconductor film can be provided to achieve high-speed response and high-speed drive. Implementation Method 4 In this embodiment, Figures 17A and 17B are used to illustrate an example of fabricating transistors and capacitors on the same substrate without increasing the number of processes. The transistor can be a single-gate structure forming one channel forming region, a double-gate structure forming two channel forming regions, or a triple-gate structure forming three channel forming regions. Alternatively, the transistor can be a dual-gate structure with two gate electrode layers disposed above and below the channel forming regions, separated by a gate insulating film. The transistor 420 shown in Figure 17B is an example of a planar transistor with a top-gate structure. The transistor 420 shown in Figure 17B comprises, on a substrate 400 having an insulating surface on which a base insulating layer 436 is provided: an oxide semiconductor film 403 including a channel forming region 409, a low-resistance region 404a, a low-resistance region 404b, an amorphous region 445a, and an amorphous region 445b; a source electrode layer 405a; a drain electrode layer 405b; a gate insulating film 402; and a gate electrode layer 401. Insulating films 406 and 407 are formed on the transistor 420. Furthermore, capacitor wiring 450, made of the same material as the gate electrode layer 401, is superimposed on the source electrode layer 405a across the gate insulating film 402 to form a capacitor 451 in which the gate insulating film 402 serves as a dielectric. Figure 17A illustrates an example of a method for manufacturing a semiconductor device. Furthermore, the processes for fabricating the substrate insulating layer 436 and the oxide semiconductor film 403 containing crystalline components are the same as those in Embodiment 2, and therefore detailed descriptions are omitted here. After forming an oxide semiconductor film 403 containing crystalline components, a conductive film serving as a source electrode layer and a drain electrode layer (including wiring formed using the same layer as them) is formed on the oxide semiconductor film 403. The conductive film can be a metal film containing elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.) containing the aforementioned elements. Next, a photoresist mask is formed on the conductive film using a photolithography process, and selective etching is performed to form the source electrode layer 405a and the drain electrode layer 405b, and then the photoresist mask is removed. Furthermore, when a conductive film is formed by sputtering or when plasma is used in etching to form the source electrode layer 405a and the drain electrode layer 405b, amorphization or impurities may occur on the surface of the oxide semiconductor film 403. In this case, it is preferable to expose the amorphous surface to oxalic acid or dilute hydrofluoric acid, or to perform plasma treatment (N... 2O plasma treatment, etc., removes amorphous surfaces to expose crystalline components or removes impurities from the surface of oxide semiconductor films. When amorphous surfaces are exposed to oxalic acid or dilute hydrofluoric acid, or subjected to plasma treatment (N... During 2O plasma treatment, the thickness of the exposed oxide semiconductor film 403 is reduced, but this is not illustrated in Figures 17A and 17B. Next, a gate insulating film 402 is formed covering the oxide semiconductor film 403, the source electrode layer 405a, and the drain electrode layer 405b. Then, a gate electrode layer 401 is formed on the gate insulating film 402 by plasma CVD or sputtering (see FIG17A). Furthermore, when a thin insulating film is used as the gate insulating film 402, planarization can be performed before forming the gate insulating film 402. In this embodiment, the capacitor wiring 450 is also formed on the gate insulating film 402 using the same material as the gate electrode layer 401. A portion of the gate insulating film 402 sandwiched between the source electrode layer 405a and the capacitor wiring 450 is used as a dielectric to form a capacitor 451. Next, using the gate electrode layer 401, source electrode layer 405a and drain electrode layer 405b as masks, rare gases or dopants are introduced into the oxide semiconductor film 403 to amorphize it, thereby forming amorphous regions 445a and 445b. Depending on the thickness of the source electrode layer 405a and the drain electrode layer 405b, and the conditions for introducing rare gases or dopants, when rare gases or dopants are also introduced into the oxide semiconductor film 403 under the source electrode layer 405a and the drain electrode layer 405b, sometimes the regions where rare gases or dopants are introduced become amorphous. By setting amorphous regions 445a and 445b, hydrogen is attracted and fixed in amorphous regions 445a and 445b, thereby minimizing the removal of hydrogen from the channel forming region 409. Furthermore, in this embodiment, the region reaching the interface between the oxide semiconductor film 403 and the substrate insulating layer 436 is shown as amorphous region 445a and amorphous region 445b. However, depending on the conditions of amorphization using the introduction of rare gases or dopants, sometimes only the upper layer becomes an amorphous region by introducing rare gases or dopants only to the vicinity of the surface. Even in this case, hydrogen can be attracted and fixed in the amorphous region, thereby minimizing the removal of hydrogen from the channel formation region 409. Next, an insulating film 406 is formed on the oxide semiconductor film 403, the gate insulating film 402, and the gate electrode layer 401. Next, an insulating film 407 is formed on the insulating film 406 as a highly dense inorganic insulating film (typically an alumina film) to serve as a protective insulating film (see FIG17B). Furthermore, although an example of a stack of insulating films 406 and 407 is shown in this embodiment, there are no particular limitations, and the insulating film 406 may be omitted. Furthermore, to efficiently introduce rare gases or dopants, the gate insulating film 402 can be etched using the gate electrode layer 401 and capacitor wiring 450 as a mask before introduction, exposing a portion of the oxide semiconductor film 403. Alternatively, after exposing a portion of the oxide semiconductor film 403, argon plasma treatment or oxygen plasma treatment can be performed to amorphize the exposed portion of the oxide semiconductor film 403. Furthermore, in Figure 17B, the regions that contact and overlap with the source electrode layer 405a and the drain electrode layer 405b are shown as low-resistance regions 404a and 404b, respectively, and an amorphous region 445a is provided between the channel forming region 409 and the low-resistance region 404a. Additionally, an amorphous region 445b is provided between the channel forming region 409 and the low-resistance region 404b. The hydrogen concentration in the amorphous regions 445a and 445b is higher than the hydrogen concentration in the channel forming region 409, the low-resistance regions 404a and 404b. As described above, in a semiconductor device having a transistor 420 comprising a channel forming region 409 containing crystalline components, an amorphous region 445a containing more amorphous components, and an amorphous region 445b, stable electrical characteristics and high reliability can be achieved. Furthermore, this embodiment can be freely combined with Embodiment 2 or Embodiment 3. For example, this embodiment and Embodiment 3 can be combined to provide a sidewall insulating layer in contact with the side of the gate electrode layer. In this case, the sidewall insulating layer is provided in contact with the side of the capacitor wiring 450. Implementation Method 5 In this embodiment, an example of a semiconductor device (memory device) that differs from Embodiment 1 is illustrated using diagrams. Figures 18A to 18C are examples of the structure of a semiconductor device. Figure 18A shows a cross-sectional view of the semiconductor device, Figure 18B shows a plan view of the semiconductor device, and Figure 18C shows a circuit diagram of the semiconductor device. Here, Figure 18A corresponds to a cross-section along lines C1-C2 and D1-D2 in Figure 18B. The semiconductor device shown in Figures 18A and 18B has a transistor 160 using a first semiconductor material at its lower part and a transistor 162 using a second semiconductor material at its upper part. The transistor 162 is an example of the structure of the transistor 420 shown in Embodiment 3. Here, the first semiconductor material and the second semiconductor material are preferably materials with different band gaps. For example, a semiconductor material other than oxide semiconductor (such as silicon) can be used for the first semiconductor material, and an oxide semiconductor can be used for the second semiconductor material. Transistors using materials other than oxide semiconductors are easier to operate at high speeds. On the other hand, transistors using oxide semiconductors can retain their charge for a long time due to their properties. Furthermore, although the above-described transistors are all n-channel transistors, p-channel transistors can of course be used. In addition, apart from the transistors shown in Embodiments 1, 2, or 3, which use oxide semiconductors to retain information, the specific structure of the semiconductor device, such as the materials used in the semiconductor device or the structure of the semiconductor device, does not need to be limited to the structures shown here. The transistor 160 in Figure 18A includes: a channel forming region 116 disposed in a substrate 185 containing a semiconductor material (e.g., silicon); an impurity region 120 disposed in a manner sandwiching the channel forming region 116; an intermetallic compound region 124 contacting the impurity region 120; a gate insulating film 108 disposed on the channel forming region 116; and a gate electrode 110 disposed on the gate insulating film 108. Note that although the presence of a source electrode or a drain electrode is not always explicitly shown in the figures, this state is sometimes referred to as a transistor for convenience. Furthermore, in this case, for the purpose of illustrating the transistor's interconnections, the source region or drain region is sometimes also referred to as a source electrode or a drain electrode. That is, in this specification, the source electrode may include the source region. An element isolation insulating layer 106 is provided on the substrate 185 in such a way as to surround the transistor 160, and insulating layers 128 and 130 are provided in such a way as to cover the transistor 160. Transistor 160, which uses a single-crystal semiconductor substrate, can operate at high speed. Therefore, by using this transistor as a readout transistor, information can be read out at high speed. As a process before forming transistor 162 and capacitor element 164, CMP processing is performed on the insulating layer covering transistor 160 to planarize insulating layer 128 and insulating layer 130, while exposing the top surface of the gate electrode layer of transistor 160. The transistor 162 shown in Figure 18A is a top-gate transistor that uses an oxide semiconductor in the channel formation region. Here, the oxide semiconductor film included in the transistor 162 has a channel formation region and an amorphous region that retains a crystalline composition. By using an oxide semiconductor that attracts hydrogen to the amorphous region and reduces the hydrogen concentration in its channel formation region, a transistor 162 with extremely excellent cutoff characteristics can be obtained. Because the off-state current of transistor 162 is small, data can be stored for a long time by using this transistor. In other words, because a semiconductor memory device that does not require updating or has an extremely low updating frequency can be formed, power consumption can be significantly reduced. A single-layer or multi-layered insulating layer 150 is provided on the transistor 162. Furthermore, a conductive layer 148b is provided in the region where it overlaps with the electrode layer 142a of the transistor 162, separated by the insulating layer 150. The electrode layer 142a, the insulating layer 150, and the conductive layer 148b constitute a capacitor element 164. In other words, the electrode layer 142a of the transistor 162 serves as one electrode in the capacitor element 164, and the conductive layer 148b serves as the other electrode in the capacitor element 164. Alternatively, when a capacitor is not required, a structure without the capacitor element 164 can be used. The capacitor element 164 can also be separately disposed above the transistor 162. Furthermore, the conductive layer 148b can be formed using the same process as the gate electrode 148a of the transistor 162. An insulating layer 152 is provided on the transistor 162 and the capacitor element 164. Furthermore, a wiring 156 is provided on the insulating layer 152 for connecting the transistor 162 to other transistors. Although not shown in FIG18A, the wiring 156 is electrically connected to the electrode layer 142b via electrodes formed in openings provided in the insulating layers 150, 152, and gate insulating film 146. Preferably, the electrodes are arranged such that they at least partially overlap with the oxide semiconductor layer 144 of the transistor 162. In Figures 18A and 18B, preferably, transistors 160 and 162 are arranged with at least a portion overlapping, and the source or drain region of transistor 160 and the oxide semiconductor layer 144 are arranged with a portion overlapping. Additionally, transistor 162 and capacitor element 164 are arranged with at least a portion overlapping with transistor 160. For example, the conductive layer 148b of capacitor element 164 is arranged with at least a portion overlapping with the gate electrode 110 of transistor 160. By adopting this planar layout, the area occupied by the semiconductor device can be reduced, thereby achieving high compactness. Next, Figure 18C shows an example of the circuit structure corresponding to Figures 18A and 18B. In Figure 18C, the first wiring (1st Line) is electrically connected to the source electrode of transistor 160, and the second wiring (2nd Line) is electrically connected to the drain electrode of transistor 160. Furthermore, the third wiring (3rd Line) is electrically connected to one of the source and drain electrodes of transistor 162, and the fourth wiring (4th Line) is electrically connected to the gate electrode of transistor 162. Additionally, the other of the gate electrode of transistor 160 and the source and drain electrodes of transistor 162 is electrically connected to one electrode of capacitor element 164, and the fifth wiring (5th Line) is electrically connected to the other electrode of capacitor element 164. In the semiconductor device shown in FIG18C, by effectively utilizing the feature that can maintain the potential of the gate electrode of transistor 160, information can be written, held, and read as shown below. The writing and holding of information are explained. First, the potential of the fourth wiring is set to a potential that turns on transistor 162, thus turning on transistor 162. As a result, the potential of the third wiring is applied to the gate electrode of transistor 160 and the capacitor element 164. That is, a predetermined charge is applied to the gate electrode of transistor 160 (writing). Here, either a charge at two different potential levels (hereinafter referred to as Low level charge and High level charge) is applied. Then, by setting the potential of the fourth wiring to a potential that turns off transistor 162, transistor 162 is turned off, and the charge applied to the gate electrode of transistor 160 is held (holding). Because the off-state current of transistor 162 is extremely small, the charge on the gate electrode of transistor 160 is maintained for a long time. Next, the information readout will be explained. When a predetermined potential (constant potential) is applied to the first wiring, and an appropriate potential (readout potential) is applied to the fifth wiring, the second wiring has a different potential depending on the amount of charge held at the gate electrode of the transistor 160. This is because, generally speaking, in the case of an n-channel transistor 160, the apparent critical value V when a high quasi-charge is applied to the gate electrode of the transistor 160 is... th_H Below the apparent critical value V when a low quasi-charge is applied to the gate electrode of transistor 160. th_L Here, the apparent critical voltage refers to the potential of the fifth wiring required to make transistor 160 "conducting". Therefore, by setting the potential of the fifth wiring to V... th_H and V th_L Potential V between 0, which can distinguish the charge applied to the gate electrode of transistor 160. For example, during writing, when a High level charge is supplied, if the potential of the fifth wiring is V 0(>V th_H If the transistor 160 is in the "conducting state", then it will be in the "conducting state". Even if the potential of the fifth wiring is V when supplied with a Low quasi-charge, 0( <V th_L Transistor 160 also remains in a "cut-off state". Therefore, the held information can be read from the potential of the second wiring. Note that when configuring memory cells in an array, it is necessary to read out the information of the desired memory cells. Thus, without reading out the information, a potential less than V is applied to the fifth wiring that keeps transistor 160 in a "cut-off state" regardless of the gate electrode state. th_H The potential is sufficient. Alternatively, a potential greater than V can be applied to the fifth wiring to ensure that transistor 160 is in the "conducting state" regardless of the state of the gate electrode. th_L The potential is sufficient. In the semiconductor device shown in this embodiment, by using a transistor with an oxide semiconductor in its channel formation region and extremely low off-state current, stored data can be retained for an extremely long time. That is, because no update operation is required, or the frequency of update operation can be reduced to an extremely low level, power consumption can be significantly reduced. In addition, stored data can be retained for a long time even in the absence of power supply (however, the preferred potential is fixed). Furthermore, in the semiconductor device shown in this embodiment, information writing does not require high voltage, and there is no problem of component degradation. For example, unlike conventional non-volatile memory, there is no need to inject or extract electrons from the floating gate, so problems such as gate insulating film degradation do not occur. That is to say, in the semiconductor device according to the disclosed invention, there is no limit to the number of times it can be rewritten, which is a problem present in conventional non-volatile memory, thus significantly improving reliability. Moreover, since information is written based on the on or off state of the transistor, high-speed operation can be easily achieved. As described above, it is possible to provide a semiconductor device that achieves miniaturization and high density and imparts high electrical characteristics, as well as a method for manufacturing the semiconductor device. The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments. Implementation Method 6 In this embodiment, one method of describing the structure of a memory device that differs from that of embodiment 5 is described. Figure 19 is a perspective view of the memory device. In the memory device shown in Figure 19, the upper part has a storage circuit with a multi-layer memory cell array (memory cell array 3400a to memory cell array 3400n, where n is a natural number greater than 2) and the lower part has a logic circuit 3004 required to make the memory cell array 3400a to memory cell array 3400n work. Figure 19 illustrates logic circuit 3004, memory cell array 3400a, and memory cell array 3400b. Memory cells 3170a and 3170b are shown as typical examples among the multiple memory cells included in memory cell arrays 3400a and 3400b. For example, memory cells 3170a and 3170b may also employ the same structure as the circuit structure described in the above embodiments. Additionally, as a typical example, FIG20 shows a transistor 3171a included in memory cell 3170a. As a typical example, a transistor 3171b included in memory cell 3170b is shown. Transistors 3171a and 3171b have channel forming regions in the oxide semiconductor film. Because the structure of the transistor forming the channel forming region in the oxide semiconductor film is the same as the structure described in any of Embodiments 1 to 3, its description is omitted. Electrode 3501a, which is formed in the same layer as the gate electrode layer of transistor 3171a, is electrically connected to electrode 3003a via electrode 3502a. Electrode 3501c, which is formed in the same layer as the gate electrode layer of transistor 3171b, is electrically connected to electrode 3003c via electrode 3502c. Furthermore, the logic circuit 3004 includes a transistor 3001 that uses a semiconductor material other than oxide semiconductor as the channel formation region. The transistor 3001 can be a transistor obtained by the following steps: providing an element isolation insulating layer 3106 in a substrate 3000 containing a semiconductor material (such as silicon), and forming a region serving as the channel formation region in the area surrounded by the element isolation insulating layer 3106. Alternatively, the transistor 3001 can also have its channel formation region formed in a semiconductor film such as a polycrystalline silicon film formed on an insulating surface, or in a silicon film of an SOI substrate. Since known structures can be used as the structure of the transistor 3001, its description is omitted. Wiring 3100a and wiring 3100b are formed between the layer where transistor 3171a is formed and the layer where transistor 3001 is formed. An insulating film 3140a is provided between wiring 3100a and the layer where transistor 3001 is formed, an insulating film 3141a is provided between wiring 3100a and wiring 3100b, and an insulating film 3142a is provided between wiring 3100b and the layer where transistor 3171a is formed. Similarly, wiring 3100c and wiring 3100d are formed between the layer where transistor 3171b is formed and the layer where transistor 3171a is formed. An insulating film 3140b is provided between wiring 3100c and the layer where transistor 3171a is formed, an insulating film 3141b is provided between wiring 3100c and wiring 3100d, and an insulating film 3142b is provided between wiring 3100d and the layer where transistor 3171b is formed. Insulating films 3140a, 3141a, 3142a, 3140b, 3141b and 3142b can function as interlayer insulating films, and their surfaces are planarized. By utilizing wiring 3100a, wiring 3100b, wiring 3100c and wiring 3100d, electrical connections between memory cells or electrical connections between logic circuit 3004 and memory cells can be achieved. The electrode 3303 included in the logic circuit 3004 can be electrically connected to the circuit located on the upper part. For example, as shown in FIG20, electrode 3303 and wiring 3100a can be electrically connected via electrode 3505. Wiring 3100a is electrically connected via electrode 3503a to electrode 3501b formed using the same layer as the gate electrode layer of transistor 3171a. In this way, wiring 3100a and electrode 3303 are electrically connected to the source or drain of transistor 3171a. In addition, electrode 3501b is electrically connected to electrode 3003b via source or drain of transistor 3171a and electrode 3502b. Electrode 3003b is electrically connected to wiring 3100c via electrode 3503b. Figure 20 shows an example of electrically connecting electrode 3303 and transistor 3171a via wiring 3100a, but it is not limited to this. Electrode 3303 and transistor 3171a can be electrically connected via wiring 3100b, or both wiring 3100a and wiring 3100b can be used to electrically connect electrode 3303 and transistor 3171a. Alternatively, electrode 3303 and transistor 3171a can be electrically connected using other electrodes without wiring 3100a and wiring 3100b. Furthermore, Figure 20 shows an example where two wiring layers are formed between the layer where transistor 3171a is formed and the layer where transistor 3001 is formed, namely, a wiring layer with wiring 3100a and a wiring layer with wiring 3100b. However, the present invention is not limited to this. One wiring layer may be formed between the layer where transistor 3171a is formed and the layer where transistor 3001 is formed, or three or more wiring layers may be formed between the layer where transistor 3171a is formed and the layer where transistor 3001 is formed. Furthermore, Figure 20 shows an example where two wiring layers are formed between the layer where transistor 3171b is formed and the layer where transistor 3171a is formed, namely, a wiring layer with wiring 3100c and a wiring layer with wiring 3100d. However, the present invention is not limited to this. One wiring layer may be formed between the layer where transistor 3171b is formed and the layer where transistor 3171a is formed, or three or more wiring layers may be formed between the layer where transistor 3171b is formed and the layer where transistor 3171a is formed. The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments. Implementation Method 7 In this embodiment, as an example of a semiconductor device, a CPU (Central Processing Unit) using a transistor disclosed in any one of Embodiments 2 to 4 is described, at least in a portion thereof. Figure 21A is a block diagram showing the specific structure of a CPU. The CPU shown in Figure 21A, on a substrate 1190, includes: an ALU 1191 (ALU: Arithmetic Logic Unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timer controller 1195, a register 1196, a register controller 1197, a bus interface (Bus I / F) 1198, a rewritable ROM 1199, and a ROM interface (ROM I / F) 1189. The substrate 1190 can be a semiconductor substrate, an SOI substrate, a glass substrate, etc. The ROM 1199 and the ROM interface 1189 can also be mounted on different chips. Of course, the CPU shown in Figure 21A is merely a simplified example, and actual CPUs have various structures depending on their applications. Instructions input to the CPU via bus interface 1198 are input to instruction decoder 1193 and decoded, and then input to ALU controller 1192, interrupt controller 1194, register controller 1197, and timer controller 1195. The ALU controller 1192, interrupt controller 1194, register controller 1197, and timer controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals to control the operation of the ALU 1191. Furthermore, the interrupt controller 1194, during CPU programming, determines and processes interrupt requests from external input / output devices or peripheral circuits based on their priority or mask state. The register controller 1197 generates the address of the register 1196 and reads or writes to the register 1196 according to the CPU state. Additionally, the timing controller 1195 generates signals to control the operating timing of the ALU 1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 has an internal clock generator that generates an internal clock signal CLK2 based on a reference clock signal CLK1 and supplies the internal clock signal CLK2 to the aforementioned circuits. In the CPU shown in FIG21A, a memory unit is provided in the temporary register 1196. The memory unit of the temporary register 1196 can be the memory unit disclosed in Embodiment 5 above. In the CPU shown in Figure 21A, the register controller 1197 selects the retention operation in register 1196 according to the instructions of ALU 1191. In other words, the register controller 1197 selects whether the data in the memory cells of register 1196 is retained by the inversion theory element or by a capacitor. When the data is retained by the inversion theory element, a power supply voltage is supplied to the memory cells in register 1196. When the data is retained by the capacitor, the data is overwritten by the capacitor, and the power supply voltage to the memory cells in register 1196 can be stopped. As shown in Figure 21B or Figure 21C, power can be stopped by setting a switching element between the memory cell group and the node to which a power supply potential VDD or VSS is applied. The circuits in Figures 21B and 21C are described below. Figures 21B and 21C show an example of the structure of a storage circuit comprising a transistor shown in any of embodiments 2 to 4 above, used to control the switching element for controlling the power supply potential to the memory cell. The memory device shown in FIG21B includes a switching element 1141 and a group of memory cells 1143 having a plurality of memory cells 1142. Specifically, the memory cells described in Embodiment 5 can be used as each memory cell 1142. Each memory cell 1142 of the group of memory cells 1143 is supplied with a high-level power supply potential VDD by means of the switching element 1141. Furthermore, each memory cell 1142 of the group of memory cells 1143 is supplied with a potential of signal IN and a low-level power supply potential VSS. In Figure 21B, the transistor disclosed in any of Embodiments 2 to 4 above is used as the switching element 1141, and the switching of the transistor is controlled by the signal SigA applied to its gate electrode. Furthermore, although Figure 21B shows a switching element 1141 with only one transistor, there are no particular limitations on it, and it can also have multiple transistors. When the switching element 1141 has multiple transistors used as switching elements, the multiple transistors can be connected in parallel, connected in series, or a combination of parallel and series connections can be used. Furthermore, in Figure 21B, the switching element 1141 controls the supply of a high-level power supply potential VDD to each memory cell 1142 of the memory cell group 1143, but the switching element 1141 can also control the supply of a low-level power supply potential VSS. Additionally, Figure 21C shows an example of a memory device in which a low-level power supply potential VSS is supplied to each memory cell 1142 of the memory cell group 1143 by means of a switching element 1141. The supply of a low-level power supply potential VSS to each memory cell 1142 of the memory cell group 1143 can be controlled by the switching element 1141. Even if a switching element is placed between the memory cell group and the node to which a power supply potential VDD or VSS is applied to temporarily stop the CPU's operation and stop the power supply voltage, data can be preserved, thereby reducing power consumption. Specifically, for example, when a personal computer user stops inputting information through an input device such as a keyboard, the CPU's operation can be stopped, thereby reducing power consumption. Although the CPU is used as an example here, the above transistors can also be applied to LSIs of DSPs (Digital Signal Processors), custom LSIs, FPGAs (Field Programmable Gate Arrays), etc. This implementation method can be appropriately combined with the above-described implementation methods. Implementation Method 8 The semiconductor devices disclosed in this specification can be applied to a variety of electronic devices (including game consoles). Examples of electronic devices include televisions, monitors and other display devices, lighting equipment, desktop or laptop personal computers, word processors, image reproduction devices that reproduce still or moving images stored on storage media such as DVDs (Digital Versatile Discs), portable CD players, radios, tape recorders, headphones, audio equipment, cordless handsets, walkie-talkies, portable wireless devices, mobile phones, car phones, portable game consoles, calculators, portable information terminals, electronic notebooks, e-book readers, electronic translators, voice input devices, cameras, digital still cameras, electric shavers, microwave ovens and other high-frequency heating devices, rice cookers, washing machines, vacuum cleaners, air conditioners and other air conditioning equipment, dishwashers, dish dryers, clothes dryers, quilt dryers, refrigerators, freezers, refrigerated freezers, DNA preservation freezers, smoke detectors, radiation counters, dialysis devices and other medical equipment, etc. Furthermore, examples of electrical equipment include industrial equipment such as guide lights, signal lights, conveyor belts, escalators, elevators, industrial robots, and energy storage systems. Additionally, mobile vehicles propelled by electric motors using petroleum-based engines or electricity from non-aqueous secondary batteries are also included in the category of electrical equipment. Examples of such mobile vehicles include electric vehicles (EVs), hybrid electric vehicles (HEVs) combining internal combustion engines and electric motors, plug-in hybrid electric vehicles (PHEVs), tracked vehicles using tracks instead of wheels, electric bicycles (including electric-assisted bicycles), motorcycles, electric wheelchairs, golf carts, small or large boats, submarines, helicopters, airplanes, rockets, artificial satellites, space probes, planetary probes, and spacecraft. Figures 22A to 22C illustrate specific examples of these electronic devices. Figure 22A shows a table 9000 with a display unit. In the table 9000, a display unit 9003 is assembled on a housing 9001, and images can be displayed using the display unit 9003. Furthermore, a structure is shown in which the housing 9001 is supported by four legs 9002. Additionally, the housing 9001 has a power supply line 9005 for supplying power. The transistor shown in any of Embodiments 1 to 3 can be used in the display unit 9003, which can make the electronic device highly reliable. The display unit 9003 has a touch screen input function. Users can perform screen operations or input information by touching the display buttons 9004 on the display unit 9003 displayed on the table 9000 with their fingers. The display unit 9003 can also be used as a control device, enabling it to communicate with or control other home appliances, thus allowing screen operation to control these appliances. For example, by using a semiconductor device with an image sensor, the display unit 9003 can have a touch screen input function. Furthermore, the screen of the display unit 9003 can be erected perpendicular to the floor using the hinges provided on the housing 9001, thus allowing the table to be used as a television. While installing a large-screen television in a small room would reduce the usable space, a table with a display unit can effectively utilize the room's space. Figure 22B shows a portable music player whose main body 3021 includes: a display unit 3023; a fixing part 3022 for hanging on the ear; a speaker; operation buttons 3024; and an external storage slot 3025, etc. The display unit 3023 can be a transistor as shown in any of Embodiments 1 to 3. By using the transistor shown in Embodiments 2 to 4 or the memory shown in Embodiment 5 as a memory or CPU built into the main body 3021, a portable music player with further reduced power consumption can be realized. Furthermore, by equipping the portable music player shown in Figure 22B with antenna, microphone, and wireless communication functions, and enabling it to interact with a mobile phone, hands-free conversations can be conducted via wireless communication while driving a car or similar vehicle. Figure 22C shows a computer including a main body 9201 containing a CPU, a casing 9202, a display unit 9203, a keyboard 9204, an external connection port 9205, a pointing device 9206, etc. This computer is manufactured by using a transistor manufactured according to one method of the present invention in the display unit 9203. By using the CPU shown in Embodiment 7, a computer with low power consumption can be manufactured. Figures 23A and 23B show a foldable tablet terminal. Figure 23A shows the open state, and the tablet terminal includes a housing 9630, a display unit 9631a, a display unit 9631b, a display mode switch 9034, a power switch 9035, a power saving mode switch 9036, a clip 9033, and an operation switch 9038. In the portable devices shown in Figures 23A and 23B, SRAM or DRAM is used as memory for temporarily storing image data. For example, the semiconductor device described in Embodiment 5 or Embodiment 6 can be used as memory. By using the semiconductor device described in the above embodiments as memory, information can be written and read at high speed, stored data can be retained for a long time, and power consumption can be significantly reduced. Furthermore, a portion of the display unit 9631a can be used as a touchscreen area 9632a, and data can be input by pressing the displayed operation keys 9638. Any of the transistors shown in Embodiments 1 to 3 can be used in both the display unit 9631a and the display unit 9631b. As an example, a structure is shown where one half of the display unit 9631a has only a display function, while the other half has a touchscreen function; however, this structure is not limited to this. A structure in which all areas of the display unit 9631a have touchscreen functionality can also be used. For example, the entire surface of the display unit 9631a can be used as a touchscreen by displaying keyboard buttons, and the display unit 9631b can be used as a display screen. Furthermore, a portion of the display unit 9631b, like the display unit 9631a, can also be used as a touchscreen area 9632b. Additionally, by pressing the display keyboard toggle button 9639 on the touchscreen with a finger or stylus, keyboard buttons can be displayed on the display unit 9631b. In addition, touch input can be performed simultaneously on both the touchscreen area 9632a and the touchscreen area 9632b. Additionally, the display mode switch 9034 can switch between portrait and landscape display orientations and select between monochrome and color display. Based on the amount of ambient light detected by the built-in light sensor of the tablet terminal, the power-saving mode switch 9036 can set the display brightness to the most suitable level. In addition to the light sensor, the tablet terminal may also include other detection devices such as a gyroscope and an accelerometer for detecting tilt. Furthermore, Figure 23A shows an example where the display area of ​​display unit 9631b is the same as that of display unit 9631a, but it is not limited to this. The size of one can be different from that of the other, and their display quality can also be different. For example, one of display units 9631a and 9631b can provide a higher resolution display compared to the other. Figure 23B shows the closed state, and the tablet terminal includes a housing 9630, a solar cell 9633, a charge / discharge control circuit 9634, a battery 9635, and a DC-DC converter 9636. Furthermore, Figure 23B shows a structure with a battery 9635 and a DC-DC converter 9636 as an example of the charge / discharge control circuit 9634. Furthermore, the tablet terminal is foldable, so the outer casing 9630 can be closed when not in use. Therefore, the display units 9631a and 9631b can be protected, and a tablet terminal with good durability and reliability from a long-term use perspective can be provided. In addition, the tablet terminals shown in Figures 23A and 23B can also have the following functions: displaying various types of information (static images, dynamic images, text images, etc.); displaying calendars, dates, or times on the display; touch input for operating or editing information displayed on the display; and control processing through various software programs. By utilizing a solar cell 9633 mounted on the surface of a tablet terminal, power can be supplied to the touchscreen, display unit, or image signal processing unit. Furthermore, the solar cell 9633 can be disposed on one or both sides of the casing 9630, allowing for a highly efficient charging structure for the battery 9635. Additionally, when a lithium-ion battery is used as the battery 9635, it offers advantages such as miniaturization. Furthermore, the structure and operation of the charge / discharge control circuit 9634 shown in FIG23B will be explained with reference to the block diagram shown in FIG23C. FIG23C shows the solar cell 9633, battery 9635, DC-DC converter 9636, converter 9637, switches SW1 to SW3, and display unit 9631. Battery 9635, DC-DC converter 9636, converter 9637, and switches SW1 to SW3 correspond to the charge / discharge control circuit 9634 shown in FIG23B. First, an example of operation when the solar cell 9633 generates electricity using external light will be explained. A DC-DC converter 9636 is used to boost or buck the power generated by the solar cell to make it the voltage required to charge the battery 9635. Furthermore, when the display unit 9631 is operated using power from the solar cell 9633, switch SW1 is turned on, and converter 9637 boosts or bucks the voltage to the voltage required by the display unit 9631. Alternatively, when the display unit 9631 is not displaying, a structure can be adopted where switch SW1 is turned off and switch SW2 is turned on to charge the battery 9635. Note that while solar cell 9633 is shown as an example of a power generation unit, it is not limited to this. Other power generation units, such as piezoelectric elements or thermoelectric conversion elements, can also be used to charge battery 9635. For example, charging can also be performed using a wireless power transmission module capable of wireless (contactless) power transmission and reception, or by combining other charging methods. In the television set 8000 of Figure 24A, a display unit 8002 is assembled on the housing 8001. Images can be displayed using the display unit 8002, and sound can be output from the speaker unit 8003. The transistor shown in any of Embodiments 1 to 4 can be used in the display unit 8002. As the display unit 8002, it can use liquid crystal display devices, light-emitting devices that have light-emitting elements such as organic EL elements in each pixel, electrophoretic display devices, DMD (Digital Micromirror Device), PDP (Plasma Display Panel) and other semiconductor display devices. The Television 8000 can also be equipped with a receiver and a modem. The Television 8000 can receive general television broadcasts using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it can also conduct one-way (from sender to receiver) or two-way (between sender and receiver or between receivers, etc.) information communication. Furthermore, the television set 8000 may also include a CPU, memory, etc., for information communication. The television set 8000 may also use the memory and CPU shown in any of embodiments 5 to 7. In Figure 24A, the air conditioner having an indoor unit 8200 and an outdoor unit 8204 is an example of an electronic device using the CPU of Embodiment 7. Specifically, the indoor unit 8200 includes a casing 8201, an air outlet 8202, a CPU 8203, etc. Figure 24A illustrates the case where the CPU 8203 is provided in the indoor unit 8200, but the CPU 8203 can also be provided in the outdoor unit 8204. Alternatively, the CPU 8203 can be provided in both the indoor unit 8200 and the outdoor unit 8204. Because the CPU shown in Embodiment 7 is a CPU using an oxide semiconductor, it has good heat resistance, thus enabling a highly reliable air conditioner. In Figure 24A, the electric refrigerator / freezer 8300 is an example of an electronic device equipped with a CPU using an oxide semiconductor. Specifically, the electric refrigerator / freezer 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, and a CPU 8304, etc. In Figure 24A, the CPU 8304 is disposed inside the housing 8301. By using the CPU shown in Embodiment 7 in the CPU 8304 of the electric refrigerator / freezer 8300, low power consumption can be achieved. Figure 24B shows an example of an electric vehicle with an electronic device. The electric vehicle 9700 is equipped with a secondary battery 9701. The power from the secondary battery 9701 is adjusted by a control circuit 9702 and supplied to the drive unit 9703. The control circuit 9702 is controlled by a processing device 9704 having ROM, RAM, CPU, etc. (not shown). By using the CPU shown in Embodiment 7 as the CPU of the electric vehicle 9700, low power consumption can be achieved. The drive unit 9703 is constructed using a DC motor or an AC motor, or a combination of an electric motor and an internal combustion engine. The processing unit 9704 outputs control signals to the control circuit 9702 based on input information such as driver operation information (acceleration, deceleration, stopping, etc.) and driving information (climbing hills, descending hills, or load on the wheels during driving, etc.). The control circuit 9702 uses the control signals from the processing unit 9704 to adjust the output of the drive unit 9703 by controlling the electrical energy supplied from the secondary battery 9701. When an AC motor is installed, although not shown, an inverter that converts DC to AC is also installed. This implementation method can be appropriately combined with other implementation methods. 1: Gate layer 2: Gate insulation layer 3: Oxide semiconductor layer 4: Source electrode layer 5: Drain electrode layer 6: Etching stop layer 7: Area 8: Area 100:Substrate

Claims

1. A semiconductor device comprising: a first transistor having a first channel forming region; a second transistor having a second channel forming region; a first insulating film on the first channel forming region; and a first conductive layer on the first insulating film; A second insulating film has a region that contacts the side surface of the first conductive layer; a third insulating film has a region that contacts the top surface of the second insulating film; a second conductive layer has a region that contacts the top surface of the third insulating film; a third conductive layer has a region that contacts the top surface of the third insulating film; an oxide semiconductor layer has a region that contacts the second conductive layer, a region that contacts the third conductive layer, a region that contacts the top surface of the third insulating film, and the second channel forming region; a fourth insulating film is on the second channel forming region; a fourth conductive layer is on the fourth insulating film; a fifth insulating film has a region that contacts the top surface of the fourth conductive layer; a fifth conductive layer is located on the fifth insulating film and is electrically connected to the second conductive layer through an opening provided in the fifth insulating film; The first conductive layer has a region that contacts the top surface of the fifth insulating film and a region that overlaps with the third conductive layer across the fifth insulating film, wherein: the first channel forming region contains silicon; the second conductive layer has a region that serves as one of the source electrode and drain electrode of the second transistor; the third conductive layer has a region that serves as the other of the source electrode and drain electrode of the second transistor; the top surface of the first conductive layer has a region that contacts the third conductive layer; the fourth conductive layer does not overlap with the second conductive layer; the fourth conductive layer does not overlap with the third conductive layer; the fifth conductive layer has a region that overlaps with the second channel forming region and a region that overlaps with the first conductive layer; the sixth conductive layer has a region that overlaps with the channel forming region of the first transistor; and the sixth conductive layer does not have a region that overlaps with the fourth conductive layer in the region that overlaps with the third conductive layer.

2. The semiconductor device as claimed in claim 1, wherein: The second conductive layer has a region that contacts the side surface of the oxide semiconductor layer; The third conductive layer has a region that contacts the side of the oxide semiconductor layer.

3. The semiconductor device as claimed in claim 1 or 2, wherein: The sixth conductive layer does not have a region overlapping with the channel forming region of the second transistor; in the plan view, the sixth conductive layer has a region extending in a direction intersecting the channel length direction of the second transistor; and the channel forming region of the first transistor has a region in which charge carriers flow in a direction intersecting the direction of extension of the sixth conductive layer.

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