Storage device and method for managing bias mode switching

Abstract

A storage device is disclosed. The storage device may include a storage unit for data and a controller for managing access to the data in the storage unit. A mechanism is provided for automatically managing the bias mode of blocks of data in the storage unit, the bias mode including one of a host bias mode and a device bias mode.

Description

Technical Field

[0001] [Related Application Data]

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 389,353, filed on Jul. 14, 2022, which is incorporated herein by reference in its entirety for all purposes.

[0003] This disclosure generally relates to storage devices, and more particularly to managing a storage device that supports both host bias and device bias. Background Art

[0004] Because storage devices support different mechanisms for accessing data, the demands for such access can also increase. Such an increase in the demands for accessing data can grow relative to the amount of data stored on the storage device: as more data is stored on the storage device, the access demands can become more stringent.

[0005] There is still a need for a method for managing access to data on a storage device. Summary of the Invention

[0006] Embodiments of this disclosure include a system. The system can include a storage device that supports both a host bias mode and a device bias mode for data on the storage device. The storage device can support bias mode management to switch data between the host bias mode and the device bias mode. Brief Description of the Drawings

[0007] The drawings set forth below are examples of how embodiments of this disclosure can be implemented and are not intended to limit the embodiments of this disclosure. Individual embodiments of this disclosure can include elements not shown in a particular figure and / or can omit elements shown in a particular figure. The drawings are intended to provide illustration and may not be drawn to scale.

[0008] FIG. 1 shows a system including a storage device that supports bias mode management, in accordance with an embodiment of this disclosure. FIG. 2 shows details of the machine shown in FIG. 1, in accordance with an embodiment of this disclosure. FIG. 3 shows details of the storage device shown in FIG. 1, in accordance with an embodiment of this disclosure. FIG. 4 shows a bias score table that can be used by the storage device shown in FIG. 1 for bias mode management, in accordance with an embodiment of this disclosure. FIG. 5 shows how the mechanism shown in FIG. 3 according to an embodiment of the present disclosure can use the bias fraction shown in FIG. 4 to determine when to switch the bias mode. FIG. 6 shows a page in the storage device shown in FIG. 1 according to an embodiment of the present disclosure undergoing a bias mode switch. FIG. 7 shows the architecture of the storage device shown in FIG. 1 according to an embodiment of the present disclosure for bias mode management using a monitoring filter. FIG. 8 shows the data that can be stored by the monitoring filter shown in FIG. 7 according to an embodiment of the present disclosure for bias mode management. FIG. 9 shows a flowchart of an exemplary procedure for the storage device shown in FIG. 1 according to an embodiment of the present disclosure to manage the bias mode using the bias fraction shown in FIG. 4. FIG. 10 shows a flowchart of an exemplary procedure for the storage device shown in FIG. 1 according to an embodiment of the present disclosure to use the bias fraction shown in FIG. 4 when a request is received from the host processor. FIG. 11 shows a flowchart of an exemplary procedure for the storage device shown in FIG. 1 according to an embodiment of the present disclosure to use the bias fraction shown in FIG. 4 when a request is received from the device itself. FIG. 12 shows a flowchart of an exemplary procedure for the storage device shown in FIG. 1 according to an embodiment of the present disclosure to perform a bias mode switch on a page in the execution area. FIG. 13 shows a flowchart of an exemplary procedure for the storage device shown in FIG. 1 according to an embodiment of the present disclosure to identify pages in a region for bias mode switching. FIG. 14 shows a flowchart of an exemplary procedure for the storage device shown in FIG. 1 according to an embodiment of the present disclosure to manage the monitoring filter shown in FIG. 8. FIG. 15 shows a flowchart of an exemplary procedure for the storage device shown in FIG. 1 according to an embodiment of the present disclosure to update an entry in the table of the monitoring filter shown in FIG. 8. FIG. 16 shows a flowchart of an exemplary procedure for the storage device shown in FIG. 1 according to an embodiment of the present disclosure to evict an entry from the monitoring filter shown in FIG. 8. FIG. 17 shows a flowchart of an exemplary procedure for the storage device shown in FIG. 1 according to an embodiment of the present disclosure to process administrative access to the monitoring filter shown in FIG. 8. Embodiments

[0009] Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it should be understood that those of ordinary skill in the art can practice the present disclosure without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

[0010] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish between the respective elements. For example, without departing from the scope of the present disclosure, a first module may be referred to as a second module, and similarly, a second module may be referred to as a first module.

[0011] The terms used in the description of the present disclosure herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular forms "a / an" and "the" used in the description of the present disclosure and the appended claims are also intended to include the plural forms. It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. More specifically, when the term "comprises and / or comprising" is used in this specification, it is specified that the presence of the described features, integers, steps, operations, elements, and / or components is present, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The components and features shown in the drawings are not necessarily drawn to scale.

[0012] Some storage devices (such as storage devices that support cache coherence interconnect protocols (such as the Compute Express Link (CXL) protocol)) allow multiple different sources to access the data stored on the storage device. For example, a host processor can access data from the storage device, but an accelerator can also access data from the storage device (the accelerator can be implemented within the storage device: the combination of the storage device and the accelerator can be referred to as a computational storage unit, computational storage device, computational memory, or compute memory, etc.).

[0013] Some sources (e.g., a host processor) may include a local cache. The local cache can be used to store data fetched from a storage device (or elsewhere) for use by the host processor. The local cache may be relatively smaller than the storage device, but the local cache itself can be accessed by the host processor more quickly compared to the storage device.

[0014] If the data on the storage device is accessed only by the host processor, the fact that the host processor may cache some of the data may be negligible. However, if the data is also accessed by other sources (e.g., an accelerator), then a copy of the data in the local cache may cause problems. For example, if the accelerator updates the data, the copy of the data in the local cache may become stale (i.e., out of date) and the host may need to fetch a copy of the updated data to stay current. Or, if the processor updates the data in the local cache but delays committing the update to the storage device, the accelerator may access stale data from the storage device and the accelerator may produce meaningless results.

[0015] To address these situations, standards for cache coherence interconnect protocols for storage devices may specify that the storage device can operate in one of two modes: host-biased or device-biased. In the host-biased mode, it is assumed that the host may have a cached copy of the data, and any device that wishes to access the data can check with the host to determine if the host processor cache includes the data. In the device-biased mode, it is assumed that the data on the storage device is up-to-date, and the host processor may need to fetch the data from the storage device rather than relying on a cached copy (which may be stale). However, the standards for cache coherence interconnect protocols for devices may not specify how to switch between the host-biased mode and the device-biased mode.

[0016] Embodiments of the present disclosure provide various ways to manage the switch between the host-biased mode and the device-biased mode to improve the performance of the storage device. In one technique, the storage device can use a locality counter to track whether a particular block of data is being accessed more frequently by the host or the device. When the counter for a particular block exceeds an appropriate threshold value, the bias mode of the block can be changed to reflect the source that is currently accessing the block more frequently.

[0017] In the case of using another technique, when the device requests to sequentially flip the bias on several chunks from the host bias mode to the device bias mode, and it is expected that the device will next request those chunks, the storage device can start changing the chunks from the host bias mode to the device bias mode in the background. This process can improve performance compared to waiting for all the chunks in the queue to flip from the host bias mode to the device bias mode before starting any processing.

[0018] In the case of using yet another technique, the storage device may include a snoop filter. The snoop filter can track chunks that are currently cached by the host processor (or that may currently be cached by the host processor). If a chunk is evicted from the snoop filter, the storage device can request the host processor to refresh the chunk from the processor cache.

[0019] FIG. 1 shows a system including a storage device that supports bias mode management according to an embodiment of the present disclosure. In FIG. 1, machine 105 (which may also be referred to as a host or a system) may include a processor 110, a memory 115, and a storage device 120. The processor 110 can be any type of processor. (For ease of illustration, the processor 110 and other components discussed below are shown as being outside the machine: embodiments of the present disclosure may include these components located within the machine.) Although FIG. 1 shows a single processor 110, machine 105 may include any number of processors, each of which may be a single-core processor or a multi-core processor, and each of the single-core or multi-core processors may implement a Reduced Instruction Set Computer (RISC) architecture or a Complex Instruction Set Computer (CISC) architecture (etc.), and may be mixed in any desired combination.

[0020] Processor 110 may be coupled to memory 115. Memory 115 may be any kind of memory, such as flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), persistent random access memory, ferroelectric random access memory (FRAM), or non-volatile random access memory (NVRAM) (such as magnetoresistive random access memory (MRAM)), etc. Memory 115 may be volatile or non-volatile memory as needed. Memory 115 may also be any desired combination of different memory types and may be managed by memory controller 125. Memory 115 can be used to store data that can be referred to as "short-term": that is, data that is not expected to be stored for an extended period of time. Examples of short-term data may include temporary files, data used locally by an application (which may be copied from other storage locations), and similar data.

[0021] Processor 110 and memory 115 can also support an operating system under which various applications can run. These applications can issue requests (which can also be referred to as commands) to read data from or write data to memory 115. When using storage device 120 to support applications that read or write data via a certain file system, device driver 130 can be used to access storage device 120. Although FIG. 1 shows one storage device 120, any number of storage devices can exist in machine 105. Each storage device 120 can support any desired one or more protocols, including for example the Non-Volatile Memory Express (NVMe) protocol. Different storage devices 120 can support different protocols and / or interfaces. For example, storage device 120 can support a cache coherent interconnect protocol that can support both block-level protocol (or any other higher granularity level) access and byte-level protocol (or any other lower granularity level) access to data on storage device 120. An example of such a cache coherent interconnect protocol is the Compute Express Link (CXL) protocol, which supports accessing data in blocks using the CXL.io protocol and accessing data in bytes using the CXL.mem protocol. In this way, data on a CXL storage device can be accessed as block-level data (such as a Solid State Drive (SSD)) or byte-level data (such as memory): the CXL storage device can be used to expand system memory.

[0022] Although FIG. 1 uses the general term "storage device", embodiments of the present disclosure can include any storage device format that can benefit from the use of computational storage units, examples of such storage devices can include hard disk drives and solid state drives (SSDs). Any reference to "SSD" hereinafter should be understood to include such other embodiments of the present disclosure. In addition, different types of storage devices can be mixed. For example, one storage device 120 can be a hard disk drive and another storage device 120 can be an SSD.

[0023] Machine 105 can also include accelerator 135. Accelerator 135 can be a form of local processing that is "closer" to storage device 120. Accelerator 135 can be used to support the processing of queries to a database that can be stored on storage device 120. By using accelerator 135, queries can be processed more quickly compared to processor 110, and the load on processor 110 can be reduced.

[0024] FIG. 2 shows details of the machine 105 shown in FIG. 1 according to an embodiment of the present disclosure. In FIG. 2, the machine 105 generally includes one or more processors 110, and the one or more processors 110 may include a memory controller 125 and a clock 205 that can be used to coordinate the operation of the components of the machine. The processor 110 may also be coupled to a memory 115. As an example, the memory 115 may include random access memory (RAM), read-only memory (ROM), or other state-holding media. The processor 110 may also be coupled to a storage device 120 and a network connector 210. The network connector 210 may be, for example, an Ethernet connector or a wireless connector. The processor 110 may also be connected to a bus 215, and a user interface 220 and an I / O interface port that can be managed using an input / output (I / O) engine 225 and other components may be attached to the bus 215.

[0025] FIG. 3 shows details of the storage device 120 shown in FIG. 1 according to an embodiment of the present disclosure. In FIG. 3, an implementation of the storage device 120 is shown as being for a solid-state drive. In FIG. 3, the storage device 120 may include a host interface layer (HIL) 305, a controller 310, and various flash memory chips 315-1 to 315-8 (also referred to as "flash memory storage" or simply "storage" and may be collectively referred to as flash memory chips 315 or storage 315). The various flash memory chips 315-1 to 315-8 may be organized into various channels 320-1 to 320-4 (which may be collectively referred to as channels 320). The host interface layer 305 may manage the communication between the storage device 120 and other components (such as the processor 110 shown in FIG. 1). The host interface layer 305 may also manage the communication with a device located remotely relative to the storage device 120. That is, the host interface layer 305 may manage the communication with a device other than the processor 110 shown in FIG. 1 (for example, the accelerator 135 shown in FIG. 1, in the case where the accelerator 135 is not included as part of the storage device 120) through one or more network connections, and the device may be local or remote relative to the machine 105 shown in FIG. 1. Such communications may include read requests for reading data from the storage device 120, write requests for writing data to the storage device 120, and delete requests for deleting data from the storage device 120.

[0026] The host interface layer 305 can manage interfaces that span only a single port, or the host interface layer 305 can manage interfaces that span multiple ports. As an alternative, the storage device 120 can include multiple ports, and each of the multiple ports can have a separate host interface layer 305 to manage the interfaces across the ports. Embodiments of the inventive concept can also mix possibilities (for example, an SSD with three ports can have one host interface layer for managing one port and a second host interface layer for managing the other two ports).

[0027] The controller 310 can use the flash memory controller 325 to manage read operations, write operations, garbage collection operations, and other operations on the flash memory chips 315. The controller 310 can also include a translation layer 330 that can manage the mapping of logical addresses (such as logical block addresses (LBAs)) used by the host 105 shown in FIG. 1 to physical addresses (such as physical block addresses (PBAs)) where the data is actually stored on the storage device 120. By using the translation layer 330, when the data moves from one physical address to another within the storage device 120, it is not necessary to notify the machine 105 shown in FIG. 1.

[0028] In some embodiments of the present disclosure, the controller 310 can include an accelerator 135. The accelerator 135 can be omitted from the storage device 120 (or more precisely, outside the controller 310 or the storage device 120), which is indicated by the dashed line around the accelerator 135.

[0029] The controller 310 may include a memory 335. The memory 335 may be a memory located within the storage device 120 (as compared to the memory 115 shown in FIG. 1 in the host 105 shown in FIG. 1). Similar to the memory 115 shown in FIG. 1, the memory 335 may be any type of memory, such as flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), persistent random access memory, ferroelectric random access memory (FRAM), or non-volatile random access memory (NVRAM) (such as magnetoresistive random access memory (MRAM)), etc. The memory 115 may be a volatile memory or a non-volatile memory as needed; however, since the storage device 120 includes a non-volatile storage in the flash chip 315, it is expected that the memory 115 is more often a volatile storage. The memory 335 may act as a faster storage for the data stored on the flash chip 315 and may act as a cache for the data stored on the flash chip 315. As an alternative to accessing data from the flash chip 315, the accelerator 135 may access data from the memory 335.

[0030] Finally, the controller 310 may include a mechanism 340. The mechanism 340 may be a mechanism for the storage device 120 to manage the bias mode of the data in the memory 315. The mechanism 340 may also be referred to as a device tunability controller or a device tunability engine. The mechanism 340 may include circuitry (such as a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or some other form of circuitry) designed to manage the bias mode in the storage device 120, or the mechanism 340 may include a processor that executes software (which may be stored in a non-volatile memory in the storage device 120) for managing the bias mode in the storage device 120. The mechanism 340 may also include a form of storage for various data used when managing the bias mode in the storage device 120 (which may be volatile or non-volatile depending on the embodiments of the present disclosure). This storage may include, for example, a form of memory (such as DRAM) or some other flash storage. The specific details of the mechanism 340 will be further discussed below.

[0031] Although FIG. 3 shows the storage device 120 as including eight flash memory chips 315 organized into four channels 320, embodiments of the inventive concept may support any number of flash memory chips organized into any number of channels. Similarly, although FIG. 3 shows the structure of an SSD, other storage devices (e.g., hard disk drives) may be implemented using a structure different from the structure shown in FIG. 3 to manage reading and writing data, but having similar potential beneficial effects. For example, a request may be issued to the storage device 120 by the processor 110 or the accelerator 135 shown in FIG. 1. In some embodiments of the present disclosure, in addition to the internal management of the data stored on the flash chips 315, the storage device 120 may also be considered a reactive device that does not initiate any actions.

[0032] In some embodiments of the present disclosure, the storage device may be divided into storage units of various sizes. For example, an SSD may be divided into pages, each of which may store approximately 8 kilobytes (KB) (2^14 bytes) of data. A block may include 128 pages: thus, the size of a block may be approximately 1 megabyte (MB) (2^21 bytes). Additionally, blocks may be grouped together to form a superblock.

[0033] Since different operations may be performed on different units, an SSD may include such various unit sizes. For example, an SSD may read or write data pages. Thus, when the processor 110 shown in FIG. 1 issues a read request or a write request, the processor 110 shown in FIG. 1 may provide up to one complete data page to be written to the SSD (any desired bits may be used to fill the page to fill the page) or provide a buffer large enough to store one complete data page to be read from the SSD.

[0034] However, SSDs generally do not support data overwriting. That is, if the processor 110 shown in FIG. 1 wishes to replace some data that has already been written to the SSD, the SSD may instead write the updated data to a new page and invalidate the original page. Then the translation table 330 may be updated to reflect the new page storing the updated data.

[0035] Since an SSD can invalidate a page instead of overwriting the page with new data, at some point, the SSD can erase the data on the invalidated page (such that new data can be written to the page). This process may be referred to as garbage collection. However, an SSD erases data in units of blocks (or superblocks) rather than in units of pages. Thus, in order to reclaim a page that has been marked as invalid, the SSD may need to erase all of the data in the block that includes the page.

[0036] If the SSD erases blocks instead of pages, the SSD can wait until all of the pages in the block have been erased. However, it is not known when all of the pages in an individual block will become invalid (or even if they ever will). If the SSD waits until all of the pages in a block are invalid before erasing the block, the SSD may run out of free space. Thus, garbage collection can sometimes involve erasing a block that stores some valid data. To prevent data loss, the SSD can copy the valid data from the block to a free page and then can erase the block (thereby returning the block to the free block pool and making all of the pages in the block available for storing data again).

[0037] As discussed above, a storage device (such as storage device 120) that supports a cache coherence interconnect protocol can be considered an extension of the memory 115 shown in FIG. 1. When the storage device 120 receives a load request or a store request (or alternatively a read request or a write request), mechanism 340 can determine the bias mode of the page having the requested data. Mechanism 340 can also determine whether the requested data is currently cached in the memory 335. Then, depending on the bias mode of the page and whether the data is currently cached in the memory 335, mechanism 340 can then read data from or write data to the memory 335, read data from or write data to the memory 335 (for data in the device bias mode), read data from or write data to the memory 115 shown in FIG. 1 (for data in the host bias mode), and / or perform a bias switch using the various embodiments described below.

[0038] FIG. 4 shows a bias score table that can be used by the storage device 120 shown in FIG. 1 for bias mode management according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the storage device 120 shown in FIG. 1 may include a bias score table 405. The bias score table 405 may include bias scores for blocks of data stored in the memory 315 shown in FIG. 3 of the storage device 120 shown in FIG. 1. The term "block" as used herein is intended to refer to any desired storage unit on the storage device 120 shown in FIG. 1. For example, a block may represent a cache line, page, block, superblock, sector, or any other desired storage unit on the storage device 120 shown in FIG. 1. Additionally, a block may represent a storage unit of a different defined size than other storage units in the storage device 120 shown in FIG. 1. For example, in some embodiments of the present disclosure, a page may include a storage capacity of approximately 8 kilobytes, and a block may include a storage capacity of approximately 1 megabyte, while a block may be determined to include a storage capacity of approximately 4 kilobytes (2^13 bytes). Alternatively, a page may include a storage capacity of approximately 8 kilobytes, and a block may be determined to include a storage capacity of approximately 4 kilobytes. In other words, the size of a block may be any desired size.

[0039] The memory 315 shown in FIG. 3 on the storage device 120 shown in FIG. 1 may then be divided into multiple units based on the block size, and each unit may be assigned an identifier (ID). For example, if the storage device 120 shown in FIG. 1 includes a total storage capacity of 500 gigabytes (GB) and each block includes a storage capacity of 4 kilobytes, then there are 134,217,728 (2^28) storage blocks. The ID of a block may range from 1 to 134,217,728. Alternatively, since computers typically start numbering from 0, the ID of a block may range from 0 to 134,218,727. In the case of using hexadecimal notation, the ID of a block may range from 0x0000 0000 to 0x07FF FFFF.

[0040] In FIG. 4, the bias score table 405 includes rows for block ID 410, score 415, and bias mode 420. The bias score table 405 also shows three table entries 425-1 to 425-3 (which may be collectively referred to as table entry 425), but embodiments of the present disclosure may include any number (zero or more) of table entries in the bias score table 405.

[0041] In some embodiments of the present disclosure, the bias score table 405 may include only the entries 425 for the chunks that are currently being tracked. For example, the bias score table 405 shows entries 425 for chunk IDs 0x0000, 0x0001, and 0x0002. In this way, the bias score table 405 can store only the entries for the chunks that are in use. Whether or not any data is stored, this can save some storage space in the bias score table 405 compared to storing entries for each chunk in the storage device 120 shown in FIG. 1. On the other hand, if the bias score table 405 includes space for each chunk in the storage device 120 shown in FIG. 1, the chunk ID can be used to index into the bias score table 405, and the row ID 410 can be omitted from the bias score table 405.

[0042] The bias score 415 can represent the current bias score of the associated chunk in the entry 425. For example, for chunk ID 0x0000, the bias score is currently 0, for chunk ID 0x0001, the bias score is currently 2, and for chunk ID 0x0002, the bias score is currently -3.

[0043] When a particular chunk is accessed by a host or a device (such as the accelerator 135 shown in FIG. 1), the bias score table 405 can be updated to reflect the access. In some embodiments of the present disclosure, when accessed by the host, the bias score 415 can be incremented by one, and when accessed by the device, the bias score 415 can be decremented by one. When the bias score 415 reaches an appropriate threshold value, the bias mode 420 of the chunk can be switched from the host bias mode to the device bias mode, or vice versa. Other embodiments of the present disclosure can adjust the bias score in different ways when accessing a chunk: all such embodiments of the present disclosure are intended to be covered by the present disclosure.

[0044] The bias mode 420 can reflect the current bias of the associated chunk. For example, the value "0" can reflect the host bias mode, and the value "1" can reflect the device bias mode. Thus, for example, the bias score table 405 shows that the chunk with ID 0x0000 and the chunk with ID 0x0001 are currently in the host bias mode, and the chunk with ID 0x0002 is currently in the device bias mode.

[0045] Since the bias mode of a block can be a host bias mode or a device bias mode, a single bit can be used to represent the bias mode 420. The number of bits used to represent the bias fraction 415 can depend on the range of values established for the bias fraction 415. For example, if the bias fraction 415 is allowed to range between -3 and +3, the total range of the bias fraction 415 is seven values, and three bits can be used to represent the bias fraction 415. (It should be noted that the number of bits used to represent the bias fraction 415 can be large enough to include values outside the allowed range: the bias fraction 415 can be restricted to a subset of all possible values supported by the number of bits used to represent the bias fraction 415.) Thus, in embodiments of the present disclosure where the bias fraction table 405 is large enough for each block in the storage device 120 shown in FIG. 1, if the storage device 120 shown in FIG. 1 includes a total of 134,217,728 blocks, the total storage required for the bias fraction table 405 can be 134,217,728 × (3 + 1) = 536,870,912 (2^30) bits or 67,108,864 (2^27) bytes: a storage of approximately 67 million bytes. For a storage device providing a storage of approximately 500 gigabytes (2^40 bytes), the bias fraction table 405 can use approximately 0.001% of the total storage.

[0046] As mentioned above, when the bias fraction 415 reaches an appropriate threshold value, the bias mode of the block can be switched. In some embodiments of the present disclosure, the same threshold values can be used for all bias fractions 415, regardless of which block the bias fraction 415 is used for. For example, when the bias fraction 415 of a particular block reaches -3, the bias mode can be switched from the host bias mode to the device bias mode, and when the bias fraction 415 of a particular block reaches +3, the bias mode can be switched from the device bias mode to the host bias mode. However, in other embodiments of the present disclosure, each block can have its own range of values for the bias fraction 415. In such embodiments of the present disclosure, the bias fraction table 405 can include threshold values for each block. For example, the device threshold 430 can represent the threshold value for switching a block from the host bias mode to the device bias mode, and the host threshold 435 can represent the threshold value for switching a block from the device bias mode to the host bias mode. Although the bias fraction table 405 shows the same threshold values for all blocks, embodiments of the present disclosure can thus support different threshold values for switching the bias modes of different blocks. Obviously, if the same one or more threshold values are used for all blocks, the shared one or more threshold values can be omitted from the bias fraction table 405.

[0047] One unsolved problem lies in what will happen when the block is accessed by the same source (host or device) that currently holds the bias mode. In some embodiments of the present disclosure, the mechanism 340 shown in FIG. 3 can determine the current bias mode of the block. If the bias mode of the block currently favors the source accessing the block, the bias score 415 may not change. In such embodiments of the present disclosure, it is expected that the bias score 415 will move in one direction until the bias score 415 reaches a threshold value, after which the bias score 415 will move in the other direction until the bias score 415 reaches another threshold value, and so on. In other embodiments of the present disclosure, the mechanism 340 shown in FIG. 3 can compare the bias score 415 with threshold values 430 and 435: as long as the bias score 415 is within the range determined by the threshold values 430 and 435, the mechanism 340 shown in FIG. 3 can continue to increment or decrement the bias score 415 with each access by the source. In such embodiments of the present disclosure, it is expected that the bias score 415 will change, but only within the range set by the threshold values 430 and 435. In still some other embodiments of the present disclosure, the mechanism 340 shown in FIG. 3 can verify that incrementing or decrementing the bias score 415 will not cause an overflow or underflow (i.e., a value that is too large or too small for the number of available bits): assuming that the bias score 415 will not overflow or underflow, the bias score 415 can be incremented or decremented without considering the threshold values 430 and 435.

[0048] Another unsolved problem lies in whether the bias score 415 has ever been reset. In some embodiments of the present disclosure, the bias score 415 is reset to a default value (such as zero) only during power-on. In other words, when the mechanism 340 shown in FIG. 3 switches the bias mode of the block, the bias score 415 of the block can remain at its current value after the bias mode is switched. In other embodiments of the present disclosure, the bias score 415 can be reset to a default value every time the bias mode of the block is switched. By resetting the bias mode of the block to a default value, it is easier to switch the bias mode again. In still some other embodiments, regardless of whether the bias score 415 is reset when the bias mode of the block is switched, a software request can be used to reset the bias score 415 (for individual blocks or for the entire bias score table 405). For example, an application may wish to reset the bias score 415 for all the data accessed by the application to avoid any earlier access affecting how and when bias can occur.

[0049] FIG. 5 illustrates how the mechanism 340 shown in FIG. 3 according to an embodiment of the present disclosure can use the bias fraction 415 shown in FIG. 4 to determine when to switch the bias mode. In FIG. 5, the mechanism 340 can use the bias fraction 415 and one (or both) of the threshold values 430 or 435. If the bias fraction 415 is greater than or equal to the threshold value 435 (or less than or equal to the threshold value 430), the mechanism 340 can perform a bias mode switch 505.

[0050] FIG. 6 illustrates a page in the storage device 120 shown in FIG. 1 undergoing a bias mode switch according to an embodiment of the present disclosure. In FIG. 6, the mechanism 340 shown in FIG. 3 can perform a look-ahead bias mode switching. For example, the device 135 shown in FIG. 1 may need to access data in several contiguous pages in the storage device 120 shown in FIG. 1: the contiguous pages can form a region. In other words, a region can be defined as a contiguous block of addresses where the data is stored (the addresses can be logical addresses for the host 105 shown in FIG. 1 or physical addresses where the storage device 120 shown in FIG. 1 stores the data). When the device 135 shown in FIG. 1 accesses the first page, the mechanism 340 shown in FIG. 3 can start switching the bias modes of the other pages in the region to the device bias mode to accelerate the data access performed by the device 135 shown in FIG. 1.

[0051] In FIG. 6, pages 605-1 to 605-8 (which can be collectively referred to as page 605) can be pages of data in the storage device 120 shown in FIG. 1. The pages 605 can form a region or range of addresses, where page 605-1 is contiguous with page 605-2, page 605-2 is contiguous with pages 605-1 and 605-3, and so on.

[0052] In FIG. 6, pages 605-1 to 605-3 have been switched to the device bias mode by the mechanism 340 shown in FIG. 3 and have been processed by the device 135 shown in FIG. 1. Page 605-4 has been switched to the device bias mode by the mechanism 340 shown in FIG. 3 and is being processed by the device 135 shown in FIG. 1. Page 605-5 is being switched to the device bias mode by the mechanism 340 shown in FIG. 3. Finally, pages 605-6 to 605-8 are waiting to be switched to the device bias mode by the mechanism 340.

[0053] To switch page 605-5 to the device bias mode, the mechanism 340 shown in FIG. 3 can invalidate any data in the host cache, as shown in operation 610. Once the copies of page 605-5 in any host cache are invalidated, page 605-5 can be switched to the device bias mode, as shown in operation 505. Operations 610 and 505 can be considered part of switching page 605-5 to the device bias mode (as shown in grouping 615).

[0054] Once a page (such as page 605-4) has been switched to the device bias mode, the device 135 shown in FIG. 1 can process the data (as shown in operation 620), and can store the updated data (as shown in operation 625). Operations 620 and 625 can be considered part of the processing performed by the device 135 shown in FIG. 1 (as shown in grouping 630).

[0055] Since page 605 is part of a region, when the device 135 shown in FIG. 1 starts accessing page 605-1, the mechanism 340 shown in FIG. 3 can identify that the device 135 shown in FIG. 3 may wish to access all of page 605. Although the device 135 shown in FIG. 1 can wait until all of page 605 is in the device bias mode before starting to process any of the data in page 605, however, for the device 135 shown in FIG. 1, it can process page 605-1 when page 605-2 is switched to the device bias mode, process page 605-2 when page 605-3 is switched to the device bias mode and so on. In other words, the device 135 shown in FIG. 1 can process the data when each page is switched to the device bias mode, rather than waiting until all of page 605 is in the device bias mode. This can enable the device 135 shown in FIG. 1 to process the data more quickly.

[0056] To achieve this result, the mechanism 340 shown in FIG. 3 can switch page 605 to the device bias mode in the background before the device 135 shown in FIG. 1 attempts to access the data. In other words, the mechanism 340 shown in FIG. 3 can switch page 605 to the device bias mode in the case where it is expected that the device 135 shown in FIG. 1 will request access to the data in page 605. Given information about the region (or the range of addresses in the region), the mechanism 340 shown in FIG. 3 can proactively switch page 605 to the device bias mode to accelerate the operations performed by the device 135 shown in FIG. 1.

[0057] Note that although FIG. 6 will illustrate the region as including page 605, embodiments of the present disclosure may include any definition of the region. For example, the region may be defined as a range of addresses not referring to the address of page 605; or the region may be defined as several chunks or some other way of partitioning the region. However, when defining the region, each page, chunk, or part of the region may be sequentially switched to the device bias mode based on being a part of the region. Continuously performing such switching may have the advantage of making the data available to the device 135 shown in FIG. 1 in the order of the data expected by the device 135 shown in FIG. 1.

[0058] FIG. 7 shows an architecture for bias mode management using a listening filter by the storage device 120 shown in FIG. 1 according to an embodiment of the present disclosure. In FIG. 7, the host 105 may send a request to the storage device 120. Depending on how the storage device 120 is implemented, there may be three different types of commands that the host 105 may send to the storage device 120. A management request for the listening filter in the mechanism 340 shown in FIG. 3 may be executed using a block-level protocol request shown as a CXL.io request in FIG. 7. Data may be accessed from the storage device 120 using a byte-level protocol request shown as a CXL.mem request in FIG. 7 as if the storage device 120 is an extension of the memory 115 shown in FIG. 1. A cache request shown as a CXL.cache request in FIG. 7 may be used to manage the cache status of the data: that is, to keep the storage device 120 informed of the data currently cached by the processor 110 and whether the data in the storage device 120 is up-to-date or may be expired relative to the data in the cache of the processor 110.

[0059] The control and status register (CSR) 705 may receive information from the host 105 via a block-level protocol request. Then the CSR 705 may perform management on the listening filter in the storage device 120: for example, an application may use the CSR 705 to learn the status of specific data from the listening filter or reset some information in the listening filter. Since the block-level protocol requests are used for accessing the listening filter using the CSR 705, such block-level protocol requests are for management rather than for data access, which is why the block-level protocol access is shown with a dashed line in FIG. 7. In some embodiments of the present disclosure, when the block-level protocol request can be used to access the listening filter, since the read request / write request from the storage device 120 may share the block-level protocol access to the storage device 120, such requests may be disabled.

[0060] The device coherence engine 340 can receive byte-level protocol requests and cache requests from the host 105, and can issue requests to other components of the storage device 120. For example, based on a cache request from the host 105, the device coherence engine 340 can send a host-to-device request to the device cache 710 and receive a device-to-host response from the device cache 710. Similarly, based on a byte-level protocol request from the host 105, the device coherence engine 340 can issue a master-to-slave request to the memory controller 710 and can receive a master-to-slave response from the memory controller 715.

[0061] When the device cache 710 receives a host-to-device request involving data (read or write), it can communicate with the memory controller 715 to process the request. Then the memory controller 715 can communicate with the host-managed device (HDM) memory to read data from or write data to the HDM memory. (Although FIG. 7 shows the HDM memory as DRAM (which can be understood as volatile memory), embodiments of the present disclosure can use persistent memory or non-volatile memory to replace the HDM memory, and / or data can also be written to a non-volatile storage not shown in FIG. 7.)

[0062] The storage device 120 may also include a snoop filter cache controller 720 that is responsible for managing the snoop filter 725. The snoop filter 725, which can be in the form of a table, can be stored in the snoop filter cache controller 720, can be stored in a snoop filter memory 730 that can be separate from or part of the HDM memory 735, can be stored in the HDM memory 735, or can be stored in any combination thereof. For example, the snoop filter 725 can be stored partially in the cache in the snoop filter cache controller 720, partially in the snoop filter memory 730, and partially in the HDM memory 735. The structure of the snoop filter 725 is further discussed below with reference to FIG. 8.

[0063] The monitoring filter cache controller 720 can perform several functions. First, the monitoring filter cache controller 720 can update the monitoring filter 725 to reflect how the host 105 is currently using various blocks. Thus, whenever the host 105 accesses data from the storage device 120, the monitoring filter cache controller 720 can update the monitoring filter 725. This is shown by the dashed line from the device cache 710 and the memory controller 715 to the monitoring filter cache controller 720: when the host 105 accesses data, the device cache 710 and the memory controller 715 can notify the monitoring filter cache controller 720, enabling the monitoring filter cache controller 720 to update the monitoring filter 725.

[0064] Second, the monitoring filter cache controller 720 can obtain data for the monitoring filter 725 from the monitoring filter memory 730 (or the HDM memory 735, depending on where the monitoring filter 725 can be stored). For example, the cache in the monitoring filter cache controller 720 may only have space for data in the order of a few million bytes, but the size of the complete monitoring filter 725 can be in the order of tens of millions of bytes. The monitoring filter cache controller 720 can store a subset of the monitoring filter 725 in its local cache, with the remainder of the monitoring filter 725 stored in the monitoring filter memory 730. When the monitoring filter cache controller 720 needs to access data in the monitoring filter 725 that is not currently in its local cache in the monitoring filter cache controller 720, the monitoring filter cache controller 720 can obtain some additional data from the monitoring filter memory 730 (and may write some data from the monitoring filter 725 to the monitoring filter memory 730 to make space for the newly obtained data).

[0065] Furthermore, the snoop filter cache controller 720 can evict data from the snoop filter 725. For example, if all entries in the snoop filter 725 are currently in use and the host 105 requests access to some data for which there is no entry in the snoop filter 725, then the snoop filter cache controller 720 can evict some data from the snoop filter 725. As part of evicting data from the snoop filter 725, the snoop filter 720 can send a device-to-host invalidate request to the device coherence engine 340, thereby requesting the host 340 to invalidate the cache of specific data relative to the host 340, and the host 105 can send a host-to-device invalidate confirmation to the cache. It should be noted that since the size of the cache in the host 105 can be different from the size of the snoop filter 725, the host 105 may not have the data that is in the cache of the host 105. For example, if each cache line stored in the cache of the host 105 is 256 bytes and the host 105 includes an 8 million byte cache, then the cache in the host 105 has space for a total of 32,768 (2^16) cache lines. However, if the snoop filter 725 (spread across the cache in the snoop filter cache controller 720 and the snoop filter memory 730) has space for, for example, 1,048,576 (2^21) cache lines, then the snoop filter 725 can store information about at least one cache line that is not stored in the cache of the host 105.

[0066] Invalidating data from the cache in the host 105 can involve simply notifying the host 105 that it should delete the data in its cache. However, if the data stored in the cache of the host 105 is more up-to-date than the data in the storage device 120, then the storage device 120 should be updated with the current data. In such a case, the snoop filter cache controller 720 can issue a back-invalidate request, rather than just an invalidate request. Once the device-to-host back-invalidate request is received, the host 105 can update the data on the storage device 120 by issuing a cache request or a byte-level protocol request to write the current data to the storage device 120.

[0067] The snooping filter 725 can track whether the host 105 desires to change data based on the type of request issued by the host 105. That is, the host 105 can issue a request (a cache request or a byte-level protocol request), which can specify whether the host 105 desires to modify data. For example, a cache coherence protocol can specify whether the data is in one of four different states: a modified state (the host 105 can cache the data and the data in the storage device 120 may be out of date); an exclusive state (the host 105 can cache the data, but the data in the storage device 120 is up-to-date); a shared state (the data can be cached by any number (one or more) of hosts, but the data in the storage device 120 is up-to-date); or an invalid state (the data is not currently cached by any host). The host 105 can specify which state the data can be in (either as a parameter of the request or by using a different request that can specify the state). The snooping filter cache controller 720, the host 105, or any other host that is currently caching the data can also issue various requests to investigate the current state of the data, and this may or may not change the current state of the data. For example, an invalidate request can be issued to force any modified data to be written to the storage device 120 and to return the state of the data to the invalid state or to query the current state of the data in the snooping filter 725.

[0068] In some embodiments of the present disclosure, the HDM memory 735 can be volatile memory; in other embodiments of the present disclosure, the HDM memory 735 can be persistent memory. The implementation depends on the needs of the host 105. On the other hand, whether the snooping filter memory 730 is persistent can depend on whether any data cached by the host 105 is persistent. If the host 105 includes a persistent cache, then the snooping filter 725 may also need to be stored in persistent storage so that in the event of a power interruption, the state of the snooping filter 725 is not lost (when the host 105 includes a persistent cache that holds its data, the result of the snooping filter 725 being lost due to a power interruption can be unpredictable, can lead to data inconsistency, or can lead to accurate calculations, etc.).

[0069] It should also be noted that the host 105 can be located remotely relative to the storage device 120. That is, the host 105 in FIG. 7 can represent a processor remotely connected to the storage device 120. In such a case, a power interruption of the storage device 120 may not cause a power interruption of the host 105, which means that any data in the cache in the host 105 may not be lost when the power of the storage device 120 is interrupted. If this can occur, then for the same reasons as those discussed above, the snooping filter 725 may also need to be persistent.

[0070] FIG. 8 shows data that can be stored by the listening filter 725 shown in FIG. 7 for bias mode management according to an embodiment of the present disclosure. In FIG. 8, the listening filter 725 is shown as a table. The listening filter 725 may include rows for block ID 410, cached 805, and clean 810. The block ID 410 may store the ID of a block (as discussed above, a block may represent a cache line, page, block, superblock, or any other desired storage unit). Cached 805 may indicate whether the particular block is currently cached by the host 105 shown in FIG. 1 (or any other host). For example, a value of zero may indicate that the data is currently cached by the host 105 shown in FIG. 1, and a value of one may indicate that the data is not currently cached by the host 105. For example, if the host 105 shown in FIG. 1 writes back the data and specifies that the data is no longer to be cached, the listening filter 725 can know that the particular block is no longer cached by the host 105 shown in FIG. 1. (Since the listening filter 725 can track its own information, the listening filter 725 may not evict the block just because the host 105 shown in FIG. 1 no longer caches the block.) Thus, for example, table entries 815-1 and 815-2 may indicate that the associated block is currently cached by the host 105 shown in FIG. 1, and table entry 815-3 may indicate that the associated block is not currently cached by the host 105 shown in FIG. 1.

[0071] Clean 810 may track whether a block currently cached by the host 105 shown in FIG. 1 is clean or dirty. A clean block may be a block for which the data stored on the storage device 120 shown in FIG. 1 is up-to-date: that is, the host 105 shown in FIG. 1 has not updated the data or has indicated that the data is not updated. On the other hand, a dirty block may be a block for which the data stored on the storage device 120 shown in FIG. 1 is considered to be out-of-date, and the host 105 shown in FIG. 1 has indicated that the data has been updated or will be updated. Values of zero and one can be used to represent the two states. Thus, for example, table entry 815-1 may indicate that the associated block is cached and dirty, and table entry 815-2 may indicate that the associated block is cached but clean.

[0072] Note that if the data is not cached on the host 105 shown in FIG. 1, then clean 810 may be irrelevant. Thus, for example, entry 815-3 may indicate that the associated block is not currently cached by the host 105 shown in FIG. 1. In such a case, it does not matter what value is used for clean 810 in entry 815-3. FIG. 8 uses the value "X" to represent this fact, and the value "X" can be understood to mean "unimportant". Since the value of clean 810 in entry 815-3 is unimportant, either zero or one can be used for clean 810 in entry 815-3 without losing any information.

[0073] The reason that the monitoring filter 725 may store clean 810 is that if the associated block is evicted from the monitoring filter 725, it is determined whether to send an invalidate request or a reverse invalidate request to the host 105 shown in FIG. 1. For example, if entry 815 indicates that the data is clean, then an invalidate request will be sufficient; if entry 815 indicates that the data is dirty, then the host 105 shown in FIG. 1 may need to write the data back to the storage device 120 shown in FIG. 1 to ensure that the data of the block is up-to-date, and thus a reverse invalidate request may be issued. As an alternative, line 810 may be omitted, in which case a reverse invalidate request may be issued for any block evicted from the monitoring filter 725 (and the host 105 shown in FIG. 1 may determine whether any data needs to be written back to the storage device 120 shown in FIG. 1).

[0074] Although FIG. 8 shows the monitoring filter 725 as including three entries 815-1 to 815-3 (which may be collectively referred to as entry 815), embodiments of the present disclosure may include any number (zero or more) of entries 815 in the monitoring filter 725.

[0075] In terms of size, each entry 815 in the snooping filter 725 may include enough bits to identify the block, plus two bits to indicate whether the block is currently cached and whether the data is clean. The number of bits required to identify the block may be a function of the size of the storage device 120 shown in FIG. 1 and the size of the individual blocks of data. For example, if the storage device 120 shown in FIG. 1 stores approximately 500 gigabytes of data and each block is 256 (2^8) bytes in size, then the storage device 120 shown in FIG. 1 may include 2,147,483,648 (2^32) blocks, which may require 32 bits to identify each individual block. Thus, each entry 815 may use 34 bits of data. To store approximately 1,000,000 entries 815, the snooping filter 725 may require a total of 35,651,584 (slightly less than 2^27) bytes. As with the bias fraction table, this amount of space is negligible with respect to the total capacity of the storage device 120 shown in FIG. 1 (approximately 0.006% of the total capacity of the storage device 120).

[0076] As discussed above, in some embodiments of the present disclosure, the data in the storage device 120 shown in FIG. 1 may be accessed by more than one host 105 shown in FIG. 1. Thus, blocks of data may be cached by more than one host 105 shown in FIG. 1. If the storage device 120 shown in FIG. 1 issues an invalidate (or reverse invalidate) request, then the storage device 120 may broadcast the request to all of the hosts 105 shown in FIG. 1. And, if a host 105 shown in FIG. 1 receives such a request, then the host 105 shown in FIG. 1 may forward the request to any other host that may have a copy of the data to ensure that all caches are cleared.

[0077] FIG. 9 shows a flowchart of an exemplary procedure in which the storage device 120 shown in FIG. 1 uses the bias fraction 415 shown in FIG. 4 to manage the bias mode in accordance with an embodiment of the present disclosure. In FIG. 9, at block 905, the storage device 120 shown in FIG. 1 may receive a request to access a block of data from a source, which may be the host 105 shown in FIG. 1 or the device 135 shown in FIG. 1. At block 910, the mechanism 340 shown in FIG. 3 may identify the bias fraction 420 shown in FIG. 4, for example, by accessing the bias fraction 420 from the bias fraction table 405 shown in FIG. 4. Finally, at block 915, the mechanism 340 shown in FIG. 3 may adjust the bias fraction 420 shown in FIG. 4 for the block based on the source of the request.

[0078] FIG. 10 shows a flowchart of an exemplary procedure in which storage device 120 shown in FIG. 1 uses bias fraction 415 shown in FIG. 4 when receiving a request from processor 110 shown in FIG. 1. In FIG. 10, at block 1005, storage device 120 shown in FIG. 1 may receive from processor 110 shown in FIG. 1 a request to access a chunk of data. At block 1010, mechanism 340 shown in FIG. 3 may determine whether the chunk of data is currently in the host bias mode. If the chunk of data is currently in the host bias mode, the process may end (by providing access to the data to processor 110 shown in FIG. 1). Otherwise, at block 1015, mechanism 340 shown in FIG. 3 may increment bias fraction 420 shown in FIG. 4 for the chunk. As discussed above, in some embodiments of the present disclosure, if the bias fraction is less than threshold value 435 shown in FIG. 4, mechanism 340 shown in FIG. 3 may only increment bias fraction 420 shown in FIG. 4; in other embodiments of the present disclosure, mechanism 340 shown in FIG. 3 may increment bias fraction 420 shown in FIG. 4 without regard to threshold value 435 shown in FIG. 4. At block 1020, mechanism 340 shown in FIG. 3 may check to see if bias fraction 420 shown in FIG. 4 is less than threshold value 435 shown in FIG. 4. If bias fraction 420 shown in FIG. 4 is at least as large as threshold value 435 shown in FIG. 4, then at block 1025, mechanism 340 shown in FIG. 3 may switch the bias mode of the chunk to the host bias mode. In either case, the process may then end (by providing access to the data to processor 110 shown in FIG. 1).

[0079] As discussed above, in some embodiments of the present disclosure, even if a chunk of data in storage device 120 shown in FIG. 1 is in the host bias mode, mechanism 340 shown in FIG. 3 may also increment bias fraction 420 shown in FIG. 4. In such embodiments of the present disclosure, block 1010 may be omitted so that the process always proceeds to block 1015, as shown by dashed line 1030.

[0080] FIG. 11 shows a flowchart of an exemplary procedure in which storage device 120 shown in FIG. 1 uses bias fraction 415 shown in FIG. 4 when receiving a request from device 135 shown in FIG. 1. In FIG. 11, at block 1105, storage device 120 shown in FIG. 1 may receive from device 135 shown in FIG. 1 a request to access a chunk of data. At block 1110, mechanism 340 shown in FIG. 3 may determine whether the chunk of data is currently in a device bias mode. If the chunk of data is currently in a device bias mode, the process may end (by providing access to the data to device 135 shown in FIG. 1). Otherwise, at block 1115, mechanism 340 shown in FIG. 3 may decrement bias fraction 420 shown in FIG. 4 for the chunk. As discussed above, in some embodiments of the present disclosure, if the bias fraction is greater than threshold value 430 shown in FIG. 4, mechanism 340 shown in FIG. 3 may only decrement bias fraction 420 shown in FIG. 4; in other embodiments of the present disclosure, mechanism 340 shown in FIG. 3 may decrement bias fraction 420 shown in FIG. 4 without considering threshold value 430 shown in FIG. 4. At block 1120, mechanism 340 shown in FIG. 3 may check to see if bias fraction 420 shown in FIG. 4 is greater than threshold value 430 shown in FIG. 4. If bias fraction 420 shown in FIG. 4 is at least as small as threshold value 430 shown in FIG. 4, then at block 1125, mechanism 340 shown in FIG. 3 may switch the bias mode of the chunk to a device bias mode. In any case, the process may then end (by providing access to the data to device 135 shown in FIG. 1).

[0081] As discussed above, in some embodiments of the present disclosure, even if a chunk of data in storage device 120 shown in FIG. 1 is in a device bias mode, mechanism 340 shown in FIG. 3 may also decrement bias fraction 420 shown in FIG. 4. In such embodiments of the present disclosure, block 1110 may be omitted so that the process always proceeds to block 1115, as indicated by dashed line 1130.

[0082] FIG. 12 shows a flowchart of an exemplary procedure for switching the bias mode of a page in the execution area of storage device 120 shown in FIG. 1 according to an embodiment of the present disclosure. In FIG. 12, at block 1205, storage device 120 shown in FIG. 1 may receive from device 135 shown in FIG. 1 a request to access a chunk of data. At block 1210, mechanism 340 shown in FIG. 3 may identify a second chunk of data in storage device 120 shown in FIG. 1. The first chunk and the second chunk may be part of a region and may be contiguous: that is, the first chunk and the second chunk may share a common boundary or be in contact. At block 1215, mechanism 340 shown in FIG. 3 may switch the bias mode of the second chunk to a device bias mode in anticipation that device 135 shown in FIG. 1 may also wish to access the second chunk.

[0083] FIG. 13 shows a flowchart of an exemplary procedure for a storage device 120 shown in FIG. 1 according to an embodiment of the present disclosure to identify pages in a region for bias mode switching. In FIG. 13, at block 1305, the storage device 120 shown in FIG. 1 may receive a request to access a chunk of data in a region. This chunk may be a cache line, a page, a block, a superblock, or any other defined portion of the region. At block 1310, the mechanism 340 shown in FIG. 3 may identify a second chunk associated with the first chunk such that the second chunk can be switched to a device bias mode to accelerate an expected access by the device 135 shown in FIG. 1.

[0084] FIG. 14 shows a flowchart of an exemplary procedure for a storage device 120 shown in FIG. 1 according to an embodiment of the present disclosure to manage the listening filter 725 shown in FIG. 8. In FIG. 14, at block 1405, the storage device 120 shown in FIG. 1 may receive a request to access a chunk of data from the processor 110 shown in FIG. 1. At block 1410, the mechanism 340 shown in FIG. 3 may update the listening filter 725 shown in FIG. 7 to reflect the requested access to the chunk of data by the processor 110 shown in FIG. 1.

[0085] FIG. 15 shows a flowchart of an exemplary procedure for a storage device 120 shown in FIG. 1 according to an embodiment of the present disclosure to update an entry in the listening filter 725 shown in FIG. 8. FIG. 15 may represent operations performed when the host 105 shown in FIG. 1 requests access to data that has not been previously requested, has not been requested for a period of time, or the host 105 shown in FIG. 1 has previously indicated that the data is no longer cached by the host 105 shown in FIG. 1.

[0086] In FIG. 15, at block 1505, the listening filter cache controller 720 shown in FIG. 7 may add the entry 815 shown in FIG. 8 to the listening filter 725 shown in FIG. 7. Block 1505 may be performed if the listening filter 725 shown in FIG. 7 does not already include the entry 815 shown in FIG. 8 for the chunk under discussion; if the listening filter 725 shown in FIG. 7 already includes the entry 815 shown in FIG. 8 for the chunk under discussion, block 1505 may be skipped, as indicated by the dashed line 1510.

[0087] At block 1515, the listening filter cache controller 720 shown in FIG. 7 may switch a block of data in the storage device 120 shown in FIG. 1 to the host bias mode. If the block of data in the storage device 120 shown in FIG. 1 is already in the host bias mode, block 1515 may be skipped, as indicated by the dashed line 1520. Finally, at block 1520, the listening filter cache controller 720 shown in FIG. 7 may configure the cache 805 shown in FIG. 8 and / or the clean 810 shown in FIG. 8 to indicate whether the host 105 shown in FIG. 1 is currently caching the block of data under discussion and / or whether the host 105 shown in FIG. 1 has modified (or will modify) the data.

[0088] FIG. 16 shows a flowchart of an exemplary procedure for the storage device 120 shown in FIG. 1 to evict an entry from the listening filter 725 shown in FIG. 8 in accordance with an embodiment of the present disclosure. In some embodiments of the present disclosure, when the listening filter 725 shown in FIG. 7 is full (i.e., when the listening filter cache controller 720 shown in FIG. 7 wishes to add the entry 815 shown in FIG. 8 to the listening filter 725 shown in FIG. 7 but there is no free entry 815 shown in FIG. 8 in the listening filter 725 shown in FIG. 7), the exemplary procedure shown in FIG. 16 may be utilized; in other embodiments of the present disclosure, the exemplary procedure shown in FIG. 16 may be utilized whenever the listening filter cache controller 720 shown in FIG. 7 wishes to evict the entry 815 shown in FIG. 8 from the listening filter 725 shown in FIG. 7, even if the listening filter 725 shown in FIG. 7 currently has some available entries 815 shown in FIG. 8.

[0089] In FIG. 16, at block 1605, the snooping filter cache controller 720 shown in FIG. 7 may select an entry 815 shown in FIG. 8 in the snooping filter 725 shown in FIG. 7 for eviction. The snooping filter cache controller 720 shown in FIG. 7 may use any desired eviction policy (e.g., least recently used (LRU) policy, least frequently used (LFU) policy, or any other desired eviction policy) to select the entry 815 shown in FIG. 8 for eviction. At block 1610, the snooping filter cache controller 720 shown in FIG. 7 may determine whether the host 105 shown in FIG. 1 has modified a block of data, which can be determined according to the clean bit 810 shown in FIG. 8. If the host 105 shown in FIG. 1 has modified the data, then at block 1615, the snooping filter cache controller 720 shown in FIG. 7 may send a reverse invalidate request to cause the host 105 shown in FIG. 1 to send the updated data back to the storage device 120 shown in FIG. 1. If the host 105 shown in FIG. 1 has not modified the data, then at block 1620, the snooping filter cache controller 720 shown in FIG. 7 may send an invalidate request to cause the host 105 shown in FIG. 1 to delete any cached copies of the block of data (which may no longer be up-to-date). Finally, at block 1625, the snooping filter cache controller 720 shown in FIG. 7 may evict the entry 815 shown in FIG. 8 from the snooping filter 725 shown in FIG. 7.

[0090] Implicit in blocks 1610, 1615, and 1620 is that the block of data in the storage device 120 shown in FIG. 1 is in the host bias mode and the host 105 shown in FIG. 1 has at least accessed a copy of the block of data from the storage device 120 shown in FIG. 1, which can be determined from the cache 805 shown in FIG. 8. If the block of data in the storage device 120 shown in FIG. 1 is in the device bias mode, then the host 105 does not cache the block of data, let alone modify the block of data, and may skip blocks 1610, 1615, and 1620. Similarly, even if the block of data in the storage device 120 shown in FIG. 1 is in the host bias mode, if the host 105 shown in FIG. 1 has not cached the block of data, then the host 105 may also not have modified the data and may skip blocks 1610, 1615, and 1620.

[0091] FIG. 17 shows a flowchart of an exemplary procedure in which the storage device 120 shown in FIG. 1 processes administrative access to the listening filter 725 shown in FIG. 8 according to an embodiment of the present disclosure. In FIG. 17, at block 1705, the listening filter cache controller 720 shown in FIG. 7 may receive a block-level protocol for accessing the listening filter 725. For example, this block-level protocol request may be issued as a CXL.io request. Finally, at block 1710, the listening filter cache controller 720 shown in FIG. 7 may process the block-level protocol request. Examples of such requests may include a query regarding the number of the entry items 815 shown in FIG. 8 in the listening filter 725 shown in FIG. 7, a query regarding whether the listening filter 725 shown in FIG. 7 includes the entry items 815 of a specific block of data, a query for evicting the entry items 815 shown in FIG. 8 from the listening filter 725 shown in FIG. 7, or a query for resetting some information in the entry items 815 shown in FIG. 8 in the listening filter 725 shown in FIG. 7.

[0092] Some embodiments of the present disclosure are shown in FIGS. 9 to 17. However, those skilled in the art will recognize that there may be other embodiments of the present disclosure by changing the order of the blocks, by omitting blocks, or by including links not shown in the figures. All such variations of the flowchart are considered embodiments of the present disclosure whether or not explicitly described.

[0093] The above FIGS. 4 to 17 illustrate various embodiments of the present disclosure. These embodiments of the present disclosure may be used individually or in combination. For example, the listening filter 725 shown in FIG. 8 may be used in combination with the preview bias mode switching described above with reference to FIGS. 6 and 12 to 13 to determine which pages can be simply invalidated and which pages can be reverse invalidated before the device can process the data located on the device.

[0094] Embodiments of the present disclosure may include a mechanism for managing the bias mode of data in a storage device. The mechanism may include a bias score table for tracking the bias scores of chunks of data, and may switch the bias mode of a chunk of data when the bias score reaches an appropriate threshold value. Alternatively, the mechanism may determine when the device is accessing a chunk of data in a region, and may start changing the bias mode of other chunks of data in the region in the background to accelerate the device's access to the data. Alternatively, the mechanism may include a listening filter that may track chunks of data that have been cached by the host processor and chunks of data that are being modified by the host processor. If a chunk is evicted from the listening filter, the listening filter may then request the host processor to invalidate or reverse-invalidate the cached data from the host processor. Embodiments of the present disclosure provide a technical advantage by accelerating the transition from the host bias mode to the device bias mode (or vice versa) based on how data is accessed from the storage device.

[0095] In a Compute Express Link (CXL) type 2 device with a coherency protocol between the host and the accelerator device, two bias modes are defined for shared memory addresses. When the memory is in the host bias mode, the host is responsible for coherency and the device can query the status before accessing this memory. The host bias mode favors host access, even if the memory may be physically located on the device or the host. In the device bias mode, the device is responsible for its coherency state and can change this memory to the host bias mode after the host accesses the memory. The device bias mode enables fast access to the device from the accelerator without involving the host's attention. Depending on the data processing, the shared address may start in the host bias mode but change to the device bias mode during acceleration and then change back to the host bias mode once the acceleration is complete. When changing from the host bias mode to the device bias mode, the CPU cache may be invalidated to maintain data coherency.

[0096] Cache invalidation may have a negative impact on the overall performance. Efficient cache invalidation may be relevant.

[0097] The CXL protocol may define the concept of memory bias but does not define a specific method for managing the bias. The details of managing the bias (the granularity of the bias table entries, the mechanism for bias mode switching, or the bias mode use cases in the actual acceleration framework) are left to the manufacturer to implement.

[0098] Bias mode switching may include the overhead of the entire coherence protocol. For different applications, the access pattern and memory management granularity may vary. For example, for a large address range that wants to switch from host bias to device bias, flooding the host CPU with invalidate requests at approximately the same time may affect other operations that the CPU is performing at that time. Additionally, if the device knows which lines are cached, blindly invalidating the entire address range may be unnecessary.

[0099] Here, three methods are presented and the three methods can be used for different scenarios.

[0100] 1) Hardware speculative bias switching based on local counters.

[0101] In addition to the basic bias bits for each approximately 4-kilobyte page in the bias table, additional statistics can be saved to track host accesses and device accesses. These statistics can represent the number of times this memory page has been accessed by the host or the device. If the access reaches a threshold, switching the bias of the hot data to favor its user can reduce the overall access overhead. This method is a general page flipping mechanism.

[0102] 2) Background bias switching when flipping sequential regions.

[0103] When performing sequential access to a region that may involve switching between host bias and device bias, bias switching can be performed in the background after some initial pages. This background bias switching can improve the latency for device applications to start earlier, rather than waiting for the entire region to switch from host bias to device bias. This method can provide improved performance for sequential access to a large memory region in one operation.

[0104] 3) Selective bias switching using a listening filter

[0105] When issuing an invalidate when switching from host bias to device bias, the number of invalidate cache lines can have a large impact on CPU performance. Have a listening filter track the lines in the CPU cache that can enable the device to refresh the data more precisely, and unnecessary over-refreshing can be avoided. This method can improve performance when the data sharing between the host and the acceleration device is minimal.

[0106] Bias switching can be performed per cache line (approx. 64 bytes), per host managed device memory (HDM) page (approx. 4 kilobytes), or per region (multiple pages).

[0107] The device can operate normally in the host bias mode. However, the host bias may require the host cache to perform a remote lookup for device memory access. Accessing the host cache may take a significant amount of time, thereby slowing down the device's access to memory. On the other hand, although the device bias has improved the latency of the device's access to memory, the device bias may still cause the coherence state to be disrupted.

[0108] Bias switching can ensure cache coherence compliance to prevent any data inconsistency between the device's HDM data and the host memory data. Before switching from the host bias to the device bias, the device can send an invalidate request to the host to ensure that the host cache does not contain the device memory.

[0109] The fraction-based bias switching is a hardware-assisted method in which the hardware can predict the optimal bias mode for the next device memory access. Each page can have an indicator of 4 bits: bit [0] can identify the bias mode (e.g., 0: host bias; 1: device bias); bits [3:1] can store the bias fraction (default value = 0 after the bias mode changes).

[0110] Whenever the host accesses a page, the fraction can be incremented by 1. Whenever the device accesses a page, the fraction can be decremented by 1. If the fraction reaches the maximum positive value (determined by a certain threshold) and if the device is in the device bias mode, the bias mode can be switched to the host bias mode. If the fraction reaches the maximum negative value (determined by a certain threshold) and if the device is in the host bias mode, the bias mode can be switched to the device bias mode.

[0111] Some applications (e.g., database accelerators) may involve switching the bias across an entire region, which can include thousands of contiguous (or non-contiguous) pages. The bias switching of a page may involve the device invalidating the host cache of the cache line belonging to the page before the page can be safely switched from the host bias to the device bias mode.

[0112] If multiple contiguous pages want to switch their bias, then when the device engine is operating on the current page (in the device bias mode), the bias switching can preview the invalidate request and start sending the invalidate request in the case of switching the bias on the next expected page. The task of preparing the page to be safely switched from the host bias to the device bias can be mainly done in the background without the potential loss of page invalidation.

[0113] In the brute force hardware method, the device can send invalidate requests / reverse invalidate requests for each cache line on the page to be biased and switched. The fine-grained control listening filter on the device can track all cache lines that have been accessed by the host and send invalidates only on those affected cache lines (rather than the entire page). A fixed-size listening filter directory (e.g., 1 million cache lines) can be implemented using a private area of dynamic random access memory (DRAM) that provides fast access to the on-chip listening filter cache.

[0114] The listening filter can implement a data structure and a replacement algorithm where new cache lines can replace existing cache lines. The device can send an invalidate request for the replaced cache line.

[0115] To ensure the normal operation of the switch from host bias to device bias, all shared cache lines resident in the host cache can be invalidated or reverse invalidated before the bias flip.

[0116] For some specific applications, since the output area of the accelerator can start anew, the device can send only invalidate requests to the host.

[0117] Invalidation policy: The device can send invalidate requests to the host for any shared copies.

[0118] Reverse invalidation policy: The device can send a read-ownership request (to invalidate the cache line and obtain the latest data), and then write back to the device-attached area on the dirty copy.

[0119] A smaller direct mapped listening filter cache (e.g., approximately 256 kilobytes) can be implemented to take advantage of the sequential access nature of the affected area.

[0120] When the listening filter is full, the replacement algorithm can select an existing line to be evicted (by sending an invalidate request / reverse invalidate request to the host) to make room for the new line to be installed.

[0121] The hardware engine can read the listening filter table entry from the on-chip cache, send a reverse invalidate request to the host, and prefetch new data from the DRAM, all of these operations can occur approximately simultaneously.

[0122] Supporting hooks for software-initiated bias mode flipping may include: control of the monitoring filter directory and status register (CSR) diagnostic read / write access, software-initiated reverse invalidation startup, and hardware-controlled reverse invalidation completion. For example, the CSR register can be used to record errors, set parameters for requested operations, and provide diagnostic access to the device.

[0123] The following discussion is intended to provide a brief general description of one or more suitable machines in which certain aspects of the present disclosure may be implemented. The one or more machines may be controlled, at least in part, by: input from conventional input devices such as a keyboard, mouse, etc.; and directives received from another machine, interactions with a virtual reality (VR) environment, biometric feedback, or other input signals. As used herein, the term "machine" is intended to broadly encompass a single machine, a virtual machine, or a system of machines, virtual machines, or devices operating together in communication. Exemplary machines include: computing devices such as personal computers, workstations, servers, portable computers, handheld devices, telephones, tablet computers, etc.; and transportation devices such as private or public transportation (e.g., cars, trains, taxis, etc.).

[0124] The one or more machines may include an embedded controller such as a programmable or non-programmable logic device or array, an application-specific integrated circuit (ASIC), an embedded computer, a smart card, and similar devices. The one or more machines may utilize one or more connections to one or more remote machines achieved, for example, via a network interface, a modem, or other communicative coupling. Machines may be interconnected by physical and / or logical networks such as an intranet, the Internet, a local area network, a wide area network, etc. Those skilled in the art will understand that network communication can utilize various wired and / or wireless short-range or long-range carriers and protocols, including radio frequency (RF), satellite, microwave, Institute of Electrical and Electronics Engineers (IEEE) 802.11, Bluetooth®, optical, infrared, cable, laser, etc.

[0125] Embodiments of the present disclosure can be described by reference to or in combination with associated data, which includes functions, programs, data structures, applications, etc. that cause a machine to perform tasks or define abstract data types or low-level hardware contexts when accessed by the machine. The associated data can be stored in, for example, volatile memory and / or non-volatile memory (e.g., RAM, ROM, etc.), or in other storage devices and their associated storage media including hard drives, floppy disks, optical storage, tapes, flash memory, memory sticks, digital video discs, biological storage, etc. The associated data can be delivered via a transmission environment including physical networks and / or logical networks in the form of packets, serial data, parallel data, propagated signals, etc., and can be used in compressed format or encrypted format. The associated data can be used in a distributed environment and can be stored locally and / or remotely for access by a machine.

[0126] Embodiments of the present disclosure can include a tangible non-transitory machine-readable medium including instructions executable by one or more processors, the instructions including instructions for performing the elements of the present disclosure as set forth herein.

[0127] The various operations of the above-described methods can be performed by any suitable means capable of performing the operations (e.g., various hardware components and / or software components, circuits and / or modules). The software can include an ordered list of executable instructions for implementing logical functions and can be implemented in any “processor-readable medium” for use by or in conjunction with an instruction execution system, apparatus, or device (e.g., a single-core processor or a multi-core processor or a system including a processor).

[0128] The blocks or steps of the methods or algorithms and functions described in connection with the embodiments disclosed herein can be implemented directly in hardware, in a software module executed by a processor, or in a combination of the two. If implemented in software, the functions can be stored as one or more instructions or code on a tangible non-transitory computer-readable medium or transmitted over a tangible non-transitory computer-readable medium. The software module can reside in random access memory (RAM), flash memory, read only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, compact disc read only memory (CD ROM), or any other form of storage medium known in the art.

[0129] Since the principles of the present disclosure have been described and illustrated with reference to the illustrated embodiments, it will be appreciated that the illustrated embodiments may be modified in arrangement and detail and combined in any desired manner without departing from such principles. And although the foregoing discussion has focused on specific embodiments, other configurations are also contemplated. Specifically, even though expressions such as "embodiments in accordance with the present disclosure" or similar expressions are used herein, such phrases are intended to generally refer to the possibility of embodiments and are not intended to limit the present disclosure to a specific embodiment configuration. The terms used herein may refer to the same or different embodiments incorporated into other embodiments.

[0130] The foregoing exemplary embodiments should not be considered as limiting the scope of their disclosure. Although several embodiments have been described, those skilled in the art should readily understand that many modifications can be made to these embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims.

[0131] Embodiments of the present disclosure may be extended to the following statements, but are not limited thereto:

[0132] Statement 1. Embodiments of the present disclosure include a storage device, the storage device comprising: a memory for data; a controller for managing access to the data in the memory; and a mechanism for automatically managing a bias mode of a block of data in the memory, the bias mode including one of a host bias mode and a device bias mode.

[0133] Statement 2. Embodiments of the present disclosure include the storage device according to Statement 1, wherein the storage device supports a cache coherence interconnect protocol.

[0134] Statement 3. Embodiments of the present disclosure include the storage device according to Statement 2, wherein the cache coherence interconnect protocol includes a Compute Express Link (CXL) protocol.

[0135] Claim 4. An embodiment of the disclosure includes the storage device according to Claim 1, wherein the mechanism for automatically managing the bias mode of blocks of data in the memory is configured to issue, to the host processor, one of an invalidate request or a reverse invalidate request for the blocks of data in the memory, at least in part based on the bias mode of the blocks of data in the memory being switched to the device bias mode.

[0136] Claim 5. An embodiment of the disclosure includes the storage device according to Claim 1, wherein the blocks of data in the memory include a size.

[0137] Claim 6. An embodiment of the disclosure includes the storage device according to Claim 5, wherein the size of the blocks of data in the memory includes 4 kilobytes.

[0138] Claim 7. An embodiment of the disclosure includes the storage device according to Claim 1, wherein the mechanism for automatically managing the bias mode of blocks of data in the memory includes a bias score of the blocks of data in the memory.

[0139] Claim 8. An embodiment of the disclosure includes the storage device according to Claim 7, wherein the mechanism for automatically managing the bias mode of blocks of data in the memory is configured to adjust the bias score of the blocks of data in the memory, at least in part based on the blocks of data in the memory being accessed by one of the device or the host processor.

[0140] Claim 9. An embodiment of the disclosure includes the storage device according to Claim 8, wherein the storage device includes the device.

[0141] Claim 10. An embodiment of the disclosure includes the storage device according to Claim 8, wherein the device includes an accelerator.

[0142] Claim 11. An embodiment of the disclosure includes the storage device according to Claim 7, wherein the mechanism for automatically managing the bias mode of blocks of data in the memory is configured to change the bias mode of the blocks of data in the memory to the host bias mode, at least in part based on the bias score reaching a first threshold value, and to change the bias mode of the blocks of data in the memory to the device bias mode, at least in part based on the bias score reaching a second threshold value.

[0143] Claim 12. An embodiment of the disclosure includes the storage device according to Claim 7, wherein the mechanism for automatically managing the bias pattern of blocks of data in the memory further includes the bias pattern of blocks of data in the memory.

[0144] Claim 13. An embodiment of the disclosure includes the storage device according to Claim 7, wherein the mechanism for automatically managing the bias pattern of blocks of data in the memory is configured to set the bias score to a preset value upon reset.

[0145] Claim 14. An embodiment of the disclosure includes the storage device according to Claim 13, wherein the preset value of the bias score includes a zero value.

[0146] Claim 15. An embodiment of the disclosure includes the storage device according to Claim 7, wherein the mechanism for automatically managing the bias pattern of blocks of data in the memory is configured to receive a reset request for the bias score of a block of data in the memory.

[0147] Claim 16. An embodiment of the disclosure includes the storage device according to Claim 15, wherein the mechanism for automatically managing the bias pattern of blocks of data in the memory is configured to apply the reset request for the bias score of a block of data in the memory.

[0148] Claim 17. An embodiment of the disclosure includes the storage device according to Claim 7, the storage device further including a second memory for the bias scores of blocks of data in the memory.

[0149] Claim 18. An embodiment of the disclosure includes the storage device according to Claim 17, wherein the memory includes the second memory.

[0150] Claim 19. An embodiment of the disclosure includes the storage device according to Claim 1, wherein the mechanism for automatically managing the bias pattern of blocks of data in the memory is configured to automatically manage the bias pattern of blocks of data in the memory based at least in part on the device accessing a second block of data in the memory.

[0151] Claim 20. An embodiment of the disclosure includes the storage device according to Claim 19, wherein the storage device includes the device.

[0152] Claim 21. An embodiment of the disclosure includes the storage device according to Claim 19, wherein the device includes an accelerator.

[0153] Claim 22. An embodiment of the disclosure includes the storage device according to Claim 19, wherein a mechanism for automatically managing a bias pattern of a block of data in a memory is configured to automatically manage the bias pattern of the block of data in the memory based at least in part on a device bias pattern of a second block of data requested by the device from the memory.

[0154] Claim 23. An embodiment of the disclosure includes the storage device according to Claim 19, wherein: a second block of data in the memory includes a first page; a block of data in the memory includes a second page; and a mechanism for automatically managing a bias pattern of a block of data in the memory is configured to automatically manage the bias pattern of the block of data in the memory based at least in part on the fact that the second page is connected to the first page.

[0155] Claim 24. An embodiment of the disclosure includes the storage device according to Claim 19, wherein: a second block of data in the memory includes a first part of a region of data in the memory; a block of data in the memory includes a second part of a region of data in the memory; and a mechanism for automatically managing a bias pattern of a block of data in the memory is configured to automatically manage the bias pattern of the block of data in the memory based at least in part on the fact that both the first part of the region and the second part of the region are part of the region.

[0156] Claim 25. An embodiment of the disclosure includes the storage device according to Claim 19, wherein a mechanism for automatically managing a bias pattern of a block of data in a memory is configured to automatically manage the bias pattern of the block of data in the memory in the event that the device is expected to access the block of data in the memory.

[0157] Claim 26. An embodiment of the disclosure includes the storage device according to Claim 25, wherein a mechanism for automatically managing a bias pattern of a block of data in a memory is configured to automatically manage the bias pattern of the block of data in the memory before the device accesses the block of data in the memory.

[0158] Claim 27. An embodiment of the disclosure includes the storage device according to Claim 19, wherein the device is configured to access a block of data in the memory before a second set of blocks of data in the memory is in the device bias mode.

[0159] Claim 28. An embodiment of the disclosure includes the storage device according to Claim 19, wherein a mechanism for automatically managing the bias mode of a block of data in the memory is configured to automatically manage the bias mode of a block of data in the memory as a background operation of the storage device.

[0160] Claim 29. An embodiment of the disclosure includes the storage device according to Claim 1, wherein a mechanism for automatically managing the bias mode of a block of data in the memory includes a monitoring filter, and the monitoring filter includes an entry for a block of data in the memory accessible by a host processor.

[0161] Claim 30. An embodiment of the disclosure includes the storage device according to Claim 29, wherein an entry for a block of data in the memory identifies that the block of data in the memory has not been modified by the host processor.

[0162] Claim 31. An embodiment of the disclosure includes the storage device according to Claim 30, wherein a mechanism for automatically managing the bias mode of a block of data in the memory is configured to update an entry for a block of data in the memory read by the host processor at least in part based on the host processor accessing the block of data in the memory.

[0163] Claim 32. An embodiment of the disclosure includes the storage device according to Claim 30, wherein a mechanism for automatically managing the bias mode of a block of data in the memory is configured to invalidate a block of data in the memory relative to a cache of the host processor at least in part based on the monitoring filter evicting an entry for the block of data in the memory.

[0164] Claim 33. An embodiment of the disclosure includes the storage device according to Claim 29, wherein an entry for a block of data in the memory identifies that the block of data in the memory has been modified by the host processor.

[0165] Claim 34. An embodiment of the disclosure includes the storage device according to Claim 33, wherein a mechanism for automatically managing a bias mode of a block of data in the memory is configured to update an entry of a block of data in the memory to be modified by the host processor at least in part based on access by the host processor to the block of data in the memory.

[0166] Claim 35. An embodiment of the disclosure includes the storage device according to Claim 33, wherein a mechanism for automatically managing a bias mode of a block of data in the memory is configured to invalidate a block of data in the memory relative to a cache of the host processor at least in part based on the monitoring filter evicting an entry of a block of data in the memory.

[0167] Claim 36. An embodiment of the disclosure includes the storage device according to Claim 29, wherein the monitoring filter includes an eviction policy.

[0168] Claim 37. An embodiment of the disclosure includes the storage device according to Claim 36, wherein the eviction policy of the monitoring filter is different from a second eviction policy of a cache of the host processor.

[0169] Claim 38. An embodiment of the disclosure includes the storage device according to Claim 29, the storage device further including a second memory for the monitoring filter.

[0170] Claim 39. An embodiment of the disclosure includes the storage device according to Claim 38, wherein the second memory includes dynamic random access memory (DRAM).

[0171] Claim 40. An embodiment of the disclosure includes the storage device according to Claim 38, wherein the second memory includes one of a volatile second memory or a non-volatile second memory.

[0172] Claim 41. An embodiment of the disclosure includes the storage device according to Claim 38, wherein: the monitoring filter includes a first part and a second part; the second memory includes the first part of the monitoring filter; and the memory includes the second part of the monitoring filter.

[0173] Claim 42. An embodiment of the disclosure includes a storage device according to Claim 38, wherein the mechanism for automatically managing the bias mode of blocks of data in the memory further includes a snoop filter cache controller for managing the snoop filter.

[0174] Claim 43. An embodiment of the disclosure includes a storage device according to Claim 42, wherein the snoop filter cache controller is configured to add an entry for a block of data in the memory to the snoop filter and evict an entry for a block of data in the memory from the snoop filter.

[0175] Claim 44. An embodiment of the disclosure includes a storage device according to Claim 42, wherein the snoop filter cache controller is configured to issue an invalidate request or a reverse invalidate request to the host processor at least in part based on evicting an entry for a block of data in the memory from the snoop filter.

[0176] Claim 45. An embodiment of the disclosure includes a storage device according to Claim 29, wherein the storage device supports a cache coherence interconnect protocol, the cache coherence interconnect protocol includes a block-level protocol and a byte-level protocol, and the block-level protocol supports access to the snoop filter.

[0177] Claim 46. An embodiment of the disclosure includes a storage device according to Claim 45, wherein the block-level protocol supports application access to the snoop filter.

[0178] Claim 47. An embodiment of the disclosure includes a method, the method comprising: receiving, at a storage device, a request to access a block of data in a memory of the storage device, the request being received from a source; identifying a bias score for a block of data in a memory of the storage device; and adjusting, at least in part based on the source of the request, the bias score for a block of data in a memory of the storage device.

[0179] Claim 48. An embodiment of the disclosure includes a method according to Claim 47, wherein receiving, at a storage device, the request to access a block of data in a memory of the storage device includes receiving, at the storage device, the request to access a block of data in a memory of the storage device, the request being received from a host processor.

[0180] Claim 49. An embodiment of the disclosure includes the method according to Claim 48, wherein adjusting the bias score of a block of data in the memory of the storage device based at least in part on the requested source includes increasing the bias score of a block of data in the memory of the storage device based at least in part on the source including a host processor.

[0181] Claim 50. An embodiment of the disclosure includes the method according to Claim 49, wherein increasing the bias score of a block of data in the memory of the storage device based at least in part on the source including a host processor includes determining a bias pattern of a block of data in the memory of the storage device including a device bias pattern.

[0182] Claim 51. An embodiment of the disclosure includes the method according to Claim 50, the method further including switching the bias pattern of a block of data in the memory of the storage device to a host bias pattern based at least in part on the block of data in the memory of the storage device being in a device bias pattern.

[0183] Claim 52. An embodiment of the disclosure includes the method according to Claim 49, the method further including switching the bias pattern of a block of data in the memory of the storage device to a host bias pattern based at least in part on the bias score exceeding a threshold value.

[0184] Claim 53. An embodiment of the disclosure includes the method according to Claim 49, wherein increasing the bias score of a block of data in the memory of the storage device based at least in part on the source including a host processor includes increasing the bias score of a block of data in the memory of the storage device based at least in part on the source including a host processor and the bias score being less than a threshold value.

[0185] Claim 54. An embodiment of the disclosure includes the method according to Claim 48, wherein adjusting the bias score of a block of data in the memory of the storage device based at least in part on the requested source includes: determining a bias pattern of a block of data in the memory of the storage device including a host bias pattern; and keeping the bias score of a block of data in the memory of the storage device unchanged based at least in part on the source including a host processor and the bias pattern including a host bias pattern.

[0186] Claim 55. An embodiment of the disclosure includes the method according to Claim 47, wherein receiving, at a storage device, the request to access a block of data in a memory of the storage device includes receiving, at the storage device, the request to access a block of data in a memory of the storage device, and the request is received from a device.

[0187] Claim 56. An embodiment of the disclosure includes the method according to Claim 55, wherein the storage device includes the device.

[0188] Claim 57. An embodiment of the disclosure includes the method according to Claim 55, wherein the device includes an accelerator.

[0189] Claim 58. An embodiment of the disclosure includes the method according to Claim 55, wherein adjusting a bias score of a block of data in a memory of a storage device based at least in part on a source of the request includes decreasing the bias score of a block of data in a memory of a storage device based at least in part on the source including the device.

[0190] Claim 59. An embodiment of the disclosure includes the method according to Claim 58, wherein decreasing the bias score of a block of data in a memory of a storage device based at least in part on the source including the device includes determining a bias pattern of a block of data in a memory of a storage device including a host bias pattern.

[0191] Claim 60. An embodiment of the disclosure includes the method according to Claim 59, the method further including switching a bias pattern of a block of data in a memory of a storage device to a device bias pattern based at least in part on the block of data in the memory of the storage device being in a host bias pattern.

[0192] Claim 61. An embodiment of the disclosure includes the method according to Claim 58, the method further including switching a bias pattern of a block of data in a memory of a storage device to a device bias pattern based at least in part on the bias score exceeding a threshold value.

[0193] Claim 62. An embodiment of the disclosure includes the method according to Claim 58, wherein decreasing the bias score of a block of data in a memory of a storage device based at least in part on the source including the device includes decreasing the bias score of a block of data in a memory of a storage device based at least in part on the source including the device and the bias score being greater than a threshold value.

[0194] Claim 63. An embodiment of the disclosure includes the method according to Claim 55, wherein adjusting a bias fraction of a block of data in a memory of a storage device based at least in part on the requested source includes: determining a bias pattern of a block of data in a memory of a storage device including a device bias pattern; and keeping the bias fraction of the block of data in the memory of the storage device unchanged based at least in part on the source including the device and the bias pattern including the device bias pattern.

[0195] Claim 64. An embodiment of the disclosure includes a method, the method including: receiving, at a storage device, a request to access a first block of data in a memory of the storage device, the request received from a device; identifying a second block of data in a memory of the storage device; and switching a bias pattern of the second block of data in the memory of the storage device to a device bias pattern.

[0196] Claim 65. An embodiment of the disclosure includes the method according to Claim 64, wherein the storage device includes the device.

[0197] Claim 66. An embodiment of the disclosure includes the method according to Claim 64, wherein the device includes an accelerator.

[0198] Claim 67. An embodiment of the disclosure includes the method according to Claim 64, wherein the request includes a bias request to switch a bias pattern of a first block of data in a memory of the storage device to a device bias pattern.

[0199] Claim 68. An embodiment of the disclosure includes the method according to Claim 64, wherein: receiving, at a storage device, a request to access a first block of data in a memory of the storage device includes receiving, at the storage device, a request to access a first page of data in a memory of the storage device; identifying a second block of data in a memory of the storage device includes identifying a second page of data in a memory of the storage device.

[0200] Claim 69. An embodiment of the disclosure includes the method according to Claim 68, wherein identifying a second page of data in the memory of the storage device includes identifying the second page of data in the memory of the storage device as being contiguous with a first page of data in the memory of the storage device.

[0201] Claim 70. An embodiment of the disclosure includes the method according to Claim 64, wherein: Receiving, at the storage device, a request to access a first set of blocks of data in the memory of the storage device includes receiving, at the storage device, a request to access a first portion of a region of data in the memory of the storage device; Identifying a second set of blocks of data in the memory of the storage device includes identifying a second portion of a region of data in the memory of the storage device.

[0202] Claim 71. An embodiment of the disclosure includes the method according to Claim 70, wherein identifying a second portion of a region of data in the memory of the storage device includes identifying the second portion of the region of data in the memory of the storage device as being contiguous with a first portion of the region of data in the memory of the storage device.

[0203] Claim 72. An embodiment of the disclosure includes the method according to Claim 64, wherein switching a bias mode of a second set of blocks of data in the memory of the storage device to a device bias mode includes switching the bias mode of the second set of blocks of data in the memory of the storage device to the device bias mode in the event that the device is expected to access the second set of blocks of data in the memory of the storage device.

[0204] Claim 73. An embodiment of the disclosure includes the method according to Claim 64, wherein the device is configured to access a first set of blocks of data in the memory of the storage device before the second set of blocks of data in the memory of the storage device is in the device bias mode.

[0205] Claim 74. An embodiment of the disclosure includes the method according to Claim 64, wherein switching a bias mode of a second set of blocks of data in the memory of the storage device to a device bias mode includes switching the bias mode of the second set of blocks of data in the memory of the storage device to the device bias mode as a background operation of the storage device.

[0206] Claim 75. An embodiment of the disclosure includes a method, the method including: At a storage device, a host processor receives a request to access a block of data in a memory of the storage device; and At least partially based on the request from the host processor, an entry for a block of data in the memory of the storage device in a listening filter of the storage device is updated.

[0207] Claim 76. An embodiment of the present disclosure includes the method according to Claim 75, wherein the listening filter is stored in a second memory of the storage device.

[0208] Claim 77. An embodiment of the present disclosure includes the method according to Claim 76, wherein the second memory of the storage device includes dynamic random access memory (DRAM).

[0209] Claim 78. An embodiment of the present disclosure includes the method according to Claim 76, wherein the second memory includes one of a volatile second memory or a non-volatile second memory.

[0210] Claim 79. An embodiment of the present disclosure includes the method according to Claim 76, wherein: The listening filter includes a first part and a second part; The second memory of the storage device includes the first part of the listening filter; and The memory of the storage device includes the second part of the listening filter.

[0211] Claim 80. An embodiment of the present disclosure includes the method according to Claim 75, wherein updating an entry for a block of data in the memory of the storage device in a listening filter of the storage device at least partially based on the request from the host processor includes adding an entry for a block of data in the memory of the storage device in the listening filter of the storage device at least partially based on the listening filter not including an entry for the block of data in the memory of the storage device.

[0212] Claim 81. An embodiment of the present disclosure includes the method according to Claim 80, wherein updating an entry for a block of data in the memory of the storage device in a listening filter of the storage device at least partially based on the request from the host processor further includes switching a bias mode of a block of data in the memory of the storage device to a host bias mode.

[0213] Claim 82. An embodiment of the disclosure includes the method according to Claim 75, wherein the request includes an identifier identifying a block of data in the storage of the storage device that the host processor does not want to modify.

[0214] Claim 83. An embodiment of the disclosure includes the method according to Claim 82, wherein updating an entry in the listening filter of the storage device for a block of data in the storage of the storage device based at least in part on a request from the host processor includes updating an entry in the listening filter of the storage of the storage device indicating that a block of data in the storage of the storage device has not been modified by the host processor.

[0215] Claim 84. An embodiment of the disclosure includes the method according to Claim 75, wherein the request includes an identifier identifying a block of data in the storage of the storage device that the host processor wants to modify.

[0216] Claim 85. An embodiment of the disclosure includes the method according to Claim 84, wherein updating an entry in the listening filter of the storage device for a block of data in the storage of the storage device based at least in part on a request from the host processor includes updating an entry in the listening filter of the storage of the storage device indicating that a block of data in the storage of the storage device has been modified by the host processor.

[0217] Claim 86. An embodiment of the disclosure includes the method according to Claim 75, the method further including evicting an entry in the listening filter of the storage device.

[0218] Claim 87. An embodiment of the disclosure includes the method according to Claim 86, wherein evicting an entry in the listening filter of the storage device includes evicting an entry in the listening filter of the storage device based at least in part on an eviction policy of the listening filter.

[0219] Claim 88. An embodiment of the disclosure includes the method according to Claim 87, wherein the eviction policy of the listening filter is different from a second eviction policy of a cache of the host processor.

[0220] Claim 89. An embodiment of the disclosure includes the method according to Claim 86, wherein evicting an entry in the listening filter of the storage device includes sending an invalidation request for a block of data in the storage of the storage device from the storage device to the host processor.

[0221] Claim 90. An embodiment of the disclosure includes the method according to Claim 89, wherein sending an invalidation request for a block of data in the memory of the storage device from the storage device to the host processor includes sending the invalidation request for the block of data in the memory of the storage device from the storage device to the host processor at least in part based on an entry in the snooping filter indicating that the block of data in the memory of the storage device has not been modified by the host processor.

[0222] Claim 91. An embodiment of the disclosure includes the method according to Claim 86, wherein evicting an entry in the snooping filter of the storage device includes sending a reverse invalidation request for a block of data in the memory of the storage device from the storage device to the host processor.

[0223] Claim 92. An embodiment of the disclosure includes the method according to Claim 91, wherein sending a reverse invalidation request for a block of data in the memory of the storage device from the storage device to the host processor includes sending the reverse invalidation request for the block of data in the memory of the storage device from the storage device to the host processor at least in part based on an entry in the snooping filter indicating that the block of data in the memory of the storage device has been modified by the host processor.

[0224] Claim 93. An embodiment of the disclosure includes the method according to Claim 75, the method further comprising: receiving, at the storage device, a block-level protocol request to access the snooping filter; and processing the block-level protocol request, wherein the storage device supports a cache coherence interconnect protocol that includes a block-level protocol and a byte-level protocol.

[0225] Claim 94. An embodiment of the disclosure includes an article that includes a non-transitory storage medium having instructions stored thereon that, when executed by a machine, cause: receiving, at the storage device, a request to access a block of data in the memory of the storage device, the request being received from a source; identifying a bias score for the block of data in the memory of the storage device; and adjusting the bias score for the block of data in the memory of the storage device at least in part based on the source of the request.

[0226] Claim 95. An embodiment of the disclosure includes an article according to Claim 94, wherein receiving, at a storage device, a request to access a block of data in a memory of the storage device includes receiving, at the storage device, the request to access a block of data in a memory of the storage device, the request being received from a host processor.

[0227] Claim 96. An embodiment of the disclosure includes an article according to Claim 95, wherein adjusting a bias score of a block of data in a memory of a storage device based at least in part on a source of the request includes incrementing a bias score of a block of data in a memory of a storage device based at least in part on the source including a host processor.

[0228] Claim 97. An embodiment of the disclosure includes an article according to Claim 96, wherein incrementing a bias score of a block of data in a memory of a storage device based at least in part on the source including a host processor includes determining a bias pattern of a block of data in a memory of a storage device including a device bias pattern.

[0229] Claim 98. An embodiment of the disclosure includes an article according to Claim 97, wherein the non-transitory storage medium has additional instructions stored thereon, the additional instructions, when executed by the machine, cause a bias pattern of a block of data in a memory of a storage device to be switched to a host bias pattern.

[0230] Claim 99. An embodiment of the disclosure includes an article according to Claim 98, wherein switching a bias pattern of a block of data in a memory of a storage device to a host bias pattern includes switching a bias pattern of a block of data in a memory of a storage device to a host bias pattern based at least in part on a bias score exceeding a threshold value.

[0231] Claim 100. An embodiment of the disclosure includes an article according to Claim 96, wherein incrementing a bias score of a block of data in a memory of a storage device based at least in part on the source including a host processor includes incrementing a bias score of a block of data in a memory of a storage device based at least in part on the source including a host processor and a bias score being less than a threshold value.

[0232] Claim 101. An embodiment of the disclosure includes an article according to Claim 95, wherein adjusting a bias score of a block of data in a memory of a storage device based at least in part on the requested source includes: Determining that a bias pattern of a block of data in a memory of a storage device includes a host bias pattern; and Keeping the bias score of a block of data in a memory of the storage device unchanged based at least in part on the source including a host processor and the bias pattern including a host bias pattern.

[0233] Claim 102. An embodiment of the disclosure includes an article according to Claim 94, wherein receiving, at a storage device, the request to access a block of data in a memory of the storage device includes receiving, at the storage device, the request to access a block of data in a memory of the storage device, the request being received from a device.

[0234] Claim 103. An embodiment of the disclosure includes an article according to Claim 102, wherein the storage device includes the device.

[0235] Claim 104. An embodiment of the disclosure includes an article according to Claim 102, wherein the device includes an accelerator.

[0236] Claim 105. An embodiment of the disclosure includes an article according to Claim 102, wherein adjusting a bias score of a block of data in a memory of a storage device based at least in part on the requested source includes decreasing the bias score of a block of data in a memory of the storage device based at least in part on the source including the device.

[0237] Claim 106. An embodiment of the disclosure includes an article according to Claim 105, wherein decreasing the bias score of a block of data in a memory of the storage device based at least in part on the source including the device includes determining that a bias pattern of a block of data in a memory of the storage device includes a host bias pattern.

[0238] Claim 107. An embodiment of the disclosure includes an article according to Claim 106, wherein the non-transitory storage medium has additional instructions stored thereon, the additional instructions, when executed by the machine, cause a bias pattern of a block of data in a memory of the storage device to be switched to a device bias pattern.

[0239] Claim 108. An embodiment of the disclosure includes an article according to Claim 107, wherein switching a bias mode of a block of data in a memory of a storage device to a device bias mode includes switching the bias mode of the block of data in the memory of the storage device to the device bias mode based at least in part on a bias fraction exceeding a threshold value.

[0240] Claim 109. An embodiment of the disclosure includes an article according to Claim 105, wherein decreasing a bias fraction of a block of data in a memory of a storage device based at least in part on the source including the device includes decreasing the bias fraction of the block of data in the memory of the storage device based at least in part on the source including the device and the bias fraction being greater than a threshold value.

[0241] Claim 110. An embodiment of the disclosure includes an article according to Claim 102, wherein adjusting a bias fraction of a block of data in a memory of a storage device based at least in part on the requested source includes: determining that a bias mode of a block of data in a memory of a storage device includes a device bias mode; and keeping the bias fraction of the block of data in the memory of the storage device unchanged based at least in part on the source including the device and the bias mode including the device bias mode.

[0242] Claim 111. An embodiment of the disclosure includes an article, the article including: receiving, at a storage device, a request to access a first block of data in a memory of the storage device, the request being received from a device; identifying a second block of data in the memory of the storage device; and switching a bias mode of the second block of data in the memory of the storage device to a device bias mode.

[0243] Claim 112. An embodiment of the disclosure includes an article according to Claim 111, wherein the storage device includes the device.

[0244] Claim 113. An embodiment of the disclosure includes an article according to Claim 111, wherein the device includes an accelerator.

[0245] Claim 114. An embodiment of the disclosure includes an article according to Claim 111, wherein the request includes a bias request to switch a bias mode of a first block of data in a memory of the storage device to a device bias mode.

[0246] Claim 115. An embodiment of the disclosure includes an article according to Claim 111, wherein: Receiving a request to access a first set of blocks of data in a storage device's memory at the storage device includes receiving a request to access a first page of data in the storage device's memory at the storage device; Identifying a second set of blocks of data in the storage device's memory includes identifying a second page of data in the storage device's memory.

[0247] Claim 116. An embodiment of the disclosure includes an article according to Claim 115, wherein identifying a second page of data in the storage device's memory includes identifying the second page of data in the storage device's memory as being contiguous with the first page of data in the storage device's memory.

[0248] Claim 117. An embodiment of the disclosure includes an article according to Claim 111, wherein: Receiving a request to access a first set of blocks of data in a storage device's memory at the storage device includes receiving a request to access a first portion of a region of data in the storage device's memory at the storage device; Identifying a second set of blocks of data in the storage device's memory includes identifying a second portion of a region of data in the storage device's memory.

[0249] Claim 118. An embodiment of the disclosure includes an article according to Claim 117, wherein identifying a second portion of a region of data in the storage device's memory includes identifying the second portion of the region of data in the storage device's memory as being contiguous with the first portion of the region of data in the storage device's memory.

[0250] Claim 119. An embodiment of the disclosure includes an article according to Claim 111, wherein switching the bias mode of a second set of blocks of data in the storage device's memory to a device bias mode includes switching the bias mode of the second set of blocks of data in the storage device's memory to the device bias mode in the event that the device is expected to access the second set of blocks of data in the storage device's memory.

[0251] Claim 120. An embodiment of the disclosure includes an article according to Claim 111, wherein the device is configured to access a first set of blocks of data in the storage device's memory before the second set of blocks of data in the storage device's memory is in the device bias mode.

[0252] Claim 121. An embodiment of the disclosure includes an article according to Claim 111, wherein switching a bias mode of a second set of blocks of data in a memory of a storage device to a device bias mode includes switching the bias mode of the second set of blocks of data in the memory of the storage device to the device bias mode as a background operation of the storage device.

[0253] Claim 122. An embodiment of the disclosure includes an article, the article including: receiving, at a storage device, a request from a host processor to access a block of data in a memory of the storage device; and updating an entry for a block of data in a memory of the storage device in a monitoring filter of the storage device at least in part based on the request from the host processor.

[0254] Claim 123. An embodiment of the disclosure includes an article according to Claim 122, wherein the monitoring filter is stored in a second memory of the storage device.

[0255] Claim 124. An embodiment of the disclosure includes an article according to Claim 123, wherein the second memory of the storage device includes a dynamic random access memory (DRAM).

[0256] Claim 125. An embodiment of the disclosure includes an article according to Claim 123, wherein the second memory includes one of a volatile second memory or a non-volatile second memory.

[0257] Claim 126. An embodiment of the disclosure includes an article according to Claim 123, wherein: the monitoring filter includes a first part and a second part; the second memory of the storage device includes the first part of the monitoring filter; and the memory of the storage device includes the second part of the monitoring filter.

[0258] Claim 127. An embodiment of the disclosure includes an article according to Claim 122, wherein updating an entry for a block of data in a memory of the storage device in a monitoring filter of the storage device at least in part based on the request from the host processor includes adding an entry for a block of data in a memory of the storage device in the monitoring filter of the storage device at least in part based on the monitoring filter not including the entry for the block of data in the memory of the storage device.

[0259] Claim 128. An embodiment of the disclosure includes an article according to Claim 127, wherein the listening filter for the storage device is updated for entries of chunks of data in the storage of the storage device, at least in part based on a request from a host processor, and further includes switching a bias mode of a chunk of data in the storage of the storage device to a host bias mode.

[0260] Claim 129. An embodiment of the disclosure includes an article according to Claim 122, wherein the request includes an identifier identifying that the host processor does not desire to modify a chunk of data in the storage of the storage device.

[0261] Claim 130. An embodiment of the disclosure includes an article according to Claim 129, wherein the listening filter for the storage device is updated for entries of chunks of data in the storage of the storage device, at least in part based on a request from a host processor, and includes updating an entry in the listening filter of the storage of the storage device indicating that a chunk of data in the storage of the storage device has not been modified by the host processor.

[0262] Claim 131. An embodiment of the disclosure includes an article according to Claim 122, wherein the request includes an identifier identifying that the host processor desires to modify a chunk of data in the storage of the storage device.

[0263] Claim 132. An embodiment of the disclosure includes an article according to Claim 131, wherein the listening filter for the storage device is updated for entries of chunks of data in the storage of the storage device, at least in part based on a request from a host processor, and includes updating an entry in the listening filter of the storage of the storage device indicating that a chunk of data in the storage of the storage device has been modified by the host processor.

[0264] Claim 133. An embodiment of the disclosure includes an article according to Claim 122, wherein the non-transitory storage medium has additional instructions stored thereon, the additional instructions causing, when executed by the machine, entries in the listening filter of the storage device to be evicted.

[0265] Claim 134. An embodiment of the disclosure includes an article according to Claim 133, wherein evicting entries in the listening filter of the storage device includes evicting entries in the listening filter of the storage device, at least in part based on an eviction policy of the listening filter.

[0266] Claim 135. An embodiment of the disclosure includes an article according to Claim 134, wherein an eviction policy of the snooping filter is different from a second eviction policy of a cache of the host processor.

[0267] Claim 136. An embodiment of the disclosure includes an article according to Claim 133, wherein an entry in the snooping filter of the eviction storage device includes sending an invalidate request for a block of data in a storage of the storage device from the storage device to the host processor.

[0268] Claim 137. An embodiment of the disclosure includes an article according to Claim 136, wherein sending an invalidate request for a block of data in a storage of the storage device from the storage device to the host processor includes sending an invalidate request for a block of data in a storage of the storage device from the storage device to the host processor at least in part based on an entry in the snooping filter for the block of data in the storage of the storage device indicating that the block of data in the storage of the storage device has not been modified by the host processor.

[0269] Claim 138. An embodiment of the disclosure includes an article according to Claim 133, wherein an entry in the snooping filter of the eviction storage device includes sending a reverse invalidate request for a block of data in a storage of the storage device from the storage device to the host processor.

[0270] Claim 139. An embodiment of the disclosure includes an article according to Claim 138, wherein sending a reverse invalidate request for a block of data in a storage of the storage device from the storage device to the host processor includes sending a reverse invalidate request for a block of data in a storage of the storage device from the storage device to the host processor at least in part based on an entry in the snooping filter for the block of data in the storage of the storage device indicating that the block of data in the storage of the storage device has been modified by the host processor.

[0271] Claim 140. An embodiment of the disclosure includes an article according to Claim 122, wherein the non-transitory storage medium has additional instructions stored thereon, the additional instructions when executed by the machine cause: receiving at the storage device a block-level protocol request to access the snooping filter; and processing the block-level protocol request, wherein the storage device supports a cache coherence interconnect protocol, the cache coherence interconnect protocol including a block-level protocol and a byte-level protocol.

[0272] Therefore, considering the various arrangements of the embodiments described herein, this detailed description and the accompanying materials are intended to be illustrative only and should not be regarded as limiting the scope of the disclosure. Accordingly, the claimed disclosure is all such modifications that may fall within the scope and spirit of the following claims and their equivalents.

[0273] 105: Machine / Host 110: Processor 115, 335: Memory 120: Storage device 125, 715: Memory controller 130: Device driver 135: Accelerator / Device 205: Clock 210: Network connector 215: Bus 220: User interface 225: Input / Output (I / O) engine 305: Host Interface Layer (HIL) 310: Controller 315-1, 315-2, 315-3, 315-4, 315-5, 315-6, 315-7, 315-8: Flash memory chips 320-1, 320-2, 320-3, 320-4: Channels 325: Flash memory controller 330: Translation table / Translation layer 340: Mechanism / Device coherence engine 405: Bias fraction table 410: Block ID / Row ID 415: Bias fraction / fraction 420: Bias mode / bias fraction 425-1, 425-2, 425-3, 815-1, 815-2, 815-3: Table entries 430, 435: Threshold values 505: Bias mode switching / operation 605-1, 605-2, 605-3, 605-4, 605-5, 605-6, 605-7, 605-8: Pages 610, 615, 620, 625: Operations 630: Grouping 705: Control and Status Register (CSR) 710: Device Cache 720: Monitoring Filter Cache Controller 725: Monitoring Filter 730: Monitoring Filter Memory 735: HDM Memory 805: Cached 810: Clean / Row 905, 910, 915, 1005, 1010, 1015, 1020, 1025, 1105, 1110, 1115, 1120, 1125, 1205, 1210, 1215, 1305, 1310, 1405, 1410, 1505, 1515, 1525, 1605, 1610, 1615, 1620, 1625, 1705, 1710: Blocks 1030, 1130, 1510, 1520: Dashed Lines

Claims

1. A storage device, comprising: Storage media for data; A controller for managing access to the data in the storage medium; And a mechanism for storing and managing, at least in part, the bias score and bias mode of blocks of data in the storage medium based on the bias score, the bias mode including one of a host bias mode and a device bias mode, the bias score including a multi-bit counter for tracking access to the blocks of data in the storage medium by a host processor or device.

2. The storage device as claimed in claim 1, wherein the mechanism for storing and managing the bias mode of the block of data in the storage medium is configured to issue an invalid request or a reverse invalid request to the host processor for the block of data in the storage medium at least in part based on the bias mode of the block of data in the storage medium being switched to the device bias mode.

3. The storage device as claimed in claim 1, wherein the mechanism for storing and managing the bias fraction and bias mode of the blocks of data in the storage medium includes the bias fraction and bias mode of the blocks of data in the storage medium.

4. The storage device as claimed in claim 3, wherein the mechanism for storing and managing the bias fraction and bias mode of the blocks of data in the storage medium is configured to adjust the bias fraction of the blocks of data in the storage medium based at least in part on access to the blocks of data in the storage medium by either the device or the host processor.

5. The storage device of claim 3, wherein the mechanism for storing and managing the bias fraction and bias mode of the blocks of data in the storage medium is configured to change the bias mode of the blocks of data in the storage medium to the host bias mode at least partially based on the bias fraction reaching a first threshold and to change the bias mode of the blocks of data in the storage medium to the device bias mode at least partially based on the bias fraction reaching a second threshold.

6. The storage device as claimed in claim 1, wherein the mechanism for storing and managing the bias fraction and bias mode of the blocks of data in the storage medium is configured to store and manage the bias fraction and bias mode of the blocks of data in the storage medium at least in part based on the device accessing a second block of data in the storage medium.

7. The storage device as claimed in claim 6, wherein: The second block of the data in the storage medium includes a first page; the block of the data in the storage medium includes a second page; the mechanism for storing and managing the bias fraction and the bias mode of the block of the data in the storage medium is further configured to store and manage the second bias fraction and the second bias mode of the second block of the data in the storage medium. The mechanism for storing and managing the bias fraction and bias mode of the blocks of data in the storage medium is configured to store and manage the bias fraction and bias mode of the blocks of data in the storage medium based at least in part on the fact that the second page is connected to the first page.

8. The storage device of claim 1, wherein the mechanism for storing and managing the bias fraction and bias mode of the blocks of data in the storage medium includes a listener filter, the listener filter including entries for the blocks of data in the storage medium accessed by the host processor, the listener filter further including a cache controller.

9. The storage device as claimed in claim 8, wherein: The entry for the block of data in the storage medium identifies that the block of data in the storage medium has not been modified by the host processor; The mechanism for storing and managing the bias mode of the blocks of data in the storage medium is configured to invalidate the blocks of data in the storage medium relative to the host processor, at least in part, based on the evicting of the entries for the blocks of data in the storage medium by the listening filter.

10. The storage device as claimed in claim 8, wherein: The entry for the block of data in the storage medium identifies that the block of data in the storage medium has been modified by the host processor; The mechanism for storing and managing the bias fraction and bias mode of the blocks of data in the storage medium is configured to invalidate the blocks of data in the storage medium relative to the host processor cache, at least in part, by evictring the entries for the blocks of data in the storage medium for the blocks of data in the storage medium based on the listening filter.

11. The storage device as claimed in claim 1, wherein the multi-bit counter comprises at least two bits.

12. A method for managing bias mode switching, comprising: A request to access a block of data in the storage medium of the storage device is received at the storage device, the request being received from a source; a bias fraction of the block of data in the storage medium of the storage device is identified, the bias fraction including a multi-bit counter for tracking access to the block of data in the storage medium by a host processor or device, the storage medium of the storage device also storing a bias pattern of the block of data, the bias pattern being at least partially based on the bias fraction; And adjust the bias fraction of the blocks of data in the storage medium of the storage device, at least in part, based on the source of the request.

13. The method as described in request item 12, wherein: Receiving a request at the storage device to access a block of data in the storage medium of the storage device includes receiving the request at the storage device to access a block of data in the storage medium of the storage device, the request being received from the host processor; and adjusting the bias fraction of the block of data in the storage medium of the storage device based at least in part on the source of the request includes increasing the bias fraction of the block of data in the storage medium of the storage device based at least in part on the source including the host processor.

14. The method of claim 13 further includes switching the bias mode of the block of data in the storage medium of the storage device to host bias mode based at least in part on the bias fraction exceeding a threshold value.

15. The method as described in request item 12, wherein: Receiving a request at the storage device to access a block of data in the storage medium of the storage device includes receiving the request at the storage device to access a block of data in the storage medium of the storage device, the request being received from the device; and adjusting the bias fraction of the block of data in the storage medium of the storage device based at least in part on the source of the request includes decreasing the bias fraction of the block of data in the storage medium of the storage device based at least in part on the source including the device.

16. The method of claim 15 further includes switching the bias mode of the block of data in the storage medium of the storage device to a device bias mode based at least in part on the bias fraction exceeding a threshold value.

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