Semiconductor devices and methods for manufacturing semiconductor devices

Abstract

The semiconductor device (1) comprises: a Si substrate (101); a back electrode (304) disposed below the Si substrate (101); a SiC layer (102) disposed above the Si substrate (101); a nitride semiconductor layer (103) disposed above the SiC layer (102); a source electrode (201) and a drain electrode (202) disposed above the nitride semiconductor layer (103); a gate electrode (203) in contact with the nitride semiconductor layer (103); and a device with a back electrode (304) disposed below the Si substrate (101); a SiC layer (102) disposed above the SiC layer (102); a gate electrode (203) in contact with the nitride semiconductor layer (103); and a device with a back electrode (304) disposed below the Si substrate (101); a SiC layer (102) disposed above the SiC layer (102); a SiC layer (102) disposed above the SiC layer (102); a SiC layer (103) disposed above the SiC layer (103); a SiC layer (102 ... The intermediate layer (105) is located in the opening (104) between the SiC layer (102) and the nitride semiconductor layer (103); a metal layer (106) is disposed above the opening (104) to cover the intermediate layer (105); and a conductor (303) is disposed inside the through hole (301) that penetrates the intermediate layer (105) and the Si substrate (101) and electrically connected to the back electrode (304) and the metal layer (106). The intermediate layer (105) is a metal nitride layer or a silicon oxide layer.

Description

Semiconductor devices and methods for manufacturing semiconductor devices Invention Field This disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices, and in particular to nitride semiconductor devices using group III nitride semiconductors and methods for manufacturing the same. Background of the Invention Nitride semiconductor devices using group III nitride semiconductors such as gallium nitride (GaN) or aluminum gallium nitride (AlGaN) exhibit high insulation breakdown voltages due to the wide bandgap of the material. Furthermore, heterostructures such as AlGaN / GaN can be easily formed in semiconductor devices using group III nitride semiconductors. In AlGaN / GaN heterostructures, a high concentration of electron channels (two-dimensional electron gas; 2DEG) is formed on the GaN layer side of the AlGaN / GaN interface due to the difference in piezoelectric polarization caused by the difference in lattice constants between the materials and the difference in spontaneous polarization between AlGaN and GaN. Nitride semiconductor devices utilizing these two-dimensional electron gas channels have higher electron saturation velocity and insulation resistance, as well as higher thermal conductivity, and are therefore used in high-frequency power devices. In such nitride semiconductor devices, Si substrates are less expensive than sapphire or SiC substrates, thus there are techniques for forming nitride semiconductor layers composed of group III nitride semiconductors on Si substrates. However, when directly forming a nitride semiconductor layer composed of group III nitride semiconductors on a Si substrate, the crystallinity of the group III nitride semiconductor in the nitride semiconductor layer is reduced compared to the case where a nitride semiconductor layer composed of group III nitride semiconductors is formed on a SiC substrate, due to the large difference in lattice constants between Si and group III nitride semiconductors. Therefore, in order to reduce the difference in lattice constants between Si and group III nitride semiconductors, a technique is proposed in which a buffer layer composed of 3C-SiC is formed on the Si substrate before forming the nitride semiconductor layer composed of group III nitride semiconductors on the 3C-SiC. By using a buffer layer made of 3C-SiC, the nitride semiconductor layer made of group III nitride semiconductors can be stacked to be thicker. Therefore, the crystallinity of the group III nitride semiconductor can be made the same as that of the case where a nitride semiconductor layer made of group III nitride semiconductors is formed on a SiC substrate. Furthermore, in high-frequency power devices, a proposed technique involves forming a grounded back electrode on the back side of a substrate and filling a through-hole through the substrate with metal, thereby electrically connecting the back electrode to the source electrode on the substrate. This configuration strengthens the grounding of the source electrode, thus suppressing gain reduction. The following describes a conventional nitride semiconductor device based on the GaN-based semiconductor device disclosed in Patent Documents 1 and 2. Figure 10 is a cross-sectional view of the nitride semiconductor device 1X disclosed in Patent Document 1. As shown in Figure 10, the nitride semiconductor device 1X disclosed in Patent Document 1 includes: a dielectric substrate 107X; a SiC layer 102 formed on the dielectric substrate 107X; a nitride semiconductor layer 103 formed on the SiC layer 102 and composed of a group III nitride semiconductor; and a source electrode 201, a drain electrode 202, and a gate electrode 203 formed on the surface of the nitride semiconductor layer 103. Furthermore, an opening 104 is provided in the drain region 202D where the drain electrode 202 is provided, penetrating the drain electrode 202, the nitride semiconductor layer 103, and the SiC layer 102, and a metal layer 305 is embedded inside the opening 104. Additionally, a through-hole 301 is provided in the dielectric layer 101X of the dielectric substrate 107X, and a conductor 303 is embedded in the through-hole 301. Furthermore, a back electrode 304 is provided on the back side of the dielectric layer 101X. Moreover, the dielectric layer 101X, the back electrode 304, and the conductor 303 constitute a dielectric substrate 107X. In the nitride semiconductor device 1X shown in FIG10, the back electrode 304 and the drain electrode 202 are electrically connected through the conductor 303 buried in the through hole 301 and the metal layer 305 buried in the opening 104. Specifically, according to the manufacturing method described in Patent Document 1, after removing the Si substrate located on the back of the SiC layer 102, the SiC layer 102 is bonded to the dielectric substrate 107X, thereby connecting the metal layer 305 and the conductor 303. Furthermore, Figure 11 is a cross-sectional view of the nitride semiconductor device 1Y disclosed in Patent Document 2. As shown in Figure 11, the nitride semiconductor device 1Y disclosed in Patent Document 2 includes: a Si substrate 101 that is an insulating substrate; a nitride semiconductor layer 103 formed on the Si substrate 101 and composed of group III nitride semiconductors; and a source electrode 201, a drain electrode 202, and a gate electrode 203 formed on the surface of the nitride semiconductor layer 103. Additionally, a metal layer 305 serving as a termination layer is provided in the source region 201S where the source electrode 201 is provided, and a back electrode 304 is provided on the back side of the Si substrate 101. In the nitride semiconductor device 1Y shown in Figure 11, a through-hole 301 penetrating the Si substrate 101 and the nitride semiconductor layer 103 reaches the metal layer 305, and the back electrode 304 is electrically connected to the source electrode 201 through the metal layer 305. Furthermore, according to the manufacturing method described in Patent Document 2, the through-hole 301 is formed from the back side of the Si substrate 101, and after the back electrode 304 is formed along the through-hole 301, a conductor 303 is filled into the through-hole 301. [Prior Art Documents Patent Documents] [Patent Document 1] Japanese Patent Application Publication No. 2013-243275 [Patent Document 2] Japanese Patent Application Publication No. 2009-033097 Invention Summary Problem to be Solved by the Invention However, in the nitride semiconductor device 1X shown in FIG10, as described above, since the metal layer 305 and the conductor 303 are connected to bond the SiC layer 102 to the dielectric substrate 107X after removing the Si substrate located on the back side of the SiC layer 102, the process is complicated and the cost is high. On the other hand, in the nitride semiconductor device 1Y shown in FIG11, the back electrode 304 is connected to the source electrode 201 by forming a through-hole 301 from the back side of the Si substrate 101. Therefore, although the manufacturing process of the nitride semiconductor device 1Y shown in FIG11 is not complicated, since there is no SiC layer between the Si substrate 101 and the nitride semiconductor layer 103, the crystallinity of the group III nitride semiconductor constituting the nitride semiconductor layer 103 is reduced due to the difference in lattice constant between Si and group III nitride semiconductor. Therefore, in the nitride semiconductor device 1Y shown in FIG11, a SiC layer is disposed between the Si substrate 101 and the nitride semiconductor layer 103. Specifically, in the nitride semiconductor device 1Z shown in FIG12, a SiC layer 102 is disposed between the Si substrate 101 and the nitride semiconductor layer 103, and a through-hole 301 is provided through the Si substrate 101, the SiC layer 102 and the nitride semiconductor layer 103, with a metal layer 106 as a stop, and a conductor 303 is embedded inside the through-hole 301. In this way, the back electrode 304 and the source electrode 201 can be electrically connected through the conductor 303 and the metal layer 106. Furthermore, in the nitride semiconductor device 1Z shown in FIG12, a metal diffusion prevention film 302 is provided on the inner surface of the through-hole 301 to prevent the conductor 303 from contacting the Si substrate 101 and causing metal diffusion. In other words, a metal diffusion prevention film 302 is provided between the Si substrate 101 and the conductor 303. However, in the configuration of the nitride semiconductor device 1Z shown in Figure 12, since the SiC constituting the SiC layer 102 is hard and chemically stable, a notch 400 is formed in the Si substrate 101 when the through-hole 301 is formed. Specifically, the through-hole 301 is formed by dry etching the Si substrate 101 and the SiC layer 102 using a fluorine-based gas or a chlorine-based gas. However, since the etching rate of SiC is slower than that of Si, side etching occurs in the vicinity of the SiC layer 102 in the Si substrate 101, which becomes the notch 400. When a notch 400 is formed in the Si substrate 101, and a conductor 303 is formed inside the through-hole 301, the notch 400 becomes a void. Due to the presence of the notch 400, the coverage of the metal diffusion prevention film 302 is reduced. The conductor 303 contacts the Si substrate 101, resulting in metal interdiffusion and increased impedance. As a result, the quality and yield of the nitride semiconductor device 1Z are reduced. This disclosure was made in view of the aforementioned problem, and its purpose is to provide a semiconductor device that, even when a SiC layer is disposed between a Si substrate and a SiC semiconductor layer, does not produce a gap, and allows for the provision of a through-hole connecting the Si substrate and the SiC layer. Means for solving the problem To achieve the above objectives, one embodiment of the semiconductor device disclosed herein comprises: a Si substrate; a back electrode disposed below the Si substrate; a SiC layer disposed above the Si substrate; a semiconductor layer disposed above the SiC layer and composed of a group III nitride semiconductor; a source electrode and a drain electrode disposed above the semiconductor layer; a gate electrode in contact with the semiconductor layer; an intermediate layer disposed at least in an opening of the SiC layer; a metal layer disposed above the opening; and a conductor disposed inside a through-hole penetrating the intermediate layer and the Si substrate, and electrically connected to the back electrode and the metal layer, wherein the metal layer covers the through-hole, and the intermediate layer is disposed between the SiC layer and the conductor, wherein the intermediate layer is a metal nitride layer or a silicon oxide layer. Furthermore, one aspect of the manufacturing method of the semiconductor device disclosed herein is as follows: a SiC layer is formed above a Si substrate; a semiconductor layer composed of a group III nitride semiconductor is formed above the SiC layer; an opening is formed at the opening of the SiC layer; an intermediate layer is formed at the opening; a source electrode, a drain electrode, and a gate electrode are formed above the semiconductor layer; a metal layer is formed above the opening to cover at least a portion of the intermediate layer; a through-hole is formed using the metal layer as a stop, penetrating from the underside of the Si substrate and the intermediate layer; a conductor is formed inside the through-hole; a back electrode is formed below the Si substrate; the back electrode and the metal layer are electrically connected through the conductor; and the intermediate layer is disposed between the SiC layer and the conductor, wherein the intermediate layer is a metal nitride layer or a silicon oxide layer. Effects of the Invention According to the semiconductor device disclosed herein, even if a SiC layer is disposed between the Si substrate and the nitride semiconductor layer, no gap will occur, and a through-hole can be disposed to penetrate the Si substrate and the SiC layer. The preferred embodiments will be described in detail below, with reference to the accompanying drawings. Furthermore, each of the embodiments described below is a specific example of this disclosure. Therefore, the values, shapes, materials, constituent elements, the arrangement and connection of constituent elements, and the steps (processes) and sequence of steps shown in the following embodiments are examples and are not intended to limit this disclosure. Therefore, in the constituent elements of the following embodiments, constituent elements not described in the independent claim showing the highest concept of this disclosure are described as arbitrary constituent elements. Furthermore, each figure is a model diagram and may not be a rigorous representation. In each figure, the same symbols are assigned to substantially the same components, and repeated explanations are omitted or simplified. Furthermore, the terms used in this specification to indicate the relationship between elements such as parallelism or perpendicularity, the shape of elements such as rectangles, and numerical ranges do not merely indicate a strict meaning, but also imply that they include substantially equivalent ranges, such as differences of a few percent. Furthermore, in this specification, the terms "above" or "upper" and "below" or "lower" in the context of the semiconductor device do not refer to the absolute spatial direction of "up" (vertical upward) and "down" (vertical downward), but are terms defined based on the stacking sequence in the stacked structure and according to the relative positional relationship. Furthermore, in this specification and drawings, the X-axis, Y-axis, and Z-axis represent the three axes of a three-dimensional orthogonal coordinate system. Specifically, in this specification, the main surface of the substrate of the semiconductor device is defined by two parallel axes as the X-axis and Y-axis, and the direction orthogonal to the main surface as the Z-axis direction. More specifically, the direction in which the source electrode, gate electrode, and drain electrode are arranged in this order, i.e., the so-called gate length direction, is the X-axis direction. Also, the term "planar viewing angle" in this specification, unless otherwise specified, refers to the viewing angle when looking at the main surface (top) of the substrate of the semiconductor device from the Z-axis direction. Furthermore, in this specification, a group III nitride semiconductor is a semiconductor that contains one or more group III elements and nitrogen. Group III elements include, for example, aluminum (Al), gallium (Ga), and indium (In). Examples of group III nitride semiconductors include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. Group III nitride semiconductors may also contain one or more elements other than group III, such as silicon (Si) and phosphorus (P). Moreover, unless otherwise specified, in the following description, when a group III nitride semiconductor is referred to as AlInGaN, it means that it also contains any one of Al, In, Ga, and N. The same applies to other designations such as AlGaN and GaN. Furthermore, the term "layer composed of group III nitride semiconductors" and "layer composed of group III nitride semiconductors" means that the layer substantially contains only group III nitride semiconductors. However, the layer may contain other elements, such as elements that cannot be unavoidably mixed in during manufacturing, as impurities, in a proportion of less than 1 at%. (Embodiment 1) First, the semiconductor device 1 of Embodiment 1 will be described using Figures 1 and 2. Figure 1 is a plan view of the semiconductor device 1 of Embodiment 1. Figure 2 is a cross-sectional view of the semiconductor device 1 of Embodiment 1 along line II-II in Figure 1. Furthermore, in Figure 1, cross-sectional lines are provided for ease of understanding the positions of the source electrode 201, drain electrode 202, and gate electrode 203. Semiconductor device 1 is a nitride semiconductor device formed using a group III nitride semiconductor. In this embodiment, the case where semiconductor device 1 is a high electron mobility transistor (HEMT) will be described. As shown in Figures 1 and 2, the semiconductor device 1 includes: a Si substrate 101, a SiC layer 102, a nitride semiconductor layer 103, an intermediate layer 105, a metal layer 106, a source electrode 201, a drain electrode 202, a gate electrode 203, a metal diffusion prevention film 302, a conductor 303, and a back electrode 304. The Si substrate 101 is, for example, a substrate with a (111) facet and made of Si. The resistivity of the Si substrate 101 is, for example, 1 kΩ or more and 20 Ω or less, but is not limited thereto. Furthermore, the dopant in the Si substrate 101 can be P-type or N-type. Also, the Si substrate 101 can be a combination of multiple resistivity or dopant types. Furthermore, in this embodiment, the Si substrate 101 is a substrate whose substrate itself is made of Si, but it is not limited to this. For example, the Si substrate 101 may also be a substrate on which silicon is formed on a substrate made of a substrate of the type of substrate, such as a sapphire substrate, a GaN substrate, or an AlN substrate. A SiC layer 102 is disposed above a Si substrate 101. In this embodiment, the SiC layer 102 is disposed on the first main surface (surface) of the Si substrate 101. The SiC layer 102 is, for example, an epitaxial layer composed of 3C-SiC. In "3C-SiC", "C" indicates cubic crystal, and the number "3" indicates the number of tetrahedral structural layers contained in one period of the stacking direction. The thickness of the SiC layer 102 is, for example, 5 nm or more and 5000 nm or less, but is not limited thereto. In this embodiment, the thickness of the SiC layer 102 is 2000 nm (2 μm). A nitride semiconductor layer 103 is disposed above the SiC layer 102. In this embodiment, the nitride semiconductor layer 103 is directly disposed above the SiC layer 102. The nitride semiconductor layer 103 is a semiconductor layer composed of group III nitride semiconductors. Specifically, the nitride semiconductor layer 103 is a stack of multiple semiconductor layers, each composed of group III nitride semiconductors. The nitride semiconductor layer 103 includes an active layer composed of group III nitride semiconductors. Furthermore, the nitride semiconductor layer 103 includes a two-dimensional electron gas layer that serves as a carrier for a transistor. The two-dimensional electron gas is generated at the heterojunction of the active layer. Moreover, the carrier for the transistor can also be formed by doping under conditions of ion implantation or epitaxial layer formation. The thickness of the nitride semiconductor layer 103 is, for example, 100 nm or more and 15,000 nm or less, but is not limited thereto. In this embodiment, the thickness of the nitride semiconductor layer 103 is 5,000 nm (5 μm). A source electrode 201 and a drain electrode 202 are disposed above the nitride semiconductor layer 103. In this embodiment, the source electrode 201 and the drain electrode 202 are disposed at a distance from each other on the surface of the nitride semiconductor layer 103. The source electrode 201 and the drain electrode 202 face each other in the X-axis direction. The source electrode 201 is disposed on the source region 201S in the nitride semiconductor layer 103. The source electrode 201 and drain electrode 202 are metal layers composed of metallic materials. Specifically, the source electrode 201 and drain electrode 202 are composed of a metal monomer or metal alloy containing at least one of metals selected from Ti, Al, Ni, Au, Ta, W, Pd, Cu, etc. In this embodiment, the source electrode 201 and drain electrode 202 are a laminate of Ti layers and Al layers sequentially stacked. Furthermore, the source electrode 201 and drain electrode 202 may also be a single layer of metallic material or a laminate of non-metallic material. Furthermore, the source electrode 201 and the drain electrode 202 are electrically connected to the two-dimensional electron gas layer. Specifically, the source electrode 201 and the drain electrode 202 are ohmically connected to the two-dimensional electron gas layer. The gate electrode 203 is disposed above the nitride semiconductor layer 103. In this embodiment, the gate electrode 203, along with the source electrode 201 and the drain electrode 202, is disposed on the surface of the nitride semiconductor layer 103. That is, the gate electrode 203 is in contact with the nitride semiconductor layer 103. Furthermore, the gate electrode 203 is disposed between the source electrode 201 and the drain electrode 202. The gate electrode 203 is constructed from a metal monomer or metal alloy comprising at least one metal selected from Ti, TiN, Ta, TaN, W, Ni, Pd, Au, Al, and Cu. In this embodiment, the gate electrode 203 is a laminate formed by sequentially stacking Ni and Au layers. Alternatively, the gate electrode 203 may not be a laminate of metal layers, but rather a single metal layer. The gate electrode 203 functions as follows: by applying voltage or current to the gate electrode 203, it controls the current flowing between the source electrode 201 and the drain electrode 202 (source-drain interphase) in the carrier formed within the nitride semiconductor layer 103. The gate electrode 203 can also be configured such that the semiconductor device 1 is a Schottky junction, or it can be configured such that the semiconductor device 1 has a so-called MIS (Metal-Insulator-Semiconductor) structure with an insulating layer between the gate electrode 203 and the nitride semiconductor layer 103, thus being normally open. Furthermore, the semiconductor device 1 can also be configured such that a P-type nitride semiconductor layer or similar structure is provided between the gate electrode 203 and the nitride semiconductor layer 103, thus being normally closed. An opening 104 is provided in the SiC layer 102. The opening 104 is open at least in the SiC layer 102. In this embodiment, the opening 104 is open in both the SiC layer 102 and the nitride semiconductor layer 103. That is, the opening 104 penetrates through the SiC layer 102 and the nitride semiconductor layer 103, exposing a portion of the surface of the Si substrate 101. An opening 104 is provided in a portion of the source region 201S in which the source electrode 201 is formed. The distance between the opening 104 and the end of the source electrode 201 on the gate electrode 203 side can be 500 nm or more. In this way, the reduction of crystallinity of the nitride semiconductor layer 103 between the gate electrode 203 and the source electrode 201 can be suppressed. In this embodiment, the opening 104 is provided in a part of the source region 201S, but is not limited thereto. For example, the opening 104 may also be provided in the region where the drain electrode 202 or the gate electrode 203 is formed, or it may be provided outside the active region where the transistor is formed. Furthermore, the side surface of the SiC layer 102 within the opening 104 is on the same horizontal plane as the side surface of the nitride semiconductor layer 103, but this is not a limitation. For example, within the opening 104, the side surface of the nitride semiconductor layer 103 may recede from the side surface of the SiC layer 102 toward the opposite side to the opening 104, or it may protrude further into the opening 104 than the side surface of the SiC layer 102. Also, the opening width of the opening 104 may be constant or different in the Z-axis direction. In this case, the opening width of the opening 104 may decrease continuously from top to bottom, or it may decrease discontinuously. An intermediate layer 105 is provided in the opening 104. The intermediate layer 105 is disposed between the Si substrate 101 exposed by the opening 104 and the metal layer 106. Specifically, the intermediate layer 105 is disposed between the upper surface of the Si substrate 101 and the lower surface of the metal layer 106 within the opening 104, and is disposed between the side surface of the SiC layer 102 (the inner side surface of the opening 104) and the side surface of the conductor 303 within the opening 104. In this embodiment, the intermediate layer 105 may also be disposed between the side surface of the nitride semiconductor layer 103 and the metal layer 106 within the opening 104. Furthermore, the upper surface of the intermediate layer 105 and the upper surface of the nitride semiconductor layer 103 are substantially on the same plane, but this is not a limitation. In a top-down view, the intermediate layer 105 (opening 104) is configured to surround the through-hole 301. That is, the intermediate layer 105 (opening 104) is configured to surround the conductor 303 and the metal diffusion prevention film 302 embedded in the through-hole 301. Therefore, the intermediate layer 105 (opening 104) is disposed between the conductor 303 (through-hole 301) and the SiC layer 102. In other words, the intermediate layer 105 is an intermediary layer between the conductor 303 and the SiC layer 102. The intermediate layer 105 is a metal nitride layer or a silicon oxide layer. The intermediate layer 105 functions as a buffer layer to mitigate problems caused by the difference in etching rates between SiC and Si when forming the through-hole 301 connecting the Si substrate 101 and the SiC layer 102 through etching. For example, if dry etching using fluorine-based or chlorine-based gases is used to etch the Si substrate 101 and the SiC layer 102, the etching rate for fluorine-based gases is Si > SiO. 2≫SiC>GaN, and the etching rate for chlorine-based gases is Si=GaN≫SiC. Therefore, as the material constituting the intermediate layer 105, a material with an etching rate faster than that of SiC can also be used. Specifically, a material constituting the intermediate layer 105 can also be used that has an etching rate faster than that of SiC and a etching rate slower than that of Si. As one example, the material constituting the intermediate layer 105 is a metal nitride such as GaN, AlN, TiN, TaN, WN, InN, or SiN, or SiO. 2. BPSG (SiO2 containing boron (B) and phosphorus (P)) 2) Silicon oxides. The intermediate layer 105 is any single layer or multiple layers selected from these. In this embodiment, the intermediate layer 105 is a silicon nitride layer (SiN layer). Furthermore, although it is based on etching conditions, GaN, AlN, TiN, SiN, and SiO... The relationship between the etching rate of GaN and Si can be set as follows: GaN = Si, AlN = Si, TiN > Si, SiN > Si, SiO 2 > Si (equal and inequal signs indicate the relative etching rates). Furthermore, the Vickers hardness of these materials is as follows: GaN 15 GPa, AlN 9.8~10.4 GPa, TiN 10.8 GPa, SiN 14 GPa, and SiO2... 2 is 9.7 GPa. Furthermore, the Vickers hardness of Si is 9.8~10.6 GPa, and the Vickers hardness of SiC is 23 GPa. Therefore, the Vickers hardness of the intermediate layer 105 can be higher than the minimum Vickers hardness of the Si substrate 101, which is 9.8 GPa, and lower than the Vickers hardness of the SiC layer 102, which is 23 GPa. Furthermore, in this embodiment, the intermediate layer 105 may also be in contact with the Si substrate 101 or the metal layer 106, but is not limited to this. That is, the intermediate layer 105 may not be in contact with the Si substrate 101, and the intermediate layer 105 may not be in contact with the metal layer 106. For example, a layer made of a material other than metal nitride and silicon oxide may also be located between the Si substrate 101 and the intermediate layer 105. Specifically, a layer made of a material having an etching rate equal to that of the Si substrate 101, or a material having an etching rate between that of the Si substrate 101 and the intermediate layer 105, is located between the Si substrate 101 and the intermediate layer 105. Also, a layer made of a material having an etching rate equal to that of the intermediate layer 105, or a material having an etching rate between that of the intermediate layer 105 and the metal layer 106, is located between the intermediate layer 105 and the metal layer 106. The thickness of the intermediate layer 105 is, for example, 100 nm or more and 15,000 nm or less. However, the thickness of the intermediate layer 105 is not limited to this. In this embodiment, the thickness of the intermediate layer 105 is 500 nm. A metal layer 106 is disposed above the opening 104. Furthermore, the metal layer 106 covers at least a portion of the intermediate layer 105. In this embodiment, the metal layer 106 is disposed such that it covers not only the intermediate layer 105 but also a portion of the source electrode 201. Furthermore, the metal layer 106 located above the opening 104 also covers the conductor 303. Specifically, the metal layer 106 covers the top surface of the conductor 303, the bottom and side surfaces of the intermediate layer 105, and a portion of the source electrode 201. Furthermore, the metal layer 106 covering the conductor 303 covers the through-hole 301. In this embodiment, the metal layer 106 covers the entire through-hole 301. Specifically, the metal layer 106 is disposed such that it protrudes from the opening of the through-hole 301. The metal layer 106 functions as an etch stop layer to halt the etching of the through-hole 301 disposed on the Si substrate 101. The metal layer 106 is composed of a metal monomer or metal alloy comprising, for example, at least one of Cu, Au, Pt, Ni, and Mo. Alternatively, the metal layer 106 may be composed of a metal monomer or metal alloy composed of high-melting-point metals such as W, Ti, or Ta. This suppresses crystal mixing between the metal layer 106 and the conductor 303. Furthermore, the metal layer 106 may also be composed of a metal nitride composed of W, Ti, or Ta. In this embodiment, the metal layer 106 is a titanium nitride layer (TiN layer) with a thickness of 300 nm. Furthermore, the metal layer 106 may be a single layer or multiple layers. The metal layer 106 is electrically connected to the source electrode 201. The metal layer 106 and the source electrode 201 can also be electrically connected through direct contact, or through a conductor such as a wiring layer (not shown). Furthermore, the metal layer 106 may also be electrically connected to the drain electrode 202 or the gate electrode 203 instead of the source electrode 201. In semiconductor device 1, a through-hole 301 is provided, penetrating the intermediate layer 105 and the Si substrate 101. In this embodiment, the through-hole 301 is provided in the source region 201S. From a planar perspective, the through-hole 301 is located inside the opening 104. The through-hole 301 is a through-hole, penetrating the intermediate layer 105 and the Si substrate 101, thus exposing the metal layer 106. Therefore, the upper surface of the through-hole 301 is the lower surface of the metal layer 106. In this case, the lowermost edge of the metal layer 106 becomes longer than the uppermost opening edge of the through-hole 301. Furthermore, from a planar perspective, the via 301 is surrounded by the intermediate layer 105. In this embodiment, the opening shape of the via 301 is circular. In this embodiment, the inner diameter (opening width) of the via 301 decreases monotonically from the bottom to the top of the via 301. That is, the opening area of ​​the via 301 decreases continuously from the bottom to the top of the via 301. As a result, the side surface of the via 301 becomes a positive cone shape from the bottom to the top of the via 301, thus preventing voids or cracks in the metal diffusion prevention film 302 or formation defects in the conductor 303 when forming the metal diffusion prevention film 302 and the conductor 303 from the back side of the Si substrate 101. In other words, a highly reliable via 301 can be formed in the semiconductor device 1. Furthermore, the inner diameter of the via 301 can also decrease discontinuously from the bottom to the top of the via 301. Furthermore, in this embodiment, the side surface of the Si substrate 101 with the through hole 301 and the side surface of the intermediate layer 105 are on the same horizontal plane, but the side surface of the Si substrate 101 and the side surface of the intermediate layer 105 may also be discontinuous. A metal diffusion prevention film 302 is disposed to cover the side surface of the through-hole 301. The metal diffusion prevention film 302 is a thin film layer disposed between the Si substrate 101 and the conductor 303 to prevent inter-diffusion of metals. The metal diffusion prevention film 302 can be an insulating film made of an insulating material, or it can be a conductive film made of a conductive material. The metal diffusion prevention film 302 is selected from Ti, Ta, TiN, TaN, WN, and SiO. 2. Any single or multiple layers of SiN. In this embodiment, the metal diffusion prevention film 302 is a laminate of Ti layers and TiN layers stacked sequentially. Furthermore, if the metal diffusion prevention film 302 is made of a conductive material, it may cover not only the side surface of the through hole 301, but also the upper surface of the through hole 301. Inside the through-hole 301, a conductor 303 made of conductive material is disposed. Specifically, the conductor 303 is disposed inside the through-hole 301, the inner surface of which is covered by a metal diffusion prevention film 302. The conductor 303 is an embedded hole formed by filling the through-hole 301. In this embodiment, conductor 303 is a metal layer made of metallic material. Conductor 303 is any single layer or multiple layers selected from Ti, Ta, Cu, Al, Au, Ni, and W. In this embodiment, conductor 303 is a laminate formed by sequentially stacking Ti layers and Cu layers, or a laminate formed by sequentially stacking Ti layers, TiN layers, or Ti layers and Cu layers. Furthermore, conductor 303 can fill the entire interior of through-hole 301, or it can fill the through-hole 301 with a portion of its remaining voids. Conductor 303 is electrically connected to back electrode 304 and metal layer 106. Back electrode 304 and metal layer 106 are electrically connected through conductor 303. In this embodiment, metal layer 106 is connected to source electrode 201, therefore source electrode 201 and back electrode 304 are electrically connected through metal layer 106 and conductor 303. The back electrode 304 is disposed below the Si substrate 101. In this embodiment, the back electrode 304 is disposed on the second main surface (back side) of the Si substrate 101 that is opposite to the first main surface (surface). The back electrode 304 is an electrode that covers a solid pattern (a pattern that is essentially continuous and without gaps) on the back side of the Si substrate 101. In this embodiment, the back electrode 304 covers the entire back side of the Si substrate 101. The back electrode 304 is composed of a metal monomer or metal alloy containing at least one metal selected from, for example, Ti, Al, W, Ta, Cu, Ni, Au, Sn, and Ag. Furthermore, the back electrode 304 can be a single-layer structure or a multilayer structure composed of multiple metal layers. In this embodiment, the back electrode 304 is a multilayer structure composed of Ti, Ni, and Au layers sequentially stacked. Moreover, the back electrode 304 and the conductor 303 can also be made of the same material. The back electrode 304 is electrically grounded. That is, the potential of the back electrode 304 is the ground potential. As mentioned above, the back electrode 304 is electrically connected to the source electrode 201 through the conductor 303 and the metal layer 106. That is, the back electrode 304 and the source electrode 201 are at the same potential. Furthermore, the back electrode 304 may not be electrically connected to the source electrode 201, but rather to the drain electrode 202 or the gate electrode 203. Next, the manufacturing method of the semiconductor device 1 according to Embodiment 1 will be described using Figures 3A to 3H. Figures 3A to 3H are diagrams illustrating the various steps of the manufacturing method of the semiconductor device 1 according to Embodiment 1. First, as shown in FIG3A, a SiC layer 102 is formed above a Si substrate 101. Specifically, the SiC layer 102 is formed by epitaxial growth of a 2 μm thick (111) plane, i.e., 3C-SiC, on the surface of the Si substrate 101. Then, a nitride semiconductor layer 103 composed of group III nitride semiconductors is formed above the SiC layer 102. Specifically, a stack of multiple semiconductor layers composed of group III nitride semiconductors is epitaxially grown, thereby forming a 5 μm thick nitride semiconductor layer 103 on the surface of the SiC layer 102. Furthermore, a two-dimensional electron gas layer that serves as a carrier for a transistor is formed within the nitride semiconductor layer 103. Next, as shown in FIG3B, an opening 104 is formed in the opening of the SiC layer 102. In this embodiment, the opening 104 is formed in both the SiC layer 102 and the nitride semiconductor layer 103. Specifically, firstly, a photoresist (not shown) is coated on the surface of the nitride semiconductor layer 103, and then the photoresist is patterned using photolithography and etching, thereby forming a photoresist mask outside the area where the opening 104 is formed. Then, the photoresist mask is used as a mask to etch away the nitride semiconductor layer 103 and the SiC layer 102 using dry etching, thereby forming the opening 104 that penetrates the nitride semiconductor layer 103 and the SiC layer 102, exposing the Si substrate 101. Then, the polymer and photoresist mask adhering due to dry etching are removed. Next, as shown in Figure 3C, an intermediate layer 105 is formed in the opening 104. Specifically, after depositing a 500 nm thick silicon nitride layer on the nitride semiconductor layer 103 using CVD (Chemical Vapor Deposition) to cover the opening 104, the silicon nitride layer outside the opening 104 is removed using photolithography and dry etching, thereby leaving only the silicon nitride layer inside the opening 104. In this way, an intermediate layer 105 composed of a silicon nitride layer can be formed to cover the inner surface of the opening 104. Next, as shown in Figure 3D, a source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above the nitride semiconductor layer 103. Specifically, a Ti layer and an Al layer patterned with a photoresist are sequentially deposited on the surface of the nitride semiconductor layer 103 using a vapor deposition method. After patterning by lift-off, alloying is performed by heat treatment, thereby forming the source electrode 201 and the drain electrode 202, which are ohmically connected to the two-dimensional electron gas in the nitride semiconductor layer 103. At this time, the area in the source electrode 201 where the through-hole 301 is formed and its surrounding area are not formed. Then, a Ni layer and an Au layer patterned with a photoresist are sequentially deposited using a vapor deposition method, and patterned by stripping to form a gate electrode 203 that is Schottky connected to the two-dimensional electron gas in the nitride semiconductor layer 103. In this embodiment, the gate electrode 203 is formed between the source electrode 201 and the drain electrode 202. Next, as shown in Figure 3E, a metal layer 106 is formed above the opening 104 to cover the intermediate layer 105. Specifically, after depositing a 200nm thick TiN layer using a solder sputtering method, a photolithography and dry etching method are used to remove the TiN layer other than the source region 201S and a portion of the TiN layer on the source electrode 201, thereby forming the metal layer 106 to cover the intermediate layer 105 and the remaining portion on the source electrode 201. Next, as shown in Figure 3F, a through-hole 301 is formed by using the metal layer 106 as a stop, penetrating from the lower surface side (back side) of the Si substrate 101 through the Si substrate 101 and the intermediate layer 105. Specifically, a through-hole 301 is formed on the lower surface side of the Si substrate 101 by using photolithography and etching to remove the material penetrating the Si substrate 101 and the intermediate layer 105. The etching method can be dry etching using fluorine-based or chlorine-based gases. In this embodiment, an intermediate layer 105 exists between the hard and difficult-to-etch SiC layer 102 and the through-hole 301, so the SiC layer 102 and the through-hole 301 do not overlap. That is, the intermediate layer 105 is provided to surround the through-hole 301. When forming the through-hole 301 using dry etching, only the Si substrate 101 and the intermediate layer 105 are etched, without etching the SiC layer 102. Therefore, when forming the through-hole 301, gaps in the Si substrate 101 can be suppressed. This allows for the easy formation of a through-hole 301 that penetrates both the Si substrate 101 and the SiC layer 102. Furthermore, the via 301 can be formed using either the Boash process or a non-Boash process. Also, the via 301 can be formed using multiple etching conditions, or the intermediate layer 105 can be selectively etched onto the Si substrate 101. In this case, a fluorine-based gas can be used to selectively etch the Si substrate 101, and if the intermediate layer 105 is a metal nitride layer, a chlorine-based gas can be used to selectively etch the intermediate layer 105. The switching of etching conditions can also occur midway through etching the Si substrate 101. Furthermore, the surface roughness of the via 301 can be below 300 nm. Next, as shown in Figure 3G, a conductor 303 is formed inside the through-hole 301. In this embodiment, Ti layers, TiN layers, Ti layers, and Cu layers are sequentially deposited using a solder sputtering method, and then the interior of the through-hole 301 is filled with a Cu layer using a plating method. Then, the Ti layers, TiN layers, Ti layers, and Cu layers deposited on the back side of the Si substrate 101 are removed by CMP (Chemical Mechanical Polishing). This allows the conductor 303, composed of Ti layers, TiN layers, and Ti layers and Cu layers, to be formed only inside the through-hole 301. Next, as shown in Figure 3H, a back electrode 304 is formed on the underside of the Si substrate 101. Specifically, a Ti layer, a Ni layer, and an Au layer are sequentially deposited on the back side of the Si substrate 101 by vapor deposition, thereby forming a stack of Ti, Ni, and Au layers, i.e., the back electrode 304, on the back side of the Si substrate 101. The back electrode 304 is electrically connected to the metal layer 106 through a conductor 303. Through this series of processes, the semiconductor device 1 with the structure shown in Figures 1 and 2 can be completed. As explained above, in the semiconductor device 1 according to this embodiment, a metal nitride layer or silicon oxide layer, i.e., an intermediate layer 105, is provided in the opening portion 104 where an opening is formed in the SiC layer 102. According to this configuration, in a HEMT structure where a SiC layer 102, made of a hard and difficult-to-etch material, is disposed between a Si substrate 101 and a nitride semiconductor layer 103, a through-hole 301 is formed by etching. Alternatively, the through-hole 301 can be formed by etching the Si substrate 101 and the SiC layer 102 simultaneously. In other words, an intermediate layer 105, which has a faster etching rate than the SiC layer 102 (i.e., is harder than the SiC layer 102), is pre-embedded into the SiC layer 102, and the through-hole 301 is formed by simultaneously etching the intermediate layer 105 and the Si substrate 101. Therefore, in the nitride semiconductor device 1Z shown in FIG. 12 above, side etching on the Si substrate 101 due to the difference in etching rates between SiC and Si can be suppressed. In other words, the formation of notches can be suppressed. Thus, according to the semiconductor device 1 of this embodiment, a through-hole 301 penetrating the Si substrate 101 and the SiC layer 102 can be easily formed without creating a notch. Therefore, it is possible to suppress the formation of voids in the conductor 303 inside the through-hole 301 due to a notch, or to prevent the metal diffusion prevention film 302 from becoming less coverable due to the presence of a notch, or to prevent high impedance due to metal interdiffusion after the conductor 303 comes into contact with the Si substrate 101. As a result, a semiconductor device 1 with high reliability can be obtained. Furthermore, in the semiconductor device 1 of this embodiment, the source electrode 201 is electrically connected to the back electrode 304, which is grounded through the metal layer 106 and conductor 303 present in the source region 201S. This allows the source electrode 201 to be grounded more securely. Furthermore, in the semiconductor device 1 of this embodiment, the Vickers hardness of the intermediate layer 105 can be greater than or equal to the Vickers hardness of the Si substrate 101 (9.8 GPa) and less than the Vickers hardness of the SiC layer 102 (23 GPa). Thus, by setting the hardness of the intermediate layer 105 to between the hardness of the Si substrate 101 and the hardness of the SiC layer 102, even in a structure where the SiC layer 102 is disposed between the Si substrate 101 and the nitride semiconductor layer 103, side etching on the Si substrate 101 due to the etch rate difference between SiC and Si can be effectively suppressed, and through-holes 301 can be easily formed. Furthermore, if a harder layer is disposed on the Si substrate 101 regardless of the substrate type, the Vickers hardness of the intermediate layer 105 can be set to between the Vickers hardness of the substrate and the harder layer, making it easy to form through-holes 301. Furthermore, in the semiconductor device 1 of this embodiment, the inner diameter of the through hole 301 decreases monotonically from the bottom to the top of the through hole 301. According to this configuration, since the side of the through hole 301 is a positive cone shape from the bottom to the top, a through hole 301 with high reliability can be formed. Furthermore, in the semiconductor device 1 of this embodiment, the upper surface of the intermediate layer 105 and the upper surface of the nitride semiconductor layer 103 are substantially on the same horizontal plane. Based on this configuration, the unevenness of the wafer-level surface, known as the overall step difference, can be mitigated. Furthermore, in the semiconductor device 1 of this embodiment, the metal layer 106 comprises at least one selected from Cu, Au, Pt, Ni, and Mo. Alternatively, the metal layer 106 may also be at least one selected from high-melting-point metals such as W, Ti, and Ta. According to this configuration, the mixing of metal layer 106 and conductor 303 can be suppressed. Furthermore, in the semiconductor device 1 of this embodiment, the metal layer 106 is electrically connected to the source electrode 201. According to this configuration, the conductor 303 inside the through-hole 301 is electrically connected to the source electrode 201 through the metal layer 106. In other words, a source hole can be realized. Furthermore, in the semiconductor device 1 of this embodiment, the source electrode 201 is disposed on the source region 201S in the nitride semiconductor layer 103, and the through hole 301 is disposed in the source region 201S. This configuration can enhance the grounding of the source electrode 201. Furthermore, in the semiconductor device 1 of this embodiment, the lowermost extent of the metal layer 106 becomes longer than the uppermost opening extent of the through hole 301. According to this configuration, it is possible to prevent the through-hole 301 from extending beyond the metal layer 106 and being etched into a portion that could be formed without etching. In other words, it is possible to prevent the through-hole 301 from extending beyond the metal layer 106. (Modification of Embodiment 1) Next, a variation of Embodiment 1 will be described. First, the configuration of the semiconductor device 1A in the variation of Embodiment 1 will be described using Figures 4 and 5. Figure 4 is a plan view of the semiconductor device 1A in the variation of Embodiment 1. Figure 5 is a cross-sectional view of the semiconductor device 1A in the variation of Embodiment 1 along the VV line in Figure 4. Furthermore, in Figure 4, similar to Figure 1, cross-sectional lines are provided for convenience in easily distinguishing the positions of the source electrode 201, drain electrode 202, and gate electrode 203. The semiconductor device 1A in this modified example differs from the semiconductor device 1 in embodiment 1 in the configuration of the opening 104 and the intermediate layer 105. Specifically, in Embodiment 1 described above, the opening 104 is formed between the SiC layer 102 and the nitride semiconductor layer 103. However, in this modified example, the opening 104 is formed not only between the SiC layer 102 and the nitride semiconductor layer 103, but also at the source electrode 201. Therefore, in this modified example, the side surface of the SiC layer 102, the side surface of the nitride semiconductor layer 103, and the side surface of the source electrode 201 are on the same horizontal plane. Furthermore, in this modified example, the opening 104 is also configured to expose the Si substrate 101. Furthermore, in embodiment 1 described above, the intermediate layer 105 is configured to cover only the opening 104 between the opening 104 and the source electrode 201. However, in this modified example, the intermediate layer 105 is configured to cover both the opening 104 and the source electrode 201. Specifically, in this modified example, the intermediate layer 105 is configured to cover the bottom and side surfaces of the opening 104 and a portion of the source electrode 201. Furthermore, in this modified example, the metal layer 106 located above the opening 104 also covers a portion of the conductor 303, the intermediate layer 105, and the source electrode 201. In this case, the metal layer 106 also covers the upper part of the intermediate layer 105 that covers the upper part of the source electrode 201. Next, the manufacturing method of the semiconductor device 1A of the modified embodiment 1 will be described using Figures 6A to 6H. Figures 6A to 6H are diagrams illustrating each step of the manufacturing method of the semiconductor device 1A of the modified embodiment 1. First, as shown in FIG6A, a SiC layer 102 is formed on top of a Si substrate 101, and a nitride semiconductor layer 103 is formed on top of the SiC layer 102. This process is the same as that shown in FIG3A of Embodiment 1 described above. Next, as shown in Figure 6B, a source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above the nitride semiconductor layer 103. Specifically, firstly, a Ti layer and an Al layer patterned with photoresist are sequentially deposited on the surface of the nitride semiconductor layer 103 by vapor deposition. After patterning by stripping, alloying is performed by heat treatment, thereby forming the source electrode 201 and the drain electrode 202, which are ohmically connected to the two-dimensional electron gas in the nitride semiconductor layer 103. Then, a Ni layer and an Au layer patterned with a photoresist are sequentially deposited by vapor deposition, and after patterning by stripping, a gate electrode 203 is formed that is connected to the two-dimensional electron gas Schottky in the nitride semiconductor layer 103. In this modified example, the gate electrode 203 is also formed between the source electrode 201 and the drain electrode 202. Secondly, as shown in FIG6C, an opening 104 is formed in the SiC layer 102 and the nitride semiconductor layer 103. In this modified example, when the opening 104 is formed in the SiC layer 102 and the nitride semiconductor layer 103, the source electrode 201 also forms an opening. Specifically, the source electrode 201, the nitride semiconductor layer 103, and the SiC layer 102 are etched away using photolithography and dry etching, thereby forming the opening 104 that penetrates the SiC layer 102, the nitride semiconductor layer 103, and the source electrode 201, thus exposing the Si substrate 101. Thus, in this modified example, since the source electrode 201, the nitride semiconductor layer 103, and the SiC layer 102 are removed in one step, the width of the opening 104 can be easily increased compared to the case where they are removed in separate processes. Therefore, the width of the bottommost part of the metal layer 106 can be easily increased, thereby expanding the boundary of the through-hole 301 beyond the metal layer 106. Next, as shown in Figure 6D, an intermediate layer 105 is formed in the opening 104. Specifically, a 500 nm thick silicon nitride layer is deposited on the nitride semiconductor layer 103 using CVD to cover the opening 104. Then, photolithography and dry etching are used to remove the silicon nitride layer outside the opening 104 and a portion of the source electrode 201, leaving only the silicon nitride layer inside the opening 104. In this way, an intermediate layer 105 composed of a silicon nitride layer can be formed in a way that covers the inner surface of the opening 104 and a portion of the source electrode 201. By forming the intermediate layer 105 in this way, compared with embodiment 1 described above, the generation of a step difference at the boundary between the surface of the nitride semiconductor layer 103 and the surface of the intermediate layer 105 can be suppressed. In this way, the generation of voids between the nitride semiconductor layer 103 and the intermediate layer 105 due to the step difference can be suppressed. Then, as shown in FIG6E, a metal layer 106 is formed above the opening 104 to cover the intermediate layer 105. Next, as shown in FIG6F, a through hole 301 is formed, passing through the Si substrate 101 and the intermediate layer 105 from the lower side (back side) of the Si substrate 101, using the metal layer 106 as a stop. Next, as shown in FIG6G, a conductor 303 is formed inside the through hole 301. Next, as shown in FIG6H, a back electrode 304 is formed below the Si substrate 101. Furthermore, the process shown in FIG6E to FIG6H can be performed in the same manner as the process in FIG3E to FIG3H of Embodiment 1 described above. Through this series of processes, the semiconductor device 1A with the structure shown in Figures 4 and 5 can be completed. As described above, the semiconductor device 1A of this modified example achieves the same effect as the semiconductor device 1 of Embodiment 1. For example, in the semiconductor device 1A of this modified example, a metal nitride layer or silicon oxide layer, i.e., an intermediate layer 105, is also provided at the opening 104 where an opening is formed in the SiC layer 102. This allows for the easy provision of a through-hole 301 connecting the Si substrate 101 and the SiC layer 102 without creating a notch. (Embodiment 2) Next, the semiconductor device 2 of Embodiment 2 will be described. First, the configuration of the semiconductor device 2 of Embodiment 2 will be described using Figures 7 and 8. Figure 7 is a plan view of the semiconductor device 2 of Embodiment 2. Figure 8 is a cross-sectional view of the semiconductor device 2 of Embodiment 2 along line VIII-VIII of Figure 7. Furthermore, in Figure 8, similar to Figure 1, cross-sectional lines are provided for ease of understanding the positions of the source electrode 201, drain electrode 202, and gate electrode 203. The semiconductor device 2 in this embodiment differs from the semiconductor device 1 in embodiment 1 in the configuration of the opening 104 and the intermediate layer 105. Specifically, in Embodiment 1 described above, the opening 104 is formed between the SiC layer 102 and the nitride semiconductor layer 103. However, in this embodiment, the opening 104 is not formed in the nitride semiconductor layer 103, but only in the SiC layer 102. Furthermore, in this embodiment, the opening 104 is also configured to expose the Si substrate 101. Furthermore, in Embodiment 1 described above, the intermediate layer 105 is formed along the inner surface of the opening 104, but in this embodiment, the intermediate layer 105 is formed to fill the opening 104. Therefore, the upper surface of the intermediate layer 105 and the upper surface of the nitride semiconductor layer 103 are on the same horizontal plane. Also, in this embodiment, the intermediate layer 105 is composed of a Group III nitride semiconductor. That is, in this embodiment, both the intermediate layer 105 and the nitride semiconductor layer 103 are composed of a Group III nitride semiconductor. Specifically, the intermediate layer 105 has the same structure as the nitride semiconductor layer 103 and is a stack of multiple semiconductor layers composed of Group III nitride semiconductors. This allows the intermediate layer 105 and the nitride semiconductor layer 103 to be formed simultaneously in the same process. Furthermore, fluorine (F) or boron fluoride (BF) can also be incorporated into the nitride semiconductor layer 103. 2) Perform impurity injection to deactivate the two-dimensional electron gas in the nitride semiconductor layer 103. Furthermore, by providing an intermediate layer 105 in a manner that fills the opening 104, the overall step difference can be mitigated compared to the opening 104 in Embodiment 1. That is, a wiring layer can be easily formed on the source region 201S. Furthermore, in this embodiment, the metal layer 106 is located above the opening 104, and also covers part of the conductor 303, the intermediate layer 105, and the source electrode 201. Next, the manufacturing method of the semiconductor device 2 according to Embodiment 2 will be described using Figures 9A to 9H. Figures 9A to 9H are diagrams illustrating each step of the manufacturing method of the semiconductor device 2 according to Embodiment 2. First, as shown in FIG9A, a SiC layer 102 is formed on top of a Si substrate 101. Specifically, the SiC layer 102 can be formed by epitaxial growth of a 2μm thick (111) plane, i.e., 3C-SiC, on the surface of the Si substrate 101. Next, as shown in FIG9B, an opening 104 is formed in the SiC layer 102. Specifically, the SiC layer 102 is etched away using photolithography and dry etching to form the opening 104 through the SiC layer 102, thereby exposing the Si substrate 101. Next, as shown in FIG9C, an intermediate layer 105 is formed in the opening 104, and a nitride semiconductor layer 103 is formed above the SiC layer 102. Specifically, an epitaxial growth of a plurality of semiconductor layers composed of group III nitride semiconductors is performed on the surface of the SiC layer 102 and on the surface of the Si substrate 101 exposed by the opening 104, thereby forming a nitride semiconductor layer SC with a thickness of 5 μm. At this time, the nitride semiconductor layer SC formed by burying the opening 104 has lower crystallinity than the nitride semiconductor layer SC formed on the SiC layer 102. Therefore, the nitride semiconductor layer SC on the SiC layer 102 becomes a nitride semiconductor layer 103 composed of group III nitride semiconductors with high crystallinity, and the nitride semiconductor layer SC in the opening 104 becomes an intermediate layer 105 composed of group III nitride semiconductors with lower crystallinity and more recombination. In other words, in this embodiment, both the nitride semiconductor layer 103 and the intermediate layer 105 are composed of group III nitride semiconductors, but their crystallinity differs. Furthermore, a two-dimensional electron gas layer that serves as a carrier for the transistor is formed within the nitride semiconductor layer 103. Next, as shown in Figure 9D, a source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above the nitride semiconductor layer 103. Specifically, a Ti layer and an Al layer patterned with a photoresist are sequentially deposited on the surface of the nitride semiconductor layer 103 by vapor deposition. After patterning by stripping, alloying is performed by heat treatment, thereby forming the source electrode 201 and the drain electrode 202, which are ohmically connected to the two-dimensional electron gas in the nitride semiconductor layer 103. Then, a Ni layer and an Au layer patterned with a photoresist are sequentially deposited using a vapor deposition method, and after patterning by stripping, a gate electrode 203 is formed that is Schottky connected to the two-dimensional electron gas in the nitride semiconductor layer 103. In this embodiment, the gate electrode 203 is also formed between the source electrode 201 and the drain electrode 202. Furthermore, the source electrode 201 can also be formed to span the top of the opening 104 from a planar view. In this way, since a pit is formed at the boundary between the intermediate layer 105 and the nitride semiconductor layer 103, the contact resistance between the source electrode 201 and the two-dimensional electron gas layer can be reduced. Then, as shown in FIG9E, a metal layer 106 is formed above the opening 104 to cover the intermediate layer 105. Next, as shown in FIG9F, a through hole 301 is formed from the bottom side (back side) of the Si substrate 101 through the Si substrate 101 and the intermediate layer 105, using the metal layer 106 as a stop. Next, as shown in FIG9G, a conductor 303 is formed inside the through hole 301. Next, as shown in FIG9H, a back electrode 304 is formed below the Si substrate 101. Furthermore, the process shown in FIG9E to FIG9H can be performed in the same manner as the process shown in FIG3E to FIG3H in Embodiment 1 described above. Through this series of processes, the semiconductor device 2 with the structure shown in Figures 7 and 8 can be completed. As described above, the semiconductor device 2 of this embodiment achieves the same effect as the semiconductor device 1 of Embodiment 1. For example, in the semiconductor device 2 of this embodiment, a metal nitride layer or silicon oxide layer, i.e., an intermediate layer 105, is provided at the opening 104 where an opening is formed in the SiC layer 102. This allows for the easy provision of a through-hole 301 connecting the Si substrate 101 and the SiC layer 102 without creating a notch. Furthermore, in the semiconductor device 2 of this embodiment, the intermediate layer 105 and the nitride semiconductor layer 103 are both composed of group III nitride semiconductors. According to this configuration, the intermediate layer 105 and the nitride semiconductor layer 103 can be formed simultaneously. This allows for the low-cost fabrication of a semiconductor device 2 having the intermediate layer 105. (Other variations) The semiconductor device disclosed herein has been described above according to embodiments 1 and 2, but this disclosure is not limited to embodiments 1 and 2. Industrial Applicability For example, forms obtained by applying various modifications to embodiments 1 and 2 that are conceived by those skilled in the art, or forms achieved by arbitrarily combining the constituent elements and functions of embodiments 1 and 2 without departing from the spirit of this disclosure, are also included in this disclosure. Furthermore, forms obtained by arbitrarily combining two or more claims from the plurality of claims recorded in the claims of the application at the time of this filing, to the extent that they are not technically contradictory, are also included in this disclosure. For example, when a claim in the form of reference recorded in the claims of the application at the time of this filing references all superior claims to form multiple claims or multiple claims dependent on multiple claims, to the extent that they are not technically contradictory, the combination of all claims contained within those multiple claims or multiple claims dependent on multiple claims is also included in this disclosure. The semiconductor devices disclosed herein can be used in communication machines or converters requiring high-speed operation, as well as power switching elements used in power circuits, etc. 1, 1A, 2: Semiconductor device; 1X, 1Y, 1Z: Nitride semiconductor device; 101: Si substrate; 101X: Dielectric layer; 102: SiC layer; 103: Nitride semiconductor layer; 104: Opening; 105: Intermediate layer; 106: Metal layer; 107X: Dielectric substrate; 201: Source electrode; 201S: Source region; 202: Drain electrode; 202D: Drain region; 203: Gate electrode; 301: Through-hole; 302: Metal diffusion prevention film; 303: Conductor; 304: Back electrode; 305: Metal layer; 400: Notch; SC: Nitride semiconductor layer; II-II: Profile line; VV: Profile line; VIII-VIII: Profile line; X, Y, Z: Axial direction. Figure 1 is a plan view of the semiconductor device of Embodiment 1. Figure 2 is a cross-sectional view of the semiconductor device of Embodiment 1 along line II-II in Figure 1. Figure 3A is a diagram illustrating the process of forming a SiC layer and a semiconductor nitride layer on a Si substrate in the manufacturing method of the semiconductor device of Embodiment 1. Figure 3B is a diagram illustrating the process of forming openings in the SiC layer and the semiconductor nitride layer in the manufacturing method of the semiconductor device of Embodiment 1. Figure 3C is a diagram illustrating the process of forming an intermediate layer at the opening in the manufacturing method of the semiconductor device of Embodiment 1. Figure 3D is a diagram illustrating the process of forming a source electrode, a drain electrode, and a gate electrode in the manufacturing method of the semiconductor device of Embodiment 1. Figure 3E is a diagram illustrating the process of forming a metal layer above the intermediate layer in the manufacturing method of the semiconductor device of Embodiment 1. Figure 3F is a diagram illustrating the process of forming a through-hole penetrating the Si substrate and the intermediate layer in the manufacturing method of the semiconductor device of Embodiment 1. Figure 3G is a diagram illustrating the process of forming a conductor in a through-hole in the manufacturing method of the semiconductor device according to Embodiment 1. Figure 3H is a diagram illustrating the process of forming a back electrode on a Si substrate in the manufacturing method of the semiconductor device according to Embodiment 1. Figure 4 is a plan view of a modified semiconductor device according to Embodiment 1. Figure 5 is a cross-sectional view of the modified semiconductor device according to Embodiment 1 along the VV line in Figure 4. Figure 6A is a diagram illustrating the process of forming a SiC layer and a nitride semiconductor layer on a Si substrate in the manufacturing method of the modified semiconductor device according to Embodiment 1. Figure 6B is a diagram illustrating the process of forming a source electrode, a drain electrode, and a gate electrode in the manufacturing method of the modified semiconductor device according to Embodiment 1. Figure 6C is a diagram illustrating the process of forming an opening in the manufacturing method of the modified semiconductor device according to Embodiment 1. Figure 6D is a diagram illustrating the process of forming an intermediate layer at the opening in the manufacturing method of the modified semiconductor device according to Embodiment 1. Figure 6E is a diagram illustrating the process of forming a metal layer on the intermediate layer in the manufacturing method of the semiconductor device according to a modified embodiment of 1. Figure 6F is a diagram illustrating the process of forming a through-hole penetrating the Si substrate and the intermediate layer in the manufacturing method of the semiconductor device according to a modified embodiment of 1. Figure 6G is a diagram illustrating the process of forming a conductor in the through-hole in the manufacturing method of the semiconductor device according to a modified embodiment of 1. Figure 6H is a diagram illustrating the process of forming a back electrode on the Si substrate in the manufacturing method of the semiconductor device according to a modified embodiment of 1. Figure 7 is a plan view of the semiconductor device according to embodiment 2. Figure 8 is a cross-sectional view of the semiconductor device according to embodiment 2 along line VIII-VIII in Figure 7. Figure 9A is a diagram illustrating the process of forming a SiC layer on the Si substrate in the manufacturing method of the semiconductor device according to embodiment 2.Figure 9B illustrates the process of forming an opening in the SiC layer in the manufacturing method of the semiconductor device according to Embodiment 2. Figure 9C illustrates the process of forming an intermediate layer and a nitride semiconductor layer in the manufacturing method of the semiconductor device according to Embodiment 2. Figure 9D illustrates the process of forming a source electrode, a drain electrode, and a gate electrode in the manufacturing method of the semiconductor device according to Embodiment 2. Figure 9E illustrates the process of forming a metal layer on top of the intermediate layer in the manufacturing method of the semiconductor device according to Embodiment 2. Figure 9F illustrates the process of forming a through-hole penetrating the Si substrate and the intermediate layer in the manufacturing method of the semiconductor device according to Embodiment 2. Figure 9G illustrates the process of forming a conductor in the through-hole in the manufacturing method of the semiconductor device according to Embodiment 2. Figure 9H illustrates the process of forming a back electrode on the Si substrate in the manufacturing method of the semiconductor device according to Embodiment 2. Figure 10 is a cross-sectional view of the nitride semiconductor device disclosed in Patent Document 1. Figure 11 is a cross-sectional view of the nitride semiconductor device disclosed in Patent Document 2. Figure 12 is a cross-sectional view of the nitride semiconductor device of the comparative example. 1: Semiconductor devices 101:Si substrate 102: SiC layer 103: Nitride semiconductor layer 104: Opening 105: Intermediate Layer 106: Metal layer 201: Source electrode 201S: Source Region 202: Drain electrode 203: Gate electrode 301: Through hole 302: Metal diffusion prevention film 303: Conductor 304: Back electrode X, Y, Z: Axis directions

Claims

1. A semiconductor device comprising: a Si substrate; a back electrode disposed below the Si substrate; a SiC layer disposed above the Si substrate; a semiconductor layer disposed above the SiC layer and composed of a group III nitride semiconductor; a source electrode and a drain electrode disposed above the semiconductor layer; a gate electrode in contact with the semiconductor layer; an intermediate layer disposed at least in an opening in the SiC layer; a metal layer disposed above the opening; and a conductor disposed inside a through-hole penetrating the intermediate layer and the Si substrate, and electrically connected to the back electrode and the metal layer, wherein the metal layer covers the through-hole, and the intermediate layer is disposed between the SiC layer and the conductor, wherein the intermediate layer is a metal nitride layer or a silicon oxide layer.

2. The semiconductor device of claim 1, wherein the Vickers hardness of the aforementioned intermediate layer is above 9.8 GPa and less than 23 GPa.

3. A semiconductor device comprising: a Si substrate; a back electrode disposed below the Si substrate; a SiC layer disposed above the Si substrate; a semiconductor layer disposed above the SiC layer and made of a group III nitride semiconductor; a source electrode and a drain electrode disposed above the semiconductor layer; a gate electrode in contact with the semiconductor layer; an intermediate layer disposed at least in an opening in the SiC layer; a metal layer disposed above the opening; and a conductor disposed inside a through-hole penetrating the intermediate layer and the Si substrate, and electrically connected to the back electrode and the metal layer, wherein the metal layer covers the through-hole, the intermediate layer is disposed between the SiC layer and the conductor, and the Vickers hardness of the intermediate layer is 9.8 GPa or more and less than 23 GPa.

4. The semiconductor device of any one of claims 1 to 3, wherein the inner diameter of the aforementioned through hole decreases monotonically from the bottom to the top of the aforementioned through hole.

5. The semiconductor device of any one of claims 1 to 3, wherein the aforementioned intermediate layer is composed of a group III nitride semiconductor.

6. The semiconductor device of claim 5, wherein the upper surface of the aforementioned intermediate layer and the upper surface of the aforementioned semiconductor layer are substantially on the same horizontal plane.

7. The semiconductor device of any one of claims 1 to 3, wherein the aforementioned metal layer comprises at least one selected from Cu, Au, Pt, Ni, and Mo.

8. The semiconductor device according to any one of claims 1 to 3, wherein the aforementioned metal layer comprises at least one selected from W, Ti, and Ta.

9. A semiconductor device according to any one of claims 1 to 3, wherein the aforementioned metal layer is electrically connected to the aforementioned source electrode.

10. A semiconductor device according to any one of claims 1 to 3, wherein the aforementioned source electrode is disposed on the source region in the aforementioned semiconductor layer, and the aforementioned through-hole is disposed in the aforementioned source region.

11. The semiconductor device of any one of claims 1 to 3, wherein the lowermost extent of the aforementioned metal layer is longer than the uppermost opening extent of the aforementioned through-hole.

12. The semiconductor device of any one of claims 1 to 3 further comprises a metal diffusion prevention film covering the side of the aforementioned through-hole.

13. A method for manufacturing a semiconductor device, comprising forming a SiC layer above a Si substrate, forming a semiconductor layer composed of a group III nitride semiconductor above the SiC layer, forming an opening in the opening of the SiC layer, forming an intermediate layer in the opening, forming a source electrode, a drain electrode and a gate electrode above the semiconductor layer, forming a metal layer above the opening to cover at least a portion of the intermediate layer, forming a through hole through the Si substrate and the intermediate layer from the lower side of the Si substrate using the metal layer as a stop, forming a conductor inside the through hole, forming a back electrode below the Si substrate, electrically connecting the back electrode and the metal layer through the conductor, and the intermediate layer being disposed between the SiC layer and the conductor, wherein the intermediate layer is a metal nitride layer or a silicon oxide layer.

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