Computer implemented method for defect recognition in an imaging dataset of a wafer, corresponding computer readable-medium, computer program product and systems making use of such methods

Abstract

The present invention relates to a computer-implemented method for defect identification in an imaging dataset of a wafer in a charged particle beam system (78) containing an embedded system (50). The method comprises: i) acquiring an imaging dataset of a wafer; ii) acquiring model data (44, 44', 44") of a model architecture (42) for a machine learning model (40, 40', 40") for defect identification in the imaging dataset of the wafer, the model architecture (42) being implemented in the embedded system (50); iii) transferring the model data (44, 44', 44") to a programmable memory (48, 48', 48") of the embedded system (50); iv) applying the machine learning model (40, 40', 40") to an imaging dataset of the wafer to identify multiple defects, comprising executing the embedded system to implement the model architecture (46) using the transferred model data (44, 44', 44").

Description

Computer-implemented method for defect identification in wafer imaging data, corresponding computer-readable medium, computer program product, and system utilizing the method The present invention relates to systems and methods for quality control and quality assurance of semiconductor structures, and more particularly, to computer-implemented methods, computer-readable media, and corresponding systems for defect identification in imaging datasets of wafers with increased throughput. The methods, computer-readable media, and systems are implemented based on general machine learning models in embedded systems. These methods can be used for quantitative metrology, defect identification, defect detection, defect classification, defect localization, or defect review of integrated circuits within semiconductor wafers, or for process monitoring, process improvement, quality control, or quality assurance during semiconductor wafer production. [Related Applications] This application claims priority from German patent application No. 10 2022 124 580.2, filed on September 23, 2022, which is hereby incorporated by reference in its entirety. Semiconductor manufacturing involves performing extremely precise operations, such as etching, on materials like silicon and oxides in the nanometer range. Therefore, quality management processes, including quality assurance and quality control, are crucial to ensuring high quality standards for manufactured wafers. Quality assurance refers to a series of activities that ensure high-quality products by preventing any defects that may arise during the development process. Quality control refers to a system for checking the final quality of the product. Quality control is part of the quality assurance process. Wafers made of thin silicon wafers serve as substrates for microelectronic devices, including semiconductor structures built within and on the wafers. Semiconductor structures are built layer by layer using repetitive processing steps involving repeated chemical, mechanical, thermal, and optical processes. The size, shape, and layout of semiconductor structures and patterns are subject to various influences. For example, in the fabrication of 3D memory devices, etching and deposition are currently the key processes. Other related process steps, such as lithography and implantation, also affect the characteristics of integrated circuit components. As a result, the fabricated semiconductor structures contain rare and unique defects. Equipment used for quantitative metrology, defect detection, and defect review detects these defects. These equipment are not only required during wafer fabrication. Optimizing production process parameters is difficult due to the complexity and high nonlinearity of the process. As a remedy, an iterative approach called process window qualification (PWQ) can be applied. In each iteration, test wafers are fabricated using the currently optimized process parameters, and different dies on the wafer are exposed to different manufacturing conditions. By detecting and analyzing defects in various molds based on quality assurance processes, optimal manufacturing process parameters can be selected. This allows production process parameters to be adjusted to achieve optimal conditions. High-precision quality control processes and equipment are then required to measure the semiconductor structures within the wafer. Therefore, identified defects can be used for root cause analysis. They can serve as feedback for improving process parameters such as exposure time and focus variation during quality assurance, or they can be used to ensure the quality of manufactured wafers during quality control. For example, bridging defects may indicate under-etching, broken lines may indicate over-etching, persistent defects may indicate a defective mask, and missing structures may indicate suboptimal material deposition. The semiconductor structures produced are based on prior knowledge. They are fabricated from a series of layers parallel to the substrate. For example, in logic-type samples, metal lines run parallel within the metal layers or in high-aspect-ratio (HAR) structures, and metal vias run perpendicular to the metal layers. The angles between metal lines in different layers are either 0° or 90°. On the other hand, for VNAND-type structures, it is known that their cross-section is, on average, circular. Furthermore, semiconductor wafers have a diameter of 300 mm and consist of a plurality of so-called dies, each containing at least one integrated circuit pattern, such as for a memory chip or a processor chip. During the manufacturing process, the semiconductor wafer undergoes approximately 1,000 process steps, and approximately 100 or more parallel layers are formed within the semiconductor wafer, including transistor layers, layers between the lines, and interconnect layers, as well as a 3D array of multiple memory cells in a memory device. The aspect ratio and number of layers in integrated circuits continue to increase, and structures are evolving into the third (vertical) dimension. Memory stacks now exceed tens of microns in height. In contrast, feature sizes are shrinking. Minimum feature sizes, or critical dimensions, are below 10 nm, for example, 7 nm or 5 nm, and in the near future, feature sizes will approach below 3 nm. While the complexity and size of semiconductor structures are growing in the third dimension, the lateral dimensions of integrated semiconductor structures are shrinking. Consequently, high-precision measurement of the shape, size, orientation, and stacking of 3D features and patterns becomes challenging. The lateral measurement resolution of charged-particle systems is typically limited by the sampling raster at each image point, or the dwell time per pixel on the sample, and the charged-particle beam diameter. The sampling raster resolution can be set within the imaging system and adapted to the charged-particle beam diameter at the sample. Typical raster resolutions are 2 nm or less, but the raster resolution can be reduced without physical limitations. The charged-particle beam diameter has limitations, depending on the beam operating conditions and lensing. Beam resolution is limited to approximately half the beam diameter. The lateral resolution may be below 2 nm, for example even below 1 nm. A key task in semiconductor inspection is determining a specific set of parameters of semiconductor objects, such as high aspect ratio (HAR) structures within the inspection volume. These parameters can include size, area, shape, or other measurement parameters. Conventional measurement techniques typically involve multiple computational steps, including object detection, feature extraction, and any type of metrology, such as calculating distance, radius, or area based on the extracted features. Each of these numerous steps requires significant computational effort. Semiconductors typically contain numerous repetitive three-dimensional structures. During process development, selected physical or geometric parameters of these representative three-dimensional structures must be measured with high accuracy and throughput. To monitor the process, an inspection volume is defined, encompassing these representative three-dimensional structures. This inspection volume is then analyzed, for example, using a slicing and imaging method. This generates a high-resolution 3D volumetric image of the inspection volume, obtained by slicing and imaging multiple cross-sections within the inspection volume. The multiple repetitive 3D structures within the examination volume can exceed hundreds or even thousands of individual structures. This results in a large number of cross-sectional images, e.g., studying at least 100 3D structures through 100 cross-sectional image slices, and the number of measurements to be performed can easily reach 10,000 or more. Furthermore, current technologies such as multibeam scanning electron microscopy (multibeam SEM) can be used to image large areas of the wafer surface with high resolution in a short time. To do this, multibeam SEM uses multiple parallel individual beams, each covering a separate portion of the surface with pixel sizes as small as 2nm. The resulting data sets are so large that manual analysis is impossible. To analyze large amounts of data that require a large number of measurements, machine learning methods can be used. These are suitable for analyzing large amounts of data while limiting user interaction to a minimum. Machine learning is a field of artificial intelligence. Machine learning methods typically use training data consisting of a large number of examples to build a parametric machine learning model. After training, the method is able to generalize the knowledge gained from the training data to new, previously unseen examples, thereby enabling predictions on new data. There are many different machine learning methods, such as linear regression, k-means, neural networks, and deep learning methods. Deep learning is a type of machine learning that mimics the human brain, using artificial neural networks with multiple hidden layers between the input and output layers. This extensive internal structure enables the network to extract progressively higher-level features from the raw input data. Each level learns to transform its input data into a slightly more abstract and complex representation, thereby capturing both low-level and high-level knowledge from the training data. Hidden layers can have different sizes and perform various functions, such as convolutional layers, pooling layers, or fully connected layers. In the quality control and quality assurance process, algorithm speed is a key factor in achieving high wafer throughput. To achieve high-speed algorithms, embedded systems can be used to implement machine learning models for quality assurance and quality control of acquired wafer imaging datasets. For example, US 2021 / 0097673 A1 and US 2021 / 0158498 A1 both disclose machine learning models for defect identification in wafer imaging datasets, which can be implemented using embedded systems such as FPGAs. For software running on traditional processors, many pre-programmed libraries are available to minimize programming effort and time. However, this is not the case for embedded systems. Furthermore, every software update requires reprogramming the embedded system. Therefore, programming embedded systems requires significant programming effort and time. Therefore, it is an object of the present invention to provide a method for obtaining a machine learning model on an embedded system. The machine learning model is reusable and versatile for different use cases or varying imaging datasets. Another object of the present invention is to program a machine learning model on an embedded system for use on wafer imaging datasets, reducing the effort, time, and resources required for defect identification. Another object of the present invention is to reduce the computation time of the machine learning model. Another object of the present invention is to adapt the machine learning model on the embedded system to a wafer quality control or quality assurance process. Another object of the present invention is to increase the yield during the wafer quality control or quality assurance process. Another object of the present invention is to minimize the run time of the wafer quality control or quality assurance process. In general, it is an object of the present invention to provide a high-throughput and high-accuracy wafer inspection method for measuring semiconductor structures in an inspection volume. It is an object of the present invention to provide a universal wafer inspection method for measuring semiconductor structures in an inspection volume that can quickly adapt to changes in the measurement effort, measurement system, or semiconductor object of interest. Another object of the present invention is to provide a fast, robust, and reliable measurement method for a set of parameters describing a semiconductor structure in an inspection volume that has high accuracy and reduced measurement artifacts. Finally, it is an object of the present invention to implement new business models for selling systems related to machine learning algorithms. These objects are achieved by the invention specified in the independent claims. Advantageous embodiments and further developments of the invention are described in detail in the dependent claims. Embodiments of the present invention relate to computer-implemented methods, computer-readable media, and systems for implementing a machine learning model for defect identification in wafer imaging datasets on an embedded system. A first embodiment relates to a computer-implemented method for defect identification in an imaging dataset of a wafer in a charged particle beam system including an embedded system. The method comprises: i) obtaining an imaging dataset of a wafer; ii) obtaining model data for a model architecture of a machine learning model for defect identification in the imaging dataset of the wafer, the model architecture being implemented in the embedded system; iii) transferring the model data to a programmable memory of the embedded system; and iv) applying the machine learning model to the imaging dataset of the wafer to identify a plurality of defects, comprising executing the embedded system-implemented model architecture using the transferred model data. The identified defects can, for example, be used in a quality assurance system and / or quality control system, particularly for wafers, but also for other manufactured items. A machine learning model is the result of running a machine learning method on training data. This model represents what has been learned through the machine learning method. It includes the model architecture, model data, and prediction methods. Model architecture includes so-called hyperparameters that define the design or structure of a machine learning model. These hyperparameters are typically not learned from the training data. For example, hyperparameters can be user-defined or obtained through AutoML methods. Hyperparameters for neural networks include, for example, the number of layers, layer sizes, filter types, optimizers, upsampling schemes, etc. Hyperparameters for decision trees include, for example, the number of tree levels and the number of decision nodes at each level. Hyperparameters for support vector machines include, for example, the number and format of hyperplanes. Hyperparameters for clustering methods include, for example, the number of clusters. Model data includes the rules, values, or any other method-specific data structure needed to make predictions about new data samples. Model data is learned from training data. For example, the model data for a neural network includes weights learned from the training data. For example, the model data for a decision tree includes the specific decisions taken at each node learned from the training data. For example, the model data for a support vector machine includes matrices and vectors defining a specific hyperplane learned from the training data. For example, the model data for a clustering method includes the specific cluster positions learned from the training data. Prediction methods are processes that dictate how model data are used to make predictions about new data. Applying a prediction method to an imaging dataset involves applying a machine learning method or model to the dataset, based on a trained model that includes the model architecture and the model data. Because the model architecture is separated from the learned model data, it can be implemented on embedded systems with low runtime and high throughput. Furthermore, the learned model data in the embedded system's programmable memory can be dynamically updated. This allows machine learning models on embedded systems to be adapted to different use cases or retrained, for example, on different imaging datasets. This can occur, for example, if image acquisition conditions change or the imaging dataset is modified. This also reduces the user's implementation workload. A second embodiment of the present invention relates to a computer-implemented method for defect identification in an imaging data set of a wafer in a charged particle beam system containing an embedded system, the method comprising: i) obtaining an imaging data set of a wafer; ii) defining, on at least one of the embedded systems, an embedded system implementation model architecture of a machine learning model for defect identification in the imaging data set of the wafer by specifying a data flow through some of a plurality of logic block circuits, wherein the plurality of logic block circuits comprise one or more modules of at least one model architecture of the at least one machine learning model for defect identification; iii) obtaining model data for the embedded system implementation model architecture; iv) transferring the model data to a programmable memory of the embedded system; v) applying the machine learning model to an imaging data set of a wafer to identify a plurality of defects, which comprises executing the embedded system implementation model architecture using the transferred model data. The identified defects can, for example, be used in quality assurance and / or quality control systems, particularly for wafers, but also for other manufactured objects. The modularity of the model architecture makes implementing machine learning models on embedded systems more flexible and versatile, as different modules can be combined to form new model architectures, and previously implemented modules can be reused for different model architectures. This allows for dynamic modification of model data and model architectures or adaptation to different use cases without requiring extensive implementation effort. As used herein, the term "plurality" of an element refers to a single, a plurality of, or all elements. In an example of the first or second embodiment, the machine learning model for defect identification of an imaging data set of a wafer comes from a group including a defect detection model, a defect classification model, a defect localization model, a defect segmentation model, anomaly detection model, anomaly detection model, anomaly classification model, anomaly localization model, and anomaly segmentation model. An anomaly is a deviation in a semiconductor structure from previously defined specifications. Generally speaking, a defect is also a type of anomaly, but not all anomalies are defects. For example, an anomaly can appear due to noise or rare structures in an imaging dataset. Charged particle beam systems include, but are not limited to, scanning electron microscopes (SEMs), focused ion beam microscopes, such as helium ion microscopes. Another example of a charged particle beam system is a corrected electron scanning microscope, which includes correction means for correcting chromatic and spherical aberrations. In various embodiments of the present invention, the embedded system may be a field programmable gate array (FPGA), a digital signal processor (DSP), an arithmetic logic unit (ALU), an application specific integrated circuit (ASIC), etc. In various embodiments of the present invention, the machine learning model used to identify defects in the acquired wafer imaging data set may come from a combination of the following: a defect detection model, a defect classification model, a defect localization model, a defect segmentation model, an anomaly detection model, an anomaly classification model, an anomaly localization model, and an anomaly segmentation model. In an example of the second embodiment, at least one model architecture of the at least one machine learning model for defect identification includes a model architecture of a neural network. According to one aspect of an example of the second embodiment, one or more modules are head-end modules, and a head-end module is a module including an output layer of a neural network. For example, one or more head-end modules may include a fully connected output layer of a neural network and / or a convolutional output layer of a neural network. In addition, one or more modules are tail modules. A tail module is a module containing multiple hidden layers of a neural network. In one example, at least one tail module, and in particular each tail module, includes all hidden layers of a neural network. In another example, at least one tail-end module, and in particular each tail-end module, includes multiple hidden layers forming a semantic entity. The term "semantic entity" refers to multiple hidden layers forming a functional unit, in a sense that they complement each other and jointly perform a specific function in the neural network. Subdividing the model architecture into head-end and tail-end modules significantly reduces user programming and application workload. The head-end module contains the neural network's output layer and is therefore task-specific. By replacing the head-end module, the neural network's operation can be modified. For example, a defect detection model architecture with a convolutional output layer can become a defect classification model architecture with a fully connected output layer. The tail modules include multiple hidden layers of a neural network. By swapping tail modules, the sizes of the hidden layer feature maps can be easily adjusted between small-scale problems and large-scale problems requiring fewer or more features, producing satisfactory results. Therefore, according to another aspect of the second embodiment, at least two tail modules include the same number of hidden layers, where the sizes of the feature maps of the corresponding hidden layers differ by the same factor. According to another aspect of an example of the second embodiment, each of the one or more modules is a head-end module including an output layer of a neural network or a tail-end module including a plurality of hidden layers of a neural network. A headend module and a tailend module can be generated from a neural network by dividing the neural network into an output layer and a set of one or more hidden layers. The one or more modules are generated from at least one model architecture of the neural network by dividing each model architecture into the headend module containing the output layer of the neural network and at least one tailend module containing multiple hidden layers of the neural network. In particular, each model architecture of the neural network can be divided into a task-specific headend module and a single tailend module, making it possible to specify the data flow through multiple modules with minimal effort. In an example of the second embodiment, the method further includes determining whether the model architecture of the machine learning model is implementable by the plurality of logic block circuits on one of the at least one embedded system before specifying the data flow through the plurality of logic block circuits; and in response to determining that the model architecture is not implementable, generating the one or more modules of the model architecture of the machine learning model and implementing the one or more modules on one of the at least one embedded system. In this way, the number of modules and model architectures implemented by embedded systems can grow with the number of use cases, and the system becomes increasingly flexible and versatile. In one example of the first or second embodiment, the model data for the embedded system implementing the model architecture is obtained by training a machine learning model containing the model architecture. Additionally or alternatively, the model data for the embedded system implementing the model architecture can be loaded from a database. Additionally or alternatively, the model data for the embedded system implementing the model architecture can also be provided by an external service that generates a new business model. The new business model provides a one-time sale of a system having an embedded system implementing the model architecture, and periodic updates of the model data as a service, for example, to improve defect identification results or adapt the system to different use cases. In one example of the first or second embodiment, the model data is transferred to the programmable memory of the embedded system by copying. Alternatively, the model data is transferred to the programmable memory of the embedded system by replacing the hardware block containing the programmable memory of the embedded system with a new hardware block containing the model data to be transferred. In any example or aspect of the first or second embodiment, identified defects may be monitored in real time or in a buffered manner for quality assurance or quality control purposes. For this purpose, the identified defects may be directed to a display device or a dashboard. Additionally or alternatively, the identified defects may be stored in long-term memory. Additionally or alternatively, the identified defects may be cached in a memory. The identified defects may be analyzed to update the embedded system implementation model architecture in step ii). The third embodiment of the present invention is about the computer implementation method of any one of the aspects and examples of the first or second embodiment of the present invention, further including performing the following steps before obtaining the imaging data set of the wafer in step i): iterating the following steps until a convergence criterion is met: selecting at least one image capture parameter according to an image sampling strategy, and capturing the imaging data set of the wafer based on the at least one image capture parameter; generating training data from the captured imaging data set of the wafer; selecting a model architecture and training the relevant machine learning model based on the generated training data; determining the quality of the model architecture and the at least one image capture parameter by calculating an objective function value associated with an objective function for evaluating the quality of the trained machine learning model; after the iterations: selecting one of the model architectures and the corresponding at least one image capture parameter based on the objective function values, wherein the imaging data set of the wafer in step i) is obtained based on the selected at least one image capture parameter, and the embedded system implementation model architecture in step ii) includes the model architecture of the selected machine learning model. In this way, the image acquisition process is optimized according to criteria defined by the objective function, such as the system's throughput, the runtime of the defect recognition method, or the system's power consumption. A fourth embodiment of the present invention relates to a computer-implemented method for defect identification in an imaging data set of a wafer, the method comprising: iterating the following steps until a convergence criterion is met: selecting at least one image capture parameter according to an image sampling strategy, and capturing the imaging data set of the wafer based on the at least one image capture parameter; generating training data from the captured imaging data set of the wafer; selecting a model architecture and training a related machine learning model based on the generated training data; evaluating the quality of the trained machine learning model by calculating a related objective function value of an objective function; after the final iteration: selecting one of the trained machine learning models based on the objective function values; and applying the selected trained machine learning model to the imaging data set of the wafer captured based on the corresponding at least one image capture parameter to identify defects. According to the third or fourth embodiment, the at least one image acquisition parameter is, for example, selected from the group consisting of imaging time, image resolution, pixel size, impact energy, and electron wave dwell time. In one example of the third or fourth embodiment, the step of selecting a model architecture includes selecting at least one hyperparameter defining the model architecture of the machine learning model based on a architecture sampling strategy, such as through automated machine learning (AutoML) techniques. This process is advantageous because the image acquisition process is jointly optimized with the machine learning model hyperparameters with respect to the objective function. In one example of the third or fourth embodiment, the objective function includes a measure of the complexity of the model architecture. In another example, the objective function includes a measure of runtime and / or throughput during defect identification and / or a measure of data rate and / or power consumption. In another example, the objective function includes a quality measure of defect identification. In another example, the objective function includes a measure of the number of bits of input data to the machine learning model. Selecting one or more of these metrics in the objective function can reduce architectural complexity, thereby shortening system runtime or increasing system throughput. Any aspect or example of the embodiment further includes determining one or more measurements of the defects identified in the imaging data set of the wafer, particularly the size, area, dimensions, shape parameters, distance, radius, aspect ratio, type, number of defects, density, spatial distribution of defects, presence of any defects (i.e., whether a defect is detected), and the like. Based on the one or more measurements, this example may further include evaluating the quality of the wafer based on the one or more measurements and at least one quality assessment rule. Based on the one or more measurements, this example may include controlling at least one wafer process parameter based on the one or more measurements of the defects identified in the imaging data set of the wafer. Wafer process parameters include, but are not limited to, exposure time, etching, deposition, implantation, thermal treatment, and other process parameters related to the process. Other defects are caused by defects or contamination from various sources, such as degradation of the lithography mask or particle contamination. The present invention also relates to a computer-readable medium having stored thereon a computer program executable by a computer device, the computer program comprising program codes for executing any one of the aspects or examples according to the embodiments. The present invention also relates to a computer program product comprising a plurality of instructions, which, when executed by a computer, causes the computer to perform the method according to any one of the aspects or examples of the embodiments. The present invention also relates to a system for controlling the quality of a plurality of wafers produced in a semiconductor manufacturing facility, the system comprising: an imaging device adapted to provide an imaging data set of a wafer; one or more processing devices; optionally, at least one embedded system; and one or more machine-readable hardware storage devices comprising a plurality of instructions executable by the one or more processing devices to perform a plurality of operations comprising a method for evaluating the quality of the wafers. The present invention also relates to a system for controlling a plurality of wafers produced in a semiconductor manufacturing plant, the system comprising: a component for producing the wafers controlled by at least one process parameter; an imaging device adapted to provide an imaging data set of a wafer; one or more processing devices; optionally, an embedded system implementing a model architecture of a machine learning model or a module thereof for defect identification in the imaging data set of the wafers, the embedded system comprising a programmable memory for transmitting the model data to the embedded system; one or more machine-readable hardware storage devices comprising a plurality of instructions executable by the one or more processing devices to perform a plurality of operations comprising a method for controlling at least one wafer process parameter. Any of the above systems may include a database, a display device and / or a user interface. Although examples and embodiments of the present invention are described with respect to semiconductor wafers, it should be understood that the present invention is not limited to semiconductor wafers, but can also be applied to reticles or masks used in semiconductor manufacturing or other manufactured articles. The present invention described using examples and embodiments is not limited to the embodiments and examples, but can be implemented by a person skilled in the art through various combinations or modifications of the embodiments and examples. Advantageous exemplary embodiments of the present invention will be described below and schematically illustrated in the accompanying drawings. Throughout the drawings and description, the same reference numerals are used to describe the same features or components. Figure 1 shows schematic cell structures 10, 10', 10" of imaging datasets 12, 12', 12" of three defect measurement locations on wafer 226. In this schematic, cells 14, 14', 14" are identical and regularly distributed across each imaging dataset 12, 12', 12". Cell structures 10, 10', 10" contain defects 16, such as "opens," "dwarfs," or "merges," i.e., deviations of the semiconductor structure from previously defined specifications. Identifying defects 16 in imaging datasets 12, 12', 12" of wafer 226 is crucial for quality control and quality assurance processes. Quality assurance is the process of ensuring that wafer manufacturing methods, technologies, techniques, and processes are implemented as required. It aims to improve parameters or conditions in laboratory wafer production processes, such as deposition, exposure, and etching. To achieve this, both known and unknown defects must be identified and analyzed. In contrast, quality control aims to ensure the quality of the final manufactured product during in-line processing. To do this, known defects must be identified and analyzed. Large amounts of data with a variety of known or unknown defects that require only limited user interaction can be processed using machine learning models. A machine learning model is the result of running a machine learning method on training data. It represents what has been learned through the machine learning method. It consists of the model architecture, model data, and prediction method. The model architecture comprises the general structure or design of the machine learning model, defined by hyperparameters, such as the neurons in a neural network and the connections between them. Model data consists of values, numbers, or any other method-specific data structure that materializes the generalized structure to solve a specific machine learning problem and make predictions about new data samples, such as the weights in a neural network. The prediction method is the process that dictates how to use the model data to make predictions about new data, such as the forward pass algorithm in a neural network. Applying a machine learning method or machine learning model to data means applying a prediction method based on the trained model to the data. The machine learning model in each embodiment of the present invention may be any type of machine learning model, including but not limited to a decision tree-based model, a linear regression-based model, a neural network-based model, a Bayesian network-based model, a support vector machine-based model, and a nearest neighbor-based model, etc. The machine learning model provided may also be a combination of different types of models. In addition, the model can be provided in any type of format. For example, a typical model such as AlexNet, GoogleNet, ResNet, DenseNet or other types of neural network formats may be used to provide a neural network model. However, in various embodiments, the type and format of the model are not limited to the above. Although the model may be preprocessed and trained in some embodiments, preprocessing is not required in other embodiments. Trained models may also be loaded from one or more archives. For example, a decision tree is a machine learning model that contains a model architecture in the form of a tree of if-then statements. The hyperparameters of the decision tree model architecture define the tree's structure, including, for example, the number of levels and the number of decision nodes. A decision tree contains model data in the form of specific values ​​for the if-then statements, as well as a prediction method that defines how to apply the if-then statements to the input data. A support vector machine (SVM) is a machine learning model that includes a model architecture in the form of at least one hyperplane. The hyperparameters of the SVM model architecture define the at least one hyperplane, including the number and format of the hyperplanes. The SVM includes model data in the form of matrices, vectors, or values ​​that define a particular hyperplane, and a prediction method based on assigning output values ​​defined by the at least one hyperplane to input data. A neural network is a machine learning model that contains a model architecture in the form of a graph structure. The hyperparameters of a neural network model architecture define the generalized structure or structure of the neural network, including the topology and size of the neural network. Examples include: the type and / or parameters of the loss function, bottleneck size, bottleneck filter size (the number of features in the bottleneck), initial filter size (the number of filters in the first layer of the network, with other network features scaled to the first layer), initial learning rate, learning rate decay factor, momentum utilization, number of epochs, regularization scale, size and content of the training set (number of images), type of convolution used, upsampling scheme, connections between layers, number of layers in the model, number of samples representing the dataset, size of layers in the model, type of layers in the model, filter size, dropout rate, kernel size of convolutional layers, utilization of Nesterov gradient acceleration, type of optimization algorithm, and more. The model data for a neural network includes model weights, which are vectors or matrices containing specific values ​​that define the transfer functions of hidden layer neurons. A neuron's transfer function converts its input data into output data, which is then passed to one or more other neurons in the neural network. Transfer functions include, for example, sigmoid functions, step functions (thresholds), piecewise linear functions, Gaussian functions, or combinations thereof. The prediction method for a neural network defines the forward propagation of input data through the network to obtain a result. Hyperparameters of the model architecture of a machine learning model are typically not learned from data. Instead, they can be selected by an expert or optimized automatically, for example, in the case of neural networks, using AutoML techniques, in particular Neural Architecture Search (NAS) methods. These techniques automatically search for optimal hyperparameter values ​​for the model architecture of a machine learning model. Based on a set of objective functions that evaluate the quality of hyperparameter values, AutoML techniques typically follow the following iterative principle: predicting at least one hyperparameter value based on previously selected hyperparameter values ​​and associated values ​​of the objective function; building the model architecture of the machine learning model based on the selected hyperparameter value and training the machine learning model based on the training data; evaluating the objective function based on the at least one hyperparameter predicted by the trained machine learning model; and, after the final iteration, selecting at least one hyperparameter value that yields the best value of the objective function. Instead, model data, such as the weights of a neural network, is learned from training data. Hyperparameters of a machine learning model's learning algorithm generally have no effect on the performance of the model architecture, but they do affect the speed and quality of the learning process. Examples of algorithmic hyperparameters include the learning rate and the minimum batch size. Both quality assurance and quality control processes require that defects be identified as accurately and quickly as possible to achieve high throughput or low algorithm runtime. For example, the system throughput can be measured by the wafer area inspected at a known resolution within a specific time span, or the time required to inspect a specific area of ​​the wafer given a known time span, e.g., a 1cm2 area with 1nm resolution can be processed in 24 hours. 2 wafer. To meet the high runtime requirements, embedded systems are often chosen for digital data processing. However, using embedded systems requires extensive design and configuration work, as the pre-programmed libraries commonly found in conventional processors are not suitable for embedded system programming. Given these limitations, various embodiments of the present invention are directed to a novel approach for implementing machine learning models in embedded systems. This approach leverages the specific structure of the machine learning model defined above, comprising a general model architecture and use case-specific model data. By implementing only the model architecture of the machine learning model on the embedded system and dynamically loading the learned model data into the embedded system's programmable memory, the implemented machine learning model architecture can be reused for another use case or retrained on a different imaging dataset, thereby saving resources, user effort, and computational time. The overall method of the first embodiment of the present invention is shown in FIG2. FIG2 is a flowchart of steps in an exemplary computer-implemented method 22 for performing defect identification in an imaging data set 12, 12', 12" of a wafer 226 in a charged particle beam system 78 including an embedded system 50, 50', the method comprising: obtaining the imaging data set 12, 12', 12" of the wafer 226 in an imaging step 26; obtaining model data 44, 44', 44" of a model architecture 42 for a machine learning model 40, 40', 40" for defect identification in the imaging data set 12, 12', 12" of the wafer 226; Specifically, in a model data step 28, the model architecture 42 is implemented in the embedded system 50, 50'; in a model data transfer step 30, the model data 44, 44', 44" is transferred to the programmable memory 48, 48', 48" of the embedded system 50, 50'; and the machine learning model 40, 40', 40" is applied to the imaging dataset 12, 12', 12" of the wafer 226 to identify defects 16, including executing the model architecture 46 implemented by the embedded system using the transferred model data 44, 44', 44" in an apply step 32. The identified defects 16 can be used, for example, in the quality assurance system 228, 234 and / or the quality control system 212, 232, particularly for the wafer 226, but also for other manufactured items. These steps can be repeated if a new use case 34 is defined or the model architecture or model data is updated. FIG3 illustrates the flexible implementation of machine learning models 40, 40′, 40″ in an embedded system 50 by partitioning the model architecture 42 and model data 44, 44′, 44″. The three machine learning models 40, 40′, 40″ include the same model architecture 42 but different model data 44, 44′, 44″. For example, three different use cases for neural networks with three different sets of weights can be implemented in the embedded system 50 by implementing the model architecture 42 in the embedded system 50 to generate an embedded system-implemented model architecture 46, and by transferring the corresponding model data 44, 44′, 44″ to the programmable memory 48 of the embedded system 50. In this way, different use cases can be easily implemented in the embedded system 50. Similarly, adaptation or improvement of the model data 44 of the machine learning model 40 is easily implemented. For example, when improved model data 44', 44" is available, such as by retraining the machine learning model 40, or when the requirements of the machine learning model 40 change, such as when an unknown defect appears in the image dataset 12, 12', 12" and the machine learning model 40 must be retrained, the new model data 44', 44" can be easily transferred to the programmable memory 48 of the embedded system 50. Due to the embedded system implementation of the machine learning model 40, implementation workload and time can be saved, while improving output and reducing running time. In one example, wafer 226 includes different measurement sites with different semiconductor structures to be investigated. Using the method according to the first embodiment, during inspection of wafer 226, a first defect inspection task, using a first imaging dataset 12 obtained at a first measurement site, can be quickly switched to a second defect inspection task, using a second imaging dataset 12' obtained at a second measurement site on wafer 226. During inspection of wafer 226, first predefined model data 44 is retrieved from the memory of charged particle beam system 78 and transferred to programmable memory 48 of embedded system 50 for performing the first defect inspection task. During inspection of wafer 226, second predefined model data 44' is retrieved from the memory of charged particle beam system 78 and transferred to programmable memory 48 of embedded system 50 for performing the second defect inspection task. In one example, a third defect inspection task, using a third imaging dataset 12'' obtained at a third measurement site on wafer 226, is added to the inspection of wafer 226. For the third defect inspection job, a third model data 44″ is determined for the model architecture 42 implemented in the embedded system 50. An example of the third model data 44″ for determining the new defect inspection job is further described below in the third embodiment. The newly determined third model data 44″ is stored in the memory of the charged particle beam system 78 and the newly determined third model data 44″ is transmitted to the programmable memory 48 of the embedded system 50 for performing the third defect inspection job. The model data 44, 44′, 44″ are stored in the memory of the charged particle beam system 78 and are associated with different defect inspection jobs corresponding to different imaging data sets 12, 12′, 12″ obtained by the charged particle beam system 78 at different measurement positions on the wafer 226. The flexibility and modularity of this approach are further enhanced by subdividing the model architecture into multiple FPGA-implemented modules, which can be combined to form different types of machine learning architectures. The overall method of the second embodiment of the present invention is shown in FIG4 . FIG4 is a flowchart illustrating steps in an exemplary computer-implemented method 52 for performing defect identification in an imaging data set 12, 12′, 12″ of a wafer 226 in a charged particle beam system 78 comprising at least one embedded system 50, 50, the method comprising: obtaining the imaging data set 12, 12′, 12″ of the wafer 226 in an imaging step 56; defining an embedded system-implemented model architecture 46 of a machine learning model 40, 40′, 40″ on one of the at least one embedded system 50, 50′ via a designated data stream 74 through a plurality of logic block circuits 72, 72′, 72″, 72″′, 74, 74″, 74″′ for defect identification in the imaging data set 12, 12′, 12″ of the wafer 226, wherein the plurality of logic block circuits 72, 72′, 72″, 72″′, 74, 74″, 74″′′, 74″′′, wherein the plurality of logic block circuits 72, 72′, 72′′, 72″′, 72″′′, 74″′ ... 72'', 72''', 74, 74', 74'', 74'' include one or more modules 102, 104 of at least one model architecture 42, at least one machine learning model 40, 40', 40'' is used for defect identification in the data flow specification step 58; in the model data step 60, model data 44, 44', 44'' of the embedded system implemented model architecture 46 is obtained; in the model data transmission step 62, the model data 44, 44', 44'' is transmitted to the programmable memory 48, 48', 48'' of the embedded system 50, 50'; the machine learning model 40, 40', 40'' is applied to the imaging data set 12, 12', 12'' of the wafer 226 to identify defects 16, including using the transmitted model data 44, 44', 44'' to execute the model architecture 46 implemented by the embedded system in the application step 64. The identified defects 16 may be used, for example, in the quality assurance system 115 and / or the quality control system 117, particularly for the wafer 226, but also for other manufactured objects. These steps may be repeated if new use cases 66 are defined or the model architecture or model data is updated. FIG5 illustrates a particularly flexible and versatile method for implementing a machine learning model 40 in a charged particle beam system 78 comprising two embedded systems 50, 50'. The embedded systems 50, 50' include modules of different model architectures, which are implemented by a plurality of logic block circuits 72, 72', 72", 72'", 74, 74', 74", 74'', respectively. To implement a particular model architecture 42 in the charged particle beam system 78, a plurality of logic block circuits 72', 72''' in one of the embedded systems 50 are selected, and the selected number of logic block circuits 72', 72''' in the embedded system 50 are interconnected. As previously described, the model data 44 can be transferred to the programmable memory 48' of the embedded system 50. In this way, the workload of implementing a machine learning model in the charged particle beam system 78 including the embedded system 50, 50' is reduced because not only the different model data 44, 44', 44", but also different model architectures 42 including various modules can be easily implemented by interconnecting a plurality of logic block circuits 72', 72'" corresponding to the modules of the model architecture 42. This is achieved due to the modular nature of the machine learning model combined with the dynamic reconfiguration possibilities provided by the embedded system. Whenever a new use case 34, 66 emerges, the machine learning model 40 can be retrained and the new model data 44', 44" can be transferred to the programmable memory 48, 48', 48" of the embedded system 50, 50' without having to modify the embedded system implementation model architecture 46. Due to the separation of the embedded system implementation of the model architecture 42 and the generation and transfer of the model data 40, 40', 40" to the programmable memory 48, 48', 48" of the embedded system 50, 50', the significant time and effort required to implement the machine learning model 40 on the embedded system 50, 50' is alleviated because the model data 44, 44', 44" can be easily exchanged in the event of a new use case 34, 66. In this way, embedded system programs for machine learning become more flexible, reusable, and versatile. At the same time, a new business model is enabled, in which the charged particle beam system includes at least one embedded system 50, 50', and the at least one embedded system 50, 50' includes an implemented model architecture 46, which includes a plurality of logic block circuits 72, 72', 72", 72''', 74, 74', 74'', 74''' implementation modules of the machine learning architecture that are sold only once to the customer, and the model data 44, 44'', 44''' can be updated regularly according to the contract, or whenever the use case or demand changes. Figure 6 illustrates the use of embedded systems 50, 50' in the form of FPGAs 51 for various use cases. An FPGA is an integrated circuit designed to be configured by the customer or designer after manufacturing. FPGA configuration is typically specified using a hardware description language. An FPGA consists of a series of programmable logic blocks and a hierarchy of reconfigurable interconnects that allow the blocks to be connected together. Logic blocks can be configured to perform complex combinational functions or act as simple logic gates such as AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete memory blocks. Many FPGAs can be reprogrammed to implement different logic functions, enabling flexible and reconfigurable computing. FPGA 51 includes adaptive logic modules 80, M512 blocks 82, M4K blocks 84, high-speed I / O channels 86 with dynamic phase alignment (DPA), I / O channels 88 with external memory interface circuitry, digital signal processing blocks 90, M-RAM blocks 92, and phase-locked loops 94. By simply exchanging the model data 44 , 44 ′, 44 ″ in the programmable memory 48 of the FPGA 51 , new use cases can be implemented in the same charged particle beam system 78 without the additional effort of reprogramming the FPGA 51 . The model data 44, 44', 44" of the FPGA-implemented model architecture 46 can be obtained in different ways. For example, the model data 44, 44', 44" of the FPGA-implemented model architecture 46 can be loaded from the database 225. The model data 44, 44', 44" of the FPGA-implemented model architecture 46 can also be obtained by training a machine learning model 40, 40', 40" comprising the model architecture 46. After training, the obtained model data 44, 44', 44" can be stored in the database 225 so that it can be used in further applications. In addition, the model data 44, 44', 44" can be provided by an external service, allowing dynamic updating of the model data 44, 44', 44", for example, in order to improve or adapt the model data 44, 44', 44" to modified requirements. Such a service can be used as a new business model, separating the hardware, including the embedded system with the implemented model architecture and the module, which is sold only once, from the model data that can be regularly updated. This saves time and effort and achieves a high degree of system flexibility. Since the embedded system 50, 50' is used to implement the machine learning model 40, 40', 40'', the quality of the defect identification method can be optimized, while maximizing the output and reducing the running time. In the examples of the first or second embodiment of the present invention, the model data 44, 44', 44" can be transferred to the programmable memory 48, 48', 48" of the embedded system 50, 50' by copying. Alternatively, the model data 44, 44', 44" can be transferred to the programmable memory 48, 48', 48" of the embedded system 50, 50' by replacing the hardware block containing the programmable memory 48, 48', 48" of the embedded system 50, 50' with a new hardware block containing the model data 44, 44', 44" to be transferred. In order to provide the defect identification results to the user for quality assessment or quality control, the identified defects 16 can be directed to a display device 227 or a dashboard, for example, thereby allowing real-time monitoring of the detected defects 16. In another example of the first or second embodiment, the identified defects 16 can be stored in a long-term memory for further analysis, for example for generating statistics about the defects 16. In another example, the identified defects can be cached to a specified time span in the memory, for example 48 hours, to allow further analysis of the detected defects 16, but without requiring a large amount of memory. In another example, the identified defects are analyzed in order to update the model architecture 46 implemented in the embedded system in step ii), for example, the defect identification results are used to receive feedback from downstream applications, and then the model architecture implemented in the embedded system is updated for each module, for example to solve data drift problems. The charged particle beam system 78 in the second embodiment of the present invention includes at least one embedded system 50, 50' to allow different model architectures 42 based on the same charged particle beam system 78 to be implemented in the same system. Each model architecture can be implemented in a separate embedded system 50, 50' in the charged particle beam system 78. Different model architectures 42 can also be implemented in the same embedded system 50, 50'. In order to make the system more flexible and versatile, the model architecture 42 of the machine learning model 40, 40', 40" can be divided into one or more modules and implemented as a plurality of logic block circuits 72, 72', 72", 72'", 74, 74', 74", 74'". In this way, during application of the defect identification method, by specifying the data flow 74 through the required number of logic block circuits 72 ′, 72 ′″ and interconnecting the logic block circuits 72 ′, 72 ′″, the new model architecture 42 of the machine learning model 40 , 40 ′, 40 ″ can be easily implemented in the charged particle beam system 78 , as shown in and described with reference to FIG. 7 . FIG7 illustrates a schematic embedded system implementation of a neural network model architecture comprising a first module 102 and a second module 104. Input data for both modules 102 and 104 is accessible via input data bus 98. Model data in the form of weights 100 for each module 102 and 104 is accessible via programmable memory 48 on embedded system 50. First module 102 comprises a convolutional layer with a single 2x2 filter based on a multiplication 110 of the input data on input data bus 98 by the weights 100 corresponding to first module 102. Second module 104 comprises two convolutional 2x2 filters based on a multiplication 110 of the input data on input data bus 98 by the weights 100 corresponding to second module 104. When defining data stream 74, modules 102 and 104 may be selected via multiplexer 108, which may be configured by a user, for example, via programmable memory 106. A module of a model architecture may include a portion of the model architecture, such as one or more layers of a neural network, a subtree of a decision tree, one or more hyperplanes of an SVM, one or more nodes of a graph structure, such as in a hidden Markov model, etc. According to one example of the second embodiment, at least one model architecture of at least one machine learning model for defect identification includes a model architecture such as a neural network for deep learning. This offers the advantage that, due to the subdivision into layers, neural networks are particularly well-suited for subdividing into logic block circuits, which reduces the workload of programming the embedded system and specifying the data flow through the logic block circuits. According to one aspect of an example of the second embodiment, one or more modules may be head-end modules, which are modules that include an output layer of a neural network. When input data is provided, the output layer produces a result of the neural network, such as classification into one of multiple categories, a binary output, or one or more specific return values. The output layer is task-specific, that is, it can only be used for a specific task. For example, one or more head-end modules may include a fully connected output layer of a neural network and / or a convolutional output layer of a neural network. For example, the fully connected output layer of a neural network is specifically designed for classification tasks because there are no restrictions on the spatial environment in the output layer. For example, due to consideration of the spatial environment, the convolutional layer of a neural network is specifically designed for defect detection, anomaly detection, or defect segmentation tasks. According to one aspect of the second embodiment, one or more modules are tail-end modules, which are modules comprising multiple hidden layers of a neural network. This allows the multiple hidden layers to be combined into a single tail-end module, thereby reducing programming workload and workload during data flow specification. The separation of head-end and / or tail-end modules offers the advantages of flexibility and versatility, since the operation of the neural network can be easily modified by exchanging the head-end modules to modify the data flow, and since the tail-end modules can be used in many different model architectures without additional work. Furthermore, subdividing the model architecture into head-end and tail-end modules allows for semantic grouping of hidden layers into a single tail module to perform specific tasks within the model architecture. In this way, the modular structure of the model architecture is simplified, reducing programming effort and the need to specify data flows. For example, FIG8 illustrates a model architecture 42 in the form of a neural network 114, broken down into a headend module 116 and a tailend module 118. FIG8 shows a neural network 114 comprising hidden layers 122 and 123 and an output layer 120 obtained by using filters of the indicated spatial and feature sizes. The neural network 114 comprises a headend module 116 and a single tailend module 118. The headend module 116 comprises the output layer 120 of the neural network 114, while the tailend module 118 comprises multiple hidden layers 122 and 123 of the neural network 114, and in particular, all hidden layers 122 and 123. The output layer is a 1x1x32 filtered pooling layer, and is therefore suitable for solving defect detection, anomaly detection, or segmentation tasks based on a feature map comprising 32 features generated by the final hidden layer 123. The separation of the task-specific headend module 116 from the rest of the model architecture is beneficial because, in this way, the headend module 116 can be easily replaced with a different headend module 116 to apply the model architecture to different tasks in different applications. For example, the headend module 116 can be adapted for classification tasks. FIG9 illustrates various head-end modules 124, 126 and tail-end modules 128, 130, 132, 134, 136, 138 for various model architectures. Due to this modular structure, a range of model architectures can be implemented on the embedded system 50, 50' by combining one or more of the different tail-end modules 128, 130, 132, 134, 136, 138 with one of the head-end modules 124, 126. The head-end modules 124, 126 can be task-specific. For example, a head-end module 124 with a filter size of 1x1xD, where D indicates the number of features, is suitable for anomaly detection, defect detection, or segmentation, while a head-end module 126 with a filter size of 1x1xCS, where S represents softmax and C represents the number of classes, is suitable for classification. The advantage of this modularization is that the operation of the neural network, e.g., the output layer of the neural network, can be easily modified by simply exchanging the head-end modules 124, 126, without having to modify the tail-end modules 128, 130, 132, 134, 136, 138, e.g., the hidden layers of the neural network, which define the data flow 74 for implementing the model architecture on the embedded system 50, 50'. According to another aspect of the second embodiment, at least one tail-end module, and in particular each tail-end module, may include all hidden layers 122 and 123 of the neural network 114, as shown in FIG8 . This is advantageous because each neural network 114 consists of only a single head-end module 116 and a single tail-end module 118. This allows for a particularly simple embedded system implementation of the neural network and a particularly simple specification of data flow within the embedded system's logic block circuits, as fewer blocks need to be interconnected. According to another aspect of the second embodiment, at least one tail-end module, and in particular each tail-end module, may include multiple hidden layers of a neural network that form semantic entities. The term "semantic entities" refers to the multiple hidden layers 122, 123 that form functional units that complement each other and together perform a specific function in the neural network 114. For example, the hidden layers of tail-end module 128 are semantic entities because they form functional units for reducing input data. The same applies to the hidden layers of tail-end module 132. The hidden layers of tail-end module 136 form functional entities because they form a bottleneck for reducing data dimensionality, for example, for representing an autoencoder. The same applies to the hidden layers of tail-end module 138. The hidden layers of tail-end module 130 are semantic entities because they form functional units for upscaling data. The same applies to the hidden layers of tail-end module 134. By defining tail-end modules that form semantic entities, the workload of implementing the model architecture on one or more embedded systems is reduced because only a few functional entities that perform specific functions must be interconnected to specify data flow within the model architecture. According to another aspect of the second embodiment, at least two tail-end modules include the same number of hidden layers, where the sizes of the feature maps of the corresponding hidden layers differ by the same factor. The hidden layers of the two modules are arranged in the order of the module hidden layers, corresponding to each other. For example, the second hidden layer of one module corresponds to the second hidden layer of the other module. This allows neural networks to be implemented with different numbers of features, for example, using small, medium, or large modules to perform the same task. In another aspect of the second embodiment, for each tail-end module, there is at least one other tail-end module that includes the same number of hidden layers, where the sizes of the feature maps of the corresponding hidden layers differ by the same factor. For example, Figure 9 shows two tail-end modules 128 and 132, which include the same number of hidden layers, namely three. The sizes of the feature maps of the corresponding first layers 129 and 129' are 32 and 16, respectively, differing by a factor of 2. The sizes of the feature maps of the corresponding second layers 131 and 131' are 16 and 8, respectively, differing by a factor of 2. The sizes of the feature maps of the corresponding third layers 133 and 133' are 8 and 4, respectively, also differing by a factor of 2. Thus, modules 128 and 132 perform the same task, differing only in the complexity of their feature maps. For example, tail-end modules 136 and 138 may contain only a single corresponding hidden layer, with feature map sizes differing by a factor of 10. This allows model architectures that consider different numbers of features, such as small-, medium-, or large-scale model architectures, to be implemented in the same embedded system, adapting the size of the model architecture to the challenge of the machine learning task. Model architectures with more or fewer features can be easily implemented on the embedded system by replacing the corresponding logic blocks in the small-scale tail-end module 138 with the logic blocks in the large-scale tail-end module 136. This makes the embedded system implementation of the model architecture extremely flexible and adaptable to the requirements of the machine learning task being solved. For example, in Figure 9, anomaly or defect detection can be performed based on a larger U-net model architecture that considers more features by specifying a data flow interconnecting tail-end modules 128, 136, and 130 with head-end module 124. Here, tail-end module 128 reduces the input data, tail-end module 136 represents the bottleneck used to obtain a very low-dimensional representation of the input data, and tail-end module 130 upscales the data. Therefore, the combination of tail-end modules 128, 136, and 130 represents the structure of an autoencoder. Head-end module 124 represents the convolutional layers used to compute the results of the defect or anomaly detection task. This large model architecture is useful for more complex defect or anomaly detection tasks that require considering more features. To perform anomaly or defect detection based on a smaller U-net model architecture that considers only a small number of features, tail-end modules 132, 138, and 134 can be interconnected with head-end module 124. The combination of tail-end modules 132, 138, and 134 also represents an autoencoder, but with fewer features and a smaller bottleneck. The headend module 124 represents a convolutional layer for computing the results of defect or anomaly detection tasks. This small-size model architecture is very useful for less complex defect or anomaly detection tasks that require considering fewer features. The modular structure shown in FIG9 can also be used for segmentation. Here, by interconnecting the tail module 128 with the head module 124, a large-scale U-net model architecture can be implemented on an embedded system. To achieve a small-scale U-net model architecture on an embedded system, the tail module 132 can be interconnected with the head module 124. The head module 124 is a convolutional layer that is used to calculate the results of the segmentation work, that is, to assign each pixel of the imaging data set to a specific category. Depending on the difficulty of the segmentation work, a larger or smaller number of features should be considered, so a large-scale model architecture or a small-scale architecture is respectively useful. The modular structure shown in Figure 9 can also be used for classification tasks. By specifying a data flow interconnecting tail modules 128, 136, and 130 with head module 126, classification can be performed based on a larger U-net model architecture that considers a large number of features. Similarly, the combination of tail modules 128, 136, and 130 represents the structure of an autoencoder. Head module 126 represents a fully connected softmax layer used to compute the classification results. This large model architecture is particularly useful for more complex classification tasks that require considering more features. To perform classification based on a smaller U-net model architecture that considers only a small number of features, tail modules 132, 138, and 134 can be interconnected with head module 126. The combination of tail modules 132, 138, and 134 also represents an autoencoder, but with fewer features and a smaller bottleneck. Head module 126 represents a fully connected layer used to compute the classification results. This small model architecture is particularly useful for less complex classification tasks that require considering fewer features. This allows large, medium, or small model architectures to be easily implemented on embedded systems, making the system highly flexible to meet the varying requirements of different workloads. Furthermore, the modular implementation of model architectures with varying feature map sizes on embedded systems simplifies the process of testing different model architectures during quality assurance to find the optimal one in terms of quality and runtime. According to one aspect of the second embodiment, each of the one or more modules is a head-end module comprising an output layer of a neural network, or a tail-end module comprising multiple hidden layers of a neural network. Furthermore, the one or more modules may include at least one head-end module and at least one tail-end module. According to one aspect of the second embodiment, one or more modules are generated from at least one model architecture of the neural network by dividing each model architecture into a headend module including an output layer of the neural network, and at least one, and in particular a single, tailend module including multiple hidden layers of the neural network. In this way, the module implemented on at least one embedded system in the charged particle beam system directly corresponds to the model architecture including all hidden layers of the neural network, making it easy to implement these neural networks in the system. According to a second embodiment of the present invention, before specifying the data flow through multiple logic block circuits in a plurality of logic block circuits, it is advantageous to determine whether the model architecture of the trained machine learning model can be implemented through the multiple logic block circuits on at least one of the embedded systems. Furthermore, upon determining whether the model architecture is not implementable, one or more modules of the model architecture of the trained machine learning model are generated and implemented on at least one of the embedded systems. In this way, a specific machine learning task and corresponding machine learning model can be checked to determine whether the model architecture of the machine learning model can be implemented using different modules already implemented in the embedded system of the charged particle beam system. If this is not the case, the missing module can be determined and implemented in one of the embedded systems of the charged particle beam system so that the model architecture can be represented by the logic block circuits of the embedded system in the charged particle beam system. This process is shown in FIG10 . FIG10 illustrates the process of implementing a new use case 34, 66 in a charged particle beam system 78 via a computer-implemented method according to one or more embodiments or examples of the present invention. Following a start 142, a family decision step 144 determines the family of machine learning models required to address the new use case 34, 66. For example, the family may include a defect detection model, a segmentation model, or a classification model. If the use case belongs to a new family not yet implemented in the system (yes 170), the expert gathers information about possible use cases for the family in a use case collection step 154. The expert defines a general model architecture for the family, which includes the possible use cases identified in the model architecture definition step 156. The expert then determines in an implementability step 158 whether the defined model architecture can be implemented on an existing embedded system in the charged particle beam system 78. If not (no 180), the defined model is generalized to the new embedded system in the charged particle beam system 78 in a model implementation step 160. Otherwise (Yes 178 ), in the data acquisition and training step 150 , training data and real data are acquired and a machine learning model is trained for the new use case 34 , 66 . The expert saves the generated model data, for example, the weights of the neural network, to a database in the model data storage step 152 . To run the machine learning model on the embedded system in the charged particle beam system 78 , pre-trained model data is loaded from the database in the model data lookup step 162 . In the model data transfer step 164 , the determined model data is downloaded from the database and transferred to the embedded system's programmable memory, which implements the model architecture of the machine learning model for the new use case 34 , 66 in the charged particle beam system 78 . Finally, in the data processing step 166 , the machine learning model implemented in the embedded system is run in real time on the input data before the process stops 168 . Otherwise, if the use case belongs to a new series already implemented in the system (No 172 ), a determination is made as to whether the use case is a new use case 34 , 66 not yet implemented in the system (Yes 174 ) or not (No 176 ). If the use case is a new use case 34, 66, then the family of model architectures is already implemented in the system, but model profiles need to be generated for the new use case 34, 66. Therefore, in a problem projection step 148, the machine learning problem is projected onto the family of predefined model architectures already implemented in the system. Model data is then obtained in a data sampling and training step 150 as described above, and the process continues as described above. On the other hand, if the use case is already implemented in the system (No 176), the model architecture and model profiles are already available, and the process continues with the model profile lookup step 162 as described above. As shown in the figure above, the model architecture implemented on the embedded system is based on a machine learning model based on a tail-end module and a specific work head-end module. It can form a data flow through the interconnection of multiple logic block circuits on the embedded system. Combined with the easily exchangeable model data in the embedded system's programmable memory, it can implement a highly flexible, adaptable and universal machine learning model on the embedded system. A third embodiment of the present invention is described below with reference to FIG11 . FIG11 is a flowchart illustrating steps in an exemplary computer-implemented method 182 for defect identification. The method comprises the computer-implemented method 22 or 52 according to the first or second embodiment of the present invention, or any instance or aspect thereof, and further comprises, prior to obtaining a wafer imaging dataset in step i), iterating 194 of the following steps until a convergence criterion, such as a maximum number of steps, is satisfied: in an image acquisition parameter step 184 , selecting at least one image acquisition parameter according to an imaging sampling strategy, and acquiring a wafer imaging dataset based on the at least one image acquisition parameter; in a training data generation step 186 , generating training data from the obtained wafer imaging dataset; selecting a model architecture and training an associated machine learning model based on the training data generated in a machine learning model training step 188 ; determining the quality of the model architecture and the at least one image acquisition parameter by calculating an associated objective function value for an objective function that evaluates the quality of the trained machine learning model in a quality assessment step 190 ; and after a final iteration 194 , selecting one of the model architectures and the corresponding at least one image acquisition parameter in a selection step 192 based on the objective function value. The imaging dataset of the wafer in step i) 26, 56 of the computer-implemented method according to the first or second embodiment of the present invention, or any instance or aspect thereof, is obtained based on the selected at least one image acquisition parameter, and the model architecture implemented by the embedded system in step ii) 28, 58 of the computer-implemented method according to the first or second embodiment of the present invention, or any instance or aspect thereof, includes the model architecture of the selected machine learning model. This is illustrated in Figures 12 and 13, where the model architecture and the corresponding at least one image acquisition parameter selected in selection step 192 are used in steps 26, 28, 56, and 58 of the computer-implemented method 22, 52. A fourth embodiment of the present invention is described below with reference to FIG14. The fourth embodiment of the present invention is a computer-implemented method 196 for defect identification in a wafer imaging dataset, the method comprising: iterating 210 of the following steps until a convergence criterion (e.g., a maximum number of steps) is met: in an image acquisition parameter step 198, selecting at least one image acquisition parameter according to an imaging sampling strategy and acquiring an imaging dataset of the wafer based on the at least one image acquisition parameter; in a training data generation step 200, generating training data from the acquired wafer imaging dataset; in a machine learning model training step 202, selecting a model architecture and training an associated machine learning model based on the generated training data; in a quality assessment step 204, assessing the quality of the trained machine learning model by calculating an objective function value associated with the objective function; after a final iteration 210: selecting one of the trained machine learning models in a selection step 206 based on the objective function value; and applying the selected trained machine learning model to the wafer imaging dataset acquired based on the corresponding at least one image acquisition parameter to identify defects in the application step 208. The identified defects may be used in quality assurance and / or quality control systems of the wafers. The method according to the third or fourth embodiment of the present invention has the following advantages: at least one image acquisition parameter is used to generate an imaging dataset of the wafer, and, therefore, the training data and the model architecture of the machine learning model can be combined to optimize the model architecture before the model architecture is implemented on one of the embedded systems in the charged particle beam system. During this process, the model architecture can be optimized based on various criteria, such as reducing runtime, further improving the throughput of the charged particle beam system, reducing the complexity of the model architecture, or improving the prediction quality of the machine learning model. The at least one image acquisition parameter may, for example, be selected from the group consisting of imaging time, image resolution, pixel size, impact energy, and electron wave dwell time. In one example of the third or fourth embodiment of the present invention, the step of selecting the model architecture 42 includes selecting at least one hyperparameter defining the model architecture 42 of the machine learning model 40, 40', 40" according to a framework sampling strategy. The framework sampling strategy can include multiple hyperparameters selected by the user, or automatically sampled hyperparameters, for example, based on AutoML techniques and hyperparameter sampling strategies known to those skilled in the art, such as the tree-structured Parzen estimator or the asynchronous successive halving strategy. This is advantageous because the hyperparameters of the machine learning model can be automatically optimized in conjunction with the at least one image acquisition parameter. In one example of the third or fourth embodiment of the present invention, the objective function may include a measure of the complexity of the model architecture 42. The measure of complexity may, for example, include the size of the model architecture 42, such as the number of layers and / or neurons in the neural network 114, the number of hyperplanes in an SVM, the number of layers and / or nodes in a decision tree, or the number of nodes and connections in a graph structure. The measure of complexity provides the following advantages: smaller-sized model architectures 42 can be used to solve machine learning tasks, thereby reducing the runtime of the machine learning models 40, 40', 40", increasing the throughput of the charged particle beam system 78 and reducing the space required on the embedded system 50, 50'. Therefore, more model architectures 42 can be implemented in the embedded system 50, 50' of the charged particle beam system 78. In another example of the third or fourth embodiment of the present invention, the objective function may include a measure of runtime and / or a measure of throughput and / or a measure of data rate and / or power consumption. In another example of the third or fourth embodiment of the present invention, the objective function may include a measure of the quality of defect identification, such as a loss function of the neural network 114 applied to the training data, or any other measure known to those skilled in the art for measuring the prediction error of the machine learning model 40, 40', 40" on the training data generated by at least one image acquisition parameter. In another example of the third or fourth embodiment of the present invention, the objective function may include a measure of the number of bits of input data to the machine learning model 40, 40', 40", such as the number of input bits of the input layer of the machine learning model 40, 40', 40". This reduces the complexity of the model architecture 42. Since less data needs to be processed, this has the advantage of reducing the runtime of the machine learning model 40, 40', 40". Furthermore, due to the reduced space requirements, the model architecture 42 with the reduced number of input bits can be more easily implemented on the embedded system 50, 50'. This allows for a wider range of model architectures 42 to be implemented on the embedded system 50, 50' of the charged particle beam system 78. In cases where a very large model architecture 42 is not suitable for implementation on the embedded system 50, 50', the size of the model architecture 42 can be reduced by reducing the number of input bits, thereby increasing the likelihood that the machine learning model 40, 40', 40" can be implemented on the embedded system 50, 50'. In one example of one of the various embodiments of the present invention, the computer-implemented method further includes determining one or more measurements of identified defects in the wafer imaging dataset, specifically, size, area, dimension, shape parameter, distance, radius, aspect ratio, type, number of defects, density, or spatial distribution of defects. The measurements can be calculated for a specific region (e.g., a user-defined reticle, wafer boundary, or wafer core) or for the entire imaging dataset. The quality of the wafer can be assessed based on one or more measurements and at least one quality assessment rule, for example according to the DIN-ISO quality specification, which defines an upper limit for acceptable non-ideal wafers. For example, the density of a specific defect type at the nucleus should be less than 1000 nm per nm. 2 / 10 pieces. According to any of the various embodiments of the present invention, at least one wafer process parameter may be controlled based on one or more measurements of defects identified in an imaging dataset of the wafer. The present invention also relates to a computer-readable medium having stored thereon a computer program executable by a computer device, the computer program including program code for performing a method according to any embodiment of the present invention. This includes a data I / O driver for low-latency hardware, a program for configuring low-latency hardware to perform image processing functions, a program for performing error checking, and the like. FIG15 schematically illustrates a system 212 that can be used to control the quality of wafers 226 produced in a semiconductor manufacturing facility. The system 212 includes an imaging device 214 and a processing device 216. The imaging device 214 is coupled to the processing device 216. The imaging device 214 is configured to acquire an imaging data set 12 of the wafer 226. The wafer 226 may include semiconductor structures, such as transistors such as field effect transistors and memory cells. Exemplary implementations of the imaging device 214 may be an SEM or a multi-beam SEM, a helium ion microscope (HIM), a cross-beam device including a FIB and a SEM, or any charged particle beam imaging device. The processing device 216 is coupled to at least one embedded system 50 including a programmable memory 48. The imaging device 214 may provide the imaging data set 12 to the processing device 216. The processing device 216 includes a processor, such as a CPU 218 or a GPU. The processor may receive the imaging data set 12 via the interface 220. The processor may load program code from the memory 222. The processor may execute the program code. When executing the program code, the processor performs techniques such as those described herein, such as assessing wafer quality based on one or more measurement results and at least one quality assessment rule, identifying defects, transferring model data to the programmable memory 48 of the embedded system 50, training the machine learning model 40, 40', 40", directing a data flow 74 through a plurality of local block circuits 72, 72', 72", 72'", 76, 76', 76", 76'" of the embedded system 50, 50', applying the machine learning model 42 implemented on the embedded system 50, 50' to the data, performing measurements on identified defects 16, optimizing at least one image acquisition parameter, etc. For example, when loading the program code from the memory 222, the processor may execute the computer-implemented methods shown in Figures 2, 4, 10, 11, 12, and 13, respectively. The processing device 216 may optionally include a user interface 224 for receiving user input, such as defect measurement types, quality assessment rules, and machine learning model parameters. The processing device 216 may optionally include a display device 227 for displaying defect identification results to the user, such as in real time or in a buffered manner. The processing device 216 may also optionally include a database 225 for storing, for example, machine learning model families 40, 40', 40", 40'", model architecture 42, or model data 44, 44", 44'", of different trained machine learning models 40, 40', 40", etc. FIG16 schematically illustrates a system 228 for controlling the production of wafers 226 in a semiconductor fabrication facility. System 228 includes the same components as those shown in FIG15 , and the above descriptions apply equally to the respective components. Furthermore, system 228 includes means 230 for producing wafers 226 controlled by at least one wafer process parameter. To this end, imaging device 214 provides imaging data set 12 to processing device 216. The processor of processing device 216 is configured to perform one of the methods disclosed in accordance with the first, second, or third embodiments of the present invention, including controlling at least one wafer process parameter based on one or more measured characteristics of defects 16 identified in imaging data set 12 of wafer 226. For example, detection of a bridge defect 16 indicates under-etching, and thus the etch amount is increased; detection of a line break defect 16 indicates over-etching, and thus the etch amount is reduced; persistent anomalies or defects 16 indicate a defective reticle, and thus the reticle must be inspected; and anomalies or defects 16, because the absence of a structure, indicate suboptimal material deposition, and thus modifications are made to the material deposition. FIG17 schematically illustrates a system 232 that can be used to control the quality of wafers 226 produced in a semiconductor fabrication facility. System 232 includes an imaging device 214 and a processing device 216. Imaging device 214 is coupled to processing device 216. Imaging device 214 is configured to acquire an imaging data set 12 of wafer 226. Wafer 226 may include semiconductor structures, such as transistors such as field effect transistors, memory cells, etc. Exemplary implementations of imaging device 214 may be a SEM or multi-beam SEM, a helium ion microscope (HIM), a cross-beam device including a FIB and a SEM, or any charged particle imaging device. The imaging device 214 can provide the imaging data set 12 to the processing device 216. The processing device 216 includes a processor, for example, implemented as a CPU 218 or a GPU. The processor can receive the imaging data set 12 via the interface 220. The processor can load program code from the memory 222. The processor can execute the program code. When executing the program code, the processor performs techniques such as those described herein according to the fourth embodiment of the present invention, for example, defect identification, measurement of identified defects, and joint optimization of at least one image capture parameter with the model architecture of the machine learning model. For example, the processor can execute the computer-implemented method shown in Figure 14 when loading the program code from the memory 222. The processing device 216 can optionally include a user interface 224 for receiving user input, such as defect measurement type, quality assessment rules, parameters of the machine learning model, etc. The processing device 216 can optionally include a display device 227 for displaying defect identification results to the user, for example in real time or buffered form. FIG18 schematically illustrates a system 234 that can be used to control the production of wafers 226 in a semiconductor fabrication facility. The components of system 228 are identical to those shown in FIG17 , and the descriptions above apply equally to the corresponding components herein. Furthermore, system 234 includes means 230 for producing wafers 226 controlled by at least one wafer process parameter. To this end, imaging device 214 provides imaging data set 12 to processing device 216. The processor of processing device 216 is configured to perform one of the disclosed methods, including controlling at least one wafer process parameter based on one or more measured characteristics of defects 16 identified in imaging data set 12 of wafer 226. For example, a detected bridge defect 16 may indicate insufficient etching, and thus the etching amount may be increased; a detected line break defect 16 may indicate excessive etching, and thus the etching amount may be decreased; a persistent anomaly or defect 16 may indicate a defective reticle, and thus the reticle may need to be inspected; and anomalies or defects 16 due to missing structures may indicate unsatisfactory material deposition, and thus the material deposition may be modified. Embodiments, examples, and aspects of the present invention may be described by the following clauses: 1. A computer-implemented method 22 for defect identification in an imaging dataset 12, 12', 12" of a wafer 226 in a charged particle beam system 78 having an embedded system 50, 50', the method comprising: i. obtaining an imaging dataset 12, 12', 12" of a wafer 226; ii. obtaining model data 44, 44', 44" of a model architecture 42 for a machine learning model 40, 40', 40" for defect identification in the imaging dataset 12, 12', 12" of the wafer 226, the model architecture 42 being implemented in the embedded system 50, 50'; iii. transferring the model data 44, 44', 44" to a programmable memory 48, 48', 48" of the embedded system 50, 50'; iv. Applying the machine learning model 40, 40', 40" to an imaging dataset 12, 12', 12" of a wafer 226 to identify a plurality of defects 16 includes executing the embedded system implemented model architecture 46 using the transferred model data 44, 44', 44". 2. A computer-implemented method 52 for defect identification in an imaging dataset 12, 12', 12" of a wafer 226 in a charged particle beam system 78 including an embedded system 50, 50', the method comprising: i. obtaining an imaging dataset 12, 12', 12" of a wafer 226; ii. defining, on one of the at least one embedded systems 50, 50', the embedded system implementing model architecture 46 for the machine learning model 40, 40', 40" for defect identification in the imaging dataset 12, 12', 12" of the wafer 226 by specifying a data flow 74 through some of the plurality of logic block circuits 72, 72', 72", 72'", 74, 74', 74", 74'", wherein the plurality of logic block circuits 72, 72', 72", 72'", 74, 74', 74", 74'" include one or more modules 102, 104 of the at least one model architecture 42 of the at least one machine learning model 40, 40', 40" for defect identification; iii. obtaining model data 44, 44', 44" for the embedded system implementing model architecture 46; iv. transferring the model data 44, 44', 44" to a programmable memory 48, 48', 48" of the embedded system 50, 50'; v. applying the machine learning model 40, 40', 40" to an imaging dataset 12, 12', 12" of a wafer 226 to identify a plurality of defects 16, which includes executing the embedded system implementing the model architecture 46 using the transferred model data 44, 44', 44".3. The computer-implemented method of clause 2, wherein the at least one model architecture 42 of the at least one machine learning model 40, 40', 40" for defect identification comprises a model architecture 42 of a neural network 114. 4. The computer-implemented method of clause 3, wherein the one or more modules 102, 104 are headend modules 116, 124, 126, and a headend module 116, 124, 126 is a module comprising an output layer 120 of a neural network 114. 5. The computer-implemented method of clause 4, wherein the one or more headend modules 116, 124, 126 comprise a fully connected output layer of a neural network 114 and / or a convolutional output layer of a neural network 114. 6. The computer-implemented method of any one of clauses 3 to 5, wherein the one or more modules 102, 104 are tail-end modules 118, 128, 130, 132, 134, 136, 138, and a tail-end module 118, 128, 130, 132, 134, 136, 138 is a module comprising a plurality of hidden layers 122 of a neural network 114. 7. The computer-implemented method of clause 6, wherein at least one tail-end module 118, 128, 130, 132, 134, 136, 138, and in particular each tail-end module 118, 128, 130, 132, 134, 136, 138, comprises all hidden layers 122 of a neural network 114. 8. The computer-implemented method of clause 6 or 7, wherein at least one tail-end module 118, 128, 130, 132, 134, 136, 138, in particular each tail-end module 118, 128, 130, 132, 134, 136, 138, comprises a plurality of hidden layers 122 forming a semantic entity. 9. The computer-implemented method of any one of clauses 6 to 8, wherein at least two of the tail-end modules 118, 128, 130, 132, 134, 136, 138 comprise the same number of hidden layers 122, 123, and the sizes of the feature maps of the corresponding layers 129, 129', 131, 131', 133, 133' differ by the same factor. 10. A computer-implemented method as described in any one of clauses 3 to 9, wherein each module 102, 104 of the one or more modules 102, 104 is a head-end module 116, 124, 126 containing an output layer 120 of a neural network 114 or a tail-end module 118, 128, 130, 132, 134, 136, 138 containing multiple hidden layers 122 of a neural network 114.11. The computer-implemented method of any of clauses 3 to 10, wherein the one or more modules 102, 104 are generated from at least one model architecture 42 of the neural network 114 by partitioning each model architecture 42 into the head-end module 116, 124, 126 containing the output layer 120 of the neural network 114 and at least one tail-end module 118, 128, 130, 132, 134, 136, 138 containing the plurality of hidden layers 122 of the neural network 114. 12. The computer-implemented method of clause 11, wherein each model architecture 42 of the neural network 114 is partitioned into a task-specific head-end module 116, 124, 126 and a single tail-end module 118, 128, 130, 132, 134, 136, 138. 13. The computer-implemented method of any one of clauses 2 to 12, further comprising determining whether the model architecture 42 of the machine learning model 40, 40', 40'' can be implemented by the multiple logic block circuits 72, 72', 72'', 72''', 74, 74', 74'', 74'' on one of the at least one embedded systems 50, 50' before specifying the data flow 74 through the logic block circuits 72', 72'', 74, 74', 74'', 74'', 74''; and in response to determining that the model architecture 42 cannot be implemented, generating the one or more modules 102, 104 of the model architecture 42 of the machine learning model 40, 40', 40'' and implementing the one or more modules 102, 104 on one of the at least one embedded systems 50, 50'. 14. The computer-implemented method of any of the preceding clauses, wherein the machine learning model 40, 40', 40" for defect identification is selected from a group consisting of a plurality of defect detection models, a plurality of defect classification models, a plurality of defect localization models, a plurality of defect segmentation models, a plurality of anomaly detection models, a plurality of anomaly classification models, a plurality of anomaly localization models, and a plurality of anomaly segmentation models. 15. The computer-implemented method of any of the preceding clauses, wherein the model data 44, 44', 44" for implementing the model architecture 46 in the embedded system is obtained by training the machine learning model 40, 40', 40" containing the model architecture. 16. The computer-implemented method of any of the preceding clauses, wherein the model data 44, 44', 44" for implementing the model architecture 46 in the embedded system is loaded from a database 225. 17. The computer-implemented method of any of the preceding clauses, wherein the model data 44, 44', 44" for implementing the model architecture 46 in the embedded system is provided by an external service.18. The computer-implemented method of any of the preceding clauses, wherein the model data 44, 44', 44" is transferred to the programmable memory 48, 48', 48" of the embedded system 50, 50' by copying. 19. The computer-implemented method of any of the preceding clauses, wherein the model data 44, 44', 44" is transferred to the programmable memory 48, 48', 48" of the embedded system 50, 50' by replacing the hardware block containing the programmable memory 48, 48', 48" of the embedded system 50, 50' with a new hardware block containing the model data 44, 44', 44" to be transferred. 20. The computer-implemented method of any of the preceding clauses, wherein the identified defects 16 are directed to a display device 227 or a dashboard. 21. The computer-implemented method of any preceding clause, wherein the identified defects 16 are stored in a long-term memory. 22. The computer-implemented method of any preceding clause, wherein the identified defects 16 are cached in a memory. 23. The computer-implemented method of any preceding clause, wherein the identified defects 16 are analyzed to update the embedded system implementation model framework 46 in step ii). 24. The computer-implemented method of any preceding clause, wherein the embedded system 50, 50' is a field programmable gate array 51. 25. The computer-implemented method 182 of any of the preceding clauses, further comprising, before obtaining the imaging dataset 12, 12', 12'' of the wafer in step i), performing the following steps: - iterating the following steps until a convergence criterion is met: ● selecting at least one image capture parameter according to an image sampling strategy, and capturing the imaging dataset 12, 12', 12'' of the wafer 226 based on the at least one image capture parameter; ● generating training data from the captured imaging dataset 12, 12', 12'' of the wafer 226; ● selecting a model architecture 42 and training the associated machine learning model 40, 40', 40'' based on the generated training data; ● determining the quality of the model architecture 42 and the at least one image capture parameter by calculating an associated objective function value of an objective function that evaluates the quality of the trained machine learning model 40, 40', 40''; - Based on the objective function values, one of the model architectures 42 and the corresponding at least one image acquisition parameter are selected, wherein the imaging data set 12, 12', 12'' of the wafer 226 in step i) is obtained based on the selected at least one image acquisition parameter, and the embedded system implementation model architecture 46 in step ii) includes the model architecture 42 of the selected machine learning model 40, 40', 40''.26. The computer-implemented method of clause 25, wherein the step of selecting the model architecture 42 comprises selecting at least one hyperparameter defining the model architecture 42 of the machine learning model 40, 40', 40" based on a framework sampling strategy. 27. The computer-implemented method of clause 26, wherein the objective function comprises a measure of the complexity of the model architecture 42. 28. The computer-implemented method of any of clauses 25 to 27, wherein the objective function comprises a measure of runtime and / or a measure of throughput and / or a measure of data rate and / or power consumption. 29. The computer-implemented method of any of clauses 25 to 28, wherein the objective function comprises a quality measure of defect identification. 30. The computer-implemented method of any of clauses 25 to 29, wherein the at least one image acquisition parameter is selected from the group consisting of imaging time, image resolution, pixel size, landing energy, and electron wave dwell time. 31. The computer-implemented method of any one of clauses 25 to 30, wherein the objective function comprises a measure of the number of bits of input data to the machine learning model 40, 40', 40". 32. A computer-implemented method 196 for defect identification in an imaging dataset 12, 12', 12'' of a wafer 226, the method comprising: - iterating the following steps until a convergence criterion is met: ● selecting at least one image capture parameter according to an image sampling strategy, and capturing the imaging dataset 12, 12', 12'' of the wafer 226 based on the at least one image capture parameter; ● generating training data from the captured imaging dataset 12, 12', 12'' of the wafer 226; ● selecting a model architecture 42 and training a corresponding machine learning model 40, 40', 40'' based on the generated training data; ● evaluating the quality of the trained machine learning model 40, 40', 40'' by calculating a corresponding objective function value of an objective function; - selecting one of the trained machine learning models 40, 40', 40'' based on the objective function values; - Applying the selected trained machine learning model 40, 40', 40" to the image dataset 12, 12', 12" of the wafer 226 captured based on the corresponding at least one image capture parameter to identify defects 16. 33. The computer-implemented method of clause 32, wherein the step of selecting the model architecture 42 comprises selecting at least one hyperparameter defining the model architecture 42 of the machine learning model 40, 40', 40" based on a framework sampling strategy. 34. The computer-implemented method of clause 33, wherein the objective function comprises a measure of the complexity of the model architecture 42.35. The computer-implemented method of any one of clauses 32 to 34, wherein the objective function comprises a measure of runtime and / or throughput and / or data rate and / or power consumption during defect identification. 36. The computer-implemented method of any one of clauses 32 to 35, wherein the objective function comprises a quality measure of defect identification. 37. The computer-implemented method of any one of clauses 32 to 36, wherein the at least one image acquisition parameter is selected from the group consisting of imaging time, image resolution, pixel size, impact energy, and electron wave dwell time. 38. The computer-implemented method of any one of clauses 32 to 37, wherein the objective function comprises a measure of the number of bits of input data to the machine learning model 40, 40', 40". 39. The computer-implemented method of any of clauses 1 to 31, further comprising determining one or more measurements of the defects 16 identified in the imaging dataset 12, 12', 12" of the wafer 226, particularly size, area, dimension, shape parameter, distance, radius, aspect ratio, type, number of defects, density, spatial distribution of defects, etc. 40. The computer-implemented method of clause 39, further comprising assessing the quality of the wafer 226 based on the one or more measurements and at least one quality assessment rule. 41. The computer-implemented method of clause 39, further comprising controlling at least one wafer process parameter based on the one or more measurements of the defects identified in the imaging dataset of the wafer. 42. The computer-implemented method of any of clauses 32 to 38, further comprising determining one or more measurements of the defects 16 identified in the imaging dataset 12, 12', 12" of the wafer 226, particularly size, area, dimension, shape parameter, distance, radius, aspect ratio, type, number of defects, density, spatial distribution of defects, presence of any defects, etc. 43. The computer-implemented method of clause 42, further comprising assessing the quality of the wafer 226 based on the one or more measurements and at least one quality assessment rule. 44. The computer-implemented method of clause 42, further comprising controlling at least one wafer process parameter based on the one or more measurements of the defects 16 identified in the imaging dataset 12, 12', 12" of the wafer 226. 45. A computer-readable medium having stored thereon a computer program executable by a computer device, the computer program comprising program code for performing the method of any of clauses 1 to 44. 46. ​​A computer program product comprising a plurality of instructions, which, when executed by a computer, causes the computer to perform the method according to any one of clauses 1 to 44.47. A system 212 for controlling the quality of a plurality of wafers 226 produced in a semiconductor manufacturing plant, the system 212 comprising: - an imaging device 214 adapted to provide an imaging data set 12, 12', 12'' of a wafer 226; - one or more processing devices 216; - at least one embedded system 50, 50'; - one or more machine-readable hardware storage devices comprising a plurality of instructions executable by the one or more processing devices 216 to perform a plurality of operations comprising the method as described in clause 40. 48. A system 228 for controlling a plurality of wafers 226 produced in a semiconductor fabrication facility, the system 228 comprising: - means 230 for producing the wafers 226 controlled by at least one process parameter; - an imaging device 214 adapted to provide an imaging data set 12, 12', 12" of a wafer 226; - one or more processing devices 216; - at least one embedded system 50, 50'; - one or more machine-readable hardware storage devices comprising instructions executable by the one or more processing devices 216 to perform operations comprising the method of clause 41. 49. The system 212, 228 of clause 47 or 48, further comprising a database 225. 50. A system 232 for controlling a plurality of wafers 226 produced in a semiconductor manufacturing plant, the system 232 comprising: - an imaging device 214 adapted to provide an imaging data set 12, 12', 12'' of a wafer 226; - one or more processing devices 216; - one or more machine-readable hardware storage devices comprising a plurality of instructions executable by the one or more processing devices 216 to perform a plurality of operations comprising the method as described in clause 43. 51. A system 234 for controlling a plurality of wafers 226 produced in a semiconductor fabrication facility, the system 234 comprising: - means 230 for producing the wafers 226 controlled by at least one process parameter; - an imaging device 214 adapted to provide an imaging data set 12, 12', 12" of a wafer 226; - one or more processing devices 216; - one or more machine-readable hardware storage devices comprising instructions executable by the one or more processing devices 216 to perform operations comprising the method of claim 44. 52. The system 212, 228, 232, 234 of any one of claims 47 to 51, further comprising a display device 227. 53. The system 212, 228, 232, 234 of any one of claims 47 to 52, further comprising a user interface 224. 10: Unit structure 10': Unit structure 10'': Unit structure 12: Imaging dataset 12': Imaging dataset 12'': Imaging dataset 14: Unit 14': Unit 14'': Unit 16: Disadvantages 22: Computer implementation method 26: Imaging step 28: Model data step 30: Model data transmission step 32: Application step 34: New use case 40: Machine learning model 40': Machine learning model 40'': Machine learning model 42: Model architecture 44: Model data 44': Model data 44'': Model data 46: Embedded system implementation model architecture 48: Programmable memory 48': Programmable memory 48'': Programmable Memory 50: Embedded System 50': Embedded System 51: Field Programmable Gate Array 52: Computer Implementation Method 56: Imaging Step 58: Data Flow Specification Step 60: Model Data Step 62: Model Data Transmission Step 64: Application Step 66: New Use Case 72: Logic Block Circuit 72': Logic Block Circuit 72'': Logic Block Circuit 72''': Logic Block Circuit 74: Data Flow 76: Logic Block Circuit 76': Logic Block Circuit 76'': Logic Block Circuit 76''': Logic Block Circuit 78: Charged Particle Beam System 80: Adaptive Logic Module 82: M512 Block 84: M4K Block 86: High-speed I / O channels with dynamic phase alignment (DPA) 88: I / O channels with external memory interface circuitry 90: Digital signal processing block 92: M-RAM block 94: Phase-locked loop 96: Programmable memory 98: Input data bus 100: Weights 102: First module 104: Second module 106: Configuration memory 108: Multiplexer 110: Multiplication 112: Addition 114: Neural network 116: Head-end module 118: Tail-end module 120: Output layer 122: Hidden layer 123: Final hidden layer 124: Head-end module 126: Head-end module 128: Tail-end module 129: Corresponding first layer 129': Corresponding to the first layer 130: tail module 131: corresponding to the second layer 131': corresponding to the second layer 132: tail module 133: corresponding to the third layer 133': corresponding to the third layer 134: tail module 136: tail module 138: tail module 142: start 144: family decision step 146: use case decision 148: problem projection step 150: data acquisition and training step 152: model data storage step 154: use case collection step 156: model architecture definition step 158: implementation step 160: model implementation step 162: model data search step 164: model data transmission step 166: data processing step 168: stop170: Yes 172: No 174: Yes 176: No 178: Yes 180: No 182: Computer Implementation Method 184: Image Capture Parameter Step 186: Training Data Generation Step 188: Machine Learning Model Training Step 190: Quality Assessment Step 192: Selection Step 194: Iteration 196: Computer Implementation Method 198: Image Capture Parameter Step 200: Training Data Generation Step 202: Machine Learning Model Training Step 204: Quality Assessment Step 206: Selection Step 208: Application Step 210: Iteration 212: System 214: Imaging Device 216: Processing Device 218: CPU 220: Interface 222: Memory 224: User Interface 225: Database 226: Wafer 227: Display Device 228: System 230: Component 232: System 234: System FIG1 shows a schematic unit structure of an imaging data set of three defective wafers; FIG2 is a flowchart illustrating steps in an exemplary computer-implemented method for defect identification according to a first embodiment of the present invention; FIG3 illustrates the flexible implementation of machine learning models in embedded systems using partitioned model architecture and model data; FIG4 is a flow chart illustrating steps in an exemplary computer-implemented method for defect identification according to a second embodiment of the present invention; FIG5 illustrates a particularly flexible and general method for implementing a machine learning model in a system comprising at least one embedded system; FIG6 illustrates the use of an embedded system in the form of an FPGA for various use cases based on the partitioning of hardware-related and software-related parts; FIG7 shows a schematic embedded system implementation of the first module and the second module of the neural network model architecture; FIG8 shows a model architecture in the form of a neural network, which is subdivided into a head-end module and a tail-end module; FIG9 shows different head-end modules and tail-end modules of various model architectures; FIG10 illustrates a process of implementing a new use case in a system via a computer-implemented method according to various embodiments of the present invention; FIG. 11 is a flow chart illustrating steps in an exemplary computer-implemented method for defect identification according to a third embodiment of the present invention. FIG. 12 is a flow chart illustrating steps in an exemplary computer-implemented method for defect identification according to a third embodiment of the present invention. FIG. 13 is a flow chart illustrating steps in an exemplary computer-implemented method for defect identification according to a third embodiment of the present invention. FIG. 14 is a flow chart illustrating steps in an exemplary computer-implemented method for defect identification according to a fourth embodiment of the present invention. FIG15 schematically illustrates a system that can be used to control the quality of wafers produced in a semiconductor fabrication plant; FIG16 schematically illustrates a system that may be used to control wafer production in a semiconductor manufacturing facility; FIG17 schematically illustrates a system that can be used to control the quality of wafers produced in a semiconductor fabrication plant; and FIG. 18 schematically illustrates a system that may be used to control the production of wafers in a semiconductor fabrication facility. 40: Machine Learning Model 40': Machine Learning Model 40”: Machine Learning Model 42: Model Architecture 44: Model information 44': Model information 44”: Model information 46: Embedded System Implementation Model Architecture 48: Programmable Memory 78: Charged Particle Beam System

Claims

1. A computer-implemented method (22) for defect identification in an imaging dataset (12, 12', 12'') of a wafer (226) in a charged particle beam system (78) containing an embedded system (50, 50'), the method comprising: i. iterating the following steps until a convergence criterion is met: a. selecting at least one image acquisition parameter according to an image sampling strategy, and acquiring the imaging dataset (12, 12', 12'') of the wafer (226) based on the at least one image acquisition parameter; b. generating training data from the acquired imaging dataset (12, 12', 12'') of the wafer (226); c. Select a model architecture (42) and train a related machine learning model (40, 40', 40'') based on the generated training data, wherein the step of selecting the model architecture (42) includes selecting at least one hyperparameter of the model architecture (42) that defines the machine learning model (40, 40', 40'') based on an architecture sampling strategy; d. The quality of the model architecture (42) and the at least one image capturing parameter are determined by calculating the value of an objective function associated with an objective function that evaluates the quality of the trained machine learning model (40, 40', 40''), and used for defect identification in the imaging dataset. ii. Based on the objective function values, select one of the model architectures (42) of the machine learning models (40, 40', 40'') and the corresponding at least one image capture parameter; iii. Based on the selected at least one image capture parameter, obtain an imaging dataset (12, 12', 12'') of a wafer (226); iv. Obtain model data (44, 44', 44'') for the model architecture (42) of the machine learning models (40, 40', 40'') for defect identification in the imaging dataset (12, 12', 12'') of the wafer (226), the model architecture (42) including the selected model architecture (42) of the machine learning models (40, 40', 40'') and implemented in the embedded system (50, 50'); v. vi. Transfer the model data (44, 44', 44'') to a programmable memory (48, 48', 48'') of the embedded system (50, 50'); vi. Apply the machine learning model (40, 40', 40'') to the imaging data set (12, 12', 12'') of the wafer (226) to identify multiple defects (16), which includes an embedded system implementation model architecture (46) that uses the transferred model data (44, 44', 44'') to execute the machine learning model (40, 40', 40'').

2. The computer implementation method as described in claim 1, wherein the objective function is configured to evaluate one of the following: a quality measure of defect identification; and at least one of a measure selected from the complexity of the model architecture, a measure of runtime, a measure of output, a measure of data rate, a measure of power consumption, and a measure of the number of bits of input data to the machine learning model; such that the selected model architecture and image capture parameters reduce the resource usage of executing the machine learning model on the embedded system.

3. A computer-implemented method (52) for defect identification in an imaging dataset (12, 12', 12'') of a wafer (226) in a charged particle beam system (78) containing an embedded system (50, 50'), the method comprising: i. acquiring the imaging dataset (12, 12', 12'') of the wafer (226); ii. On one of the at least one of the embedded systems (50, 50'), by specifying a data stream (74) through some of the logic block circuits (72', 72''') of a plurality of logic block circuits (72, 72'''), an embedded system implements a model architecture (46) for defect identification in the imaging dataset (12, 12'', 12'') of the wafer (226), wherein the plurality of logic block circuits (72, 72', 72''', 72''', 74, 74'', 74''', 74''') includes one or more modules (102, 104), wherein the machine learning model (40, 40', 40'') for defect identification is implemented by comparing the machine learning model (40, 40', 40'') for defect identification with at least one of another machine learning models. At least one model architecture (42) is divided into a head-end module (116, 124, 126) containing an output layer (120) of a neural network (114) and at least one tail-end module (118, 128, 130, 132, 134, 136, 138) containing multiple hidden layers (122) of the neural network (114), thereby generating one or more modules (102, 104), wherein the at least one model architecture (42) includes a model architecture of the neural network (114), wherein the one or more modules (102, 104) are combinable to form the embedded system implementation model architecture (46) of the machine learning model (40, 40', 40''), wherein the head-end module is independently replaceable to adapt the machine learning model to different defect identification tasks, and wherein the data flow through the multiple logic block circuits can be configured; iii. Obtain model data (44, 44', 44'') for the embedded system implementation model architecture (46); iv. Transfer the model data (44, 44', 44'') to a programmable memory (48, 48', 48'') of the embedded system (50, 50'); v. Apply the machine learning model (40, 40', 40'') to the imaging dataset (12, 12', 12'') of the wafer (226) to identify multiple defects (16), which includes executing the embedded system implementation model architecture (46) using the transferred model data (44, 44', 44'').

4. The computer implementation method as described in claim 3, wherein the one or more head-end modules (116, 124, 126) includes a fully connected output layer of the neural network (114) and / or a convolutional output layer of the neural network (114).

5. The computer implementation method as described in claim 3, wherein at least one tail module (118, 128, 130, 132, 134, 136, 138), particularly each tail module (118, 128, 130, 132, 134, 136, 138), contains all the hidden layers (122) of the neural network (114).

6. The computer implementation method as described in claim 3, wherein at least one tail module (118, 128, 130, 132, 134, 136, 138), particularly each tail module (118, 128, 130, 132, 134, 136, 138), comprises multiple hidden layers (122) forming a semantic entity.

7. The computer implementation method as described in claim 3, wherein at least two of the tail modules (118, 128, 130, 132, 134, 136, 138) contain the same number of hidden layers (122, 123), and the dimensions of the feature maps of the plurality of corresponding layers (129, 129', 131, 131', 133, 133') differ by the same factor.

8. The computer implementation method as described in claim 3, wherein each model architecture (42) of the neural network (114) is divided into a working-specific head module (116, 124, 126) and a single tail module (118, 128, 130, 132, 134, 136, 138).

9. The computer implementation method as described in any one of claims 3 to 4 further includes, before specifying the data flow (74) through the logic block circuits (72', 72''', 72''', 74, 74', 74'', 74''') in the plurality of logic block circuits (72, 72'''), determining whether the model architecture (42) of the machine learning model (40, 40', 40'') is available from the at least one embedded system (50, 50'). The plurality of logic block circuits (72, 72', 72'', 72''', 74, 74', 74'', 74''') are implemented on one of the plurality of logic block circuits (72, 72', 72'', 72''', 74, 74''', 74''') in response to the determination that the model architecture (42) cannot be implemented, and the one or more modules (102, 104) of the model architecture (42) that generate the machine learning model (40, 40', 40'') are implemented on one of the at least one embedded system (50, 50').

10. The computer implementation method as claimed in any one of claims 1 to 4, wherein the machine learning model (40, 40', 40'') for defect identification is derived from a group comprising multiple defect detection models, multiple defect classification models, multiple defect localization models, multiple defect segmentation models, multiple anomaly detection models, multiple anomaly classification models, multiple anomaly localization models, and multiple anomaly segmentation models.

11. The computer implementation method as claimed in any one of claims 1 to 4, wherein the model data (44, 44', 44'') for implementing the model architecture (46) in the embedded system is obtained by training the machine learning model (40, 40', 40'') containing the model architecture.

12. The computer implementation method as claimed in any one of claims 1 to 4, wherein the model data (44, 44', 44'') for implementing the model architecture (46) in the embedded system is loaded from a database (225).

13. The computer implementation method as claimed in any one of claims 1 to 4, wherein the model data (44, 44', 44'') for implementing the model architecture (46) in the embedded system is provided by an external service.

14. The computer implementation method as described in any one of claims 1 to 4, wherein the model data (44, 44', 44'') is transferred to the programmable memory (48, 48', 48'') of the embedded system (50, 50') by copying.

15. The computer implementation method according to any one of claims 1 to 4, wherein the model data (44, 44', 44'') is transferred to the programmable memory (48, 48', 48'') of the embedded system (50, 50') by replacing the hardware block containing the programmable memory (48, 48', 48'') of the embedded system (50, 50') with a new hardware block containing the model data (44, 44', 44'') to be transferred.

16. The computer implementation method of any one of claims 1 to 4, wherein the identified defects (16) are directed to a display device (227) or an instrument panel.

17. The computer implementation method as claimed in any one of claims 1 to 4, wherein the identified defects (16) are stored in a long-term memory.

18. The computer implementation method as claimed in any one of claims 1 to 4, wherein the identified defect (16) is cached in memory.

19. The computer implementation method as claimed in any one of claims 1 to 4, wherein the identified defects (16) are analyzed to update the embedded system implementation model architecture (46) in step ii).

20. The computer implementation method as claimed in any one of claims 1 to 4, wherein the embedded system (50, 50') is a field-programmable gate array (51).

21. The computer implementation method (182) of any one of claims 3 to 4 further comprises, before obtaining the imaging data set (12, 12', 12'') of the wafer in step i), performing the following steps: - Iterating the following steps until a convergence criterion is met: ● Selecting at least one image capturing parameter according to an image sampling strategy, and capturing the imaging data set (12, 12', 12'') of the wafer (226) based on the at least one image capturing parameter; ● Generating training data from the captured imaging data set (12, 12', 12'') of the wafer (226); ● Selecting a model architecture (42) and training the relevant machine learning model (40, 40', 40'') based on the generated training data; ● The quality of the model architecture (42) and the at least one image capture parameter are determined by calculating an objective function associated with an objective function that evaluates the quality of the trained machine learning model (40, 40', 40''); - Based on the objective function values, one of the model architectures (42) and the corresponding at least one image capture parameter are selected, wherein the imaging dataset (12, 12', 12'') of the wafer (226) in step i) is obtained based on the selected at least one image capture parameter, and the model architecture (46) in the embedded system in step ii) includes the model architecture (42) of the selected machine learning model (40, 40', 40'').

22. The computer implementation method as described in claim 21, wherein the step of selecting the model architecture (42) includes selecting at least one hyperparameter of the model architecture (42) that defines the machine learning model (40, 40', 40'') based on an architecture sampling strategy.

23. The computer implementation method as described in claim 21, wherein the objective function includes a measurement of the complexity of the model architecture (42).

24. The computer implementation method as described in claim 21, wherein the objective function includes measurements of runtime and / or output and / or data rate and / or power consumption.

25. The computer implementation method as described in claim 21, wherein the objective function includes a quality measure of defect identification.

26. The computer implementation method as claimed in claim 1 or 21, wherein the at least one image acquisition parameter is from a group including imaging time, image resolution, pixel size, landing energy, and residence time of the electron wave.

27. The computer implementation method as described in claim 21, wherein the objective function includes a measurement of the number of bits of the input data of the machine learning model (40, 40', 40'').

28. A computer-implemented method (196) for defect identification in an imaging dataset (12, 12', 12'') of a wafer (226), the method comprising: - iterating the following steps until a convergence criterion is met: ● selecting at least one image extraction parameter according to an image sampling strategy, and extracting the imaging dataset (12, 12', 12'') of the wafer (226) based on the at least one image extraction parameter; ● generating training data from the extracted imaging dataset (12, 12', 12'') of the wafer (226); ● selecting a model architecture (42) and training a related machine learning model (40, 40', 40'') based on the generated training data, wherein the step of selecting the model architecture (42) comprises selecting at least one hyperparameter of the model architecture (42) defining the machine learning model (40, 40', 40'') based on an architecture sampling strategy; ● The quality of the trained machine learning models (40, 40', 40'') is evaluated by calculating a relevant objective function value, wherein the objective function includes a measure of the complexity of the model architecture (42); - Based on the objective function values, one of the trained machine learning models (40, 40', 40'') is selected; - Model data (44, 44', 44'') for an embedded system implementation model architecture (46) of the selected trained machine learning model (40, 40', 40'') is obtained; - The model data (44, 44', 44'') is transferred to a programmable memory (48, 48', 48'') of an embedded system (50, 50'); The selected trained machine learning model (40, 40', 40'') is applied to the imaging data set (12, 12', 12'') of the wafer (226) captured based on at least one corresponding image capturing parameter to identify defects (16), which includes using the transferred model data (44, 44', 44'') to implement the embedded system implementation model architecture (46).

29. A computer-implemented method (196) for defect identification in an imaging dataset (12, 12', 12'') of a wafer (226), the method comprising: - iteratively performing the following steps until a convergence criterion is met: ● Selecting at least one image capturing parameter according to an image sampling strategy, and capturing the imaging dataset (12, 12', 12'') of the wafer (226) based on the at least one image capturing parameter, wherein the at least one image capturing parameter is from a group containing imaging time, image resolution, pixel size, impact energy, and residence time of electron waves; ● Generating training data from the captured imaging dataset (12, 12', 12'') of the wafer (226); ● Select a model architecture (42) and train a related machine learning model (40, 40', 40'') based on the generated training data, wherein the step of selecting the model architecture (42) includes selecting at least one hyperparameter of the model architecture (42) that defines the machine learning model (40, 40', 40'') based on an architecture sampling strategy; ● Evaluating the quality of the trained machine learning model (40, 40', 40'') by calculating a related objective function value of an objective function; - Selecting one of the trained machine learning models (40, 40', 40'') based on the objective function values; - Obtaining model data (44, 44', 44'') for an embedded system implementation model architecture (46) of the selected trained machine learning model (40, 40', 40''); The model data (44, 44', 44'') is transferred to a programmable memory (48, 48', 48'') of an embedded system (50, 50'); - The selected trained machine learning model (40, 40', 40'') is applied to the imaging data set (12, 12', 12'') of the wafer (226) captured based on at least one corresponding image capturing parameter to identify defects (16), which includes using the transferred model data (44, 44', 44'') to implement the model architecture (46) in the embedded system.

30. The computer-implemented method as claimed in any one of claims 28 to 29, wherein the objective function includes measurements of runtime and / or output and / or data rate and / or power consumption during defect identification.

31. The computer-implemented method as described in any one of claims 28 to 29, wherein the objective function includes a quality measure of defect identification.

32. The computer implementation method as described in claim 28, wherein the at least one image acquisition parameter is from a group including imaging time, image resolution, pixel size, impact energy, and residence time of the electron wave.

33. The computer implementation method as claimed in any one of claims 28 to 29, wherein the objective function includes a measurement of the number of bits of the input data of the machine learning model (40, 40', 40'').

34. The computer implementation method as claimed in any one of claims 1 to 4 and 28 to 29 further includes determining one or more measurements of the identified defects (16) in the imaging dataset (12, 12', 12'') of the wafer (226), particularly size, area, dimensions, shape parameters, distance, radius, aspect ratio, type, number of defects, density, spatial distribution of defects, etc.

35. The computer implementation method as described in claim 34 further includes evaluating the quality of the wafer (226) based on the one or more measurements and at least one quality assessment rule.

36. The computer implementation method as described in claim 34 further includes controlling at least one wafer process parameter based on one or more measurements of the defects identified in the imaging dataset of the wafer.

37. A computer-readable medium having stored thereon a computer program executable by a computer device, the computer program including program code for performing the methods described in any one of claims 1 to 36.

38. A computer program product containing multiple instructions, which, when executed by a computer, causes the computer to perform the method described in any one of claims 1 to 36.

39. A system (212) for controlling the quality of a plurality of wafers (226) produced in a semiconductor manufacturing plant, the system (212) comprising: - an imaging device (214) adapted to provide an imaging data set (12, 12', 12'') of a wafer (226); - one or more processing devices (216); - at least one embedded system (50, 50'); - one or more machine-readable hardware storage devices containing a plurality of instructions executable by the one or more processing devices (216) to perform a plurality of operations comprising the methods described in claim 35.

40. A system (228) for controlling a plurality of wafers (226) produced in a semiconductor manufacturing plant, the system (228) comprising: - components (230) for producing the wafers (226) controlled by at least one process parameter; - an imaging device (214) adapted to provide an imaging dataset (12, 12', 12'') of a wafer (226); - one or more processing devices (216); - at least one embedded system (50, 50'); - one or more machine-readable hardware storage devices containing a plurality of instructions executable by the one or more processing devices (216) to perform a plurality of operations comprising the methods described in claim 36.

41. The system as described in claim 39 or 40 (212, 228) further includes a database (225).

42. A system (232) for controlling a plurality of wafers (226) produced in a semiconductor manufacturing plant, the system (232) comprising: - an imaging device (214) adapted to provide an imaging data set (12, 12', 12'') of a wafer (226); - one or more processing devices (216); - one or more machine-readable hardware storage devices containing a plurality of instructions executable by the one or more processing devices (216) to perform a plurality of operations comprising the methods described in claim 35.

43. A system (234) for controlling a plurality of wafers (226) produced in a semiconductor manufacturing plant, the system (234) comprising: - components (230) for producing the wafers (226) controlled by at least one process parameter; - an imaging device (214) adapted to provide an imaging dataset (12, 12', 12'') of a wafer (226); - one or more processing devices (216); - one or more machine-readable hardware storage devices containing a plurality of instructions executable by the one or more processing devices (216) to perform a plurality of operations comprising the methods described in claim 36.

44. The system (212, 228, 232, 234) of any one of claims 39, 40 and 42 to 43 further includes a display device (227).

45. The system (212, 228, 232, 234) as described in any one of claims 39, 40 and 42 to 43 further includes a user interface (224).

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