Method for manufacturing semiconductor device structure

Abstract

One embodiment of this disclosure provides a method for manufacturing a semiconductor device structure. The method includes removing a first semiconductor layer disposed between a second semiconductor layer and a third semiconductor layer, and performing an oxide backfill process to form a seamless dielectric material between the second and third semiconductor layers. The oxide backfill process includes exposing the second conductor layer and the third semiconductor layer to a silicon-containing precursor for a first duration to form a monolayer, and exposing the monolayer to an oxygen-containing precursor for a second duration to form a seamless dielectric material. The oxygen-containing precursor has a second flow rate, the second flow rate being approximately 2 to approximately 20 times the first flow rate, and the second duration being approximately 2 to approximately 20 times the first duration.

Description

Method for manufacturing a semiconductor device structure Embodiments of the present invention relate to semiconductor technology, and more particularly to a method for manufacturing a semiconductor device structure having a seamless dielectric material. The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have led to several generations of integrated circuits, with each successive generation being smaller and more complex than the previous one. During the evolution of integrated circuits, the functional density (i.e., the number of interconnect devices per unit chip area) generally increases while the geometric size (i.e., the smallest component (or line) that can be produced using the process) decreases. This process of miniaturization typically provides benefits in terms of increased production efficiency and reduced associated costs. This miniaturization is also accompanied by more complex designs and processes for incorporating the integrated circuits into devices. Therefore, there is a need to improve the processes and manufacturing of integrated circuits. One embodiment is a method for manufacturing a semiconductor device structure. The method includes removing a first semiconductor layer disposed between a second semiconductor layer and a third semiconductor layer, and performing an oxide refill process to form a seamless dielectric material between the second semiconductor layer and the third semiconductor layer. The oxide refill process includes exposing the second semiconductor layer and the third semiconductor layer to a silicon-containing precursor for a first duration to form a monolayer, the silicon-containing precursor having a first flow rate and a chemical structure: and each R group contains at least two carbons. The oxide refill process further includes exposing the monolayer to an oxygen-containing precursor for a second duration to form the seamless dielectric material, the oxygen-containing precursor having a second flow rate, the second flow rate being about 2 to about 20 times the first flow rate, and the second duration being about 2 to about 20 times the first duration. Another embodiment is a method of manufacturing a semiconductor device structure. The method includes forming a fin structure from a substrate, wherein the fin structure includes a semiconductor layer stack, and the semiconductor layer stack includes a plurality of alternating first semiconductor layers and a plurality of second semiconductor layers. The method further includes forming a sacrificial gate stack on a first portion of the fin structure, recessing a second portion of the fin structure, removing the second semiconductor layer disposed under the sacrificial gate stack to form a plurality of openings between vertically adjacent first semiconductor layers, and performing an atomic layer deposition process to form a seamless dielectric material in the openings. The atomic layer deposition process includes performing a plurality of first cycles, each of the first cycles including flowing a first silicon-containing precursor into the process chamber at a first flow rate for a first duration, and flowing a first oxygen-containing precursor into the process chamber at a second flow rate for a second duration, and then performing a plurality of second cycles, each of the second cycles including flowing a second silicon-containing precursor different from the first silicon-containing precursor into the process chamber at a third flow rate for a third duration, and flowing a second oxygen-containing precursor into the process chamber at a fourth flow rate for a fourth duration. Another embodiment is a method of manufacturing a semiconductor device structure. The method includes forming a fin structure from a substrate, wherein the fin structure includes a semiconductor layer stack, and the semiconductor layer stack includes a plurality of alternating first semiconductor layers and a plurality of second semiconductor layers. The method further includes recessing a portion of the fin structure to expose a well portion of the fin structure, removing the second semiconductor layer to form a plurality of openings between vertically adjacent first semiconductor layers, and performing a hybrid atomic layer deposition process to form a seamless dielectric material in the openings. The hybrid atomic layer deposition process includes performing a plasma-enhanced atomic layer deposition process at a first temperature, and then performing a thermal atomic layer deposition process at a second temperature, the second temperature being substantially greater than the first temperature. The method further includes forming source / drain regions from the well portion, removing the seamless dielectric material, and forming a gate electrode layer surrounding exposed portions of the first semiconductor layer. The following disclosure provides many embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, when it is described that a first element is formed on a second element, embodiments where the first and second elements are in direct contact may be included, and embodiments where additional elements are formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the present invention may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations discussed. Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", "on", "top", "higher", and the like, may be used herein for ease of description to describe the relationship of one or more components or elements to another component or element in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation as well as the orientation depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will be interpreted accordingly to the new orientation. Embodiments of the present disclosure provide a semiconductor device structure and a method of manufacturing the same. In some embodiments, an oxide refill process, such as a thermal horizontal oxide refill (THOR) process, is performed to form a seamless dielectric material between vertically adjacent semiconductor layers. Although some embodiments described herein are described in the context of nanosheet channel field-effect transistors (FETs), implementations of some aspects of the present disclosure may be used in other processes and / or other devices, such as horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, and other suitable devices. Those of ordinary skill in the art will readily understand other modifications that can be made within the scope of the present disclosure. In the case of using a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the structure, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography processes with self-alignment processes to create patterns with, for example, a smaller pitch than that obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the GAA structure. FIGS. 1 to 20 illustrate exemplary processes for manufacturing a semiconductor device structure 100 in accordance with embodiments of the present disclosure. It should be understood that additional operations may be provided before, during, and after the steps shown in FIGS. 1 to 20 for additional embodiments of the method, and in additional embodiments of the method, some of the steps described below may be replaced or deleted. The order of the steps / processes is not limited and may be interchanged. FIG. 1 to FIG. 10 are perspective views showing a semiconductor device structure 100 at various manufacturing stages according to some embodiments. As shown in FIG. 1, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over a front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhancement. In one aspect, the insulating layer is an oxygen-containing layer. The substrate 101 may include various regions doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be, for example, boron for an n-type field effect transistor (NFET) and phosphorus for a p-type field effect transistor (PFET). The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of a nanostructured channel in a multi-gate device such as a nanosheet channel FET. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of silicon (Si), and the second semiconductor layer 108 may be made of silicon germanium (SiGe). In some examples, the first semiconductor layer 106 may be made of silicon germanium (SiGe), and the second semiconductor layer 108 may be made of silicon (Si). Alternatively, in some embodiments, either of the semiconductor layers 106, 108 may be or may include other materials such as germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or any combination of the foregoing. The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, epitaxial growth of the layers of the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. The first semiconductor layer 106 or a portion of the first semiconductor layer 106 can form the (multiple) nanosheet channels of the semiconductor device structure 100 in a subsequent manufacturing stage. The term nanostructure is used herein to refer to any material portion having nano-scale or even micro-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of this portion. Thus, this term refers to elongated material portions with circular and substantially circular cross-sections, as well as bundle or strip-shaped material portions, including, for example, cylindrical or substantially rectangular cross-sections. The (multiple) nanosheet channels of the semiconductor device structure 100 can be surrounded by gate electrodes. The semiconductor device structure 100 can include nanostructure transistors. Nanostructure transistors can be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below. Each first semiconductor layer 106 can have a thickness in the range of about 5 nanometers (nm) to about 30 nm. Each second semiconductor layer 108 can have a thickness equal to, less than, or greater than that of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in the range of about 2 nm to about 50 nm. Three first semiconductor layers 106 and three second semiconductor layers 108 are alternately arranged, as shown in FIG. 1, for illustrative purposes and not intended to limit beyond what is specifically set forth in the claims. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100. As shown in FIG. 1, an oxide layer 110 is formed on the topmost first semiconductor layer 106, and a nitride layer 111 is formed on the oxide layer 110. The oxide layer 110 can be silicon oxide and can have different etching selectivities compared to the nitride layer 111. The nitride layer 111 can include any suitable nitride material, such as silicon nitride. In some embodiments, the oxide layer 110 and the nitride layer 111 can be a mask structure. In FIG. 2, the fin structure 112 is formed by the semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106 and 108, and a well portion 116 formed by the substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (such as the oxide layer 110 and the nitride layer 111) formed on the semiconductor layer stack 104 by using a multiple patterning operation including lithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The lithography process can include forming a photoresist layer (not shown) above the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element can be performed using an electron beam (e-beam) lithography process. The etching process forms trenches 114 through the hard mask layer, the semiconductor layer stack 104 and into the substrate 101 in the unprotected areas, leaving a plurality of extended fin structures 112. The trenches 114 extend in the X direction. Dry etching (e.g., RIE), wet etching, and / or a combination of the foregoing can be used to etch the trenches 114. In FIG. 3, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. Then, a planarization operation such as a chemical mechanical polishing (CMP) method and / or an etch-back method is performed to expose the tops of the fin structures 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), fluorine-doped silicate glass (FSG), a low dielectric constant (K) dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or flowable CVD (FCVD). In FIG. 4, the insulating material 118 is recessed to form the isolation region 120. The recess of the insulating material 118 exposes portions of the fin structure 112, such as the semiconductor layer stack 104. The recess of the insulating material 118 causes the trench 114 to be formed between adjacent fin structures 112. A suitable dry etching process, wet etching process, or a combination of the foregoing can be used to form the isolation region 120. The top surface of the insulating material 118 can be flush with or lower than the surface of the second semiconductor layer 108, and the second semiconductor layer 108 is in contact with the well portion 116 formed by the substrate 101. In some embodiments, the isolation region 120 is a shallow trench isolation (STI). In some embodiments, the oxide layer 110 and the nitride layer 111 are also removed during the recess of the insulating material 118. In FIG. 5, one or more sacrificial gate structures 130 are formed over the semiconductor device structure 100. The sacrificial gate structures 130 are formed over the first portion of the fin structure 112 and the first portion of the isolation region 120 while exposing the second portion of the fin structure 112 and the second portion of the isolation region 120. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. In some embodiments, the mask layer 136 is a multi-layer structure. For example, the mask layer 136 includes an oxide layer 135 and a nitride layer 137 formed on the oxide layer 135. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 can be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these film layers into the sacrificial gate structures 130. The sacrificial gate dielectric layer 132 may include one or more layers of dielectric materials, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as the channel region of the semiconductor device structure 100. In FIG. 6, a gate spacer layer 138 is formed to cover the sacrificial gate structures 130, the second portion of the fin structure 112, and the second portion of the isolation region 120. The gate spacer layer 138 may include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbide, silicon oxynitride carbonitride (SiOCN), and / or a combination of the foregoing. In some embodiments, the gate spacer layer 138 is formed by a conformal process, such as an atomic layer deposition (ALD) process. In some embodiments, the thickness of the gate spacer layer 138 ranges from about 2 nm to about 10 nm. In FIG. 7, an anisotropic etching process is performed to remove the horizontal portion of the gate spacer layer 138. The anisotropic etching process can be a selective etching process that substantially does not affect the nitride layer 137, the first semiconductor layer 106, and the isolation region 120. In this way, the second portion of the fin structure 112 is exposed. In FIG. 8, one or more etching processes are performed to recess the exposed second portion of the fin structure 112 that is not covered by the sacrificial gate structure 130 (and the portion of the gate spacer layer 138 formed on the sidewalls of the sacrificial gate structure 130), and to remove a portion of the gate spacer layer 138. The portion of the gate spacer layer 138 formed on the sidewalls of the mask layer 136 may also be recessed. The one or more etching processes may include dry etching (such as reactive ion etching (RIE), neutral beam etch (NBE), etc.) and / or wet etching (such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH)). The one or more etching processes form the gate spacer 140, and the gate spacer 140 includes a first portion 140a formed on the sidewalls of the sacrificial gate electrode layer 134 and a second portion 140b formed on the second portion of the isolation region 120. In some embodiments, as shown in FIG. 8, the one or more etching processes also remove a portion of the second portion of the isolation region 120. In this way, the top surface 120t of the second portion of the isolation region 120 is located at a level substantially lower than the top surface 116t of the well portion 116. In FIG. 9, the second semiconductor layer 108 is removed. In some embodiments, the second semiconductor layer 108 includes germanium (Ge), and the subsequently formed source / drain (S / D) regions include phosphorus-doped silicon for n-type FETs. The Ge in the second semiconductor layer 108 and the phosphorus in the S / D regions may inter-diffuse, which can cause a high interfacial state density (Dit) on the first semiconductor layer 106. As a result, the mobility of the n-type device may be reduced. Therefore, in some embodiments, as shown in FIG. 9, the second semiconductor layer 108 is removed before forming the S / D regions. In some embodiments, the second semiconductor layer 108 is completely removed, and an opening 141 is formed between the vertically adjacent first semiconductor layers 106. The second semiconductor layer 108 can be removed by a selective etching process, such as a selective dry etching process, a selective wet etching process, or a combination of the foregoing. The selective etching process substantially does not affect the gate spacer 140, the first semiconductor layer 106, the isolation region 120, and the nitride layer 137. In FIG. 10, a dielectric material 143 is formed in the opening 141 and on the exposed surfaces of the semiconductor device structure 100. In some embodiments, the dielectric material 143 is an oxide, such as silicon dioxide, formed by a thermal horizontal oxide refill (THOR) process. In some embodiments, the THOR process is a thermal atomic layer deposition (thermal ALD) process. FIG. 10-1 is a cross-sectional side view of a portion 300 of the semiconductor device structure of FIG. 10 according to some embodiments. As shown in FIG. 10-1, the dielectric material 143 is formed not only in the opening 141 but also on the sidewalls of the sacrificial gate structure 130. In some embodiments, the gate spacer 140 includes two dielectric layers. FIGS. 11A to 11D are cross-sectional side views of a portion 200 of the semiconductor device structure 100 of FIG. 10 at various stages of a thermal atomic deposition process for forming a dielectric material 143, in accordance with some embodiments. The portion 200 includes a first semiconductor layer 106 that is vertically adjacent, and FIGS. 11A to 11D illustrate an ALD process for seamlessly forming the dielectric material 143 between the vertically adjacent first semiconductor layers 106. For clarity, the dielectric material 143 formed on the side surfaces of the first semiconductor layer 106 is omitted in FIGS. 11A to 11D. As shown in FIG. 11A, a monolayer 202 is formed on the exposed surface of the first semiconductor layer 106. In some embodiments, the monolayer 202 is formed by exposing the first semiconductor layer 106 to a silicon-containing precursor at a process temperature in the range of about 200 degrees Celsius to about 500 degrees Celsius (such as 250 degrees Celsius to about 400 degrees Celsius). The silicon-containing precursor can include any suitable silicon-containing material. In some embodiments, the silicon-containing precursor includes a material having the chemical structure shown in FIG. 12. As shown in FIG. 12, the silicon-containing precursor includes two R groups and two hydrogen atoms attached to the silicon atom. In some embodiments, each R group contains at least two carbons. The silicon-containing precursor can have a symmetric chemical structure. For example, the appearance of the molecule shown in FIG. 12 will not change when the molecule is rotated about line A-A (the axis of symmetry passing through the silicon atom). For the silicon-containing precursor shown in FIG. 12, it is more likely to form a peroxy linkage (POL) in the dielectric material 143, where a peroxy linkage is a bond between two oxygen atoms. Referring back to FIG. 11A, a silicon-containing precursor can flow into a processing chamber in which a semiconductor device structure 100 is disposed. The silicon-containing precursor has a first flow rate and a first duration. Next, the flow of the silicon-containing precursor is stopped and a pumping process is performed to pump out any silicon-containing precursor in the processing chamber. After the pumping process, an oxygen-containing precursor flows into the processing chamber, and the oxygen-containing precursor reacts with the single layer 202 to form a dielectric material 143, as shown in FIG. 11B. The process temperature during the inflow of the oxygen-containing precursor can be the same as the process temperature during the inflow of the silicon-containing precursor. In some embodiments, the process temperature ranges from about 200 degrees Celsius to about 500 degrees Celsius, such as from about 250 degrees Celsius to about 400 degrees Celsius. The oxygen-containing precursor can include any suitable oxygen-containing material. In some embodiments, the oxygen-containing precursor includes ozone. The oxygen-containing precursor can flow into the processing chamber at a second flow rate that is substantially greater than the first flow rate of the silicon-containing precursor. In some embodiments, the second flow rate can be 2 to 20 times the first flow rate, such as about 5 to about 10 times, or about 10 to about 20 times. The oxygen-containing precursor can flow into the processing chamber for a second duration that is substantially longer than the first duration of the silicon-containing precursor. In some embodiments, the second duration can be 2 to 20 times the first duration, such as about 5 to about 10 times, or about 10 to about 20 times. In some embodiments, the second flow rate is about 5 to about 10 times the first flow rate, and the second duration is about 5 to about 10 times the first duration. FIG. 13 illustrates various states of a compound formed by a thermal atomic deposition process according to some embodiments. As shown in FIG. 13, the dielectric material 143 formed by the process described in FIGS. 11A and 11B has states A, B, C, D, and E. In state A, a peroxy linkage (POL) is formed. In some embodiments, the POL is formed in state A by using a silicon-containing precursor having the chemical structure shown in FIG. 12 and ozone as an oxygen-containing precursor. If the process temperature of the thermal ALD process is greater than about 500 degrees Celsius, or if the deposition process is a plasma ALD process, reduction may occur, which changes the dielectric material 143 from state A to state C. As described above, in some embodiments, the flow rate of the oxygen-containing precursor is about 2 times to about 20 times, such as about 10 times to about 20 times, the flow rate of the silicon-containing precursor. In some embodiments, the duration for which the semiconductor device structure 100 is exposed to the oxygen-containing precursor is about 2 times to about 20 times, such as about 10 times to about 20 times, the duration for which the semiconductor device structure 100 is exposed to the silicon-containing precursor. In some embodiments, the flow rate of the oxygen-containing precursor is about 5 times to about 10 times the flow rate of the silicon-containing precursor, and the duration for which the semiconductor device structure 100 is exposed to the oxygen-containing precursor is about 5 times to about 10 times the duration for which the semiconductor device structure 100 is exposed to the silicon-containing precursor. These process conditions facilitate the activation of the dielectric material 143 in state A, which results in state E, as shown in FIG. 13. The dielectric material 143 in state E is unstable and more prone to network re-organization, resulting in the dielectric material 143 being in state F, as shown in FIG. 13. The state change from state A to state E and then to state F can produce a seamless dielectric material 143, which is described in detail in FIG. 11D. If the flow rate of the oxygen-containing precursor is less than 10 times the flow rate of the silicon-containing precursor, the duration of exposure to the oxygen-containing precursor is less than 10 times the duration of exposure to the silicon-containing precursor, or the combined flow rate of the oxygen-containing precursor is less than 5 times the flow rate of the silicon-containing precursor and the duration of exposure to the oxygen-containing precursor is less than 5 times the duration of exposure to the silicon-containing precursor, it is more beneficial for the reduction and / or oxygen vacancy recovery of the dielectric material 143 in state A. In this way, the dielectric material 143 can be changed from state A to state B and / or state D. On the other hand, if the flow rate of the oxygen-containing precursor is greater than 20 times the flow rate of the silicon-containing precursor, the duration of exposure to the oxygen-containing precursor is greater than 20 times the duration of exposure to the silicon-containing precursor, or the combined flow rate of the oxygen-containing precursor is greater than 10 times the flow rate of the silicon-containing precursor and the duration of exposure to the oxygen-containing precursor is greater than 10 times the duration of exposure to the silicon-containing precursor, the manufacturing cost increases without obvious advantages. In other words, using the thermal ALD process of the silicon-containing precursor shown in FIG. 12, ozone as the oxygen-containing precursor, a faster flow rate of the oxygen-containing precursor, and / or a longer duration of exposure to the oxygen-containing precursor, the formed dielectric material 143 has improved horizontal gap filling ability. After exposing the semiconductor device structure 100 to an oxygen precursor, the process chamber is pumped down again. The flow of the silicon precursor into the process chamber and the flow of the oxygen precursor into the process chamber (with the process chamber being pumped down between the two steps) are considered a cycle of the thermal ALD process. After multiple cycles, the dielectric material 143 fills the opening 141 vertically adjacent between the first semiconductor layers 106, as shown in FIGS. 11C and 11D. As shown in FIG. 11C, a single layer 202 is formed on the dielectric material 143, and a gap is formed between a portion of the single layer 202 formed above the bottom first semiconductor layer 106 and a portion of the single layer 202 formed below the top first semiconductor layer 106. The gap is very small. In some embodiments, the gap ranges from about 0.1 nm to about 0.3 nm. In some embodiments, the gap is less than the bond length of Si-O-O-Si. Next, the oxygen precursor flows into the process chamber and reacts with the single layer 202 to form the dielectric layer 143. As described above, the process conditions are favorable for the dielectric material 143 to change from state A to state E and then to state F. As shown in FIG. 13, the Si-O-O-Si in state A breaks into dangling Si bonds and peroxy radicals, as shown in state E. Since the gap between the portions of the single layer 202 is very small, the peroxy radicals of the portion of the single layer 202 formed above the bottom first semiconductor layer 106 can bond with the dangling Si bonds of the portion of the single layer 202 formed below the top first semiconductor layer 106, which changes the dielectric material 143 from state E to state F. In this way, the gap is filled and the dielectric material 143 seamlessly fills the opening 141. Additionally, the dielectric material 143 formed through the process described in FIGS. 11A to 11D has a wet etching rate greater than about 100 Angstroms per minute (using a 1:100 diluted hydrofluoric acid (HF) solution). In some embodiments, the thermal ALD process includes multiple cycles to form the dielectric material 143. A first number of cycles are performed under a first process condition, and a second number of cycles are performed under a second process condition different from the first process condition. The second process condition can be the process condition described in FIGS. 11A to 11D, and the first process condition can result in rapid deposition and / or use less precursor. For example, the first process condition can include flowing a silicon-containing precursor and an oxygen-containing precursor at substantially the same flow rate and / or for the same duration. In some embodiments, the flow rate of the silicon-containing precursor under the first process condition is the same as the flow rate of the silicon-containing precursor under the second process condition, and the flow rate of the oxygen-containing precursor under the second process condition is about 2 to about 20 times the flow rate of the oxygen-containing precursor under the first process condition. In some embodiments, the duration of exposure to the silicon-containing precursor under the first process condition is the same as the duration of exposure to the silicon-containing precursor under the second process condition, and the duration of exposure to the oxygen-containing precursor under the second process condition is about 2 to about 20 times the duration of exposure to the oxygen-containing precursor under the first process condition. The process temperature under the first process condition can be greater than 500 degrees Celsius. The silicon-containing precursor in the first process condition can be any suitable silicon-containing material, such as silane, disilane, dichlorosilane, trichlorosilane, and the oxygen-containing precursor can be any suitable oxygen-containing material, such as oxygen, nitrogen dioxide (NO 2 ), carbon dioxide (CO 2 ). In some embodiments, about 60% to about 90% of the multiple cycles are performed under the first process condition, and about 10% to about 40% of the multiple cycles are performed under the second process condition. After the cycles performed under the first process condition, the cycles performed under the second process condition are performed. In other words, the thermal ALD process includes performing multiple first cycles under the first process condition to form the dielectric material 143 between vertically adjacent first semiconductor layers 106, and forming a gap between portions of the dielectric material 143 formed on the top first semiconductor layer 106 and the bottom first semiconductor layer 106. The thermal ALD process further includes performing multiple second cycles under the second process condition to fill the gap with the dielectric material 143, and the resulting dielectric material 143 between the vertically adjacent first semiconductor layers 106 is seamless. In some embodiments, the multiple first cycles include a first number of cycles, the multiple second cycles include a second number of cycles, and the first number of cycles is about 1.5 to about 9 times the second number of cycles. In some embodiments, a low-temperature thermal ALD process is performed to form the dielectric material 143. The deposited dielectric material 143 includes SiO 2 , where the silicon-to-oxygen ratio is less than about 2. The deposition temperature ranges from about 200 degrees Celsius to about 500 degrees Celsius, and the deposition rate in growth per cycle (GPC) for each cycle ranges from about 0.01 angstroms / cycle to about 10 angstroms / cycle or from about 0.1 angstroms / minute to about 20 angstroms / minute. The low-temperature thermal ALD process can be single chamber ALD or batch type ALD. In some embodiments, an organosilicon precursor and an oxygen-containing precursor are used in the low-temperature thermal ALD process. The oxygen-containing precursor can include O 2 radicals and / or O 3 . If the process temperature is properly controlled, a self-limited effect can be achieved. The dielectric material 143 deposited by the low-temperature thermal ALD process can have a wet etch rate (WER) greater than 100 angstroms / minute (such as from about 100 angstroms / minute to about 800 angstroms / minute) in 1:100 diluted hydrofluoric acid with a density ranging from about 1.5 g / cm 3 (g / cm 3 ) to about 2.3 g / cm 3 . Using Fourier-transform infrared spectroscopy (FTIR), the dielectric material 143 can have an -OH peak feature at 3400±100. The dielectric material 143 can have a leakage greater than about 1x10 -6 amperes / cm 2 (A / cm 2 ) at 2 MV / cm. During the deposition of the dielectric material 143, the silicon consumption of the first semiconductor layer 106 can range from about 2 angstroms to about 10 angstroms due to oxidation. The dielectric material 143 can include carbon and nitrogen with an atomic concentration less than 1x10 4 and greater than 1x10 4Atomic concentration of hydrogen and hydroxides. The roughness of the dielectric material 143 can be less than 0.5 angstroms (root mean square, RMS) or less than 5 angstroms (Rmax). In some embodiments, a hybrid ALD process is performed to form a seamless dielectric material 143 between vertically adjacent first semiconductor layers 106. The hybrid ALD process includes a plasma stage and a thermal stage. For example, the plasma stage includes a plurality of first cycles performed as a plasma enhanced atomic layer deposition (PEALD) process, and the thermal stage includes a plurality of second cycles performed as a thermal ALD process. The thermal ALD process can be the thermal ALD process described in FIGS. 11A to 11D. The PEALD process can be performed at a substantially lower process temperature, such as from about 50 degrees Celsius to about 100 degrees Celsius. The silicon-containing precursor and the oxygen-containing precursor in the PEALD can be the same as the silicon-containing precursor and the oxygen-containing precursor of the first process conditions described above, and the silicon-containing precursor and the oxygen-containing precursor can be activated by plasma, such as capacitively coupled plasma (CCP), inductively coupled plasma (ICP), transformer coupled plasma (TCP). Similar to the first process conditions, compared with the second process conditions of the thermal ALD (or the thermal stage of the hybrid ALD), the plasma stage of the hybrid ALD uses fewer precursors and is faster. FIGS. 14 to 20 are perspective views showing the semiconductor device structure 100 at various manufacturing stages according to some embodiments. As shown in FIG. 14, an etch-back process is performed to remove a portion of the dielectric material 143, except for the portion of the dielectric material 143 formed in the opening 141. In some embodiments, the etch-back process is an anisotropic etching process. At this stage, as shown in FIG. 14, the ends of the dielectric material 143 and the ends of the first semiconductor layer 106 have substantially flat surfaces, and the flat surfaces can be flush with the corresponding first portions 140a of the gate spacers 140. As shown in FIG. 15, the ends of the dielectric material 143 are horizontally removed along the X direction. In other words, the dielectric material 143 is recessed along the X direction. The removal of the ends of the dielectric material 143 forms cavities. In some embodiments, the ends of the dielectric material 143 are removed by a selective wet etching process using an etchant (such as hydrofluoric acid (HF) and ammonia water (NH 3 3), diluted hydrofluoric acid (DHF) solution, or deionized water with ozone and DHF solution). FIG. 15-1 is a cross-sectional side view of a portion 300 of the semiconductor device structure of FIG. 15, according to some embodiments. As shown in FIG. 15-1, the ends of the dielectric material 143 are removed, and a cavity is formed between the vertically adjacent first semiconductor layers 106. FIG. 15-2 is a cross-sectional side view of a portion 200 of the semiconductor device structure of FIG. 15, according to some embodiments. As shown in FIG. 15-2, the dielectric material 143 includes side surfaces 143s after a horizontal depression. Since the dielectric material 143 is formed seamlessly between the adjacent first semiconductor layers 106, the side surfaces 143s are substantially linear. If a seam is formed in the dielectric material 143, the side surfaces 143s may be concave, which may cause an electrical short circuit between the gate electrode layer 172 (FIG. 20) and the S / D region 146 (FIG. 20). As shown in FIG. 16, after removing the ends of the dielectric material 143, a dielectric layer is deposited in the cavity to form dielectric spacers 144. The dielectric spacers 144 can be made of a dielectric material such as silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxynitride carbonitride (SiOCN), or silicon nitride (SiN). The formation of the dielectric spacers 144 can be achieved by first forming a conformal dielectric layer using a conformal deposition process such as ALD, and then performing an anisotropic etching to remove portions of the conformal dielectric layer other than the dielectric spacers 144. During the anisotropic etching process, the dielectric spacers 144 are protected by the first semiconductor layers 106. As shown in FIG. 16, the dielectric material 143 covers between the dielectric spacers 144 in the X direction. In some embodiments, the dielectric spacers 144 and the dielectric material 143 include different materials having different etching selectivities. As shown in FIG. 17, the source / drain (S / D) region 146 is formed by the well region 116. In some embodiments, the S / D region 146 can grow vertically and horizontally to form facets that can correspond to the crystalline planes of the material used for the well region 116. In the present disclosure, the source region and the drain region can be used interchangeably and have substantially the same structure. In addition, the source / drain region can refer to the source or the drain individually or collectively depending on the context. In some embodiments, the S / D region 146 is an n-type S / D epitaxial component and can be made of one or more layers of silicon (Si), silicon phosphide (SiP), silicon carbide (SiC), and silicon carbon phosphide (SiCP) used for n-type channel FETs. In some embodiments, the S / D region 146 is a p-type epitaxial component and can be made of one or more layers of silicon (Si), silicon germanium (SiGe), and germanium (Ge) used for p-type channel FETs. For p-type channel FETs, p-type dopants such as boron (B) can also be included in the S / D region 146. The S / D region 146 can be formed by an epitaxial growth method using CVD, atomic layer deposition (ALD), or molecular beam epitaxy (MBE). As described above, the second semiconductor layer 108 (FIG. 8) is removed during the formation of the S / D region 146. In this way, the germanium (Ge) source is removed before forming the S / D region 146 and the high interfacial state density (Dit) is improved. As shown in FIG. 17, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the sidewalls of the first portion 140a of the gate spacer 140 and is disposed on the second portion 140b of the gate spacer 140 and the S / D regions 146. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, etc., or a combination of the foregoing, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 163 is formed on the CESL 162. The material of the ILD layer 163 may include a compound containing silicon (Si), oxygen (O), carbon (C), and / or hydrogen (H), such as silicon oxide, silicon carbon hydroxide (SiCOH), or silicon carbon oxide (SiOC). An organic material such as a polymer may also be used for the ILD layer 163. The ILD layer 163 may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after the ILD layer 163 is formed, the semiconductor device structure 100 may be subjected to a heat treatment to anneal the ILD layer 163. A planarization process is performed to expose the sacrificial gate electrode layer 134, as shown in FIG. 17. The planarization process may be any suitable process, such as a chemical mechanical polish (CMP) process. The planarization process removes a portion of the ILD layer 163 and a portion of the CESL 162 disposed on the sacrificial gate stack 130. The planarization process may also remove the mask structure 136. As shown in FIG. 18, the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132 are removed, exposing a portion of the top surface of the topmost first semiconductor layer 106. The first portion of the isolation region 120 is also exposed. The sacrificial gate electrode layer 134 may first be removed by any suitable process, such as dry etching, wet etching, or a combination of the foregoing, and then the sacrificial gate dielectric layer 132 is removed, which may be performed by any suitable process, such as dry etching, wet etching, or a combination of the foregoing. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the sacrificial gate electrode layer 134 without removing the spacer 140, the ILD layer 163, and the CESL 162. As shown in FIG. 19, the dielectric material 143 is removed. The dielectric material 143 can be removed by any suitable process. In some embodiments, the dielectric material 143 is removed by a selective etching process. The selective etching process can remove the dielectric material 143 between the first semiconductor layers 106, but does not remove the first semiconductor layers 106, the ILD layer 163, the CESL 162, and the gate spacers 140. After removing the dielectric material 143, portions of each first semiconductor layer 106 that are not covered by the dielectric spacers 144 can be exposed. Each first semiconductor layer 106 can be a nanostructured channel. As shown in FIG. 20, after forming the nanostructured channels (i.e., the exposed portions of the first semiconductor layers 106), a gate dielectric layer 170 is formed to surround the exposed portions of the first semiconductor layers 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 can be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) 168 is formed between the gate dielectric layer 170 and the exposed surfaces of the first semiconductor layers 106. The IL 168 can include an oxide, such as silicon oxide, and can be formed due to a cleaning process. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Exemplary high-k dielectric materials include hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), aluminum oxide (Al 2 O 3 ), hafnium oxide-aluminum oxide (HfO 2 -Al2O 3)(i) An alloy, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 can include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 can be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate dielectric layer 170 and the gate electrode layer 172 can also be deposited over the ILD layer 163. Then, the gate dielectric layer 170 and the gate electrode layer 172 formed over the ILD layer 163 are removed by using, for example, CMP until the top surface of the ILD layer 163 is exposed. Embodiments of the present disclosure provide a method for forming a semiconductor device structure 100. In some embodiments, the method is a THOR process. The THOR process can be a thermal ALD process, a thermal ALD process with different process conditions for different numbers of cycles, or a hybrid ALD process. Some embodiments can achieve advantages. For example, the dielectric material 143 formed between vertically adjacent first semiconductor layers 106 by the THOR process is seamless. One embodiment is a method of manufacturing a semiconductor device structure. The method includes removing a first semiconductor layer disposed between a second semiconductor layer and a third semiconductor layer, and performing an oxide refill process to form a seamless dielectric material between the second semiconductor layer and the third semiconductor layer. The oxide refill process includes: exposing the second conductor layer and the third semiconductor layer to a silicon-containing precursor for a first duration to form a monolayer, the silicon-containing precursor having a first flow rate and a chemical structure: and each R group contains at least two carbons. The oxide refill process further includes exposing the monolayer to an oxygen-containing precursor for a second duration to form a seamless dielectric material, the oxygen-containing precursor having a second flow rate, the second flow rate being about 2 to about 20 times the first flow rate, and the second duration being about 2 to about 20 times the first duration. In some embodiments, the second flow rate is about 10 times to about 20 times the first flow rate, or the second duration is about 10 times to about 20 times the first duration. In some embodiments, the second flow rate is about 5 times to about 10 times the first flow rate, and the second duration is about 5 times to about 10 times the first duration. In some embodiments, the oxygen-containing precursor includes ozone. In some embodiments, the process temperature of the oxide backfill process ranges from about 200 degrees Celsius to about 500 degrees Celsius. In some embodiments, the first semiconductor layer includes silicon germanium, and the second semiconductor layer and the third semiconductor layer each include silicon. Another embodiment is a method of manufacturing a semiconductor device structure. The method includes forming a fin structure from a substrate, wherein the fin structure includes a semiconductor layer stack including a plurality of alternating first semiconductor layers and a plurality of second semiconductor layers. The method further includes forming a sacrificial gate stack on a first portion of the fin structure, recessing a second portion of the fin structure, removing the second semiconductor layer disposed under the sacrificial gate stack to form a plurality of openings between vertically adjacent first semiconductor layers, and performing an atomic layer deposition process to form a seamless dielectric material in the openings. The atomic layer deposition process includes performing a plurality of first cycles, each of the first cycles including flowing a first silicon-containing precursor into the process chamber at a first flow rate for a first duration, and flowing a first oxygen-containing precursor into the process chamber at a second flow rate for a second duration, and then performing a plurality of second cycles, each of the second cycles including flowing a second silicon-containing precursor different from the first silicon-containing precursor into the process chamber at a third flow rate for a third duration, and flowing a second oxygen-containing precursor into the process chamber at a fourth flow rate for a fourth duration. In some embodiments, the first flow rate is substantially the same as the second flow rate. In some embodiments, the third flow rate is substantially the same as the first flow rate. In some embodiments, the fourth flow rate is substantially greater than the second flow rate. In some embodiments, the first duration is substantially the same as the second duration. In some embodiments, the third duration is substantially the same as the first duration. In some embodiments, the fourth duration is substantially greater than the second duration. In some embodiments, the method further includes removing a plurality of ends of the seamless dielectric material to form a plurality of cavities. In some embodiments, the method further includes depositing a plurality of dielectric spacers in the cavities. In some embodiments, the first cycle includes a first number of cycles, and the second cycle includes a second number of cycles, and the second number of cycles is less than the first number of cycles. Another embodiment is a method of manufacturing a semiconductor device structure. The method includes forming a fin structure from a substrate, wherein the fin structure includes a semiconductor layer stack that includes a plurality of alternating first semiconductor layers and a plurality of second semiconductor layers. The method further includes recessing a portion of the fin structure to expose a well portion of the fin structure, removing the second semiconductor layers to form a plurality of openings between vertically adjacent first semiconductor layers, and performing a hybrid atomic layer deposition process to form a seamless dielectric material in the openings. The hybrid atomic layer deposition process includes performing a plasma-enhanced atomic layer deposition process at a first temperature and then performing a thermal atomic layer deposition process at a second temperature, the second temperature being substantially greater than the first temperature. The method further includes forming source / drain regions from the well portion, removing the seamless dielectric material, and forming a gate electrode layer around exposed portions of the first semiconductor layers. In some embodiments, the first temperature ranges from about 50 degrees Celsius to about 100 degrees Celsius, and the second temperature ranges from about 200 degrees Celsius to about 500 degrees Celsius. In some embodiments, the plasma-enhanced atomic layer deposition process includes a first number of cycles, and the thermal atomic layer deposition process includes a second number of cycles, the second number of cycles being less than the first number of cycles. In some embodiments, the first number of cycles is about 1.5 times to about 9 times the second number of cycles. The foregoing outlines components of several embodiments so that those of ordinary skill in the art to which the present invention pertains can more readily understand the perspective of the embodiments of the present invention. Those of ordinary skill in the art to which the present invention pertains should understand that they can, based on the embodiments of the present invention, design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those of ordinary skill in the art to which the present invention pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention. 100: Semiconductor device structure 101: Substrate 104: Semiconductor layer stack 106: First semiconductor layer 108: Second semiconductor layer 110: Oxide layer 111: Nitride layer 112: Fin structure 114: Trench 116: Well region 116t: Top surface 118: Insulating material 120: Isolation region 120t: Top surface 130: Sacrificial gate structure 132: Sacrificial gate dielectric layer 134: Sacrificial gate electrode layer 135: Oxide layer 136: Mask layer 137: Nitride layer 138: Gate spacer layer 140: Gate spacer 140a: First part 140b: Second part 141: Opening 143: Dielectric material 143s: Side surface 144: Dielectric spacer 146: Source / drain region 162: Contact etch stop layer 163: Interlayer dielectric layer 168: Interface layer 170: Gate dielectric layer 172: Gate electrode layer 174: Gate structure 200 / 300: Portion 202: Single layer A / B / C / D / E / F: State The various aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the elements can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present invention. FIGS. 1 to 10 are perspective views of a semiconductor device structure at various manufacturing stages according to some embodiments. FIG. 10-1 is a cross-sectional side view of a portion of the semiconductor device structure of FIG. 10 according to some embodiments. FIGS. 11A to 11D are cross-sectional side views of a portion of the semiconductor device structure of FIG. 10 at various stages of a thermal atomic deposition process according to some embodiments. FIG. 12 is a chemical structure of a silicon-containing precursor used in a thermal atomic deposition process according to some embodiments. FIG. 13 is a view showing various states of a compound formed by a thermal atomic deposition process according to some embodiments. FIGS. 14 to 20 are perspective views of a semiconductor device structure at various manufacturing stages according to some embodiments. FIG. 15-1 is a cross-sectional side view of a portion of the semiconductor device structure of FIG. 15 according to some embodiments. FIG. 15-2 is a cross-sectional side view of a portion of the semiconductor device structure of FIG. 15 according to some embodiments. 100: Semiconductor device structure 101: Substrate 116: Well region 118: Insulating material 120: Isolation region 130: Sacrificial gate structure 132: Sacrificial gate dielectric layer 134: Sacrificial gate electrode layer 135: Oxide layer 136: Mask layer 137: Nitride layer 140: Gate spacer 140a: First part 140b: Second part 143: Dielectric material 200 / 300: Portion

Claims

1. A method for manufacturing a semiconductor device structure, comprising: Removing a first semiconductor layer, wherein the first semiconductor layer is disposed between a second semiconductor layer and a third semiconductor layer, wherein removing the first semiconductor layer forms an opening between the second semiconductor layer and the third semiconductor layer; and performing an oxide refill process to form a seamless dielectric material to fill the opening between the second semiconductor layer and the third semiconductor layer, comprising: exposing the second semiconductor layer and the third semiconductor layer to a silicon-containing precursor for a first duration to form a monolayer, wherein the silicon-containing precursor has a first flow rate and a chemical structure: , wherein each R group contains at least two carbons; exposing the monolayer to an oxygen-containing precursor for a second duration to form the seamless dielectric material, wherein the oxygen-containing precursor has a second flow rate, the second flow rate being approximately 2 to approximately 20 times the first flow rate, and the second duration being approximately 2 to approximately 20 times the first duration.

2. A method for manufacturing a semiconductor device structure as claimed in claim 1, wherein the second flow rate is approximately 5 to approximately 10 times the first flow rate, and the second duration is approximately 5 to approximately 10 times the first duration.

3. A method for manufacturing a semiconductor device structure as claimed in claim 1 or 2, wherein the oxygen-containing precursor includes ozone.

4. A method for manufacturing a semiconductor device structure, comprising: Forming a fin structure from a substrate, wherein the fin structure includes a semiconductor layer stack comprising alternating plurality of first semiconductor layers and plurality of second semiconductor layers; forming a sacrificial gate stack on a first portion of the fin structure; recessing a second portion of the fin structure; removing the second semiconductor layers disposed below the sacrificial gate stack to form a plurality of openings between vertically adjacent first semiconductor layers; and performing an atomic layer deposition process to form a seamless dielectric material in the openings, including: Perform a plurality of first cycles, each of which includes flowing a first silicon-containing precursor into a process chamber at a first flow rate for a first duration, and flowing a first oxygen-containing precursor into the process chamber at a second flow rate for a second duration; and then perform a plurality of second cycles, each of which includes flowing a second silicon-containing precursor, different from the first silicon-containing precursor, into the process chamber at a third flow rate for a third duration, and flowing a second oxygen-containing precursor into the process chamber at a fourth flow rate for a fourth duration.

5. A method for manufacturing a semiconductor device structure as claimed in claim 4, wherein the first flow rate is substantially the same as the second and third flow rates, and the fourth flow rate is substantially greater than the second flow rate.

6. A method for manufacturing a semiconductor device structure as claimed in claim 4, wherein the first duration is substantially the same as the second duration and the third duration, and the fourth duration is substantially greater than the second duration.

7. The method of manufacturing a semiconductor device structure as claimed in claim 4 further includes removing multiple ends of the seamless dielectric material to form a plurality of cavities, and depositing a plurality of dielectric spacers in the cavities.

8. A method for manufacturing a semiconductor device structure, comprising: A fin structure is formed from a substrate, wherein the fin structure includes a semiconductor layer stack comprising alternating plurality of first semiconductor layers and plurality of second semiconductor layers; a portion of the fin structure is recessed to expose a well portion of the fin structure; the second semiconductor layers are removed to form a plurality of openings between vertically adjacent first semiconductor layers; Performing a hybrid atomic layer deposition process to form a seamless dielectric material in the openings includes: performing a plasma-enhanced atomic layer deposition process at a first temperature; and then performing a thermal atomic layer deposition process at a second temperature substantially greater than the first temperature; forming a source / drain region from the well; removing the seamless dielectric material; and forming a gate electrode layer surrounding a plurality of exposed portions of the first semiconductor layers.

9. A method of manufacturing a semiconductor device structure as claimed in claim 8, wherein the first temperature is in the range of about 50 degrees Celsius to about 100 degrees Celsius, and the second temperature is in the range of about 200 degrees Celsius to about 500 degrees Celsius.

10. A method of manufacturing a semiconductor device structure as claimed in claim 8, wherein the plasma-enhanced atomic layer deposition process includes a first number of cycles, and the thermal atomic layer deposition process includes a second number of cycles, the first number of cycles being approximately 1.5 to approximately 9 times the second number of cycles.

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