Methods of metal gapfill

Abstract

The embodiments of this disclosure relate to methods for filling metal interstitials with low resistivity. Specific embodiments provide a method for forming tungsten interstitials without a high-resistivity nucleation layer. Some embodiments of this disclosure utilize a nucleation underlayer to promote the growth of the metal interstitial filler.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to methods for depositing metal gapfill within substrate features. More particularly, embodiments of the present disclosure are directed to methods for providing gapfill having improved resistivity. Prior Art

[0002] The gapfill process is an integral part of some semiconductor manufacturing processes. It is used to fill gaps (or features) with insulating or conductive materials. For example, shallow trench isolation (STI), intermetallic dielectric (IMD) layers, passivation layers, and dummy gates are often implemented using the gapfill process.

[0003] As device geometries continue to shrink (e.g., critical dimensions <20 nm, <10 nm, and smaller), the reduction in metal volume creates higher resistivity for metal interconnects.

[0004] Typically, for tungsten gapfill, a nucleation layer comprising silicon or boron is deposited on top of a PVD tungsten liner before forming a tungsten bulk fill to promote the formation / growth of the bulk fill on the PVD liner. However, due to the presence of BW and / or WSi, these nucleation layers result in a relatively high resistance stack.

[0005] Therefore, there is a need for a gap filling method that provides lower resistivity. In particular, there is a need for a gap filling method that does not use a nucleation layer between the PVD liner and the bulk fill material. Summary of the Invention

[0006] One or more embodiments of the present disclosure are directed to a method for metal gapfill. The method includes exposing a substrate surface having at least one feature therein to a nucleation pre-soak to form a nucleation base layer. The feature extends from the substrate surface to a depth at its bottom and has two sidewalls. A metal liner is deposited on the nucleation base layer by physical vapor deposition (PVD). A metal gapfill is deposited on the metal liner and the nucleation base layer.

[0007] Additional embodiments of the present disclosure are directed to a method for metal gapfill. The method includes exposing a substrate surface having at least one feature therein to a nucleation pre-soak comprising silane to form a silicon nucleation base layer. The feature extends from the substrate surface to a depth at its bottom and has two sidewalls. A metal liner comprising tungsten is deposited on the silicon nucleation base layer by physical vapor deposition (PVD). A metal gapfill comprising tungsten is deposited over the metal liner and the silicon nucleation base layer.

[0008] Further embodiments of the present disclosure are directed to a method for metal gapfill. The method includes exposing a substrate surface having at least one feature therein to a nucleation pre-soak comprising diborane to form a boron nucleation primer. The feature extends from the substrate surface to a depth at its bottom and has two sidewalls. A metal liner comprising tungsten is deposited on the boron nucleation primer by physical vapor deposition (PVD). A metal gapfill comprising tungsten is deposited over the metal liner and the boron nucleation primer. Simple diagram description

[0009] In order to understand in detail the above-described features of the present disclosure, a more particular description of the present disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the disclosure and are therefore not to be considered limiting of its scope, as the disclosure may admit to other equally effective embodiments. The embodiments described herein are illustrated by way of example and not limitation in the figures of the accompanying drawings, wherein like reference numerals represent similar elements.

[0010] Figure 1 shows a process flow chart of a deposition method according to one or more embodiments;

[0011] 2A-2D illustrate cross-sectional views of a substrate during processing according to one or more embodiments; and

[0012] FIG. 3 illustrates a schematic top view of a multi-chamber processing system according to one or more embodiments. Implementation Method

[0013] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0014] As used herein, the term "about" means approximately or close to, and in the context of a value or range, refers to a variation of ±15% or less of the value. For example, values ​​that differ by ±14%, ±10%, ±5%, ±2%, ±1%, ±0.5%, or ±0.1% would meet the definition of "about."

[0015] As used in this specification and the appended claims, the term "substrate" or "wafer" refers to a surface or portion of a surface upon which a process is performed. Those skilled in the art will also understand that references to a substrate refer only to a portion of a substrate unless the context clearly indicates otherwise. Furthermore, deposition on a substrate can refer to both a bare substrate and a substrate upon which one or more films or features are deposited or formed.

[0016] As used herein, "substrate surface" refers to any substrate or surface of a material formed on a substrate upon which film processing is performed during a manufacturing process. For example, depending on the application, substrate surfaces that may be processed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, any of the film processing steps disclosed in this disclosure may also be performed on an underlying layer formed on the substrate, as described in more detail below, and the term "substrate surface" is intended to include such underlying layers as indicated by the context. Thus, for example, when a film / layer or portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0017] The substrate surface may have one or more features formed therein, one or more layers formed thereon, and combinations thereof. The shape of the features may be any suitable shape, including, but not limited to, grooves, holes, and vias (circular or polygonal). The term "feature," as used herein, refers to any intentional surface irregularity. Suitable examples of features include, but are not limited to, grooves having a top, two sidewalls, and a bottom extending into the substrate, and vias having one or more sidewalls extending into the substrate to the bottom.

[0018] The term "on..." indicates that there is direct contact between elements. The term "directly on..." indicates that there is direct contact between elements, with no intervening elements.

[0019] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactant gas," and the like are used interchangeably to refer to any gaseous species capable of reacting with a substrate surface.

[0020] Embodiments of the present disclosure advantageously provide methods for depositing a metal gapfill having low resistivity. Certain embodiments advantageously provide methods for depositing a metal gapfill having reduced resistivity, as opposed to methods utilizing a nucleation layer on a metal liner. In some embodiments, the metal of the disclosed metal liner and / or metal gapfill comprises tungsten.

[0021] The disclosed embodiments are described with reference to the accompanying drawings, which illustrate processes, substrates, and apparatus according to one or more embodiments of the present disclosure. The illustrated processes, schemes, and resulting substrates are merely illustrative of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0022] With reference to Figures 1 through 2D, the present disclosure relates to a method 100 for depositing a metal gapfill. Figure 1 depicts a process flow diagram of the deposition method 100 according to one or more embodiments of the present disclosure. Figures 2A through 2D depict a substrate 200 during processing according to one or more embodiments of the present disclosure.

[0023] FIG. 2A illustrates a substrate 200 having a substrate surface 205. As described above, a substrate surface refers to the exposed surface of a substrate on which layers may be formed. Substrate surface 205 has at least one feature 210 formed therein. While only a single feature is shown in the figure, those skilled in the art will recognize that multiple features may be affected by the disclosed method, each in a similar manner.

[0024] At least one feature 210 has an opening 212 having a width W. The opening 212 is formed in a top surface 215 of the substrate 200. The feature 210 also has one or more sidewalls 214 and extends a depth D from the top surface 215 to a bottom 216. Although straight, vertical sidewalls are shown, the disclosed methods can also be performed on sloped, irregular, or concave sidewalls.

[0025] In some embodiments, the width W of the opening 212 is greater than or equal to about 10 nm, greater than or equal to about 15 nm, greater than or equal to about 20 nm, greater than or equal to about 25 nm, greater than or equal to about 30 nm, or greater than or equal to about 35 nm. In some embodiments, the width W is in a range from about 5 nm to about 15 nm, or in a range from about 10 nm to about 35 nm.

[0026] In some embodiments, the depth D of feature 210 is greater than or equal to about 50 nm, greater than or equal to about 75 nm, greater than or equal to about 100 nm, greater than or equal to about 150 nm, greater than or equal to about 200 nm, or greater than or equal to about 250 nm. In some embodiments, the depth D is in a range from about 50 nm to about 250 nm, or in a range from about 200 nm to about 250 nm.

[0027] Those skilled in the art will recognize the increasing challenges of depositing metal gapfill in features with narrowing widths (also known as critical dimensions (CDs)) and / or increasing depths. The aspect ratio of at least one feature 210 is defined as the depth D divided by the width W of the feature 210. In some embodiments, the at least one feature has an aspect ratio (D:W) greater than or equal to approximately 2:1, greater than or equal to approximately 5:1, greater than or equal to approximately 10:1, or greater than or equal to approximately 20:1.

[0028] 1 and 2B , method 100 begins at operation 110. At 110, a nucleation bottom layer 220 is formed on substrate surface 205 and within at least one feature 210. In some embodiments, as shown in FIG. 2B , nucleation bottom layer 220 is continuous and deposited on top surface 215, sidewalls 214, and bottom 216.

[0029] At operation 110, a nucleation base layer 220 is formed by exposing the substrate surface to a nucleation pre-soak. In some embodiments, the nucleation pre-soak comprises a silicon compound. In some embodiments, the nucleation pre-soak comprises a boron compound. As used herein, "silicon compound" or "boron compound" refers to any material capable of forming a silicon or boron layer, respectively, on the substrate surface.

[0030] In some embodiments, the silicon compound comprises or consists essentially of silane (SiH₄), disilane, trisilane, trisilane, tetrasilane, cyclopentasilane, or cyclohexasilane. In some embodiments, the boron compound comprises or consists essentially of borane, diborane (B₂H₆), triborane, tetraborane, or cycloborane. As used herein, a process gas consisting essentially of a specified material comprises greater than approximately 95%, greater than approximately 98%, greater than approximately 99%, or greater than approximately 99.5% of the specified material on a molar basis, excluding any inert diluent or carrier gas.

[0031] In some embodiments, the nucleation bottom layer is substantially conformal. As used herein, a "substantially conformal" layer has an average thickness that varies by less than 10%, 5%, or 2% of the average thickness of the layer. In some embodiments, the nucleation bottom layer has an average thickness of less than 10 Å or less than 5 Å. In some embodiments, the nucleation bottom layer comprises 1-2 monolayers of silicon and / or boron.

[0032] In some embodiments, operation 110 represents a chemical vapor deposition (CVD) process. In some embodiments, the temperature of the CVD process is in a range of about 250° C. to about 450° C., about 250° C. to about 350° C., or about 350° C. to about 450° C. In some embodiments, the CVD process is performed without plasma.

[0033] After nucleation bottom layer 220 is formed, method 100 proceeds to operation 120. Referring to FIG. 2C , method 100 continues at operation 120 with the deposition of a metal liner 230 on nucleation bottom layer 220. In some embodiments, metal liner 230 is deposited by a physical vapor deposition process. In some embodiments, the metal liner is not continuous. In some embodiments, the metal liner does not cover the sidewalls 214 of feature 210. In some embodiments, the average thickness of metal liner 230 outside of at least one feature 210 is less than or equal to approximately 50 Å.

[0034] Without being limited by theory, it is believed that the presence of the nucleation bottom layer 220 promotes the growth of the metal gap fill 240 (described below) in areas not covered by the metal liner 230. In addition, the order of formation prevents the nucleation bottom layer 220 from forming a high resistance BW and / or WSi between the metal liner 230 and the metal gap fill 240.

[0035] After forming the metal liner 230, method 100 proceeds to operation 130. Referring to FIG. 2D, method 100 continues at operation 130 by depositing a metal gapfill 240 on the metal liner 230 and the nucleation bottom layer 220. In some embodiments, the metal gapfill 240 is deposited by an atomic layer deposition (ALD) process. In some embodiments, the metal gapfill 240 is deposited by a chemical vapor deposition (CVD) process. In some embodiments, the metal gapfill 240 is deposited by an atomic layer deposition (ALD) process followed by a chemical vapor deposition (CVD) process.

[0036] In some embodiments, the metal gapfill 240 is formed directly on the metal liner 230 and the nucleation bottom layer 220. In other words, in some embodiments, the metal gapfill 240 is deposited on the metal liner 230 without a typical nucleation layer. As discussed above, without being bound by theory, it is believed that the disclosed method provides a metal gapfill without using or forming a high-resistance nucleation layer. In some embodiments, the metal liner 230 and the metal gapfill 240 are referred to as a metal stack. In some embodiments, the nucleation bottom layer does not increase the resistance of the metal stack. Furthermore, the inventors have surprisingly discovered that the presence of the nucleation bottom layer 220 does not adversely affect the adhesion of the metal stack to the underlying substrate.

[0037] FIG3 is a schematic top view of an exemplary multi-chamber processing system 300 according to an embodiment of the present disclosure. The processing system 300 generally includes a factory interface 302, load lock chambers 304 and 306, transfer chambers 308 and 310 with corresponding transfer robots 312 and 314, holding chambers 316 and 318, and processing chambers 320, 322, 324, 326, 328, and 330. As described in detail herein, wafers in the processing system 300 can be processed in and transferred between various chambers without exposing the wafers to an ambient environment external to the processing system 300 (e.g., such as the ambient atmosphere that may exist in a wafer fab). For example, during various processes performed on wafers in the processing system 300, the wafers can be processed in and transferred between various chambers in a low pressure (e.g., less than or equal to approximately 300 Torr) or vacuum environment without disrupting the low pressure or vacuum environment. Thus, the processing system 300 can provide an integrated solution for several processing steps of a wafer.

[0038] Examples of processing systems that may be suitably modified according to the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc., located in Santa Clara, Calif. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from the aspects described herein.

[0039] In the illustrated example of FIG. 3 , the factory interface 302 includes a docking station 340 and a factory interface robot 342 to facilitate wafer transfer. The docking station 340 is configured to receive one or more front-opening unified pods (FOUPs) 344. In some examples, each factory interface robot 342 generally includes a blade 348 disposed on one end of the respective factory interface robot 342, which is configured to transfer wafers from the factory interface 302 to the load lock chambers 304, 306.

[0040] The load lock chambers 304 and 306 have respective ports 350 and 352 coupled to the factory interface 302 and respective ports 354 and 356 coupled to the transfer chamber 308. The transfer chamber 308 also has respective ports 358 and 360 coupled to the holding chambers 316 and 318 and respective ports 362 and 364 coupled to the processing chambers 320 and 322. Similarly, the transfer chamber 310 has respective ports 366 and 368 coupled to the holding chambers 316 and 318 and respective ports 370, 372, 374, and 376 coupled to the processing chambers 324, 326, 328, and 330. Ports 354, 356, 358, 360, 362, 364, 366, 368, 370, 372, 374, and 376 may be slit valve openings, for example, having slit valves, for wafers to be passed through by transfer robots 312 and 314 and for providing a seal between chambers to prevent gas transfer between them. Generally, any port is open for wafer transfer therethrough. Otherwise, the port is closed.

[0041] The load lock chambers 304, 306, transfer chambers 308, 310, holding chambers 316, 318, and processing chambers 320, 322, 324, 326, 328, 330 can be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits that fluidly connect the various chambers. In operation, the factory interface robot 342 transfers wafers from a FOUP 344 to a load lock chamber 304 or 306 via port 350 or 352. The gas and pressure control system then evacuates the load lock chamber 304 or 306. The gas and pressure control system also maintains the transfer chambers 308, 310 and holding chambers 316, 318 in an internal low-pressure or vacuum environment (which can include an inert gas). Thus, pumping of the load lock chamber 304 or 306 facilitates the transfer of wafers between, for example, the atmospheric environment of the factory interface 302 and the low pressure or vacuum environment of the transfer chamber 308 .

[0042] With the wafer in the already evacuated load lock chamber 304 or 306, the transfer robot 312 transfers the wafer from the load lock chamber 304 or 306 to the transfer chamber 308 via the port 354 or 356. The transfer robot 312 can then transfer the wafer to and / or between any of the processing chambers 320, 322 via the corresponding ports 362, 364 for processing, and transfer the wafer to the holding chamber 316, 318 via the corresponding ports 358, 360 for holding pending further transfer. Similarly, the transfer robot 314 can access wafers in the holding chamber 316 or 318 via port 366 or 368 and can transfer the wafers to and / or between any of the processing chambers 324, 326, 328, 330 for processing via the corresponding ports 370, 372, 374, 376, and transfer the wafers to the holding chamber 316, 318 via the corresponding ports 366, 368 for holding pending further transfer. The transfer and holding of wafers within and between different chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0043] Processing chambers 320, 322, 324, 326, 328, and 330 may be any suitable chambers for processing wafers. In some embodiments, processing chamber 320 may be capable of performing a nucleation pre-soak, processing chamber 322 may be capable of performing a PVD deposition process, and processing chamber 324 may be capable of performing an ALD and / or CVD deposition process.

[0044] A system controller 390 is coupled to the processing system 300 for controlling the processing system 300 or components thereof. For example, the system controller 390 can control the operation of the processing system 300 using direct control of the chambers 304, 306, 308, 316, 318, 310, 320, 322, 324, 326, 328, 330 of the processing system 300, or by controlling controllers associated with the chambers 304, 306, 308, 316, 318, 310, 320, 322, 324, 326, 328, 330. In operation, the system controller 390 can collect data and feedback from the various chambers to coordinate the performance of the processing system 300.

[0045] System controller 390 generally includes a central processing unit (CPU) 392, memory 394, and support circuits 396. CPU 392 can be any general-purpose processor suitable for use in an industrial environment. Memory 394, or non-transitory computer-readable media, is accessible by CPU 392 and can be one or more types of memory, such as random-access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital memory. Support circuits 396 are coupled to CPU 392 and can include cache memory, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein can generally be implemented under the control of CPU 392 by CPU 392 executing computer instruction code stored, for example, as software routines, in memory 394 (or the memory of a particular processing chamber). When the computer instruction code is executed by CPU 392, CPU 392 controls the chamber to perform processing according to the various methods.

[0046] Other processing systems may employ other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 308 and 310 and holding chambers 316 and 318. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chamber) may be implemented as the transfer device in the processing system.

[0047] The process can generally be stored as a software routine in the memory of the system controller 390. When executed by the processor, the software routine causes the processing chamber to perform the process of the present disclosure. The software routine can also be stored and / or executed by a second processor (not shown) that is remote from the hardware controlled by the processor. Some or all of the methods of the present disclosure can also be implemented in hardware. Thus, the process can be implemented in software and executed using a computer system, in hardware as, for example, an application-specific integrated circuit or other type of hardware, or as a combination of software and hardware. When executed by the processor, the software routine converts a general-purpose computer into a specialized computer (controller) that controls the operation of the chamber, thereby executing the process.

[0048] Embodiments of the present disclosure are directed to non-transitory computer-readable media. In one or more embodiments, the non-transitory computer-readable media includes instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform operations of any of the methods described herein (e.g., gapfill method 100). In one or more embodiments, the controller causes the processing chamber to perform operations of deposition method 100. In one or more embodiments, the controller causes the processing chamber to perform an operation of depositing a nucleation bottom layer on a substrate surface having at least one feature therein (operation 110). The at least one feature includes at least one surface defining a through-hole having a bottom surface and at least one sidewall. In one or more embodiments, the controller causes the processing chamber to deposit a metal liner on the substrate surface (operation 120).

[0049] For ease of description, spatially relative terms such as "below," "beneath," "below," "above," "upper," and similar terms may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both orientations of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0050] The use of the terms "a," "an," "the," and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the claims below) should be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better illuminate the materials and methods and does not limit the scope unless otherwise indicated. No language in the specification should be construed as indicating any non-claimed element is essential to the practice of the disclosed materials and methods.

[0051] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one disclosed embodiment. Thus, the appearance of phrases such as "in one or more embodiments," "certain embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0052] Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is intended to include modifications and variations that come within the scope of the appended claims and their equivalents.

[0053] 100: Method 110: Operation 120: Operation 130: Operation 200:Substrate 205:Substrate surface 210: Features 212: Open 214: Sidewall 215: Top surface 216: bottom 220: Nucleation bottom layer 230:Metal liner 240:Metal gap filling 300:Processing system 302:Factory Interface 304: Loading lock chamber 306: Loading lock chamber 308: Transfer chamber 310: Transfer chamber 312: Transfer Robot 314: Transfer Robot 316: Holding Chamber 318: Holding Chamber 320: Processing chamber 322: Processing chamber 324: Processing chamber 326: Processing chamber 328: Processing chamber 330: Processing chamber 340: Docking Station 342:Factory Interface Robot 344: Front-opening wafer transfer box 348: Blade 350: Port 352: Port 354: Port 356: Port 358: Port 360: Port 362: Port 364: Port 366: Port 368: Port 370: Port 372: Port 374: Port 376: Port 390: System Controller 392: Central Processing Unit (CPU) 394:Memory 396: Support Circuit D: Depth W: width

[0054] Domestic storage information (please note the order of storage institution, date, and number) none Overseas deposit information (please note the order of deposit country, institution, date, and number) none

Claims

1. A method for filling metal gaps, the method comprising the steps of: exposing a substrate surface having at least one feature to a nucleation pre-soak to form a nucleation substrate, the feature extending a depth from the substrate surface to a bottom and having two sidewalls; depositing a metal pad on the nucleation substrate by physical vapor deposition (PVD); and depositing a metal gap filler on the metal pad and the nucleation substrate.

2. The method as described in claim 1, wherein the aspect ratio of the at least one feature is at least 5:

1.

3. The method as described in claim 1, wherein the metal gasket and the metal gap filler comprise tungsten.

4. The method as described in claim 1, wherein the nucleation pre-soaking comprises a silicon compound.

5. The method as described in claim 4, wherein the nucleation pre-soaking is substantially composed of silane (SiH4).

6. The method as described in claim 1, wherein the nucleation pre-soaking comprises a boron compound.

7. The method as described in claim 6, wherein the nucleation pre-soaking is substantially composed of diborane (B₂H₆).

8. The method as described in claim 1, wherein the nucleation substrate comprises 1 to 2 silicon and / or boron monolayers.

9. The method as claimed in claim 1, wherein the average thickness of the metal pad on the substrate surface other than the at least one feature is about 50 Å.

10. The method as described in claim 1, wherein the metal gap is filled by atomic layer deposition (ALD).

11. The method as described in claim 1, wherein the metal interstitial filling is performed by chemical vapor deposition (CVD).

12. The method as described in claim 1, wherein the metal gap filler is formed directly on the metal liner and the nucleation substrate.

13. The method as described in claim 1, wherein the nucleation substrate does not increase the resistance of the metal pad and the metal gap fill stack.

14. The method as described in claim 1, wherein the nucleation substrate does not adversely affect the adhesion of the metal pad and the metal gap fill stack.

15. A method for filling metal gaps, the method comprising the steps of: exposing a substrate surface having at least one feature to a nucleation pre-soak comprising silane to form a silicon nucleation substrate, the feature extending a depth from the substrate surface to a bottom and having two sidewalls; depositing a metal pad comprising tungsten on the silicon nucleation substrate by physical vapor deposition (PVD); and depositing a metal gap fill comprising tungsten on the metal pad and the silicon nucleation substrate.

16. The method as described in claim 15, wherein the silicon nucleation substrate comprises an average of 1 to 2 silicon monolayers.

17. The method as described in claim 15, wherein the metal gap filler is formed directly on the metal liner and the nucleation substrate.

18. A method for filling metal gaps, the method comprising the steps of: exposing a substrate surface having at least one feature to a nucleation pre-soak comprising diborane to form a boron nucleation substrate, the feature extending a depth from the substrate surface to a bottom and having two sidewalls; depositing a tungsten-containing metal pad on the boron nucleation substrate by physical vapor deposition (PVD); and depositing a tungsten-containing metal gap filler on the metal pad and the boron nucleation substrate.

19. The method as described in claim 18, wherein the boron nucleation substrate comprises an average of 1 to 2 boron monolayers.

20. The method as described in claim 18, wherein the metal gap filler is formed directly on the metal liner and the nucleation substrate.

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