Semiconductor structure and method for forming the same

Abstract

A semiconductor structure is provided, comprising a functional cell region including an n-type functional transistor and a p-type functional transistor. The semiconductor structure also includes a first power transmission cell region, including a first dicing member and a first contact rail within the first dicing member. The semiconductor structure also includes a first power rail electrically connected to the source terminal of the p-type functional transistor and the first contact rail of the first power transmission cell region. The semiconductor structure also includes a second power transmission cell region adjacent to the first power transmission cell region, and includes a second dicing member and a second contact rail within the second dicing member. The semiconductor structure also includes an insulating strip extending from the first dicing member to the second dicing member in a first direction.

Description

Semiconductor Structure and Method of Forming the Same Embodiments of the present invention relate to semiconductor technology, and more particularly to a semiconductor structure and a method of forming the same. The electronics industry has an increasing demand for smaller and faster electronic devices that can support more and more complex and sophisticated functions at the same time. Therefore, manufacturing low-cost, high-performance, and low-power integrated circuits (ICs) in the semiconductor industry is a continuous trend. So far, these goals have been largely achieved by shrinking the size of semiconductor integrated circuits (e.g., minimizing component sizes), thereby improving production efficiency and reducing related costs. However, these miniaturizations have also increased the complexity of the semiconductor manufacturing process. Therefore, to achieve continuous progress in semiconductor integrated circuits and devices, similar progress in semiconductor manufacturing processes and technologies is needed. In recent years, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and / or reducing short-channel effects (SCEs). One such multi-gate device is the gate-all around (GAA) transistor. The gate-all around device gets its name from the gate structure. The gate structure of the gate-all around device can extend around the channel region and provide a path to the channel on two or four sides. The gate-all around device is compatible with traditional complementary metal-oxide-semiconductor (CMOS) processes, and these structures allow the gate-all around device to be aggressively miniaturized while maintaining gate control and alleviating short-channel effects. In traditional processes, the gate-all around device provides a channel in a silicon nanowire. However, manufacturing an integrated gate-all around component around the nanowire can be challenging. For example, although existing methods have been satisfactory in many aspects, continuous improvement is still needed. In some embodiments, a method of forming a semiconductor structure is provided. The method includes forming an isolation structure surrounding a first active region; forming a first dummy gate structure spanning the first active region and the isolation structure; replacing at least a portion of the first dummy gate structure with an insulating strip; forming a first cutting member passing through the insulating strip and the isolation structure; forming a first contact rail in the first cutting member; forming a first via rail overlapping the first contact rail in the first cutting member; and forming a first metal wire overlapping the first via rail. In some embodiments, a method of forming a semiconductor structure is provided. The method includes forming a plurality of active regions over a substrate; forming a plurality of insulating strips spanning the plurality of active regions, wherein the plurality of insulating strips vertically extend through the plurality of active regions and into the substrate; forming a first contact rail between a first active region and a second active region among the plurality of active regions, and forming a second contact rail between the second active region and a third active region among the plurality of active regions; and forming a first via rail and a second via rail on the first contact rail and the second contact rail, respectively. In some other embodiments, a semiconductor structure is provided. The semiconductor structure includes a functional unit region including an n-type functional transistor and a p-type functional transistor; a first power transmission unit region including a first cutting member and a first contact rail in the first cutting member; a first power supply rail electrically connected to a source terminal of the p-type functional transistor and the first contact rail of the first power transmission unit region; a second power transmission unit region adjacent to the first power transmission unit region and including a second cutting member and a second contact rail in the second cutting member; and an insulating strip extending from the first cutting member to the second cutting member in a first direction. It is to be understood that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject matter. Specific examples of various components and their arrangements are described below to simplify the description of the disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the dimensions of the components are not limited to the scope or values of one embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the components. In addition, in the subsequent description, embodiments in which a first component is formed over or on a second component include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components such that the first and second components are not in direct contact. In addition, repeated reference symbols and / or words may be used in different examples of the disclosure. These repeated symbols or words are for the purpose of simplification and clarity and are not intended to limit the relationship between the various embodiments and / or the described external structures. Some variations of the embodiments are described herein. In various views and display embodiments, like reference symbols are used to label like components. It should be understood that additional operations may be provided before, during, and after the method, and for other embodiments of the method, some of the described operations may be replaced or eliminated. The all-around gate (GAA) transistors described below can be patterned using any suitable method. For example, these structures can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitch, for example, patterns with a smaller pitch than those obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the all-around gate structure can then be patterned using the remaining spacers. Embodiments of semiconductor structures are provided herein. Aspects of embodiments of the present invention relate to semiconductor structures having a backside power rail structure. The backside power rail structure can reduce the overall resistance of the back end of lines (BEOL) metal layers, and / or can reduce the complexity of metal wiring on the front side of the substrate, which can facilitate the continued miniaturization of semiconductor devices. In embodiments of the present invention, a semiconductor structure can include power transfer unit regions. Each power transfer unit region includes a contact rail electrically connected to a front side power rail and a via rail electrically connected to a backside power rail, thereby transferring power from the backside metal layer to the front side metal layer. According to some embodiments of the present invention, a semiconductor structure includes an insulating strip between power transfer unit regions. The insulating strip can replace a dummy gate structure that initially extends between the power transfer unit regions, thereby reducing the risk of leakage between the power transfer unit regions. Thus, the reliability and manufacturing yield of the final semiconductor device can be improved. Figures 1A to 1M-6 are schematic diagrams showing the formation of a semiconductor structure 100 at various intermediate stages according to some embodiments. Figure 1A is a plan view (front side layout) of the semiconductor structure 100, showing the formation of active regions (including active regions 104A and 104B) and isolation regions 100. Figure 1A-1 is a perspective view of the semiconductor structure 100 in region 50B. Figures 1A-2, 1A-3, 1A-4, and 1A-5 are cross-sectional schematic diagrams corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of Figure 1A. According to some embodiments, as shown in FIGS. 1A to 1A-5, the semiconductor structure 100 includes a substrate 102 and a plurality of active regions (such as including active regions 104A and 104B) above the substrate 102. According to some embodiments, the front side of the semiconductor structure 100 faces upward. For a better understanding of the semiconductor structure 100, X-Y-Z coordinate references are provided in the figures. The X-axis and the Y-axis are generally oriented along the lateral (or horizontal) directions parallel to the main surface of the substrate 102. The Y-axis intersects (e.g., is generally perpendicular to) the X-axis. The Z-axis is generally oriented along the direction perpendicular to the main surface of the substrate 102 (or the X-Y plane). The substrate 102 can be a part of a semiconductor wafer, a semiconductor chip (or die), and the like. In some embodiments, the substrate 102 is a silicon substrate. In some embodiments, the substrate 102 includes an elemental semiconductor (such as germanium), a compound semiconductor (including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb)), an alloy semiconductor (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or a combination of the foregoing. Furthermore, the substrate 102 may optionally include an epitaxial layer (epi-layer), which can be strained for performance enhancement, and can include a silicon-on-insulator (SOI) structure and / or have other suitable enhancement components. In some embodiments, the semiconductor structure 100 is used to form high-density devices. According to some embodiments, some regions of the substrate 102 are defined as a first region 50A and a second region 50B. The first region 50A is used to form a functional unit region therein, and the second region 50B is used to form a power transmission unit region therein. According to some embodiments, the functional unit region in the first region 50A can be a memory unit region (such as a static random-access memory (SRAM) unit region) or a logic unit region (such as a NOR, AND, OR, Flip-Flop, and / or scan unit region). Each functional unit region may include a functional circuit formed by a plurality of functional transistors interconnected with each other. According to some embodiments, the power transmission unit region in the second region 50B is configured to transmit power from the back-side metal layer of the semiconductor structure 100 to the front-side metal layer of the semiconductor structure 100. Each power transmission unit region includes an electrical connection structure between the front-side metal layer and the back-side metal layer, and does not have functional transistors therein. The formation of the functional unit region and the power transmission unit region will be discussed in detail below. Although a first region 50A for forming a functional unit region is shown on one side (left side) of a second region 50B for forming a power transmission unit region, another first region 50A may be defined on the other side (right side) of the second region 50B. According to some embodiments, a third region 50C is defined between the first region 50A and the second region 50B. According to some embodiments, the third region 50C serves as an isolation region between the first region 50A and the second region 50B. According to some embodiments, an active region 104A is formed in the first region 50A, and an active region 104B is formed in the second region 50B. According to some embodiments, the active regions 104A and 104B extend in the X direction. That is, according to some embodiments, the active regions 104A and 104B have a longitudinal axis parallel to the X direction. In some embodiments, the active regions 104A and 104B are also referred to as semiconductor fins or semiconductor fin structures. In some embodiments, the width W1 of the active region 104A is smaller than the width W2 of the active region 104B. In some embodiments, the ratio of the width W1 to the width W2 is in the range of about 0.1 to about 0.5. In some embodiments, the edges (sidewalls) of the active region 104A are substantially aligned with the edges (sidewalls) of the active region 104B. In some embodiments, the pitch S1 between two adjacent active regions 104A is smaller than the pitch S2 between two adjacent active regions 104B. According to some embodiments, each of the active regions 104A and 104B is defined as a plurality of channel regions and a plurality of source / drain regions, where the channel regions and the source / drain regions are alternately arranged. Herein, the source / drain is referred to as the source and / or the drain. It should be noted that herein, the source and the drain can be used interchangeably, and the structures of the source and the drain are substantially the same. The X direction may also be referred to as the channel extension direction. The current of the final semiconductor device (i.e., the nanoscale transistor) flows through the channel in the X direction. A gate structure or a gate stack having a longitudinal axis parallel to the Y direction will be formed, and the gate structure or the gate stack extends above the channel regions of the active regions 104A and 104B. The Y direction may also be referred to as the gate extension direction. According to some embodiments, an n-type dopant (such as phosphorus or arsenic) is implanted into the substrate 102 to form an n-type well NW. According to some embodiments, a p-type dopant (such as boron or BF 2 ) is implanted into the substrate 102 to form a p-type well PW. According to some embodiments, the n-type well NW and the p-type well PW are alternately arranged in the Y direction. According to some embodiments, two active regions 104A are located in the n-type well NW or the p-type well PW in the first region 50A. According to some embodiments, one active region 104B is located in the p-type well PW in the second region 50B, and no active region 104B is located in the n-type well NW in the second region 50B. In some embodiments, the corresponding concentrations of the dopants in the n-type well and the p-type well are about 10 16 / cm 3 to about 10 18 / cm 3 in the range of. In some embodiments, multiple ion implantation processes with different doses and different energy intensities can be performed. In some embodiments, the ion implantation process can include anti-punch through (APT) implantation. According to some embodiments, the formation of the active regions 104A and 104B includes forming an epitaxial stack over the substrate 102 using an epitaxial growth process. The epitaxial stack can be formed by depositing a first semiconductor layer 106 on the substrate 102, depositing a second semiconductor layer 108 on the first semiconductor layer 106, and repeating the cycle of depositing the first semiconductor layer 106 and the second semiconductor layer 108 multiple times. According to some embodiments, the first semiconductor layer 106 and the second semiconductor layer 108 are vertically stacked alternately. The epitaxial growth process can be molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), or other suitable techniques. In some embodiments, the first semiconductor layer 106 is made of a first semiconductor material, and the second semiconductor layer 108 is made of a second semiconductor material. According to some embodiments, the first semiconductor material for the first semiconductor layer 106 has a lattice constant different from that of the second semiconductor material for the second semiconductor layer 108. In some embodiments, the first semiconductor material and the second semiconductor material have different oxidation rates and / or etching selectivities. In some embodiments, the first semiconductor layer 106 is made of SiGe, where the percentage of germanium (Ge) in the SiGe is in the range of about 20 atomic percent to about 50 atomic percent, and the second semiconductor layer 108 is made of pure silicon or substantially pure silicon. In some embodiments, the first semiconductor layer 106 is Si 1-x Ge x (where x is greater than about 0.3) or Ge (x = 1.0), and the second semiconductor layer 108 is Si or Si 1-y Ge y , where y is less than about 0.4, and x > y. According to some embodiments, the first semiconductor layer 106 is configured as a sacrificial layer and will be removed to form a gap for accommodating gate material, and the second semiconductor layer 108 will form nanostructures (such as nanowires or nanosheets), which laterally extend between the source / drain components and serve as the channel region of the final semiconductor device (such as a nanostructure transistor). Although three first semiconductor layers 106 and three second semiconductor layers 108 are shown, the number is not limited to three and can be two or four, and less than ten. According to some embodiments, the formation of the active regions 104A and 104B further includes forming a patterned mask layer (not shown) on the epitaxial stack, and then etching the epitaxial stack and the underlying n-type well NW and p-type well PW using the patterned mask layer, thereby forming trenches, and the active regions 104A and 104B protrude from between the trenches. According to some embodiments, the portions of the n-type well NW and p-type well PW that protrude from between the trenches serve as the underlying fin elements 103 of the active regions 104A and 104B. According to some embodiments, the remaining portions of the epitaxial stack (including the first semiconductor layer 106 and the second semiconductor layer 108) serve as the upper fin elements of the active regions 104A and 104B. According to some embodiments, an isolation structure 110 is formed to surround the underlying fin elements 103 of the active regions 104A and 104B. According to some embodiments, the isolation structure 110 is configured to electrically isolate the active regions 104A and 104B from each other and is also referred to as a shallow trench isolation (STI) component. According to some embodiments, the formation of the isolation structure 110 includes forming an insulating material to overfill the trenches. In some embodiments, the insulating material is made of silicon oxide (SiO 2 )、silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination of the foregoing. In some embodiments, the insulating material is deposited by using chemical vapor deposition (such as flowable chemical vapor deposition (FCVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), or high aspect ratio process (HARP)), atomic layer deposition (ALD), other suitable techniques, or a combination of the foregoing. According to some embodiments, a planarization process is performed on the insulating material to remove the portion of the insulating material above the active regions 104A and 104B. This planarization can be chemical mechanical polishing (CMP), an etch-back process, or a combination of the foregoing. According to some embodiments, the insulating material is then recessed by an etching process (such as dry plasma etching and / or wet chemical etching) until the fin elements above the active regions 104A and 104B are exposed. FIG. 1B is a plan view (front-side layout) of the semiconductor structure 100, and FIG. 1B shows the formation of the dummy gate structure 112 (including the dummy gate structure 112 1 to 112 15 ), the gate spacer 118, the source / drain components 124, the internal spacer 126, the contact etching stop layer (CESL) 130, and the first interlayer dielectric (ILD) layer 132. FIG. 1B-1 is a perspective view of the semiconductor structure 100 in the second region 50B. FIGS. 1B-2, 1B-3, 1B-4, and 1B-5 are cross-sectional schematic views corresponding to the lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of FIG. 1B. According to some embodiments, as shown in FIGS. 1B to 1B-5, the dummy gate structure 112 (including the dummy gate structure 112 1 to 112 15)Formed above and / or spanning the active regions 104A and 104B and the isolation structure 110. According to some embodiments, the dummy gate structure 112 is configured as a sacrificial structure and will be replaced by a final gate stack and an insulating strip. In some embodiments, the dummy gate structure 112 extends in the Y direction. That is, according to some embodiments, the dummy gate structure 112 has a longitudinal axis parallel to the Y direction. According to some embodiments, the dummy gate structure 112 2 to 112 6 is located in the first region 50A, and the dummy gate structure 112 10 to 112 12 is located in the second region 50B. According to some embodiments, the dummy gate structure 112 1,7,9,13,15 is located at the region boundary. According to some embodiments, although three dummy gate structures 112 are shown in the second region 50B, the number of dummy gate structures 112 can be from 1 to 5. For example, if the number of dummy gate structures 112 in the second region 50B is too small, the resistance of the electrical connection structure in the power transmission unit region may be too high. If the number of dummy gate structures 112 in the second region 50B is too large, the utilization efficiency of the substrate surface may be reduced. According to some embodiments, the dummy gate structure 112 surrounds the channel regions of the active regions 104A and 104B. According to some embodiments, each dummy gate structure 112 includes a dummy gate dielectric layer 114 and a dummy gate electrode layer 116 above the dummy gate dielectric layer 114. In some embodiments, the dummy gate dielectric layer 114 conformally forms along the top surfaces of the fin elements above the active regions 104A and 104B and the isolation structure 110. In some embodiments, the dummy gate dielectric layer 114 is made of one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), HfO 2, HfZrO, HfSiO, HfTiO, HfAlO. In some embodiments, the dielectric material is deposited by using atomic layer deposition, chemical vapor deposition, thermal oxidation, physical vapor deposition (PVD), other suitable techniques, or a combination of the foregoing. In some embodiments, the dummy gate electrode layer 116 is made of a semiconductor material, such as polysilicon or polysilicon germanium. In some embodiments, the material for the dummy gate electrode layer 116 is deposited by using chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable techniques, or a combination of the foregoing. In some embodiments, the formation of the dummy gate structure 112 includes depositing a dielectric material for the dummy gate dielectric layer 114 over the semiconductor structure 100, depositing a material for the dummy gate electrode layer 116 over the dielectric material, planarizing the material for the dummy gate electrode layer 116, and patterning the material for the dummy gate electrode layer 116 and the dielectric material into the dummy gate structure 112 by using photolithography and etching processes. According to some embodiments, as shown in FIGS. 1B-3 and 1B-4, the gate spacer layer 118 is formed along the sidewalls of both sides of the dummy gate structure 112. According to some embodiments, the gate spacer layer 118 extends in the Y direction and spans the active regions 104A and 104B and the isolation structure 110. According to some embodiments, the gate spacer layer 118 is used to offset the subsequently formed source / drain components and separate the source / drain components from the gate structure. In some embodiments, the gate spacer layer 118 includes a first dielectric material 120 and a second dielectric material 122 over the first dielectric material 120. In some embodiments, the first dielectric material 120 may be the same as or different from the second dielectric material 122. In some embodiments, the first dielectric material 120 and the second dielectric material 122 may be silicon oxide (SiO 2 ), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), oxygen-doped silicon carbonitride (Si(O)CN), and / or a combination of the foregoing. In some embodiments, the formation of the gate spacer layer 118 includes conformally depositing the first dielectric material 120 and the second dielectric material 122, followed by an anisotropic etching process. In some embodiments, the etching process is performed without an additional photolithography process. According to some embodiments, as shown in FIGS. 1B-4, the source / drain component 124 is formed in and / or above the source / drain region of the active region 104B. Although not shown, the source / drain component 124 is also formed in and / or above the source / drain region of the active region 104A. According to some embodiments, the formation of the source / drain component 124 includes using the dummy gate structure 112 and the gate spacer 118 as an etching mask to form source / drain notches on both sides of the dummy gate structure 112. According to some embodiments, during the recess process, the isolation structure 110 is also recessed, as shown in FIGS. 1B-3 and 1B-4. The recess process can be an anisotropic etching process (e.g., dry plasma etching), an isotropic etching process (e.g., dry chemical etching, remote plasma etching, or wet chemical etching), or a combination of the foregoing. According to some embodiments, as shown in FIG. 1B-4, an etching process is performed to laterally recess the first semiconductor layer 106 of the active regions 104A and 104B from the source / drain notches to form a notch, and then the internal spacer 126 is formed in the notch. According to some embodiments, the internal spacer 126 abuts the recessed sidewall surfaces of the first semiconductor layer 106 and is located between adjacent second semiconductor layers 108 and between the lowermost second semiconductor layer 108 and the underlying fin element 103. According to some embodiments, the internal spacer 126 can prevent the source / drain component 124 from directly contacting the gate stack and is configured to reduce the parasitic capacitance (i.e., Cgs and Cgd) between the gate stack and the source / drain component. In some embodiments, the internal spacer 126 is made of a dielectric material, such as silicon oxide (SiO 2 ), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), oxygen-doped silicon carbonitride (Si(O)CN), and / or a combination of the foregoing. In some embodiments, the internal spacer 126 is formed by depositing a dielectric material to fill the notch and then etching away the dielectric material outside the notch. In some embodiments, the deposition process includes atomic layer deposition, chemical vapor deposition (e.g., plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition, or high aspect ratio process), other suitable techniques, or a combination of the foregoing. In some embodiments, the etch-back process includes an anisotropic etching process (e.g., dry plasma etching), an isotropic etching process (e.g., dry chemical etching, remote plasma etching, or wet chemical etching), or a combination of the foregoing. According to some embodiments, as shown in FIG. 1B-4, the sacrificial layer 128 is grown in the source / drain notches on the underlying fin element 103. In some embodiments, the sacrificial layer 128 is made of an epitaxial semiconductor material (e.g., silicon, silicon germanium, or germanium) and is formed by molecular beam epitaxy, metalorganic chemical vapor deposition, vapor phase epitaxy, other suitable techniques, or a combination of the foregoing. Subsequently, according to some embodiments, as shown in FIGS. 1B - 4, source / drain components 124 are grown in source / drain recesses on the surfaces of the second semiconductor layer 108 and the sacrificial layer 128. In some embodiments, the source / drain components 124 are made of any suitable semiconductor material applicable to both n - type semiconductor devices and p - type semiconductor devices, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or combinations thereof. In some embodiments, the source / drain components 124 are doped in - situ during the epitaxial growth process. In some embodiments, the source / drain components 124 in the n - type well NW have a different conductivity type from the source / drain components 124 in the p - type well PW. In some embodiments, in the p - type well PW, the source / drain components 124 are made of semiconductor materials such as SiP, SiAs, SiCP, SiC, Si, GaAs, other suitable semiconductor materials, or combinations thereof. In some embodiments, these source / drain components 124 are doped with n - type dopants during the epitaxial growth process. For example, the n - type dopant can be phosphorus (P) or arsenic (As). For example, these source / drain components 124 can be epitaxially grown with silicon doped with phosphorus to form a silicon:phosphorus (Si:P) source / drain component, and / or doped with arsenic to form a silicon:arsenic (Si:As) source / drain component. In some embodiments, the concentration of the dopant (such as phosphorus) in the n - type source / drain component 124 is in the range of about 2×10 19 cm -3 to about 3×10 21 cm -3 range. In some embodiments, in the n - type well NW, the source / drain components 124 are made of semiconductor materials such as SiGe, Si, GaAs, other suitable semiconductor materials, or combinations thereof. In some embodiments, these source / drain components 124 are doped with p - type dopants during the epitaxial growth process. For example, the p - type dopant can be boron (B) or BF 2 2. For example, these source / drain components 124 can be epitaxially grown with silicon germanium doped with boron (B) to form a silicon germanium:boron (SiGe:B) source / drain component. In some embodiments, the concentration of the dopant (such as boron) in the p - type source / drain component 124 is in the range of about 1×10 19 cm -3 to about 6×10 20 cm -3 within the range of. In some embodiments, the source / drain component 124 is in-situ doped during the epitaxial growth process. In some embodiments, the source / drain component 124 can be a multi-layer structure including epitaxial layers L1, L2, and L3 formed in sequence. In some embodiments, the concentration of dopants in the epitaxial layer L2 is higher than the concentration of dopants in the epitaxial layer L1, for example, by 1-2 orders of magnitude. In some embodiments, the concentration of dopants in the epitaxial layer L3 is higher than the concentration of dopants in the epitaxial layer L2, for example, by 1-2 orders of magnitude. According to some embodiments, as shown in FIGS. 1B-3 and 1B-4, the contact etch stop layer 130 is formed over the semiconductor structure 100 and covers the source / drain component 124. In some embodiments, the contact etch stop layer 130 is made of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO 2 ), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination of the foregoing. In some embodiments, the material for the contact etch stop layer 130 is deposited over the semiconductor structure 100 by using chemical vapor deposition (such as low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, or high aspect ratio process), atomic layer deposition, other suitable techniques, or a combination of the foregoing. According to some embodiments, as shown in FIGS. 1B-3 and 1B-4, a first interlayer dielectric layer 132 is formed over the contact etch stop layer 130. According to some embodiments, the first interlayer dielectric layer 132 overfills the space between the dummy gate structures 112. In some embodiments, the first interlayer dielectric layer 132 is made of a dielectric material such as un-doped silicate glass (USG), doped silicon oxide (such as borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG)), and / or other suitable dielectric materials. In some embodiments, the material for the first interlayer dielectric layer 132 is deposited by using chemical vapor deposition (such as high-density plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, high aspect ratio process, or flowable chemical vapor deposition), other suitable techniques, or a combination of the foregoing. According to some embodiments, the dielectric materials of the contact etch stop layer 130 and the first interlayer dielectric layer 132 are removed from the top surface of the dummy gate electrode layer 116, for example, by using chemical mechanical polishing. FIG. 1C is a plan view (front-side layout) of the semiconductor structure 100, and FIG. 1C shows the formation of the insulating strip 134. FIGS. 1C-1, 1C-2, 1C-3, and 1C-4 are cross-sectional schematic views corresponding to the lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of FIG. 1C. According to some embodiments, as shown in FIGS. 1C to 1C-3, the insulating strip 134 is formed in the second region 50B through the dummy gate structures 112 10 、112 11 及112 12 及 below the active region 104B. According to some embodiments, the insulating strip 134 includes an extension portion that penetrates the underlying fin element 103, the n-type well NW, and the p-type well PW and further enters the substrate 102. In some embodiments, the bottom of the insulating strip 134 may be lower than the bottom surface of the isolation structure 110. In some embodiments, the insulating strip 134 completely replaces the dummy gate structures 112 in the second region 50B 10 、112 11 及112 12 . In some other embodiments, the insulating strip 134 only replaces the dummy gate structure 112 10 , 112 11 and 112 12 The portion between the power transmission units. In some embodiments, the insulating strip 134 divides each active region 104B into a plurality of electrically isolated segments. In some embodiments, the insulating strip 134 extends in the Y direction. That is, according to some embodiments, the insulating strip 134 has a longitudinal axis parallel to the Y direction. The insulating strip 134 may also be referred to as a cut poly gate on oxide definition edge (CPODE) pattern. In some embodiments, the insulating strip 134 is configured to prevent leakage between adjacent power transmission unit regions, which will be described in more detail below. The insulating strip 134 is made of a dielectric material, such as silicon oxide (SiO 2 ), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), oxygen-doped silicon carbonitride (Si(O)CN), or a combination of the foregoing. In some embodiments, the insulating strip 134 comprises a dielectric material having a dielectric constant value greater than 7.9, such as LaO, AlO, AlON, ZrO, HfO, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, or a combination of the foregoing. According to some embodiments, the formation of the insulating strip 134 includes using photolithography and etching processes to pattern the dummy gate structures 112 10 , 112 11 and 112 12 and the active region 104B to form a cutting groove (where the insulating strip 134 will be formed), depositing a dielectric material for the insulating strip 134 to overfill the cutting groove. The etching process may be an anisotropic etching process (such as dry plasma etching), an isotropic etching process (such as dry chemical etching, remote plasma etching, or wet chemical etching), or a combination of the foregoing. In some embodiments, the deposition process is atomic layer deposition, chemical vapor deposition (such as low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, or high aspect ratio process), other suitable techniques, or a combination of the foregoing. Then, according to some embodiments, a planarization process is performed on the dielectric material until the dummy gate structures 112 and the first interlayer dielectric layer 132 are exposed. The planarization may be chemical mechanical polishing, a re-etching process, or a combination of the foregoing. FIG. 1D is a plan view (front-side layout) of a semiconductor structure 100, and FIG. 1D shows the formation of a final gate stack 136 (including final gate stacks 136 1 to 136 12 ). FIGS. 1D-1, 1D-2, 1D-3, and 1D-4 are cross-sectional schematic views corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of FIG. 1D. According to some embodiments, one or more etching processes are performed to remove dummy gate structures 112 1-9 and dummy gate structures 112 13-15 to form gate trenches and to remove the first semiconductor layer 106 of active regions 104a and 104b to form gate gaps. In some embodiments, the gate trenches expose the channel regions of active regions 104a and 104b. In some embodiments, the gate trenches further expose the sidewalls of gate spacer 118 facing the channel regions. In some embodiments, the gate gaps expose the inner sidewalls of inner spacer 126 facing the channel regions. In one or more etching processes, the top surface of isolation structure 110 is also recessed, as shown in FIGS. 1D-2 and 1D-3. The one or more etching processes may include an anisotropic etching process (e.g., dry plasma etching), an isotropic etching process (e.g., dry chemical etching, remote plasma etching, or wet chemical etching), or a combination of the foregoing. According to some embodiments, after the one or more etching processes, four major surfaces of second semiconductor layer 108 are exposed. According to some embodiments, the exposed second semiconductor layer 108 forms multiple sets of nanostructures. According to some embodiments, each set includes three nanostructures that are vertically stacked and spaced apart from each other. As used herein, the term “nanostructure” represents a semiconductor layer having a cylindrical, rod-like, and / or sheet-like shape. According to some embodiments, the nanostructures (second semiconductor layer 108) serve as channels for final semiconductor devices (e.g., nanostructure transistors of all-around gate transistors). According to some embodiments, as shown in FIGS. 1D, 1D-2, 1D-3, and 1D-4, a final gate stack (including final gate stacks 136 1 to 136 12 ) is formed in the gate trenches and gaps, thereby surrounding the nanostructures (second semiconductor layer 108). In some embodiments, the final gate stack extends in the Y direction. That is, according to some embodiments, the final gate stack has a longitudinal axis parallel to the Y direction. The final gate stack occupies the channel region such that current flows between source / drain regions during operation. According to some embodiments, the final gate stack 136 2-6 is located in the first region 50A and serves as a functional gate that can be electrically connected to a subsequently formed signal line. According to some embodiments, the final gate stack 136 located at the cell boundary 1,7,9,11,12­­ and the final gate stack 136 located in the third region 50C 8,11 serve as isolation gates. In some embodiments, the isolation gate can be electrically connected to a subsequently formed power rail. According to some embodiments, each final gate stack includes an interface layer 138, a gate dielectric layer 139, and a metal gate electrode layer 140. According to some embodiments, the interface layer 138 is formed on the exposed surfaces of the nanostructure (the second semiconductor layer 108) and the underlying fin element 103. According to some embodiments, the interface layer 138 surrounds the nanostructure (the second semiconductor layer 108). In some embodiments, the interface layer 138 is made of chemically formed silicon oxide or nitrogen-doped silicon oxide. In some embodiments, the interface layer 138 is formed by using an oxidation process. According to some embodiments, the semiconductor materials of the nanostructure (the second semiconductor layer 108) and the underlying fin element 103 are oxidized to form the interface layer 138. According to some embodiments, the gate dielectric layer 139 is conformally formed along the interface layer 138 to surround the nanostructure (the second semiconductor layer 108). According to some embodiments, the gate dielectric layer 139 is also conformally formed along the sidewalls of the gate spacer layer 118 facing the channel region, the sidewalls of the internal spacer layer 126, and the top surface of the isolation structure 110. The gate dielectric layer 139 can be a high-k dielectric layer. In some embodiments, the high-k dielectric layer is a dielectric material having a high dielectric constant (k value), such as greater than 7.9, such as greater than 13. In some embodiments, the high-k dielectric layer includes hafnium oxide (HfO 2 ), TiO 2 , HfZrO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2 , LaO, Al 2 O 3, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3 (BST), the foregoing combinations or other suitable materials. The high-k dielectric layer can be deposited by using atomic layer deposition, physical vapor deposition, chemical vapor deposition, and / or other suitable techniques. According to some embodiments, the metal gate electrode layer 140 is formed over the gate dielectric layer 139 and overfills the remaining portions of the gate trench and the gap. The metal gate electrode layer 140 can be a multi-layer structure, and the multi-layer structure has various combinations of a diffusion barrier layer, a work function layer having a selected work function to enhance the device performance (such as the threshold voltage) of the n-type channel field effect transistor and the p-type channel field effect transistor, and a metal fill layer to reduce the total resistance of the gate stack and / or other suitable layers. The metal gate electrode layer 140 can be formed by using atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable techniques. In some embodiments, the metal gate electrode layer 140 can be formed separately for the n-type channel field effect transistor and the p-type channel field effect transistor, and different work function materials can be used for the n-type channel field effect transistor and the p-type channel field effect transistor. According to some embodiments, a planarization process (such as chemical mechanical polishing) is then performed on the semiconductor structure 100 to remove the gate dielectric layer 139 and the metal gate electrode layer 140 from the top surface of the first interlayer dielectric layer 132. According to some embodiments, the interface layer 138, the gate dielectric layer 139, and the metal gate electrode layer 140 together form a final gate stack (including the final gate stack 136 1 to 136 12 ). The final gate stack surrounding the nanostructure (second semiconductor layer 108) couples to adjacent source / drain components 124 to form nanostructure transistors, such as n-type channel nanostructure transistors in a p-type well PW and p-type channel nanostructure transistors in an n-type well NW. In some embodiments, functional unit regions (only functional unit regions CA1 and CA2 are shown for simplicity) are formed and arranged in a first region 50A. In some embodiments, each functional unit region in the first region 50A includes a plurality of n-type channel functional transistors and a plurality of p-type channel functional transistors. In one embodiment, the functional unit regions (such as functional unit regions CA1 and CA2) are static random access memory unit regions. FIG. 1E is a plan view (front-side layout) of the semiconductor structure 100, and FIG. 1E shows the formation of cutting components (including cutting components 142A and 142B). FIGS. 1E-1 and 1E-2 are cross-sectional schematic views corresponding to line Y1-Y1 and line X1-X1 of FIG. 1E. According to some embodiments, as shown in FIGS. 1E to 1E-2, the cutting components (including cutting components 142A and 142B) are formed in the final gate stack (including final gate stack 136 1 to 136 12 ), insulating strip 134, gate spacer layer 118, contact etch stop layer 130, first interlayer dielectric layer 132, isolation structure 110, and in and / or through the n-type well NW and p-type well PW and further into the substrate 102. In some embodiments, the cutting components (including cutting components 142A and 142B) extend in the X direction. That is, according to some embodiments, the cutting components (including cutting components 142A and 142B) have a longitudinal axis parallel to the X direction. According to some embodiments, the cutting components (including cutting components 142A and 142B) cut the final gate stack (including final gate stack 136 1 to 136 12 ) and the insulating strip 134 into multiple segments. The cutting components (including cutting components 142A and 142B) may also be referred to as a cut metal gate (CMG) pattern. According to some embodiments, the cutting component 142A is located in the first region 50A, and the cutting component 142B is located in the second region 50B. According to some embodiments, the cutting component 142A is configured to cut the final gate stack (including final gate stack 136 1 to 136 12) The segments of () are electrically isolated from each other. In some embodiments, the cutting member 142B is formed in the n-type well NW. According to some embodiments, the cutting member 142B is configured as an isolation region, and an electrical connection structure is formed in this isolation region. In some embodiments, the width W3 of the cutting member 142A is smaller than the width W4 of the cutting member 142B. In some embodiments, the ratio of the width W3 to the width W4 is in the range of about 0.1 to about 0.5. The cutting members (including the cutting members 142A and 142B) are made of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), oxygen-doped silicon carbonitride (Si(O)CN), silicon oxide (SiO 2 ) or a combination of the foregoing. In some embodiments, the cutting members (including the cutting members 142A and 142B) comprise a dielectric material having a dielectric constant value greater than 7.9, such as LaO, AlO, AlON, ZrO, HfO, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN or a combination of the foregoing. In some embodiments, the deposition process is atomic layer deposition, chemical vapor deposition (such as low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition or high aspect ratio process), other suitable techniques or a combination of the foregoing. According to some embodiments, the formation of the cutting members (including the cutting members 142A and 142B) includes using photolithography and etching processes to pattern the final gate stack (including the final gate stack 136 1 to 136 12 ), the insulating strip 134, the gate spacer 118, the contact etch stop layer 130, the first interlayer dielectric layer 132, the isolation structure 110 and the substrate 102 to form a gate cutting groove (the cutting members will be formed in this gate cutting groove). The etching process can be an anisotropic etching process (such as dry plasma etching), an isotropic etching process (such as dry chemical etching, remote plasma etching or wet chemical etching) or a combination of the foregoing. According to some embodiments, the formation of the cutting members (including the cutting members 142A and 142B) further includes depositing a dielectric material for the cutting members to overfill the gate cutting groove. Thereafter, according to some embodiments, a planarization process is performed on the dielectric material for the cutting members (including the cutting members 142A and 142B) until the insulating strip 134 and the first interlayer dielectric layer 132 are exposed. The planarization can be chemical mechanical polishing, a re-etching process or a combination of the foregoing. FIG. 1F is a plan view (front-side layout) of semiconductor structure 100, and FIG. 1F shows the formation of an etch stop layer 144, a second interlayer dielectric layer 146, and front-side contact plugs (including front-side contact plugs 148A and 148B1) and contact rails 148B2. FIGS. 1F-1, 1F-2, 1F-3, and 1F-4 are cross-sectional schematic views corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of FIG. 1F. According to some embodiments, as shown in FIGS. 1F to 1F-4, the etch stop layer 144 and the second interlayer dielectric layer 146 are sequentially formed over the semiconductor structure 100. In some embodiments, the etch stop layer 144 is made of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO 2 ), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination of the foregoing. In some embodiments, the second interlayer dielectric layer 146 is made of a dielectric material, such as undoped silicate glass, borophosphosilicate glass, fluorine-doped silicate glass, phosphosilicate glass, borosilicate glass, and / or other suitable dielectric materials. In some embodiments, the etch stop layer 144 and the second interlayer dielectric layer 146 are deposited by using chemical vapor deposition (such as high-density plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, high aspect ratio process, or flowable chemical vapor deposition), other suitable techniques, or a combination of the foregoing. According to some embodiments, as shown in FIGS. 1F to 1F-3, contact plugs (including contact plugs 148A and 148B1) and contact rails 148B2 are formed. According to some embodiments, contact plugs 148A and 148B1 are formed to pass through the second interlayer dielectric layer 146, the etch stop layer 144, the first interlayer dielectric layer 132, and the contact etch stop layer 130. According to some embodiments, as shown in FIGS. 1F to 1F-3, some contact plugs 148A and 148B1 overlapping the active regions 104A and 104B are located on the source / drain components 124 and are electrically connected to the source / drain components 124. In some embodiments, contact plugs 148A and 148B1 extend in the Y direction. That is, according to some embodiments, contact plugs 148A and 148B1 have a longitudinal axis parallel to the Y direction. In some embodiments, contact plug 148A is formed in the first region 50A, and contact plugs 148B1 are formed in the second region 50B and the third region 50C. In some embodiments, contact plugs 148B1 are dummy patterns, and these dummy patterns are used to improve the stability of the patterning process for forming the contact plugs and the contact rails. In some other embodiments, there may be no contact plugs 148B1 in the second region 50B and the third region 50C. According to some embodiments, the contact rail 148B2 is formed through the second interlayer dielectric layer 146, the etch stop layer 144, and the cut member 142B. According to some embodiments, the contact rail 148B2 is located in the second region 50B and is completely confined within the region of the cut member 142B in a plan view. In some embodiments, the contact rail 148B2 extends in the X direction. That is, according to some embodiments, the contact rail 148B2 has a longitudinal axis parallel to the X direction. In some embodiments, the contact rail 148B2 serves as the upper part of the electrical connection structure of the power transmission unit region. In some embodiments, the formation of the contact plugs 148A and 148B1 and the contact rail 148B2 includes patterning the semiconductor structure 100 using photolithography and etching processes to form contact trenches (the contact plugs 148A and 148B1 and the contact rail 148B2 will be formed in the contact trenches) until the source / drain components 124 are exposed. The etching process may include dry etching, such as reactive ion etch (RIE), neutral beam etch (NBE), inductive coupled plasma (ICP) etching, capacitively coupled plasma (CCP) etching, other suitable methods, or combinations of the foregoing. The silicide layer 150 is formed on the exposed surface of the source / drain component 124. In some embodiments, the silicide layer 150 is made of WSi, NiSi, TiSi, and / or CoSi. In some embodiments, the formation of the silicide layer 150 includes depositing a metal material and then performing one or more annealing processes. According to some embodiments, the semiconductor material (such as silicon) of the source / drain component 124 reacts with the metal material to form the silicide layer 150. Then, the unreacted metal material is removed, for example, using wet etching. According to some embodiments, the contact pad 147 is formed along the sidewalls of the contact trenches using a deposition process and an etch-back process. In some embodiments, the contact pad 147 is made of an insulating material, such as a dielectric material (such as SiC, LaO, AlO, AlON, ZrO, HfO, SiN, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, SiN, HfSi, or SiO) or undoped silicon (Si). Thereafter, according to some embodiments, one or more conductive materials for contact plugs 148A and 148B1 and contact rails 148B2 are deposited to overfill the contact trenches. In some embodiments, chemical vapor deposition, physical vapor deposition, electron beam evaporation, atomic layer deposition, electroplating (ECP), electroless deposition (ELD), other suitable methods, or a combination of the foregoing are used to deposit one or more conductive materials to overfill the contact trenches. Chemical mechanical polishing, for example, is used to planarize the one or more conductive materials above the upper surface of the second interlayer dielectric layer 146. Contact plugs 148A and 148B1 and contact rails 148B2 may have a multi-layer structure. For example, a barrier / adhesion layer (not shown) may be selectively deposited along the sidewalls and bottom surface of the contact trench. The barrier / adhesion layer may be made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), other suitable materials, or a combination of the foregoing. Then, a bulk metal layer is deposited on the barrier / adhesion layer (if formed) to fill the remaining portion of the contact trench. In some embodiments, the bulk metal layer is made of one or more conductive materials having low resistance and good gap filling ability, such as cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), rhodium (Rh), iridium (Ir), platinum (Pt), aluminum (Al), ruthenium (Ru), molybdenum (Mo), other suitable metal materials, or a combination of the foregoing. FIG. 1G is a plan view (front-side layout) of the semiconductor structure 100, and FIG. 1G shows the formation of the etch stop layer 152, the third interlayer dielectric layer 154, the vias 156, the intermetal dielectric layer 158, and the front-side first metal layer F_M1. FIGS. 1G-1, 1G-2, 1G-3, and 1G-4 are cross-sectional schematic views corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of FIG. 1G. According to some embodiments, as shown in FIGS. 1G-1 to 1G-4, the etch stop layer 152 and the third interlayer dielectric layer 154 are sequentially formed over the semiconductor structure 100. In some embodiments, the etch stop layer 152 is made of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO 2) silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination of the foregoing. In some embodiments, the third interlayer dielectric layer 154 is made of a dielectric material, such as undoped silicate glass, borophosphosilicate glass, fluorine-doped silicate glass, phosphosilicate glass, borosilicate glass, and / or other suitable dielectric materials. In some embodiments, the etch stop layer 152 and the third interlayer dielectric layer 154 are deposited by using chemical vapor deposition (such as high-density plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, high aspect ratio process, or flowable chemical vapor deposition), other suitable techniques, or a combination of the foregoing. According to some embodiments, as shown in FIGS. 1G-1 and 1G-2, the vias 156 are formed in and / or pass through the etch stop layer 152 and the third interlayer dielectric layer 154 and are located on the contact rail 148B2. Although not shown, the vias 156 are also located on the contact plugs 148A and the final gate stack 136 in the first region 50A 2-6 above. According to some embodiments, the vias 156 electrically connected to the source / drain terminals of the nanostructure transistors through the contact plugs 148A may also be referred to as source / drain vias (VS or VD). The vias 156 electrically connected to the gate terminals of the nanostructure transistors may also be referred to as gate vias (VG). In some embodiments, as shown in FIG. 1G-2, the vias 156 located on the contact rail 148B2 may extend in the X direction to increase the contact area with the contact rail 148B2, thereby reducing the contact resistance. In some embodiments, the extension lines of the edges of the vias 156 located on the contact rail 148B2 extend between the edge of the contact rail 148B2 and the edge of the cutting member 142B. In some embodiments, the formation of the vias 156 includes patterning the third interlayer dielectric layer 154 and the etch stop layer 152 using photolithography and etching processes to form via openings (the vias 156 will be formed in the via openings). The etching process may include dry etching, such as reactive ion etching, neutron beam etching, inductively coupled plasma etching, capacitively coupled plasma etching, other suitable methods, or a combination of the foregoing. Thereafter, according to some embodiments, one or more conductive materials are deposited by using chemical vapor deposition, physical vapor deposition, electron beam evaporation, atomic layer deposition, electroplating, electroless deposition, other suitable methods, or a combination of the foregoing to overfill the via openings. The upper surface of the third interlayer dielectric layer 154 is planarized using, for example, chemical mechanical polishing for the one or more conductive materials above. The via hole 156 may have a multi-layer structure. For example, a barrier / adhesion layer (not shown) may be selectively deposited along the sidewalls and bottom surface of the via hole opening. The barrier layer may be made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), other suitable materials, or a combination of the foregoing. Next, a bulk metal layer is deposited on the barrier / adhesion layer (if formed) to fill the remaining portion of the via hole opening. In some embodiments, the bulk metal layer is made of one or more conductive materials, such as cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), rhodium (Rh), iridium (Ir), platinum (Pt), aluminum (Al), ruthenium (Ru), molybdenum (Mo), or a combination of the foregoing. According to some embodiments, as shown in FIGS. 1G-1, 1G-2, and 1G-4, an inter-metal dielectric layer 158 is formed over the semiconductor structure 100. In some embodiments, the inter-metal dielectric layer 158 is made of one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), aluminum oxide (Al 2 O 3 )), a dielectric material having a low dielectric constant (low-k) (such as SiCOH, SiOCN, and / or SiOC), or a combination of the foregoing. In some embodiments, the inter-metal dielectric layer 158 is made of an extremely low dielectric constant (ELK) dielectric material having a dielectric constant less than about 3.0 or even less than about 2.5. In some embodiments, the extremely low dielectric constant dielectric material includes carbon-doped silicon oxide, amorphous fluorocarbon, parylene, bis-benzocyclobutenes (BCB), polytetrafluoroethylene (PTFE) (Teflon), or silicon oxycarbide polymer (SiOC). In some embodiments, the extremely low dielectric constant dielectric material includes a porous version of an existing dielectric material, such as hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous silicon oxide (SiO 2)。In some embodiments, the inter-metal dielectric layer 158 is formed by using chemical vapor deposition (such as low-pressure chemical vapor deposition, high aspect ratio process, and flowable chemical vapor deposition), atomic layer deposition, spin coating, other suitable methods, or a combination of the foregoing. A post-curing process (such as ultraviolet curing) can be performed on the deposited ultra-low dielectric constant dielectric material for the inter-metal dielectric layer 158 to form a porous structure. According to some embodiments, as shown in FIGS. 1G to 1G-4, the front-side first metal layer F_M1 is formed in and / or through the inter-metal dielectric layer 158. According to some embodiments, the front-side first metal layer F_M1 includes a plurality of wires (tracks), such as power supply lines 160A and 160B (sometimes referred to as power rails) and signal lines. According to some embodiments, the wires of the front-side first metal layer F_M1 extend in the X direction. That is, according to some embodiments, these wires have a longitudinal axis parallel to the X direction. For simplicity and clarity, FIG. 1G only shows some metal lines of the front-side first metal layer F_M1. According to some embodiments, the power supply lines 160A and 160B include a VDD power rail that provides a positive voltage and a VSS power rail that can be electrically grounded. According to some embodiments, the signal lines are configured for signal transmission. According to some embodiments, the VDD power supply line 160A is located in the first region 50A, and the VDD and VSS power supply lines 160B are located in the second region 50B. According to some embodiments, the VSS power supply line 160A extends in the first region 50A and the second region 50B. According to some embodiments, the VDD and VSS power supply lines 160A shown in FIG. 1G supply power to the functional unit regions CA1 and CA2. According to some embodiments, in the first region 50A, the VSS power rail is electrically connected to the VSS node (such as the source terminal) of the n-channel nanostructure transistor in the (p-type well PW) through the via 156 and the contact plug 148A, and the VDD power rail is electrically connected to the VDD node (such as the source terminal) of the p-channel nanostructure transistor in the (n-type well NW) through the via 156 and the contact plug 148A. In the second region 50B, the VSS power rail and the VDD power rail are each electrically connected to a contact rail 148B2 through the via 156. According to some embodiments, the signal line can be electrically connected to the final gate stack (including the final gate stack 136 1 to 136 12 ), and is electrically connected to the non-VDD / VSS nodes (such as the drain terminals) of the n-channel transistor and the p-channel transistor through the via 156 and the contact plug 148A. In some embodiments, the formation of the front-side first metal layer F_M1 includes patterning the intermetal dielectric layer 158 using photolithography and etching processes to form trenches. The etching process may include dry etching, such as reactive ion etching, neutron beam etching, inductively coupled plasma etching, capacitively coupled plasma etching, other suitable methods, or a combination of the foregoing. Then, one or more conductive materials for the front-side first metal layer F_M1 are deposited using chemical vapor deposition, physical vapor deposition, electron beam evaporation, atomic layer deposition, electroplating, electroless deposition, other suitable methods, or a combination of the foregoing to overfill the trenches. Thereafter, a planarization process (such as chemical mechanical polishing and / or etch-back process) is performed to remove the excess portion of the conductive material from the upper surface of the intermetal dielectric layer 158. The front-side first metal layer F_M1 may have a multi-layer structure. For example, a barrier / adhesion layer (not shown) may be selectively deposited along the sidewalls and bottom surface of the trenches. The barrier layer may be made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), other suitable materials, or a combination of the foregoing. Then, a bulk metal layer is deposited on the barrier / adhesion layer (if formed) to fill the remaining portion of the trenches. In some embodiments, the bulk metal layer is made of one or more conductive materials, such as cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), rhodium (Rh), iridium (Ir), platinum (Pt), aluminum (Al), ruthenium (Ru), molybdenum (Mo), other suitable metal materials, or a combination of the foregoing. FIGS. 1H-1 and 1H-2 are cross-sectional schematic views of the semiconductor structure 100, showing the formation of the etch stop layer 162, the intermetal dielectric layer 164, and the front-side second metal layer F_M2. FIGS. 1H-1 and 1H-2 are corresponding to line Y1-Y1 and line X1-X1 of FIG. 1G. According to some embodiments, as shown in FIGS. 1H-1 and 1H-2, the etch stop layer 162 and the intermetal dielectric layer 164 are sequentially formed over the semiconductor structure 100. In some embodiments, the materials and formation of the etch stop layer 162 and the intermetal dielectric layer 164 may be similar to or substantially the same as those of the etch stop layer 152 and the intermetal dielectric layer 158. According to some embodiments, as shown in FIGS. 1H-1 and 1H-2, the front-side second metal layer F_M2 is formed in and / or through the inter-metal dielectric layer 164. According to some embodiments, the front-side second metal layer F_M2 includes a plurality of wires 166 (tracks) electrically connected to the front-side first metal layer F_M1. Although not shown, vias are formed between the front-side first metal layer F_M1 and the front-side second metal layer F_M2 and are electrically connected to the front-side first metal layer F_M1 and the front-side second metal layer F_M2. In some embodiments, the material and formation of the front-side second metal layer F_M2 may be similar to or substantially the same as those of the front-side first metal layer F_M1. According to some embodiments, the wires 166 of the front-side second metal layer F_M2 extend in the Y direction. That is, according to some embodiments, the wires 166 have a longitudinal axis parallel to the Y direction. According to some embodiments, referring to FIG. 1G, the VSS power supply line 160B in the second region 50B is electrically connected to the VSS power supply lines 160A in the first region 50A and the second region 50B through the front-side second metal layer F_M2. According to some embodiments, the VDD power supply line 160B in the second region 50B is electrically connected to the VDD power supply line 160A in the first region 50A through the front-side second metal layer F_M2. The semiconductor structure 100 may further undergo a back-end process to form various interconnect conductive components (not shown) above the semiconductor structure 100, such as the front-side third metal layer (F_M3) to the front-side tenth metal layer (F_M10) and the vias between adjacent two metal layers. According to some embodiments, as shown in FIGS. 1I-1 to 1I-4, the semiconductor structure 100 can be flipped upside down. FIGS. 1I-1, 1I-2, 1I-3, and 1I-4 are cross-sectional schematic views corresponding to the lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of FIG. 1G. In some embodiments, a carrier substrate (not shown) may be formed above the front side of the semiconductor structure 100 and seal the front side of the semiconductor structure 100 to protect the front-side components of the semiconductor structure 100 during subsequent back-side processes. According to some embodiments, after flipping the semiconductor structure 100, the back side of the substrate 102 (the back side of the semiconductor structure 100) faces upward. Figures 1J-1, 1J-2, 1J-3, and 1J-4 are cross-sectional schematic diagrams showing a removal process. Figures 1J-1, 1J-2, 1J-3, and 1J-4 are cross-sectional schematic diagrams corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of Figure 1G. According to some embodiments, as shown in Figures 1J-1 to 1J-4, the substrate 102, the underlying fin element 103, the isolation structure 110, the insulating strip 134, and the cutting members 142A and 142B are planarized from the back side of the semiconductor structure 100 using, for example, chemical mechanical polishing, grinding process, etching process, or a combination of the foregoing until the sacrificial layer 128 is exposed. Figure 1K is a plan view (back-side layout) of the semiconductor structure 100, and Figure 1K shows the formation of the dielectric layer 167 and the trench 170. Figures 1K-1 and 1K-2 are cross-sectional schematic diagrams corresponding to line Y1-Y1 and line X1-X1 of Figure 1K. According to some embodiments, as shown in Figures 1K-1 and 1K-2, the dielectric layer 167 and the patterned mask layer 168 are then formed over the back side of the semiconductor structure 100. The dielectric layer 167 is made of one or more dielectric materials, such as silicon oxide (SiO 2 ), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), oxygen-doped silicon carbonitride (Si(O)CN), or a combination of the foregoing. In some embodiments, the dielectric layer 167 is formed by using atomic layer deposition, chemical vapor deposition (such as plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition, or high aspect ratio process), other suitable techniques, or a combination of the foregoing. According to some embodiments, the patterned mask layer 168 has a trench pattern that exposes the dielectric layer 167 and corresponds to (or overlaps) the contact track 148B2. In some embodiments, the patterned mask layer 168 is a patterned photoresist layer. For example, the photoresist can be formed over the back side of the semiconductor structure 100 by spin coating and patterned by exposing the photoresist using a suitable photomask. Depending on whether a positive photoresist or a negative photoresist is used, the exposed or unexposed portions of the photoresist can be removed. In an alternative embodiment, the patterned mask layer 168 is a patterned hard mask layer. The patterned mask layer 168 can be made of metal oxide (such as AlO, TiO, LaO, HfO, etc.), nitrogen-free anti-reflection layer (NFARL), carbon-doped silicon oxide (such as SiO 2:C), titanium nitride (TiN), boron nitride (BN), the foregoing multi-layers, other suitable materials, or combinations thereof. For example, a material for patterning the mask layer 168 is deposited, and the patterned photoresist layer can be formed over the material for patterning the mask layer 168 using the above photolithography process. The material for patterning the mask layer 168 can be etched using the patterned photoresist layer to form the patterned mask layer. According to some embodiments, as shown in FIGS. 1K-1 and 1K-2, an etching process is performed on the semiconductor structure 100 using the patterned mask layer 168 to form a trench 170 that passes through the dielectric layer 167 and the cutting member 142B. The etching process can include dry etching, such as reactive ion etching, neutron beam etching, inductively coupled plasma etching, capacitively coupled plasma etching, other suitable methods, or combinations thereof. The trench 170 exposes the back surface (i.e., the top surface in the current figures) and sidewalls of the contact rail 148B2. In some embodiments, the trench 170 extends in the X direction. That is, according to some embodiments, the trench 170 has a longitudinal axis parallel to the X direction. According to some embodiments, in a plan view, the trench 170 is completely confined within the area of the cutting member 142B. In some embodiments, the dimension D1 (or width) of the contact rail 148B2 in the Y direction is less than the dimension D2 (or width) of the contact rail 148B2 in the Y direction. In some embodiments, the dimension D3 (or width) of the contact rail 148B2 in the X direction is less than the dimension D4 (or width) of the contact rail 148B2 in the X direction. FIG. 1L is a plan view (backside layout) of the semiconductor structure 100, and FIG. 1L shows the formation of the via rail 172 and the via hole 174. FIGS. 1L-1, 1L-2, 1L-3, and 1L-4 are cross-sectional schematic views corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of FIG. 1L. According to some embodiments, as shown in FIGS. 1L and 1L-2, the via rail 172 is formed in the trench 170. According to some embodiments, the via rail 172 is located on the contact rail 148B2 and is electrically connected to the contact rail 148B2. According to some embodiments, the via rail 172 directly contacts the back surface (i.e., the top surface in the current figures) and sidewalls of the contact rail 148B2. In some embodiments, the via rail 172 surrounds a portion of the contact rail 148B2. In some embodiments, the power transmission unit regions CB1 and CB2 are formed and arranged in the second region 50B, and include an electrical connection structure composed of the via track 172 and the contact track 148B2. According to some embodiments, the power transmission unit regions CB1 and CB2 are configured to transmit the power supplied from the backside metal layer of the semiconductor structure 100 to the frontside metal wires of the semiconductor structure 100. According to some embodiments, the power transmission unit regions CB1 and CB2 do not have functional transistors therein. In some embodiments, the via track 172 serves as the bottom of the electrical connection structure of the power transmission unit region. In some embodiments, the formation of the via track 172 includes depositing one or more conductive materials for the via track 172 to overfill the trench 170. In some embodiments, chemical vapor deposition, physical vapor deposition, electron beam evaporation, atomic layer deposition, electroplating, electroless deposition, other suitable methods, or a combination of the foregoing are used to deposit one or more conductive materials to overfill the trench 170. The one or more conductive materials above the upper surface of the dielectric layer 167 are planarized using, for example, chemical mechanical polishing. According to some embodiments, the patterned mask layer 168 is also removed. The via track 172 may have a multi-layer structure. For example, a barrier / adhesion layer (not shown) may be selectively deposited along the sidewalls and bottom surface of the trench 170. The barrier / adhesion layer may be made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), other suitable materials, or a combination of the foregoing. Then, a bulk metal layer is deposited on the barrier / adhesion layer (if formed) to fill the remaining part of the trench 170. In some embodiments, the bulk metal layer is made of one or more conductive materials, such as cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), rhodium (Rh), iridium (Ir), platinum (Pt), aluminum (Al), ruthenium (Ru), molybdenum (Mo), or a combination of the foregoing. In some embodiments, the via track 172 extends in the X direction. That is, according to some embodiments, the via track 172 has a longitudinal axis parallel to the X direction. According to some embodiments, in a plan view, the via track 172 is completely confined within the region of the cutting member 142B. In some embodiments, the dimension D1 (or width) of the contact track 148B2 in the Y direction is smaller than the dimension D2 (or width) of the via track 172 in the Y direction. In some embodiments, the dimension D3 (or width) of the contact track 148B2 in the X direction is smaller than the dimension D4 (or width) of the via track 172 in the X direction. In some embodiments, a semiconductor structure 100 is used to form high-density devices, and a cell region having a small cell height (i.e., a dimension in the Y direction). According to the design rules for patterning the active regions of high-density devices, an active region 104B can be formed in a p-type well PW on the boundary between a power transmission cell region CB1 and a power transmission cell region CB2 to maintain the stability of the patterning process for forming the active region 104B. Thus, there is no space on the boundary between the power transmission cell region CB1 and the power transmission cell region CB2 to form an isolation component (such as a cut component 142B). In some cases, a semiconductor structure is used to form high-current devices, and a cell region having a large cell height. For example, the ratio of the small cell height (of the high-density device) to the large cell height (of the high-current device) can be in the range of about 0.5 to about 0.95. According to the design rules for patterning the active regions of high-current devices, an isolation structure (such as an isolation structure 110) is located on the boundary between power transmission cell regions, so there is space to form an isolation component (such as a cut component 142B). According to some embodiments of the present invention, an insulating strip 134 is used to replace the dummy gate structure 112 instead of a metal gate stack 10-12 。When replacing the dummy gate structure 112 with a metal gate stack 10-12 In an example, the portion of the metal gate stack between the power transmission cell region CB1 and the power transmission cell region CB2 may provide a leakage path. Thus, the formation of the insulating strip 134 can reduce the leakage risk between the power transmission cell region CB1 and the power transmission cell region CB2. Embodiments of the present invention can facilitate the manufacture of high-density devices having power transmission cell regions. According to some embodiments, as shown in FIGS. 1L-3, a via 174 is formed in and / or through a dielectric layer 167 and a fin element 103 therebelow and is located on the back surface (i.e., the top surface in the current figure) of the source / drain component 124. In some embodiments, the formation of the via 174 includes patterning the dielectric layer 167 and the sacrificial layer 128 using photolithography and etching processes to form a via opening (the via 174 will be formed in the via opening). The etching process can include dry etching, such as reactive ion etching, neutron beam etching, inductively coupled plasma etching, capacitively coupled plasma etching, other suitable methods, or a combination of the foregoing. In some embodiments, the sacrificial layer 128 is substantially completely removed. According to some embodiments, a silicide layer 175 is formed on the exposed backside surface of the source / drain component 124. In some embodiments, the silicide layer 175 is made of WSi, NiSi, TiSi, and / or CoSi. In some embodiments, the formation of the silicide layer 175 can be similar to the formation of the silicide layer 150. Thereafter, according to some embodiments, one or more conductive materials for the via 174 are deposited to overfill the via opening. In some embodiments, chemical vapor deposition, physical vapor deposition, electron beam evaporation, atomic layer deposition, electroplating, electroless deposition, other suitable methods, or a combination of the foregoing are used to deposit the conductive material (such as cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), rhodium (Rh), iridium (Ir), platinum (Pt), aluminum (Al), ruthenium (Ru), molybdenum (Mo), or a combination of the foregoing) to overfill the via opening. Chemical mechanical polishing, for example, is used to planarize one or more conductive materials until the dielectric layer 167 is exposed. FIG. 1M is a plan view (backside layout) of the semiconductor structure 100, and FIG. 1M shows the formation of the backside first metal layer B_M1. FIGS. 1M-1 and 1M-2 are perspective views showing the power transmission unit regions CB1 and CB2. FIG. 1M-2 only shows the conductive components of the semiconductor structure 100 (such as the source / drain component 124, the contact rail 148B2, the via rail 172, the frontside and backside metal layers, etc.). FIGS. 1M-3, 1M-4, 1M-5, and 1M-6 are schematic cross-sectional views corresponding to the lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of FIG. 1M. According to some embodiments, as shown in FIGS. 1M-1, 1M-3, and 1M-6, an intermetal dielectric layer 176 is formed over the backside of the semiconductor structure 100. In some embodiments, the material and formation of the intermetal dielectric layer 176 can be similar to or substantially the same as the intermetal dielectric layer 158. According to some embodiments, as shown in FIGS. 1M to 1M-6, the backside first metal layer B_M1 is formed in and / or through the intermetal dielectric layer 176. According to some embodiments, the backside first metal layer B_M1 includes a plurality of conductive lines (rails), such as the power supply line 178 (sometimes referred to as the power rail). According to some embodiments, the power supply line 178 includes a VDD power rail that provides a positive voltage and a VSS power rail that can be electrically grounded. According to some embodiments, the power supply line 178 of the backside first metal layer B_M1 extends in the X direction. That is, according to some embodiments, the power supply line 178 has a longitudinal axis parallel to the X direction. In some embodiments, in the Y direction, the width W5 of the power supply line 178 of the backside first metal layer B_M1 is greater than the width W6 of the power supply line 160B of the frontside first metal layer F_M1. According to some embodiments, the backside VSS power rail is located in the second region 50B and overlaps with the power transmission unit region CB2. According to some embodiments, the backside VSS power rail directly contacts the via rail 172. Thus, according to some embodiments, the backside VSS power supply line 178 is electrically connected to the frontside VSS power supply line 160B through the via rail 172 and the contact rail 148B2 of the power transmission unit region CB2. According to some embodiments, the backside VDD power supply line 178 extends through the first region 50A and the second region 50B and overlaps with the functional unit region CA1 and the power transmission unit region CB1. In some other embodiments, the backside VDD power supply line 178 may only extend in the second region 50B. According to some embodiments, the backside VDD power rail directly contacts the via rail 172 (in the second region 50B) and the via hole 174 (in the first region 50A). Thus, according to some embodiments, the backside VDD power supply line 178 is electrically connected to the frontside VDD power supply line 160B through the via rail 172 and the contact rail 148B2 of the power transmission unit region CB1. In addition, according to some embodiments, the backside VDD power supply line 178 is electrically connected to the frontside VDD power supply line 160A that overlaps with the functional unit region CA1 through the VDD node (such as the source terminal) of the p-type channel nanoscale transistor (in the n-type well NW). Thus, according to some embodiments, the power rails can be disposed on both sides of the semiconductor structure 100, which can further reduce the total resistance of the metal layer. The semiconductor structure 100 may further undergo a back-end process to form various interconnect conductive components (not shown) above the backside of the semiconductor structure 100, such as the backside second metal layer (B_M2) to the backside eighth metal layer (B_M8), via holes between adjacent metal layers, passivation layers, bump pads, etc. FIG. 2 is a plan view (backside layout) of a semiconductor structure 200 according to some embodiments of the present invention. FIG. 2-1 is a schematic cross-sectional view of the semiconductor structure 200 of FIG. 2 according to some embodiments of the present invention. FIG. 2 is similar to FIGS. 1A to 1M-6, except that the semiconductor structure 200 is used to form a high-current device. According to some embodiments, the semiconductor structure 200 is used to form a high-current device with a large cell height. In some embodiments, the ratio of the cell height of the functional cell region of the semiconductor structure 100 to the cell height of the functional cell region of the semiconductor structure 200 is in the range of about 0.5 to about 0.95. According to the design rules for patterning the active region, two active regions 104B are defined in a p-type well PW, and the isolation structure 110 is located on the boundary between the power transmission unit region CB1 and the power transmission unit region CB2. In some embodiments, the width W7 of the active region 104A in the p-type well PW is greater than the width W8 of the active region 104A in the n-type well NW and is substantially the same as the width W9 of the active region 104B. According to some embodiments, the cutting component in the second region 50B includes a cutting component 142B1, and the cutting component 142B1 is formed between two adjacent active regions 104B in the p-type well PW. According to some embodiments, the cutting component 142B1' is located on the boundary between the power transmission unit region CB1 and the power transmission unit region CB2. According to some embodiments, the cutting component 142B1' can further reduce the risk of leakage between the power transmission unit region CB1 and the power transmission unit region CB2. FIG. 3 is a plan view (backside layout) of a semiconductor structure 300 according to some embodiments of the present invention. FIG. 3-1 is a schematic cross-sectional view of the semiconductor structure 300 of FIG. 3 according to some embodiments of the present invention. The embodiment of FIG. 3 is similar to FIGS. 2 and 2-1, except that no cutting component 142B1 is formed on the boundary between the power transmission unit region CB1 and the power transmission unit region CB2. FIG. 4 is a plan view (backside layout) of a semiconductor structure 400 according to some embodiments of the present invention. FIG. 4-1 is a schematic cross-sectional view of the semiconductor structure 400 of FIG. 4 according to some embodiments of the present invention. The embodiment of FIG. 4 is similar to FIGS. 2 and 2-1, except that an additional power transmission unit region CB3 is formed between the power transmission unit region CB1 and the power transmission unit region CB2. According to some embodiments, a contact rail 148B2' and a via rail 172B are formed in the cutting component 142B1'. In some embodiments, the power transmission unit region CB3 is arranged between the power transmission unit region CB1 and the power transmission unit region CB2 in the second region 50B and includes an electrical connection structure composed of the via rail 172B and the contact rail 148B2'. Similarly, according to some embodiments, the power transmission unit region CB3 is configured to transmit power from the backside metal layer to the frontside metal wires and does not have functional transistors therein. According to some embodiments, the backside VDD power supply line 178 extends through the first region 50A and the second region 50B and overlaps with the functional unit regions CA1 and CA2 and the power transmission unit regions CB1 and CB2. The backside VDD power rail is electrically connected to the frontside VDD power rail through the VDD node (such as the source terminal) of a p-type channel nanostructure transistor (in the n-type well NW). According to some embodiments, the backside VSS power supply line 178 extends through the first region 50A and the second region 50B and overlaps with the power transmission unit region CB3 and the boundary between the functional unit regions CA1 and CA2. The backside VSS power rail is electrically connected to the frontside VSS power rail through the VSS node (such as the source terminal) of an n-type channel nanostructure transistor (in the p-type well PW). In some embodiments, in the Y direction, the backside VSS power supply line 178 is thinner than the backside VDD power supply line 178. Adding additional power rails on the backside of the semiconductor structure can further reduce the overall resistance of the back-end metal layer. FIG. 5 is a plan view of a semiconductor structure 500 according to some embodiments of the present invention. The embodiment of FIG. 5 is similar to FIGS. 1A to 1M-6, except that the contact rail 148B2 may include a portion extending in the Y direction. According to some embodiments, the contact rail 148B2 includes a protruding portion 148P extending between the insulating strips 134 in the Y direction. According to some embodiments, the protruding portion 148P extends beyond the edge of the cutting member 142B. Therefore, the contact rail 148B2 has a larger cross-sectional area, which can further reduce the overall resistance of the back-end metal layer. FIG. 6 is a plan view of a semiconductor structure 600 according to some embodiments of the present invention. FIG. 6-1 is a schematic cross-sectional view of the semiconductor structure 600 of FIG. 6 according to some embodiments of the present invention. The embodiment of FIG. 6 is similar to FIGS. 1A to 1M-6, except that the insulating strip 134 replaces the dummy gate structure 112 10-12 In the part between and above the via rails 172 of the power transmission unit regions CB1 and CB2. According to some embodiments, the final gate stack (such as the final gate stack 136B) replaces the dummy gate structure 112 10-12 in other parts. FIG. 7 is a plan view of a semiconductor structure 700 according to some embodiments of the present invention. FIG. 7-1 is a schematic cross-sectional view of the semiconductor structure 700 of FIG. 7 according to some embodiments of the present invention. The embodiment of FIG. 7 is similar to FIGS. 2 and 2-1, except that the insulating strip 134 replaces the dummy gate structure 112 10-12The portion between and above the via rails 172 of the power transmission unit regions CB1 and CB2. According to some embodiments, the final gate stack (such as the final gate stack 136B) replaces the dummy gate structure 112 10-12 in other parts. As described above, aspects of embodiments of the present invention relate to semiconductor structures having a backside power rail architecture. The semiconductor structure 100 includes power transmission unit regions CB1 and CB2. Each of the power transmission unit regions CB1 and CB2 includes a contact rail 148B2 electrically connected to the front-side power rail and a via rail 172 electrically connected to the backside power rail, thereby transferring power from the backside of the semiconductor structure 100 to the front side of the semiconductor structure 100. The semiconductor structure 100 includes an insulating strip 134 between the power transmission unit region CB1 and the power transmission unit region CB2. Since the insulating strip 134 replaces the dummy gate structure 112, there is no leakage path between the power transmission unit region CB1 and the power transmission unit region CB2. Therefore, the reliability and manufacturing yield of the final semiconductor device can be improved. Embodiments of a semiconductor structure having a power transmission unit and a method of forming the semiconductor structure are provided. The method may include replacing a dummy gate structure with an insulating strip, forming a cutting member through the insulating strip and an isolation structure, and forming an electrical connection structure in the cutting member to form a power transmission unit. Therefore, the risk of leakage between the power transmission unit regions can be reduced. Therefore, the reliability and manufacturing yield of the final semiconductor device can be improved. In some embodiments, a method of forming a semiconductor structure is provided, the method including forming an isolation structure surrounding a first active region; forming a first dummy gate structure spanning the first active region and the isolation structure; replacing at least a portion of the first dummy gate structure with an insulating strip; forming a first cutting member through the insulating strip and the isolation structure; forming a first contact rail in the first cutting member; forming a first via rail overlapping the first contact rail in the first cutting member; and forming a first metal wire overlapping the first via rail. In some other embodiments, the above method further includes forming a second cutting member through the insulating strip and the isolation structure, wherein the first active region is located between the first cutting member and the second cutting member, and the insulating strip extends continuously from the first cutting member to the second cutting member. In some other embodiments, the above method further includes forming a second contact rail in the second cutting member; forming a second via rail overlapping the second contact rail in the second cutting member; and forming a second metal wire overlapping the second via rail. In some other embodiments, the above method further includes, after forming the first contact track in the first cutting component and before forming the first via track overlapping the first contact track in the first cutting component: polishing the first active region and the first isolation structure to expose the surface of the first cutting component from the back side. In some other embodiments, the above method further includes forming a second metal line above the contact track, and the second metal line is electrically connected to the first metal line, wherein the contact track and the via track are vertically located between the first metal line and the second metal line. In some other embodiments, the step of replacing at least a part of the first dummy gate structure with an insulating strip includes: etching the first dummy gate structure, the first active region, and the isolation structure to form a groove; and forming a dielectric material in the groove. In some other embodiments, the step of forming the first via track overlapping the first contact track in the first cutting component includes: etching the first cutting component to form a groove exposing the surface of the first contact track; and filling the groove with a conductive material. In some other embodiments, the above method further includes forming a second dummy gate structure spanning the first active region and the isolation structure; and replacing the second dummy gate structure with a gate stack, wherein the second dummy gate structure includes a gate dielectric layer above the first active region and a metal gate electrode layer above the gate dielectric layer. In some other embodiments, the above method further includes forming an isolation structure surrounding the second active region; forming a source / drain component above the second active region, wherein the first metal line is electrically connected to the source / drain component; and forming a gate stack spanning the second active region and the isolation structure. In some other embodiments, the second active region is narrower than the first active region. In some embodiments, a method for forming a semiconductor structure is provided, the method including forming a plurality of active regions above a substrate; forming a plurality of insulating strips spanning the plurality of active regions, the plurality of insulating strips vertically extending through the plurality of active regions and into the substrate. The method also includes forming a first contact track between a first active region and a second active region among the plurality of active regions, and forming a second contact track between the second active region and a third active region among the plurality of active regions. The method also includes forming a first via track and a second via track on the first contact track and the second contact track respectively. In some other embodiments, the above method further includes forming a cutting component between the second active region and a fourth active region among the plurality of active regions, wherein the first active region is formed in a first p-type well, the second active region and the fourth active region are formed in a second p-type well, and the third active region is formed in a third p-type well. In some other embodiments, the above method further includes forming a third via track in the cutting component; forming a first VDD power track on the first via track; forming a second VDD power track on the second via track; and forming a VSS power track on the third via track. In some other embodiments, the above method further includes forming a stack of a plurality of alternating first semiconductor layers and a plurality of second semiconductor layers above the substrate; patterning the stack and a part of the substrate to form a plurality of active regions; removing the plurality of first semiconductor layers to form a plurality of nanostructures from the plurality of second semiconductor layers; and forming a gate stack surrounding the plurality of nanostructures. In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a functional unit region including an n-type functional transistor and a p-type functional transistor. The semiconductor structure also includes a first power transmission unit region including a first cutting component and a first contact track in the first cutting component. The semiconductor structure also includes a first power track electrically connected to the source terminal of the p-type functional transistor and the first contact track of the first power transmission unit region. The semiconductor structure also includes a second power transmission unit region adjacent to the first power transmission unit region and including a second cutting component and a second contact track in the second cutting component. The semiconductor structure also includes an insulating strip extending from the first cutting component to the second cutting component in a first direction. In some other embodiments, the above semiconductor structure further includes a semiconductor fin element extending between the first power transmission unit region and the second power transmission unit region in a second direction perpendicular to the first direction; and a first source / drain component and a second source / drain component located on the semiconductor fin element, wherein the insulating strip is located between the first source / drain component and the second source / drain component. In some other embodiments, the insulating strip is buried in the semiconductor fin element. In some other embodiments, the above semiconductor structure further includes a second power track electrically connected to the source terminal of the n-type functional transistor and the second contact track of the second power transmission unit region. In some other embodiments, the first power transmission unit region further includes a first via track between the first contact track and the first power track, and the second power transmission unit region further includes a second via track between the second contact track and the second power track. In some other embodiments, the first contact track includes a first portion extending in the first direction and a second portion extending in the second direction, and the second portion extends beyond the edge of the first cutting component. The foregoing text outlines the features of many embodiments, enabling those of ordinary skill in the art to better understand the embodiments of the present invention from various aspects. Those of ordinary skill in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. 50A: First region 50B: Second region 50C: Third region 100, 200, 300, 400, 500, 600, 700: Semiconductor structure 102: Substrate 103: Underlying fin element 104A, 104B: Active region 106: First semiconductor layer 108: Second semiconductor layer 110: Isolation structure 112, 112 1 , 112 2 , 112 3 , 112 4 , 112 5 , 112 6 , 112 7 , 112 8 , 112 9 , 112 10 , 112 11 , 112 12 , 112 13 , 112 14 , 112 15 :Dummy gate structure 114: Dummy gate dielectric layer 116: Dummy gate electrode layer 118: Gate spacer layer 120: First dielectric material 122: Second dielectric material 124: Source / drain component 126: Inner spacer layer 128: Sacrificial layer 130: Contact etch stop layer 132: First interlayer dielectric layer 134: Insulating strip 136 1, 136 2 , 136 3 , 136 4 , 136 5 , 136 6 , 136 7 , 136 8 , 136 9 , 136 10 , 136 11 , 136 12 , 136 B: Final gate stack 138: Interface layer 139: Gate dielectric layer 140: Metal gate electrode layer 142A, 142B, 142B1, 142B1’: Cutting components 144, 152, 162: Etch stop layer 146: Second interlayer dielectric layer 147: Contact pad 148A, 148B1: Contact plug 148B2, 148B2’: Contact rail 148P: Protrusion 150, 175: Silicide layer 154: Third interlayer dielectric layer 156, 174: Via 158, 164, 176: Intermetal dielectric layer 160A, 160B, 178: Power supply line 166: Conductor 167: Dielectric layer 168: Patterned mask layer 170: Trench 172, 172B: Via rail CA1, CA2: Functional unit region CB1, CB2, CB3: Power transmission unit region L1, L2, L3: Epitaxial layer NW: n-type well PW: p-type well D1, D2, D3, D4: Dimensions S1, S2: Spacing W1, W2, W3, W4, W5, W6, W7, W8, W9: Width F_M1: Front-side first metal layer F_M2: Front-side second metal layer B_M1: Back-side first metal layer Embodiments of the present invention can be better understood with reference to the following detailed description and the accompanying drawings. It should be noted that, according to the standard practice in this industry, the various components (features) in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various components may be arbitrarily enlarged or reduced for clear illustration. FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1K, 1L, and 1M are plan views (layouts) showing the formation of semiconductor structures at various intermediate stages according to some embodiments of the present invention. FIGS. 1A-1, 1B-1, 1M-1, and 1M-2 are perspective views showing the formation of semiconductor structures at various intermediate stages according to some embodiments of the present invention. FIGS. 1A-2, 1A-3, 1A-4, and 1A-5 are cross-sectional schematic views of the semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 in FIG. 1A according to some embodiments of the present invention. FIGS. 1B-2, 1B-3, 1B-4, and 1B-5 are cross-sectional schematic views of the semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 in FIG. 1B according to some embodiments of the present invention. FIGS. 1C-1, 1C-2, 1C-3, and 1C-4 are cross-sectional schematic views of the semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 in FIG. 1C according to some embodiments of the present invention. FIGS. 1D-1, 1D-2, 1D-3, and 1D-4 are cross-sectional schematic views of the semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 in FIG. 1D according to some embodiments of the present invention. FIGS. 1E-1 and 1E-2 are cross-sectional schematic views of the semiconductor structure corresponding to lines Y1-Y1 and X1-X1 in FIG. 1E according to some embodiments of the present invention. FIGS. 1F-1, 1F-2, 1F-3, and 1F-4 are cross-sectional schematic views of the semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 in FIG. 1F according to some embodiments of the present invention. FIGS. 1G-1, 1G-2, 1G-3, and 1G-4 are cross-sectional schematic views of the semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 in FIG. 1G according to some embodiments of the present invention. FIGS. 1H-1 and 1H-2 are cross-sectional schematic views of the semiconductor structure corresponding to lines Y1-Y1 and X1-X1 in FIG. 1G according to some embodiments of the present invention. FIGS. 1I-1, 1I-2, 1I-3, and 1I-4 are cross-sectional schematic views of the semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 in FIG. 1G according to some embodiments of the present invention. FIGS. 1J-1, 1J-2, 1J-3, and 1J-4 are cross-sectional schematic views of the semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 in FIG. 1G according to some embodiments of the present invention.FIGS. 1K-1 and 1K-2 are cross-sectional schematic views of a semiconductor structure corresponding to lines Y1-Y1 and X1-X1 of FIG. 1K in accordance with some embodiments of the present invention. FIGS. 1L-1, 1L-2, 1L-3 and 1L-4 are cross-sectional schematic views of a semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2 and Y2-Y2 of FIG. 1L in accordance with some embodiments of the present invention. FIGS. 1M-3, 1M-4, 1M-5 and 1M-6 are cross-sectional schematic views of a semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2 and Y2-Y2 of FIG. 1M in accordance with some embodiments of the present invention. FIG. 2 is a plan view (layout) of a semiconductor structure in accordance with some embodiments of the present invention. FIG. 2-1 is a cross-sectional schematic view of the semiconductor structure of FIG. 2 in accordance with some embodiments of the present invention. FIG. 3 is a plan view (layout) of a semiconductor structure in accordance with some embodiments of the present invention. FIG. 3-1 is a cross-sectional schematic view of the semiconductor structure of FIG. 3 in accordance with some embodiments of the present invention. FIG. 4 is a plan view (layout) of a semiconductor structure in accordance with some embodiments of the present invention. FIG. 4-1 is a cross-sectional schematic view of the semiconductor structure of FIG. 4 in accordance with some embodiments of the present invention. FIG. 5 is a plan view (layout) of a semiconductor structure in accordance with some embodiments of the present invention. FIG. 6 is a plan view (layout) of a semiconductor structure in accordance with some embodiments of the present invention. FIG. 6-1 is a cross-sectional schematic view of the semiconductor structure of FIG. 6 in accordance with some embodiments of the present invention. FIG. 7 is a plan view (layout) of a semiconductor structure in accordance with some embodiments of the present invention. FIG. 7-1 is a cross-sectional schematic view of the semiconductor structure of FIG. 7 in accordance with some embodiments of the present invention. 50A: First region 50B: Second region 50C: Third region 100: Semiconductor structure 103: Lower fin element 104A, 104B: Active regions 134: Insulating strip 136 1 , 136 2 , 136 3 , 136 4 , 136 5 , 136 6 , 136 7 , 136 8 , 136 9 ,136 10 ,136 11 ,136 12 : Final gate stack 172: Via track 178: Power supply line CA1, CA2: Functional unit area CB1, CB2: Power transmission unit area NW: n-type well PW: p-type well W4: Width

Claims

1. A method of forming a semiconductor structure, comprising: forming an isolation structure surrounding a first active region; forming a first dummy gate structure spanning the first active region and the isolation structure; replacing at least a portion of the first dummy gate structure with an insulating strip; forming a first dicing member passing through the insulating strip and the isolation structure; forming a first contact rail in the first dicing member; forming a first through-hole rail overlapping the first contact rail in the first dicing member; and forming a first metal wire overlapping the first through-hole rail.

2. The method of forming a semiconductor structure as claimed in claim 1 further includes: forming a second dicing member through the insulating strip and the isolation structure, wherein the first active region is located between the first dicing member and the second dicing member, and the insulating strip extends continuously from the first dicing member to the second dicing member.

3. The method for forming a semiconductor structure as claimed in claim 2 further includes: forming a second contact rail in the second dicing member; forming a second through-hole rail overlapping the second contact rail in the second dicing member; and forming a second metal wire overlapping the second through-hole rail.

4. The method of forming a semiconductor structure according to any one of claims 1 to 3 further includes, after forming the first contact rail in the first dicing member and before forming the first through-hole rail overlapping the first contact rail in the first dicing member: grinding the first active region and the first isolation structure to expose a surface of the first dicing member from the back side.

5. The method of forming a semiconductor structure as claimed in claim 1 or 2 further includes: forming a second metal line above the contact rail, and the second metal line being electrically connected to the first metal line, wherein the contact rail and the via rail are vertically located between the first metal line and the second metal line.

6. The method of forming a semiconductor structure according to any one of claims 1 to 3 further includes: forming an isolation structure surrounding a second active region; forming a source / drain component above the second active region, wherein the first metal line is electrically connected to the source / drain component; and forming a gate stack spanning the second active region and the isolation structure.

7. The method for forming a semiconductor structure as claimed in claim 6, wherein the second active region is narrower than the first active region.

8. A method for forming a semiconductor structure, comprising: forming a plurality of active regions over a substrate; forming a plurality of insulating strips spanning the plurality of active regions, wherein the plurality of insulating strips extend vertically through the plurality of active regions and into the substrate; forming a first contact rail between a first active region and a second active region among the plurality of active regions, and forming a second contact rail between the second active region and a third active region among the plurality of active regions; and forming a first via rail and a second via rail on the first contact rail and the second contact rail, respectively.

9. The method of forming a semiconductor structure as claimed in claim 8 further includes: forming a dicing member between the second active region and a fourth active region among the plurality of active regions, wherein the first active region is formed in a first p-type well, the second active region and the fourth active region are formed in a second p-type well, and the third active region is formed in a third p-type well.

10. The method for forming a semiconductor structure as claimed in claim 9 further includes: forming a third via rail in the dicing member; forming a first VDD power rail on the first via rail; forming a second VDD power rail on the second via rail; and forming a VSS power rail on the third via rail.

11. A semiconductor structure comprising: a functional cell region including an n-type functional transistor and a p-type functional transistor; a first power transmission cell region including a first dicing member and a first contact rail in the first dicing member; a first power rail electrically connected to a source terminal of the p-type functional transistor and the first contact rail of the first power transmission cell region, wherein the first power transmission cell region further includes a first via rail between the first contact rail and the first power rail; a second power transmission cell region adjacent to the first power transmission cell region and including a second dicing member and a second contact rail in the second dicing member; and an insulating strip extending from the first dicing member to the second dicing member in a first direction.

12. The semiconductor structure of claim 11 further includes: a semiconductor fin extending in a second direction perpendicular to the first direction between the first power transmission unit region and the second power transmission unit region; and a first source / drain component and a second source / drain component located on the semiconductor fin, wherein the insulating strip is located between the first source / drain component and the second source / drain component.

13. The semiconductor structure of claim 11 or 12 further includes: a second power rail electrically connected to a source terminal of the n-type functional transistor and the second contact rail of the second power transmission unit region.

14. The semiconductor structure of claim 13, wherein the second power transmission unit region further includes a second through-hole rail between the second contact rail and the second power rail.

15. The semiconductor structure of claim 11, wherein the first contact rail includes a first portion extending in the first direction and a second portion extending in a second direction, the second portion extending beyond an edge of the first cut member.

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