Nanostructure field-effect transistor and manufacturing method thereof

Abstract

Various embodiments include multiple protective layers for a transistor and various methods for forming such protective layers. In one embodiment, a method includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing the deposition selectivity between the top surface of the semiconductor nanostructure and the top surface of the isolation region relative to a selective deposition process; depositing a protective layer on the top surface of the isolation region by performing a selective deposition process; removing the dummy nanostructure by selectively etching the dummy material of the dummy nanostructure at a faster rate relative to the protective material of the protective layer; and forming a gate structure surrounding the semiconductor nanostructure.

Description

Technical Field

[0001] None Prior Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate; and using lithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, additional problems arise that should be addressed. Summary of the Invention

[0004] None Brief Description of the Drawings

[0005] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates an example of a nanostructure field-effect transistor (nanostructure-FET) in the form of a three-dimensional view according to some embodiments. FIGS. 2 to 20B are views of intermediate stages in the manufacture of a nanostructure FET according to some embodiments. FIGS. 21A to 21B are views of a nanostructure FET according to some other embodiments. FIGS. 22A to 23B are views of intermediate stages in the manufacture of a nanostructure FET according to some other embodiments. Embodiments

[0006] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features do not directly contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes, and in itself does not indicate a relationship between the various embodiments and / or configurations being discussed.

[0007] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] According to various embodiments, during a gate replacement process, a protective layer is selectively deposited on the isolation region but not on the exposed semiconductor nanostructures. Specifically, after the dummy gate is removed to expose the isolation region and the semiconductor nanostructures, the protective layer is selectively deposited on the isolation region. A pendant amine or an inhibition layer is selectively formed on the top surface of the semiconductor nanostructures, such an inhibition layer inhibiting the deposition of the protective layer such that the protective layer is selectively deposited on the isolation region but not on the semiconductor nanostructures. The protective layer protects the isolation region from etching loss during the process for removing the dummy nanostructures to expose the top and bottom surfaces of the semiconductor nanostructures. Since the protective layer is not formed on the semiconductor nanostructures, the top surface of the upper semiconductor nanostructures may be more readily exposed in subsequent processing before the gate structure is formed around the semiconductor nanostructures. Over-etching of the semiconductor nanostructures can thus be avoided, thereby improving device reliability.

[0009] FIG. 1 illustrates an example of a nanostructure FET (e.g., a nanowire FET, a nanosheet FET, a multi bridge channel (MBC) FET, a nanoribbon FET, a gate-all-around (GAA) FET, or the like) according to some embodiments. FIG. 1 is a three-dimensional view, where some features of the nanostructure FET are omitted for clarity of illustration.

[0010] The nanostructure FET includes a semiconductor nanostructure 66 (e.g., a nanosheet, a nanowire, or the like) above a semiconductor fin 62 on a substrate 50 (e.g., a semiconductor substrate), where the semiconductor nanostructure 66 is a semiconductor feature serving as the channel region of the nanostructure FET. Isolation regions 70 such as shallow trench isolation (STI) regions are disposed between adjacent semiconductor fins 62, and the fins 62 can be above and protrude from between adjacent isolation regions 70. The semiconductor nanostructure 66 is disposed above and between adjacent isolation regions 70. Although the isolation regions 70 are depicted / illustrated as being separated from the substrate 50, as used herein, the term "substrate" can refer to a single semiconductor substrate or a combination of a semiconductor substrate and isolation regions. Additionally, although the bottom portion of the semiconductor fin 62 is shown as being of a single, continuous material with the substrate 50, the bottom portion of the semiconductor fin 62 and / or the substrate 50 can include a single material or a plurality of materials.

[0011] The gate dielectric 132 is above the top surface of the semiconductor fin 62 and along the top surface, sidewalls, and bottom surface of the semiconductor nanostructure 66. The gate electrode 134 is above the gate dielectric 132. Source / drain regions 102 are disposed on the semiconductor fin 62 on opposite sides of the gate dielectric 132 and the gate electrode 134. The source / drain regions 102 can refer to the source or the drain individually or collectively depending on the context. The source / drain regions 102 can be shared among various semiconductor nanostructures 66 in the semiconductor nanostructure 66. For example, adjacent source / drain regions 102 can be electrically connected, such as by epitaxial growth to merge the source / drain regions 102 or by coupling the source / drain regions 102 to the same contact. An inter-layer dielectric (ILD) 114 is formed above the source / drain regions 102.

[0012] FIG. 1 further illustrates reference cross-sections for subsequent figures. Cross-section A-A' is along the longitudinal axis of the gate electrode 134. Cross-section B-B' is perpendicular to cross-section A-A', along the longitudinal axis of the semiconductor fin 62 of the nanostructure FET, and in the direction of the current between the source / drain regions 102 of the nanostructure FET. Cross-section C-C' is parallel to cross-section A-A' and extends through the source / drain region 102 of the nanostructure FET. The subsequent figures clearly indicate these reference cross-sections.

[0013] FIGS. 2 to 20B are views of intermediate stages in manufacturing a nanostructure FET according to some embodiments. FIGS. 2, 3, 4, 5, and 6 are three-dimensional views similar to the three-dimensional view in FIG. 1. FIGS. 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A illustrate cross-sectional views along a cross-section similar to the reference cross-section A-A' in FIG. 1. FIGS. 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, and 20B illustrate cross-sectional views along a cross-section similar to the reference cross-section B-B' in FIG. 1. FIGS. 10C and 10D illustrate cross-sectional views along a cross-section similar to the reference cross-section C-C' in FIG. 1. The nanostructure FET is illustrated in FIGS. 20A to 20B.

[0014] In FIG. 2, a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which can be doped (e.g., by a p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, usually a silicon or glass substrate. Other substrates, such as multi-layer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, gallium indium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof.

[0015] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices, such as NMOS transistors, e.g., n-type nanostructure FETs, and the p-type region 50P can be used to form p-type devices, such as PMOS transistors, e.g., p-type nanostructure FETs. The n-type region 50N can (or may not) be physically separated from the p-type region 50P (not shown separated), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0016] A multilayer stack 52 is formed over the substrate 50. The multilayer stack 52 includes alternating dummy layers 54 and semiconductor layers 56. In the illustrated embodiment, and as described in more detail later, the dummy layers 54 will be removed, and the semiconductor layers 56 will be patterned to form channel regions for the nanostructure FETs in the n-type region 50N and the p-type region 50P.

[0017] The dummy layers 54 are formed of a dummy material, and the semiconductor layers 56 are formed of one or more semiconductor materials. The dummy material of the dummy layers 54 can be a dielectric material or can be a semiconductor material. The dummy material can be silicon oxide, silicon oxynitride, silicon carbonitride, or the like. The semiconductor materials can each be selected from the candidate semiconductor materials of the substrate 50. In some embodiments, the semiconductor layers 56 in the n-type region 50N and the p-type region 50P are formed of the same semiconductor material, which can be suitable for both n-type devices and p-type devices. In some embodiments, the dummy material of the dummy layers 54 is silicon-germanium or silicon oxide, and the semiconductor material of the semiconductor layers 56 is silicon. Thus, the channel regions in both the n-type region 50N and the p-type region 50P can have the same material composition (e.g., silicon or another semiconductor material) and can be formed simultaneously. In another embodiment, the semiconductor layer 56 of the p-type region 50P is formed of a first semiconductor material, while the semiconductor layer 56 in the n-type region 50N is formed of a second semiconductor material. The first semiconductor material can be suitable for p-type devices, such as silicon germanium (e.g., Si xGe 1-x, where x can be in the range of 0 to 1), pure germanium, or the like. The second semiconductor material can be suitable for n-type devices, such as silicon, silicon carbide, or the like. The dummy material of the dummy layers 54 has a high etch selectivity with respect to the semiconductor material of the semiconductor layers 56. Thus, the dummy material of the dummy layers 54 can be removed at a faster rate compared to the semiconductor material of the semiconductor layers 56 in subsequent processing.

[0018] The multi-layer stack 52 is illustrated as including a specific number of dummy layers 54 and a specific number of semiconductor layers 56. It should be understood that the multi-layer stack 52 may include any number of dummy layers 54 and semiconductor layers 56. Each layer in the multi-layer stack 52 can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like.

[0019] In FIG. 3, a semiconductor fin 62 is formed in the substrate 50, and nanostructures 64, 66 (including a dummy nanostructure 64 and a semiconductor nanostructure 66) are formed in the multi-layer stack 52. In some embodiments, the nanostructures 64, 66 and the semiconductor fin 62 can be formed in the multi-layer stack 52 and the substrate 50 respectively by etching trenches in the multi-layer stack 52 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching can be anisotropic. Forming the nanostructures 64, 66 by etching the multi-layer stack 52 can define the dummy nanostructure 64 from the dummy layer 54, and can define the semiconductor nanostructure 66 from the semiconductor layer 56.

[0020] The semiconductor fin 62 and the nanostructures 64, 66 can be patterned by any suitable method. For example, the semiconductor fin 62 and the nanostructures 64, 66 can be patterned using one or more optical lithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine optical lithography and self-alignment processes, thereby allowing patterns to be generated that have, for example, a pitch smaller than the pitch obtained using a single direct optical lithography process otherwise. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the semiconductor fin 62 and the nanostructures 64, 66.

[0021] The nano-structures 64, 66 are illustrated as having substantially equal widths in both the n-type region 50N and the p-type region 50P. In some embodiments, the widths of the nano-structures 64, 66 in the n-type region 50N may be different from the widths of the nano-structures 64, 66 in the p-type region 50P. Additionally, although each of the semiconductor fins 62 and the nano-structures 64, 66 is illustrated as having a constant width throughout, in other embodiments, the semiconductor fins 62 and / or the nano-structures 64, 66 may have tapered sidewalls such that the width of each of the semiconductor fins 62 and / or the nano-structures 64, 66 continuously increases in the direction towards the substrate 50. In such embodiments, each of the nano-structures 64, 66 may have a different width and be trapezoidal in shape.

[0022] In FIG. 4, an insulating material 68 is formed above the substrate 50 and between the semiconductor fins 62 and the nano-structures 64, 66. The insulating material 68 may be an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. The insulating material 68 is formed of a carbon-free dielectric material. In some embodiments, the insulating material 68 includes silicon oxide formed by an FCVD process. Once the insulating material 68 is formed, an annealing process may be performed. Although the insulating material 68 is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not separately illustrated) may first be formed along the surfaces of the substrate 50, the semiconductor fins 62, and the nano-structures 64, 66. Thereafter, a fill material such as one of the insulating materials described previously may be formed above the liner.

[0023] The insulating material 68 may be deposited above the semiconductor fins 62 and the nano-structures 64, 66 such that an excess of the insulating material 68 covers the nano-structures 64, 66. A removal process is then applied to the insulating material 68 to remove the excess insulating material 68 above the nano-structures 64, 66. In some embodiments, a planarization process such as chemical mechanical polish (CMP), an etch-back process, a combination thereof, or the like may be utilized. The planarization process exposes the nano-structures 64, 66 such that the top surfaces of the nano-structures 64, 66 and the insulating material 68 are substantially coplanar (within process variations) after the planarization process is completed.

[0024] In FIG. 5, the insulating material 68 is recessed to form isolation regions 70. The isolation regions 70 are adjacent to the semiconductor fins 62. The insulating material 68 is recessed such that the upper portions of the semiconductor fins 62 and / or the nanostructures 64, 66 protrude between the adjacent isolation regions 70. The upper portions of the semiconductor fins 62 and / or the nanostructures 64, 66 are above the isolation regions 70. Additionally, the top surface of the isolation regions 70 may have a flat surface, a raised surface, a recessed surface (such as a dish shape), or a combination thereof as shown. The top surface of the isolation regions 70 can be formed to be flat, raised, and / or recessed by appropriate etching. The isolation regions 70 can be recessed using any acceptable etching process, such as an etching process that is selective for the material of the insulating material 68 (e.g., etching the material of the insulating material 68 at a faster rate compared to the materials of the semiconductor fins 62 and the nanostructures 64, 66). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid can be used. In some embodiments, the etching is anisotropic.

[0025] The processes described previously are merely an example of how the semiconductor fins 62 and the nanostructures 64, 66 can be formed. In some embodiments, the semiconductor fins 62 and / or the nanostructures 64, 66 can be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. An epitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the semiconductor fins 62 and / or the nanostructures 64, 66. The epitaxial structure can include the alternating semiconductor materials described previously, such as dummy materials and semiconductor materials. In some embodiments where the epitaxial structure is epitaxially grown, the epitaxially grown material can be in-situ doped during growth, which can alleviate prior and / or subsequent implantations, although in-situ and implantation doping can be used together.

[0026] Additionally, appropriate wells (not shown separately) may be formed in the semiconductor fin 62 and / or the nanostructures 64, 66. In embodiments having different well types, different implantation steps for the n-type region 50N and the p-type region 50P may be achieved using photoresist or other masks (not shown separately). For example, photoresist may be formed over the semiconductor fin 62, the nanostructures 64, 66, and the isolation region 70 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed by using a spin coating technique and may be patterned using acceptable optical lithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist may act as a mask to substantially prevent n-type impurity implantation into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration ranging from 10^13 atoms / cm^3 to 10^14 atoms / cm^3. After implantation, the photoresist is removed, such as by any acceptable ashing process.

[0027] After or before implanting the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the semiconductor fin 62, the nanostructures 64, 66, and the isolation region 70 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist may be formed by using a spin coating technique and may be patterned using acceptable optical lithography techniques. Once the photoresist is patterned, p-type impurity implantation may be performed in the n-type region 50N, and the photoresist may act as a mask to substantially prevent p-type impurity implantation into the p-type region 50P. The p-type impurity may be boron, boron fluoride, indium, or the like implanted in the region to a concentration ranging from 10^13 atoms / cm^3 to 10^14 atoms / cm^3. After implantation, the photoresist may be removed, such as by any acceptable ashing process.

[0028] After implanting the n-type region 50N and the p-type region 50P, an annealing process may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments where an epitaxial structure is epitaxially grown, the epitaxial growth material may be in-situ doped during growth, which may reduce implantation, although in-situ and implantation doping may be used together.

[0029] In FIG. 6, a dummy dielectric layer 72 is formed on the semiconductor fin 62 and / or the nanostructures 64, 66. The dummy dielectric layer 72 can be formed of silicon oxide, silicon nitride, a combination thereof, or the like, and the foregoing materials can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 74 is formed above the dummy dielectric layer 72. The dummy gate layer 74 can be deposited above the dummy dielectric layer 72 and then planarized, such as by a chemical mechanical polish (CMP) process. The dummy gate layer 74 can be formed of a conductive or non-conductive material and can be selected from the group including amorphous silicon, polycrystalline-silicon (polysilicon), polycrystalline silicon germanium (polycrystalline-SiGe), metal nitride, metal silicide, metal oxide, and metal. The material of the dummy gate layer 74 can be deposited by CVD, physical vapor deposition (PVD), sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 74 can be formed of a material having a high etch selectivity with respect to etching of other insulating materials (such as the isolation region 70 and / or the dummy dielectric layer 72). A mask layer 76 is formed above the dummy gate layer 74. The mask layer 76 can be made of a dielectric material such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 72 covers the isolation region 70 such that the dummy dielectric layer 72 extends between the dummy gate layer 74 and the isolation region 70. In another embodiment, the dummy dielectric layer 72 only covers the semiconductor fin 62 and / or the nanostructures 64, 66.

[0030] FIGS. 7A to 20B illustrate various additional steps in manufacturing the exemplary device. FIGS. 7A to 20B illustrate features in either the n-type region 50N or the p-type region 50P. For example, the illustrated structures can be applicable to both the n-type region 50N and the p-type region 50P. Structural differences (if any) between the n-type region 50N and the p-type region 50P will be explained in the description of each figure.

[0031] In FIGS. 7A to 7B, the mask layer 76 is patterned using acceptable optical lithography and etching techniques to form a mask 86. The pattern of the mask 86 can then be transferred to the dummy gate layer 74 and to the dummy dielectric layer 72 to form a dummy gate 84 and a dummy dielectric 82, respectively. The dummy gate 84 covers the respective channel regions of the nanostructures 64, 66. The pattern of the mask 86 can be used to physically separate each of the dummy gates 84 from an adjacent dummy gate 84. The dummy gate 84 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective semiconductor fins 62. The mask 86 can be removed as needed after patterning, such as by any acceptable etching technique.

[0032] In FIGS. 8A to 8B, gate spacers 92 are formed over the nanostructures 64, 66 and the isolation region 70, on the exposed sidewalls of the mask 86 (if present), the dummy gate 84, and the dummy dielectric 82. The gate spacers 92 can be formed by conformally forming one or more dielectric materials and then etching the dielectric materials. Acceptable dielectric materials can include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide nitride, or the like, which can be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Other insulating materials formed by any acceptable process can be used. Any acceptable etching process, such as dry etching, wet etching, the like, or a combination thereof, can be performed to pattern the dielectric materials. The etching can be anisotropic. The dielectric materials have portions remaining on the sidewalls of the dummy gate 84 when etched (thus, forming the gate spacers 92). As described in more detail subsequently, the dielectric materials can also have portions remaining on the sidewalls of the semiconductor fins 62 and / or the nanostructures 64, 66 when etched (thus forming fin spacers 94, see FIGS. 10C to 10D). After etching, the fin spacers 94 and / or the gate spacers 92 can have straight sidewalls (as illustrated), or can have curved sidewalls (not shown separately).

[0033] Additionally, implantation for lightly doped source / drain (LDD) regions (not shown separately) can be performed. The LDD implantation can be performed before forming the gate spacers 92. In embodiments with different device types, similar to the implantation of the wells described previously, a mask such as photoresist can be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type (e.g., p-type) of impurity can be implanted into the semiconductor fins 62 and nanostructures 64, 66 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask such as photoresist can be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type (e.g., n-type) of impurity can be implanted into the semiconductor fins 62 and nanostructures 64, 66 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have an impurity concentration in the range of 10^15 atoms / cm^3 to 10^19 atoms / cm^3. Annealing can be used to repair implantation damage and activate the implanted impurities.

[0034] Note that the previously disclosed content generally describes processes for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be utilized, different step sequences can be employed, additional spacers can be formed and removed, and / or the like. Additionally, n-type and p-type devices can be formed using different structures and steps.

[0035] Source / drain recesses 96 are patterned in the semiconductor fins 62, nanostructures 64, 66, and substrate 50. Epitaxial source / drain regions will then be formed in the source / drain recesses 96. The source / drain recesses 96 can extend through the nanostructures 64, 66 and into the substrate 50. In some embodiments, the semiconductor fin 62 can be etched such that the bottom surface of the source / drain recess 96 is positioned below the top surface of the isolation region 70. The source / drain recesses 96 can be formed by etching the semiconductor fins 62, nanostructures 64, 66, and substrate 50 using an anisotropic etching process such as RIE, NBE, or the like. The gate spacers 92 and dummy gates 84 shield portions of the semiconductor fins 62, nanostructures 64, 66, and substrate 50 during the etching process used to form the source / drain recesses 96. A single etching process or multiple etching processes can be used to etch each layer of the nanostructures 64, 66 and / or the semiconductor fins 62. A timed etching process can be used to stop the etching of the source / drain recesses 96 after the source / drain recesses 96 reach the desired depth.

[0036] In FIGS. 9A to 9B, internal spacers 98 are formed on the sidewalls of the remaining portions of the dummy nanostructures 64, such as those sidewalls exposed by the source / drain recesses 96. As will be described in more detail subsequently, source / drain regions will be formed in the source / drain recesses 96, and the dummy nanostructures 64 will subsequently be replaced with corresponding gate structures. The internal spacers 98 serve as isolation features between the subsequently formed source / drain regions and the subsequently formed gate structures. Additionally, the internal spacers 98 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as the etching process used to subsequently remove the dummy nanostructures 64.

[0037] As an example for forming the internal spacer 98, the source / drain recess 96 can be laterally extended. Specifically, a portion of the sidewall of the dummy nanostructure 64 exposed by the source / drain recess 96 can be recessed to form a sidewall recess. Although the sidewalls of the dummy nanostructure 64 are illustrated as straight, the sidewalls can be recessed or convex. The sidewalls can be recessed by any acceptable etching process, such as an etching process that is selective for the material of the dummy nanostructure 64 (e.g., etching the material of the dummy nanostructure 64 at a faster rate compared to the material of the semiconductor nanostructure 66). The etching can be isotropic. For example, when the semiconductor nanostructure 66 is formed of silicon and the dummy nanostructure 64 is formed of silicon germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In some embodiments, the same etching process can be continuously performed to both form the source / drain recess 96 and recess the sidewalls of the dummy nanostructure 64. An insulating material can then be conformally formed in the source / drain recess 96 (including the sidewall recess) and subsequently etched. The insulating material can be silicon nitride or silicon oxynitride, although any suitable material can be utilized, such as a low-dielectric constant (low-k) material having a k value less than about 3.5. The insulating material can be formed by a deposition process, such as ALD, CVD, or the like. The etching of the insulating material can be anisotropic. For example, the etching process can be a dry etching, such as RIE, NBE, or the like. The insulating material has a portion remaining in the sidewall recess when etched (thus forming the internal spacer 98). Although the outer sidewalls of the internal spacer 98 are illustrated as flush with the sidewalls of the semiconductor nanostructure 66, the outer sidewalls of the internal spacer 98 can extend beyond the sidewalls of the semiconductor nanostructure 66 or be recessed from those sidewalls. In other words, the internal spacer 98 can partially fill, completely fill, or overfill the sidewall recess. Additionally, although the sidewalls of the internal spacer 98 are illustrated as straight, the sidewalls of the internal spacer 98 can be recessed or convex.

[0038] In FIGS. 10A to 10B, the epitaxial source / drain region 102 is formed in the source / drain recess 96. In some embodiments, the epitaxial source / drain region 102 applies stress to the respective channel regions of the semiconductor nanostructure 66, thereby improving performance. The epitaxial source / drain region 102 is formed in the source / drain recess 96 such that each dummy gate 84 is disposed between respective adjacent pairs of epitaxial source / drain regions 102. In some embodiments, the gate spacer 92 is used to separate the epitaxial source / drain region 102 from the dummy gate 84, and the inner spacer 98 is used to separate the epitaxial source / drain region 102 from the dummy nanostructure 64 by an appropriate lateral distance such that the epitaxial source / drain region 102 does not short-circuit connect to the subsequently formed gate of the resulting nanostructure FET.

[0039] The epitaxial source / drain region 102 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the epitaxial source / drain region 102 is epitaxially grown in the source / drain recess 96 in the n-type region 50N. The epitaxial source / drain region 102 in the n-type region 50N can include any acceptable material suitable for an n-type nanostructure FET. For example, if the semiconductor nanostructure 66 is formed of silicon, the epitaxial source / drain region 102 in the n-type region 50N can include a material that applies tensile strain on the semiconductor nanostructure 66, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 102 in the n-type region 50N can be referred to as an "n-type source / drain region". The epitaxial source / drain region 102 can have a surface elevated from the respective upper surfaces of the nanostructures 64, 66, and can have a facet.

[0040] The epitaxial source / drain region 102 in the p-type region 50P can be formed by masking the n-type region 50N. Then, the epitaxial source / drain region 102 is epitaxially grown in the source / drain recess 96 in the p-type region 50P. The epitaxial source / drain region 102 in the p-type region 50P can include any acceptable material suitable for a p-type nanostructure FET. For example, if the semiconductor nanostructure 66 is formed of silicon, the epitaxial source / drain region 102 in the p-type region 50P can include a material that applies compressive strain on the dummy nanostructure 64, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain region 102 in the p-type region 50P can be referred to as a "p-type source / drain region". The epitaxial source / drain region 102 can also have a surface elevated from the respective surfaces of the nanostructures 64, 66, and can have a facet.

[0041] Similar to the process for forming lightly doped source / drain regions described previously, the epitaxial source / drain regions 102, the nanostructures 64, 66, and / or the semiconductor fins 62 can be implanted with dopants to form the source / drain regions, followed by annealing. The source / drain regions can have an impurity concentration between 10^19 atoms / cm^3 and 10^21 atoms / cm^3. The n-type and / or p-type impurities in the source / drain regions can be any of the impurities described previously. In some embodiments, the epitaxial source / drain regions 102 can be in-situ doped during growth.

[0042] As a result of the epitaxial process for forming the epitaxial source / drain regions 102, the upper surface of the epitaxial source / drain regions 102 has facets that laterally extend outward beyond the sidewalls of the nanostructures 64, 66. In some embodiments, these facets cause adjacent epitaxial source / drain regions 102 of the same nanostructure FET to merge, as illustrated in FIG. 10C. In other embodiments, the adjacent epitaxial source / drain regions 102 remain separated after the epitaxial process is completed, as illustrated by FIG. 10D. In the illustrated embodiment, fin spacers 94 are formed on the top surface of the isolation region 70, thereby blocking epitaxial growth. In some other embodiments, the fin spacers 94 can cover multiple portions of the sidewalls of the nanostructures 64, 66, and / or the semiconductor fins 62, thereby further blocking epitaxial growth. In another embodiment, the spacers used to form the gate spacers 92 are adjusted not to form the fin spacers 94, so as to allow the epitaxial source / drain regions 102 to extend to the surface of the isolation region 70.

[0043] The epitaxial source / drain regions 102 can include one or more semiconductor layers. For example, the epitaxial source / drain regions 102 can include a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. Any number of semiconductor layers can be used for the epitaxial source / drain regions 102. Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer can be formed of a different semiconductor material and can be doped to different dopant concentrations. In some embodiments, the first semiconductor layer can have a dopant concentration less than that of the second semiconductor layer and greater than that of the third semiconductor layer. In embodiments where the epitaxial source / drain regions 102 include three semiconductor layers, the first semiconductor layer can be grown on the sidewalls of the semiconductor nanostructures 66, the second semiconductor layer can be grown on the first semiconductor layer, and the third semiconductor layer can be grown on the second semiconductor layer.

[0044] In FIGS. 11A to 11B, a first ILD 114 is deposited over the epitaxial source / drain regions 102, the gate spacers 92, and the mask 86 (if present) or dummy gate 84. The first ILD 114 may be formed of a dielectric material, which may be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used.

[0045] In some embodiments, a contact etch stop layer (CESL) 112 is formed between the first ILD 114 and the epitaxial source / drain regions 102, the gate spacers 92, and the mask 86 (if present) or dummy gate 84. The CESL 112 may be formed of a dielectric material such as silicon nitride, silicon oxynitride, or the like that has a high etch selectivity for etching the first ILD 114, and the first ILD 114 may be formed by any suitable deposition process such as CVD, ALD, or the like.

[0046] In FIGS. 12A to 12B, a removal process is performed to make the top surface of the first ILD 114 flush with the top surfaces of the gate spacers 92 and the mask 86 (if present) or dummy gate 84. In some embodiments, a planarization process such as chemical mechanical polish (CMP), an etch-back process, a combination thereof, or the like may be utilized. The planarization process may also remove the mask 86 on the dummy gate 84 and portions of the gate spacers 92 along the sidewalls of the mask 86. After the planarization process, the top surfaces of the first ILD 114, the gate spacers 92, and the mask 86 (if present) or dummy gate 84 are substantially coplanar (within process variations). Accordingly, the top surface of the mask 86 (if present) or dummy gate 84 is exposed via the first ILD 114.

[0047] In FIGS. 13A to 13B, an ILD mask 116 is formed over the remaining portion of the first ILD 114. The ILD mask 116 covers the first ILD 114 to protect the first ILD 114 during subsequent gate replacement processes. As an example for forming the ILD mask 116, the first ILD 114 may be recessed such that recesses are formed between opposing gate spacers 92 in the gate spacers 92. The recessing may be any acceptable etching process, such as wet or dry etching. An insulating material may then be conformally formed in the recesses. The insulating material may be silicon nitride or silicon oxynitride, however any suitable material may be utilized, such as a low-dielectric constant (low-k) material having a k value of less than about 3.5. The insulating material may be formed by a deposition process, such as ALD, CVD, or the like. Excess portions of the insulating material are then removed that are above the top surfaces of the gate spacers 92 and the mask 86 (if present) or dummy gate 84. In some embodiments, a planarization process, such as chemical mechanical polish (CMP), etchback process, a combination thereof, or the like may be utilized. The insulating material has remaining portions in the recesses after the removal process (thus forming the ILD mask 116).

[0048] In FIGS. 14A to 14B, the mask 86 (if present) and the dummy gate 84 are removed in one or more etching steps such that recesses 122 are formed between the gate spacers 92. Portions of the dummy dielectric 82 in the recesses 122 are also removed. In some embodiments, the dummy gate 84 and the dummy dielectric 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the material of the dummy gate 84 at a faster rate compared to the materials of the gate spacers 92 and the ILD mask 116 (if present) or the first ILD 114. The etching process 122 exposes and / or overlies portions of the semiconductor nanostructure 66 that serve as the channel region in the subsequently completed nanostructure FET. The portions of the semiconductor nanostructure 66 that serve as the channel region are disposed between adjacent pairs of epitaxial source / drain regions 102. During the removal, the dummy dielectric 82 may be used as an etch stop layer when the dummy gate 84 is etched. The dummy dielectric 82 may then be removed after the dummy gate 84 is removed.

[0049] Additionally, pendant hydroxyl groups (OH) are formed on the top surface of the upper semiconductor nanostructure 66 and on the top surface of the isolation region 70. The hydroxyl groups can be bonded to the silicon atoms of the semiconductor nanostructure 66 and the isolation region 70. The hydroxyl groups can be formed due to native oxidation and / or exposure to moisture during the formation of the recess 122, or can be formed by a surface hydroxylation process after the formation of the recess 122. The surface hydroxylation process can be a plasma treatment performed by precursors that leave hydroxyl groups on the treated surface, such as a combination of oxygen (O2) and hydrogen (H2). The surface hydroxylation process can be anisotropic such that the top surfaces of the upper semiconductor nanostructure 66 and the isolation region 70 are hydroxylated. Accordingly, the sidewalls of the gate spacer 92, the nanostructures 64, 66, and the semiconductor fin 62 may not be hydroxylated. The ILD mask 116 can protect the first ILD 114 from being hydroxylated.

[0050] In FIGS. 15A to 15B, a processing procedure 124 is performed to selectively replace some of the pendant hydroxyl groups with pendant amino groups (NH2). Specifically, at least some of the hydroxyl groups pendant from the top surface of the upper semiconductor nanostructure 66 are replaced with pendant amino groups. As described in more detail subsequently, a protective layer is formed on the isolation region 70 by selectively depositing a protective material on the desired surface. The precursor of the protective material reacts with the hydroxyl groups but not with the amino groups, thereby effectively inhibiting the deposition of the protective material on the surface where the pendant hydroxyl groups are replaced by the pendant amino groups. Accordingly, replacing at least some of the pendant hydroxyl groups with pendant amino groups (e.g., at the top surface of the upper semiconductor nanostructure 66) effectively increases the deposition selectivity between the top surface of the upper semiconductor nanostructure 66 and the top surface of the isolation region 70 with respect to the selective deposition process for forming the protective layer. Accordingly, the orientation of the subsequently deposited protective layer can be advantageously controlled by replacing the desired hydroxyl groups with amino groups.

[0051] The processing procedure 124 breaks the hydroxyl groups from the silicon atoms of the semiconductor nanostructure 66 and attaches amino groups to those silicon atoms, thereby replacing the hydroxyl groups with amino groups. The processing procedure 124 has a first replacement ratio on the top surface of the upper semiconductor nanostructure 66, and the processing procedure 124 has a second replacement ratio on the top surface of the isolation region 70. In this case, the "replacement ratio" refers to the percentage of hydroxyl groups replaced by amino groups by the processing procedure 124. It is more difficult for the processing procedure 124 to reach the lower portion of the recess 122 compared to reaching the upper portion of the recess 122. Accordingly, the first replacement ratio of the top surface of the upper semiconductor nanostructure 66 is greater than the second replacement ratio of the top surface of the isolation region 70. The processing procedure 124 is controlled such that the difference between the replacement ratios of the semiconductor nanostructure 66 and the isolation region 70 is large.

[0052] After the processing step 124, the top surface of the upper semiconductor nanostructure 66 has fewer dangling hydroxyl groups and more dangling amino groups compared to the top surface of the isolation region 70. In this embodiment, the hydroxyl groups dangling from the top surface of the upper semiconductor nanostructure 66 are not completely replaced by amino groups, and the hydroxyl groups dangling from the top surface of the isolation region 70 are not replaced by amino groups at all. Therefore, the top surface of the isolation region 70 is substantially free of amino groups after the processing step 124. In another embodiment (described subsequently with reference to FIGS. 21A-21B), the hydroxyl groups dangling from the top surfaces of the upper semiconductor nanostructure 66 and the isolation region 70 are replaced by amino groups, but the hydroxyl groups dangling from the top surface of the upper semiconductor nanostructure 66 are replaced by amino groups to a greater extent than the hydroxyl groups dangling from the top surface of the isolation region 70. Therefore, amino groups still dangle from the top surface of the isolation region 70 after the processing step 124.

[0053] In some embodiments, the processing step 124 is a nitrogen soaking process in which the semiconductor nanostructure 66 is soaked in a nitrogen-containing gas without generating plasma. The nitrogen soaking process can be performed in a chamber into which the nitrogen-containing gas is dispensed. The nitrogen-containing gas can include a nitrogen precursor and a carrier gas. The nitrogen precursor can be ammonia (NH3), nitrogen gas (N2), a combination thereof, or the like. The carrier gas can be an inert gas such as Ar, He, Xe, Ne, Kr, Rn, the like, or a combination thereof. The nitrogen soaking is performed at an elevated temperature, such as by heating the chamber during the nitrogen soaking process. In some embodiments, the nitrogen soaking is performed at a temperature in the range of 400 °C to 800 °C and for a duration in the range of 4 hours to 8 hours. Accordingly, the hydroxyl groups are broken off from the silicon atoms of the semiconductor nanostructure 66, the hydroxyl groups react with the nitrogen precursor to form amino groups, and the amino groups attach to those silicon atoms. Performing the nitrogen soaking in the presence of a nitrogen-containing gas and at an elevated temperature can help achieve the aforementioned large difference in the replacement ratio between the semiconductor nanostructure 66 and the isolation region 70.

[0054] In some embodiments, the processing process 124 is nitrogen plasma processing, in which the semiconductor nanostructure 66 is bombarded by nitrogen-containing ions. The nitrogen-containing ions can be nitrenium ions (NH2+), nitrogen ions (N2+), combinations thereof, or the like. The nitrogen plasma processing can be performed in a chamber to which a source gas is dispensed. The source gas can include a nitrogen precursor and a carrier gas. The nitrogen precursor can be ammonia (NH3), nitrogen gas (N2), combinations thereof, or the like. The carrier gas can be an inert gas such as Ar, He, Xe, Ne, Kr, Rn, the like, or combinations thereof. The plasma is generated from the source gas in the chamber. The plasma can be generated by a plasma generator such as an inductively coupled plasma system, a capacitively coupled plasma system, a microwave plasma generating gas, or the like. The plasma generator generates radio frequency power, and the radio frequency power generates the plasma from the source gas by exciting the source gas to a plasma state. The plasma generation power can pulsate between a low power (e.g., substantially zero watts) and a high power. In some embodiments, the nitrogen plasma processing is performed using a plasma generation power having a high power in the range of 200 watts to 800 watts. In some embodiments, the nitrogen plasma processing is performed at a temperature in the range of 200 °C to 450 °C and for a duration in the range of 30 minutes to 2 hours. The generated plasma includes nitrogen-containing ions, and the semiconductor nanostructure 66 is bombarded by the nitrogen-containing ions. Accordingly, the hydroxyl groups are disconnected from the silicon atoms of the semiconductor nanostructure 66, the hydroxyl groups react with the nitrogen-containing ions to form amine groups, and the amine groups are attached to those silicon atoms. Performing the nitrogen plasma processing with the nitrogen precursor and at the desired plasma generation power or temperature can help achieve the aforementioned large difference between the semiconductor nanostructure 66 and the replacement ratio of the isolation region 70.

[0055] In FIGS. 16A to 16B, a protective layer 128 is formed on the top surface of the isolation region 70. The protective layer 128 is formed by selectively depositing a protective material on the top surface of the isolation region 70. The protective material can be a carbon-containing dielectric material such as silicon carbonitride, silicon carbonitride, or the like, and the aforementioned dielectric material can be deposited by a selective deposition process such as a selective ALD process, a selective CVD process, or the like. The protective material can be doped with impurities such as hydrogen. The protective material of the protective layer 128 is different from the insulating material of the isolation region 70. For example, the protective material of the protective layer 128 can have a higher carbon concentration compared to the insulating material of the isolation region 70.

[0056] As described in more detail below, the dummy nanostructure 64 will be replaced by the corresponding gate structure. The protective layer 128 will protect the isolation region 70 during the removal of the dummy nanostructure 64. Specifically, the protective material of the protective layer 128 has a high etching selectivity relative to the dummy material of the dummy nanostructure 64. Thus, the etching loss of the isolation region 70 during subsequent gate replacement processes can be reduced. In some embodiments, the protective layer 128 is formed to a thickness in the range of 0 Å to 100 Å. This thickness of the protective layer 128 can help provide protection to the isolation region 70 during the removal of the dummy nanostructure 64. In some embodiments, the composition of the protective material includes from 30% to 50% silicon, from 10% to 20% carbon, and from 0% to 10% nitrogen, where the carbon-to-silicon ratio is in the range of 0.3 to 0.5 (such as in the range of 0.3 to 0.4). This composition of the protective material can cause the protective material to have a low etching rate during the removal of the dummy nanostructure 64. In some embodiments, the etching rate of the protective material in diluted hydrofluoric acid (dHF) is less than 10 Å / minute. The etching rate of the protective material can be adjusted to a desired amount by adjusting the composition of the protective material.

[0057] In some embodiments, the protective layer 128 is formed by a selective ALD process that is performed by cyclically dispensing different source precursors into the recesses 122. The source precursors include a silicon-carbon precursor and one or more other precursors that react with the silicon-carbon precursor to form the protective material of the protective layer 128. The silicon-carbon precursor is a precursor that includes both silicon and carbon, such as bis(tertiary-butyl-amino)silane (BTBAS), bis(diethylamino)silane (BDEAS), or the like. The other precursors can be precursors that include nitrogen and / or oxygen, such as oxygen, amine, or the like. The ALD cycle is performed by sequentially dispensing each of the source precursors, where each ALD cycle results in the deposition of an atomic layer (sometimes referred to as a monolayer) of the protective material of the protective layer 128. The ALD cycles are repeated multiple times until the protective layer 128 is formed to the desired thickness (previously described). The selective ALD process can be plasma enhanced, where the plasma is generated after dispensing at least some of the source precursors. The plasma can be generated from argon, helium, oxygen, a combination thereof, or the like, and is excited into a plasma state using a plasma generator. During the ALD cycle of the selective ALD process, the top surface of the isolation region 70 is immersed in the silicon-carbon precursor. The process conditions (e.g., temperature, pressure, and plasma generation) of the selective ALD process are selected such that the hydrogen atom in the hydroxyl group is disconnected. Thus, the silicon atom in the silicon-carbon precursor adsorbs onto the oxygen atom remaining from the hydroxyl group and attaches to the oxygen atom. The silicon-carbon precursor preferably attaches to the hydroxyl group and preferably does not attach to the amine group. Thus, the amine group acts as an inhibitor, thereby inhibiting the physical and / or chemical adsorption of the silicon-carbon precursor. Effectively, the processing step 124 (previously described with respect to FIGS. 15A-15B) increases the deposition selectivity with respect to the selective ALD process between the top surface of the upper semiconductor nanostructure 66 and the top surface of the isolation region 70. Since the hydroxyl groups hang from the top surface of the isolation region 70 and the amine groups hang from the top surface of the upper semiconductor nanostructure 66, the silicon-carbon precursor attaches to the isolation region 70 but is inhibited from attaching to the semiconductor nanostructure 66. Thus, the adsorption of the silicon-carbon precursor is selective for the isolation region 70, and the protective material of the protective layer 128 is selectively deposited on the top surface of the isolation region 70. The top surface of the upper semiconductor nanostructure 66 can be substantially free of the protective layer 128. Additionally, the top surface of the upper semiconductor nanostructure 66 can be substantially carbon-free after the protective layer 128 is deposited. Forming the hanging amine groups on the semiconductor nanostructure 66 is a low-cost way to avoid forming the protective layer 128 on the semiconductor nanostructure 66.

[0058] In FIGS. 17A to 17B, the remaining portion of the dummy nanostructure 64 is removed to form an opening 130 between the semiconductor nanostructures 66. The remaining portion of the dummy nanostructure 64 can be removed by any acceptable etching process that selectively etches the material of the dummy nanostructure 64 at a faster rate compared to the materials of the semiconductor nanostructure 66 and the protective layer 128. The etching can be isotropic. For example, when the dummy nanostructure 64 is formed of silicon germanium, the semiconductor nanostructure 66 is formed of silicon, and the protective layer 128 is formed of silicon carbonitride, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. Similarly, when the dummy nanostructure 64 is formed of silicon oxide, the semiconductor nanostructure 66 is formed of silicon, and the protective layer 128 is formed of silicon carbonitride, the etching process can be a wet etching using dilute hydrofluoric (dHF) acid or the like. The protective layer 128 protects the isolation region 70 during the etching of the dummy nanostructure 64, thereby reducing the etching loss of the isolation region 70. In some embodiments, the isolation region 70 and the dummy nanostructure 64 are formed of the same material, and forming the protective layer 128 allows the dummy nanostructure 64 to be removed without removing the isolation region 70.

[0059] In FIGS. 18A to 18B, the dangling amines are removed, for example, from the surface of the semiconductor nanostructure 66. The dangling amines can be removed by any acceptable etching process, such as dry etching and / or wet etching, that selectively etches the dangling amines at a faster rate compared to the materials of the semiconductor nanostructure 66 and the protective layer 128. In some embodiments, the dangling amines are removed by the same etching process used to remove the remaining portion of the dummy nanostructure 64. In some embodiments, the dangling amines are removed by a separate etching process that is performed after the etching process used to remove the remaining portion of the dummy nanostructure 64.

[0060] The dangling amines are more easily etched compared to the protective material of the protective layer 128. By avoiding the formation of the protective layer 128 on the semiconductor nanostructure 66, the semiconductor nanostructure 66 can be more easily exposed after the deposition of the protective layer 128. Over-etching of the semiconductor nanostructure 66 can thus be avoided, thereby improving device reliability.

[0061] In FIGS. 19A to 19B, the gate dielectric 132 and the gate electrode 134 are formed for replacing the gate. Each respective pair of the gate dielectric 132 and the gate electrode 134 may be collectively referred to as a "gate structure". Each gate structure covers the channel region of the semiconductor nanostructure 66 such that the gate structure extends along the sidewalls, bottom surface, and top surface of the semiconductor nanostructure 66. Some of the gate structures also extend along the sidewalls and / or top surface of the semiconductor fin 62.

[0062] The gate dielectric 132 includes one or more gate dielectric layers disposed on: the sidewalls and / or top surface of the semiconductor fin 62; the top surface, sidewalls, and bottom surface of the channel region of the semiconductor nanostructure 66; the sidewalls of the internal spacer 98; and the sidewalls of the gate spacer 92. The gate dielectric 132 may be formed of an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, a combination thereof, a multilayer thereof, or the like. Additionally or alternatively, the gate dielectric 132 may be formed of a high-k dielectric material (e.g., a dielectric material having a k value greater than about 7.0), such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The dielectric material of the gate dielectric 132 may be formed by molecular-beam deposition (MBD), ALD, PECVD, or the like. Although a single-layer gate dielectric 132 is illustrated, the gate dielectric 132 may include any number of interface layers and any number of main layers. For example, the gate dielectric 132 may include an interface layer and an overlying high-k dielectric layer.

[0063] The gate electrode 134 includes one or more gate electrode layers disposed above the gate dielectric 132. The gate electrode 134 may be formed of a metal-containing material such as: titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multilayers thereof, or the like. Although a single-layer gate electrode 134 is illustrated, the gate electrode 134 may include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and filling materials.

[0064] As an example for forming a gate structure, one or more gate dielectric layers may be deposited in the recesses 122 and the openings 130. The gate dielectric layers may also be deposited on the top surfaces of the gate spacers 92 and the ILD mask 116 (if present) or the first ILD 114. Subsequently, one or more gate electrode layers may be deposited on the gate dielectric layers and in the remaining portions of the recesses 122 and the openings 130. A removal process may then be performed to remove the excess portions of the gate dielectric layers and the gate electrode layers, the excess portions being above the top surfaces of the gate spacers 92 and the ILD mask 116 (if present) or the first ILD 114. In some embodiments, a planarization process such as chemical mechanical polish (CMP), an etch-back process, a combination thereof, or the like may be utilized. The gate dielectric layers have remaining portions in the recesses 122 and the openings 130 after the removal process (thus forming the gate dielectric 132). The gate electrode layers have remaining portions in the recesses 122 and the openings 130 after the removal process (thus forming the gate electrodes 134). When a planarization process is utilized, the top surfaces of the gate spacers 92, the ILD mask 116 (if present) or the first ILD 114, the gate dielectric 132, and the gate electrodes 134 are substantially coplanar (within process variations).

[0065] In FIGS. 20A to 20B, a second ILD 144 is deposited over the gate spacers 92, the ILD mask 116 (if present) or the first ILD 114, the gate dielectric 132, and the gate electrodes 134. In some embodiments, the second ILD 144 is a flowable film formed by a flowable CVD process. In some embodiments, the second ILD 144 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, which may be formed by any suitable deposition method such as CVD, PECVD, or the like.

[0066] In some embodiments, an etch stop layer (ESL) 142 is formed between the second ILD 144 and the gate spacers 92, the ILD mask 116 (if present) or the first ILD 114, the gate dielectric 132, and the gate electrodes 134. The ESL 142 may be formed of a dielectric material having a high etch selectivity for etching the dielectric material of the second ILD 144, such as silicon nitride, silicon oxynitride, or the like, and the second ILD 144 may be formed by any suitable deposition process such as CVD, ALD, or the like.

[0067] The gate contact 146 and the source / drain contact 148 are formed through the second ILD 144 and the first ILD 114 to be electrically coupled to the gate electrode 134 and the epitaxial source / drain region 102 respectively. As an example for forming the gate contact 146 and the source / drain contact 148, the opening for forming the gate contact 146 passes through the second ILD 144 and the ESL 142, and the opening for forming the source / drain contact 148 passes through the second ILD 144, the ESL 142, the ILD mask 116 (if any), the first ILD 114, and the CESL 112. The openings can be formed using acceptable optical lithography and etching techniques. Liners (not separately shown) such as diffusion barrier layers, adhesion layers, or the like, and conductive materials are formed in the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be cobalt, tungsten, copper, copper alloy, indium, gold, aluminum, nickel, or the like. A planarization process such as CMP can be performed to remove excess material from the top surface of the second ILD 144. The remaining liner and conductive material form the gate contact 146 and the source / drain contact 148 in the openings. The gate contact 146 and the source / drain contact 148 can be formed in a unique process or can be formed in the same process. Although shown as having the same cross-section, it should be understood that each of the gate contact 146 and the source / drain contact 148 can be formed with a different cross-section, which can avoid short-circuit connections of the contacts.

[0068] Optionally, a metal-semiconductor alloy region 150 is formed at the interface between the epitaxial source / drain region 102 and the source / drain contact 148. The metal-semiconductor alloy region 150 can be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon-germanium region formed of both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy region 150 can be formed prior to the material of the source / drain contact 148 by depositing a metal in the opening of the source / drain contact 148 and then performing a thermal annealing process. The metal can be any metal such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or their alloys, which can react with the semiconductor material (e.g., silicon, silicon germanium, germanium, etc.) of the epitaxial source / drain region 102 to form a low-resistance metal-semiconductor alloy. The metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like. After the thermal annealing process, a cleaning process such as wet cleaning can be performed to remove any residual metal from the opening of the source / drain contact 148, such as from the surface of the metal-semiconductor alloy region 150. The material of the source / drain contact 148 can then be formed on the metal-semiconductor alloy region 150.

[0069] In the previously described embodiments, the semiconductor layer 56 (see FIG. 2) is patterned to form channel regions in both the n-type region 50N and the p-type region 50P. In another embodiment (not separately shown), different sets of semiconductor layers are patterned to form channel regions in the n-type region 50N and the p-type region 50P. For example, the multilayer stack 52 (previously described with respect to FIG. 2) may include alternating first semiconductor layers and second semiconductor layers formed of a first semiconductor material and a second semiconductor material, respectively. The first nanostructure and the second nanostructure are formed in the multilayer stack 52 by a similar process as previously described with respect to FIG. 3. The first semiconductor material of the first nanostructure may be suitable for p-type devices, while the second semiconductor material of the second nanostructure may be suitable for n-type devices. The etching of the first semiconductor material and the second semiconductor material relative to each other may have a high etch selectivity such that the first nanostructure can be removed without significantly removing the second nanostructure in the n-type region 50N, and the second nanostructure can be removed without significantly removing the first nanostructure in the p-type region 50P. The internal spacer 98 in the n-type region 50N is formed on the sidewalls of the first nanostructure, and the internal spacer 98 in the p-type region 50P is formed on the sidewalls of the second nanostructure by a process similar to that previously described with respect to FIGS. 9A-9B. The gate structure (including the gate dielectric 132 and the gate electrode 134) in the p-type region 50P is formed around the first nanostructure, and the gate structure in the n-type region 50N is formed around the second nanostructure by a process similar to that previously described with respect to FIGS. 14A-19B. Various masking steps can be used to mask and expose appropriate regions when forming the internal spacer 98 and the gate structure.

[0070] FIGS. 21A-21B are views of a nanostructure FET according to some other embodiments. This embodiment is similar to the embodiment of FIGS. 20A-20B, except that there are some amine groups suspended from the top surface of the isolation region 70. Accordingly, a protective layer 128 is formed over and covers those amine groups, which remain suspended and do not react with the protective material of the protective layer 128.

[0071] Other functional groups can be utilized. More generally, any first functional group can be formed to be suspended from the top surface of the upper semiconductor nanostructure 66 and the top surface of the isolation region 70. The processing procedure 124 can then be performed to selectively replace some of the first functional groups by a second functional group. The protective layer 128 can then be formed by a selective deposition process, which preferably attaches to the first functional group and preferably does not attach to the second functional group. Accordingly, replacing at least some of the first functional groups by the second functional group effectively increases the deposition selectivity between the top surface of the upper semiconductor nanostructure 66 and the top surface of the isolation region 70 with respect to the selective deposition process.

[0072] Figures 22A to 23B are views of intermediate stages in manufacturing a nanostructure FET according to some other embodiments. Figures 22A and 23A illustrate cross-sectional views along a cross-section similar to reference cross-section A-A' in Figure 1. Figures 22B and 23B illustrate cross-sectional views along a cross-section similar to reference cross-section B-B' in Figure 1.

[0073] In Figures 22A to 22B, similar steps as those described previously are performed to form the structure of Figures 14A to 14B. In this embodiment, instead of performing process 124, the suppression layer 126 is deposited on the top surface of the upper semiconductor nanostructure 66. The suppression layer 126 covers (e.g., passivates) the hydroxyl groups on the top surface of the upper semiconductor nanostructure 66. The suppression layer 126 can be formed of a dielectric material such as silicon nitride, silicon oxynitride, or the like, and the foregoing dielectric material can be deposited by a selective deposition process such as a selective ALD process, a selective CVD process, or the like. The suppression layer 126 may not be deposited on the isolation region 70.

[0074] In Figures 23A to 23B, a protective layer 128 is formed on the top surface of the isolation region 70. The protective layer 128 is formed by selectively depositing a protective material on the top surface of the isolation region 70 in a manner similar to that described previously for Figures 16A to 16B. The top surface of the suppression layer 126 may be substantially free of hydroxyl groups, and thus the selective deposition process used to form the protective material is preferably not the suppression layer 126. Effectively, forming the suppression layer 126 increases the deposition selectivity between the top surface of the upper semiconductor nanostructure 66 and the top surface of the isolation region 70 relative to the selective deposition process. The protective layer 128 may not be deposited on the suppression layer 126.

[0075] Subsequently, similar steps as those described previously are performed to complete the manufacture of the nanostructure FET. The suppression layer 126 can be removed before the gate structure is formed around the semiconductor nanostructure 66. The suppression layer 126 can be removed by any acceptable etching process (such as dry etching and / or wet etching), and the acceptable etching process selectively etches the material of the suppression layer 126 at a faster rate compared to the materials of the semiconductor nanostructure 66 and the protective layer 128. In some embodiments, the suppression layer 126 is removed by the same etching process used to remove the remaining portion of the dummy nanostructure 64 (previously for Figures 17A to 17B). In some embodiments, the suppression layer 126 is removed by a separate etching process that is performed after the etching process used to remove the remaining portion of the dummy nanostructure 64.

[0076] Embodiments can achieve multiple advantages. Forming a hanging amine or inhibitory layer 126 on the top surface of the upper semiconductor nanostructure 66 increases the selectivity for selectively depositing the protective layer 128. Specifically, the hanging amine or inhibitory layer 126 inhibits the deposition of the protective layer 128 on the top surface of the upper semiconductor nanostructure 66. Thus, the top surface of the upper semiconductor nanostructure 66 can be more easily exposed in subsequent processing before the gate structure is formed around the semiconductor nanostructure 66. Over-etching of the semiconductor nanostructure 66 can thus be avoided, improving device reliability.

[0077] In one embodiment, a method includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing the deposition selectivity between the top surface of the semiconductor nanostructure and the top surface of the isolation region relative to a selective deposition process; depositing a protective layer on the top surface of the isolation region by performing the selective deposition process; removing the dummy nanostructure by selectively etching the dummy material of the dummy nanostructure at a faster rate compared to the protective material of the protective layer; and forming a gate structure around the semiconductor nanostructure. In some embodiments of the method, multiple hydroxyl groups hang from the top surface of the semiconductor nanostructure and from the top surface of the isolation region, and increasing the deposition selectivity between the top surface of the semiconductor nanostructure and the top surface of the isolation region includes: replacing these hydroxyl groups hanging from the top surface of the semiconductor nanostructure with multiple amine groups. In some embodiments of the method, replacing these hydroxyl groups includes: immersing the semiconductor nanostructure in a nitrogen-containing gas without generating plasma. In some embodiments of the method, replacing these hydroxyl groups includes: bombarding the semiconductor nanostructure with multiple nitrogen-containing ions. In some embodiments of the method, increasing the deposition selectivity between the top surface of the semiconductor nanostructure and the top surface of the isolation region includes: depositing an inhibitory layer on the top surface of the semiconductor nanostructure. In some embodiments of the method, multiple hydroxyl groups hang from the top surface of the isolation region, and depositing the protective layer includes: immersing the isolation region in a silicon carbon precursor that adsorbs onto the oxygen atoms of these hydroxyl groups. In some embodiments of the method, the dummy nanostructure is formed of silicon germanium, the semiconductor nanostructure is formed of silicon, the protective layer is formed of silicon carbonitride oxide, and removing the dummy nanostructure includes: etching the dummy nanostructure with tetramethylammonium hydroxide or ammonium hydroxide. In some embodiments of the method, the dummy nanostructure is formed of silicon oxide, the semiconductor nanostructure is formed of silicon, the protective layer is formed of silicon carbonitride oxide, and removing the dummy nanostructure includes etching the dummy nanostructure with diluted hydrofluoric acid.

[0078] In one embodiment, a method includes: exposing a semiconductor nanostructure and an isolation region by removing a dummy gate, wherein a plurality of hydroxyl groups are suspended from a top surface of the semiconductor nanostructure and from a top surface of the isolation region; performing a processing process to selectively replace some of these hydroxyl groups by a plurality of amino groups suspended from the top surface of the semiconductor nanostructure; depositing a protective layer on the top surface of the isolation region using a silicon carbide precursor, the silicon carbide precursor reacting with these hydroxyl groups and not reacting with these amino groups, the top surface of the semiconductor nanostructure being substantially carbon-free after the protective layer is deposited; and removing these amino groups suspended from the top surface of the semiconductor nanostructure. In some embodiments of the method, the processing process includes: soaking the semiconductor nanostructure in ammonia or nitrogen without generating plasma. In some embodiments of the method, the processing process includes: bombarding the semiconductor nanostructure with nitrogen positive ions or nitrogen ions. In some embodiments of the method, the top surface of the isolation region is substantially amino-group-free after the processing process. In some embodiments of the method, a plurality of amino groups are suspended from the top surface of the isolation region after the processing process. In some embodiments of the method, the silicon carbide precursor is bis(tert-butylamino)silane or bis(diethylamino)silane.

[0079] In one embodiment, a device includes: a source / drain region; a semiconductor nanostructure adjacent to the source / drain region; an isolation region adjacent to the semiconductor nanostructure, the isolation region including a first dielectric material; a protective layer on the isolation region, the protective layer including a second dielectric material, the second dielectric material including more carbon than the first dielectric material; a gate structure on the protective layer and surrounding the semiconductor nanostructure; and a spacer between the gate structure and the source / drain region, the spacer electrically isolating the gate structure from the source / drain region, the spacer physically contacting the semiconductor nanostructure. In some embodiments of the device, the second dielectric material is silicon carbonitride or silicon carbon nitride. In some embodiments of the device, the second dielectric material is doped with hydrogen. In some embodiments of the device, the protective layer is on the top surface of the isolation region, and the top surface of the isolation region is substantially amino-group-free. In some embodiments of the device, the protective layer is on the top surface of the isolation region, and a plurality of amino groups are suspended from the top surface of the isolation region. In some embodiments of the device, the second dielectric material has a carbon-to-silicon ratio in the range of 0.3 to 0.5.

[0080] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made herein without departing from the spirit and scope of the present disclosure.

[0081] 50: Substrate 50N: n-type region 50P: p-type region 52: Multilayer stack 54: dummy layer 56: Semiconductor layer 62: Semiconductor fin 64: Nanostructure 66: Nanostructure 68: Insulating material 70: Isolation region 72: Dummy dielectric layer 74: Dummy gate layer 76: Mask layer 82: Dummy dielectric 84: Dummy gate 86: Mask 92: Gate spacer 94: Fin spacer 96: Source / drain recess 98: Inner spacer 102: Epitaxial source / drain region 112: Contact etch stop layer (CESL) 114: First interlayer dielectric (ILD) 116: Interlayer dielectric (ILD) mask 122: Etching process 124: Processing process 126: Inhibiting layer 128: Protection layer 130: Opening 132: Gate dielectric 134: Gate electrode 142: Etch stop layer (ESL) 144: Second interlayer dielectric (ILD) 146: Gate contact 148: Source / Drain Contact 150: Metal-Semiconductor Alloy Region

[0082] Domestic Deposited Information (Please note in the order of depository institution, date, and number) None Overseas Deposited Information (Please note in the order of depositing country, institution, date, and number) None

Claims

1. A method for manufacturing nanostructured field-effect transistors, comprising: By removing a dummy gate, a semiconductor nanostructure, a dummy nanostructure, and an isolation region are exposed; The selective deposition process increases the deposition selectivity between a top surface of the semiconductor nanostructure and a top surface of the isolation region; a protective layer is deposited on the top surface of the isolation region by performing the selective deposition process; the dummy nanostructure is removed by selectively etching a dummy material of the dummy nanostructure at a faster rate than a protective material of the protective layer; and a gate structure is formed around the semiconductor nanostructure.

2. The method as described in claim 1, wherein a plurality of hydroxyl groups are suspended from the top surface of the semiconductor nanostructure and from the top surface of the isolation region, and increasing the deposition selectivity between the top surface of the semiconductor nanostructure and the top surface of the isolation region includes: The hydroxyl groups suspended on the top surface of the semiconductor nanostructure are replaced by multiple amine groups.

3. The method as described in claim 1, wherein increasing the deposition selectivity between the top surface of the semiconductor nanostructure and the top surface of the isolation region includes: An inhibition layer is deposited on the top surface of the semiconductor nanostructure.

4. The method as described in claim 1, wherein a plurality of hydroxyl groups are suspended from the top surface of the isolation region, and the deposition of the protective layer comprises: The isolation zone was immersed in a silicon-carbon precursor, which adsorbed onto the oxygen atoms of the hydroxyl groups.

5. A method for manufacturing nanostructured field-effect transistors, comprising: A semiconductor nanostructure and an isolation region are exposed by removing a dummy gate, wherein a plurality of hydroxyl groups are suspended from a top surface of the semiconductor nanostructure and from a top surface of the isolation region; a processing step is performed to selectively replace some of the hydroxyl groups by a plurality of amine groups suspended from the top surface of the semiconductor nanostructure; a protective layer is deposited on the top surface of the isolation region using a silicon-carbon precursor, the silicon-carbon precursor reacting with the hydroxyl groups but not with the amine groups, the top surface of the semiconductor nanostructure being substantially carbon-free after the protective layer is deposited; and the amine groups suspended from the top surface of the semiconductor nanostructure are removed.

6. The method as described in claim 5, wherein the processing procedure includes: The semiconductor nanostructure was immersed in ammonia or nitrogen gas without generating a plasma.

7. The method as described in claim 5, wherein the processing procedure includes: The semiconductor nanostructure is bombarded with nitrogen positive ions or nitrogen ions.

8. A nanostructured field-effect transistor, comprising: A source / drain region; a semiconductor nanostructure adjacent to the source / drain region; an isolation region adjacent to the semiconductor nanostructure, the isolation region including a first dielectric material; a protective layer on the isolation region and in direct contact with a top surface of the isolation region, the protective layer including a second dielectric material, the second dielectric material including more carbon than the first dielectric material; a gate structure on the protective layer and surrounding the semiconductor nanostructure; and a spacer between the gate structure and the source / drain region, the spacer electrically isolating the gate structure from the source / drain region, the spacer physically contacting the semiconductor nanostructure.

9. The nanostructured field-effect transistor as described in claim 8, wherein the top surface of the isolation region is substantially free of amine groups.

10. The nanostructured field-effect transistor as described in claim 8, wherein a plurality of amine groups are suspended from the top surface of the isolation region.

Images