Semiconductor devices

Abstract

A semiconductor device is provided. In one example, the semiconductor device includes: a substrate, a first circuit region and a second circuit region extending along a first direction, and a gate structure extending along a second direction substantially perpendicular to the first direction. The gate structure further includes: two gate electrode portions respectively located in the first and second circuit regions, and a low-resistance portion located between the two gate electrode portions and interconnecting the two gate electrode portions. The two gate electrode portions are configured to serve as gate electrodes of two transistors located in the first and second circuit regions, respectively. The two gate electrodes have a first width (W0) along the first direction, the low-resistance portion has a second width (W) along the first direction, and the ratio of W to W0 (W / W0) is at least 1.1.

Description

Technical Field

[0001] The embodiments disclosed herein generally relate to semiconductor devices, and more specifically, to field-effect transistor (FET) devices. Prior Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous advancements in the integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, this increase in integration density is driven by the continuous reduction in the minimum feature size, allowing more components to be integrated into a given area. Therefore, there is a constant need to improve the performance of semiconductor devices. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] When read in conjunction with the accompanying drawings, the following detailed description is the best way to understand the nature of this disclosure. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In practice, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1A is a top view schematic diagram of the layout of a semiconductor device according to some embodiments; Figure 1B illustrates a schematic cross-sectional view of a semiconductor device according to Figure 1A based on some embodiments; Figure 1C illustrates a schematic cross-sectional view of a semiconductor device according to Figure 1A according to some embodiments; Figure 1D illustrates a top view of the layout of another semiconductor device according to some embodiments; Figure 1E illustrates a schematic cross-sectional view of a semiconductor device according to Figure 1D based on some embodiments; Figure 1F illustrates a top view of the layout of another semiconductor device according to some embodiments; Figure 1G illustrates a schematic cross-sectional view of a semiconductor device according to Figure 1F of some embodiments; Figure 2A illustrates a top view of the layout of another semiconductor device according to some embodiments; Figure 2B illustrates a top view of the layout of yet another semiconductor device according to some embodiments; Figure 2C illustrates a top view of the layout of another semiconductor device according to some embodiments; Figure 2D illustrates a top view of the layout of a further semiconductor device according to some embodiments; Figure 3 illustrates a top view of the layout of another semiconductor device according to some embodiments; and Figure 4 illustrates a top view of the layout of another semiconductor device according to some embodiments. Implementation

[0005] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Additionally, for ease of description, spatial relative terms (e.g., "below," "under," "bottom," "overlapping," "upper," and similar terms) may be used herein to describe the relationship between one component or feature and another illustrated in the figures. Besides the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or positioned in other orientations), and thus the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] Additionally, the source / drain region may refer to the source or drain individually or jointly, depending on the context. For example, the device may include a first source / drain region and a second source / drain region, as well as other components. The first source / drain region may be a source region, and the second source / drain region may be a drain region, or vice versa. Various variations, modifications, and substitutions of the embodiments disclosed herein will be understood by those skilled in the art.

[0008] This disclosure describes several embodiments. Additional steps may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be replaced or omitted. Some features described below may be replaced or omitted, and additional features may be added for different embodiments. Although some embodiments are discussed through steps performed in a particular order, these operations may be performed in an alternative logical order.

[0009] Overview

[0010] In recent developments of semiconductor devices, particularly those with multiple active regions and transistors, gate connectors are frequently used to interconnect the gate electrodes of transistors in different active regions. According to some embodiments disclosed herein, a gate structure may have two gate electrode portions and an intermediate portion connecting the two gate electrode portions. The two gate electrode portions can serve as the two gate electrodes of two different transistors in the semiconductor device. Typically, the gate structure is homogeneous. In other words, the gate electrode portions and the intermediate portion are composed of the same material. A typical material for a homogeneous gate structure is a work function metal, which typically has a high resistivity. At least to some extent, due to the high resistivity of the intermediate portion, the overall resistance of a homogeneous gate structure can be very high. This high resistance can lead to numerous problems, such as overheating in the semiconductor device, poor power dissipation, and low durability of functional components.

[0011] Furthermore, according to some embodiments disclosed herein, an inter-layer dielectric (ILD) layer is typically formed around a gate structure and other conductive elements in a semiconductor device. Prior art ILD layers are typically homogeneous in composition and consist of a dielectric material (e.g., silicon dioxide) with a relatively high dielectric constant. At least to some extent, because the ILD layer fills the gap between the gate structure and another conductive element adjacent to the gate structure, parasitic capacitance may be generated between the gate structure and the other conductive element adjacent to the gate structure. Parasitic capacitance is quite detrimental and can also interfere with nearby transistors and / or cause problems with the normal functioning of active elements.

[0012] This disclosure provides techniques to address the aforementioned challenges. One embodiment provided in this disclosure relates to a novel heterogeneous gate structure having a low-resistance portion connecting two gate electrode portions. According to some embodiments, the low-resistance portion of the heterogeneous gate structure can have a larger width or cross-sectional area than the gate electrode portions. Compared to prior art homogeneous gate structures, the overall resistance of the heterogeneous gate structure can be significantly reduced due to the increased size of the low-resistance portion. According to some embodiments, the low-resistivity portion of the heterogeneous gate structure can be composed of a low-resistivity material, and this low-resistivity material is different from the material of the gate electrode portions. The low-resistivity material can also contribute to reducing the resistance of the heterogeneous gate structure. According to some embodiments, the low-resistivity portion can simultaneously possess the characteristics of increased size and low-resistivity material. According to some embodiments, a semiconductor device can include multiple heterogeneous gate structures having low-resistivity portions. Furthermore, multiple low-resistivity portions can significantly reduce overall power consumption and improve the performance of the semiconductor device.

[0013] Another embodiment provided in this disclosure is a heterogeneous interlayer dielectric (ILD) layer with different ILD structures surrounding different portions of a heterogeneous gate structure in a semiconductor device. According to some embodiments, the heterogeneous ILD layer includes a first ILD structure surrounding a gate electrode portion and a second ILD structure surrounding a low-resistance portion. Compared to the first ILD structure, the second ILD structure may be composed of a dielectric material having a relatively low dielectric constant and / or a relatively high dielectric strength. The second ILD structure may fill the gap between two adjacent low-resistance portions, or fill the gap between a low-resistance portion and another conductive element (e.g., a metal contact) adjacent to that low-resistance portion. Therefore, parasitic capacitance between two adjacent low-resistance portions or between a low-resistance portion and another conductive element can be significantly reduced. Furthermore, due to the relatively high dielectric strength of the second ILD structure, the risk of dielectric breakdown between the low-resistance portion and another conductive element can be reduced or prevented.

[0014] Exemplary semiconductor device with heterogeneous gate structure

[0015] Figure 1A is a top view of the layout of a semiconductor device 100A according to some embodiments. Figure 1B is a cross-sectional view of the semiconductor device 100A along an imaginary line 110 of section AA' in a first direction (i.e., the latitudinal direction or the X direction). Figure 1C is a cross-sectional view of the semiconductor device 100A along an imaginary line 120 of section BB' in a second direction (i.e., the longitudinal direction or the Y direction). In the example shown, the layout of the semiconductor device 100A includes, in addition to other components or elements, a substrate 101, a plurality of active regions including a first active region 111 and a second active region 112, at least two transistors 125 and 126, and at least one heterogeneous gate structure 103 having a low-resistance portion 140. The term "low-resistance portion" as used in this disclosure also refers to a "low-resistance connector," a "low-resistance gate connector," a "low-resistance gate connector portion," or an equivalent thereof.

[0016] Various components or elements of the semiconductor device 100A are formed on the substrate 101. The elements of the semiconductor device 100A include active elements and / or passive elements. In at least one embodiment, active elements are disposed in a circuit region or transistor region of the semiconductor device for the purpose of providing one or more functions and / or operations performed by the semiconductor device. In at least one embodiment, the semiconductor device 100A further includes a non-circuit region, such as a sealing region, which extends around and protects the circuit region. Examples of active elements include, but are not limited to, transistors and diodes. Figure 1A of this disclosure illustrates examples with respect to transistors 125 and 126. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, and resistors. Multiple metal layers and via layers are alternately formed over the substrate 101 to electrically couple the elements of the semiconductor device 100A to each other and / or to external devices. In at least one embodiment, the substrate 101 comprises a silicon substrate. In at least one embodiment, substrate 101 comprises silicon germanium (SiGe), gallium arsenide, p-type doped Si, n-type doped Si, or a suitable semiconductor material. For example, within the scope of various embodiments, semiconductor materials comprising group III, IV, and V elements are included. In some embodiments, substrate 101 further includes one or more other features, such as various doped regions, buried layers, and / or epitaxial (epitaxy) layers. In some embodiments, substrate 101 comprises semiconductor-on-insulator, such as silicon-on-insulator (SOI). In some embodiments, substrate 101 includes a doped epi layer, a gradient semiconductor layer, and / or a semiconductor layer covering another type of semiconductor layer (e.g., a silicon layer on a silicon germanium layer).

[0017] Active regions 111 and 112 extend along the X direction of the layout of semiconductor device 100A. In some embodiments, active regions 111 and 112 are also referred to as oxide-definition (OD) regions. Exemplary materials for active regions 111 and 112 include, but are not limited to, semiconductor materials doped with various types of p-dopers and / or n-dopers. In at least one embodiment, active regions 111 and 112 comprise the same type of dopant. In at least one embodiment, one of active regions 111 and 112 comprises a type of dopant different from the dopant type of the other active region 111 and 112. Active regions 111 and 112 may be isolated from each other by one or more gate isolation portions as described in this disclosure. In some embodiments, active regions 111 and 112 are located within respective well regions. For example, in one or more embodiments, active region 111 may be located within well region 113, and well region 113 is an n-well region, while in one or more embodiments, active region 112 is located within well region 114, and well region 114 is a p-well region. The described conductive well regions 113 and 114 are exemplary. Other configurations are also within the scope of various embodiments.

[0018] The n-well region 113 and p-well region 114 are located on opposite sides of the imaginary line 110 and can divide the semiconductor device 100A into separate regions for different types of devices or transistors. Examples of transistors include, but are not limited to, metal oxide semiconductor field-effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with raised source / drain layers, gate-all-around (GAA) transistors, or nanosheet transistors. In the examples shown in Figures 1A to 1C, the n-well region 113 is the region for forming a p-channel metal-oxide semiconductor (PMOS) transistor, while the p-well region 114 is the region for forming an n-channel metal-oxide semiconductor (NMOS) transistor. The first active region 111 and the second active region 112 each include a first circuit region 121 and a second circuit region 122, and both the first circuit region 121 and the second circuit region 122 extend along the X direction. The first circuit region 121 and the second circuit region 122 further each include at least one transistor. In the example shown, the first circuit region 121 includes a first transistor 125, and the second circuit region 122 includes a second transistor 126.

[0019] As shown in Figures 1A and 1C, the first transistor 125 includes a first gate electrode 117, a channel region 131, and two S / D regions 127a and 127b. The first gate electrode 117 is a portion (e.g., a section or part) of the gate structure 103 located in the first circuit region 121. For convenience, the term "gate electrode" of the transistor used in this disclosure is also referred to as the "gate electrode portion" connected to the gate structure of the transistor. The first gate electrode 117 is disposed on and in contact with the channel region 131. The two S / D regions 127a and 127b are formed on opposite sides of the first gate electrode 117 and connected to the channel region 131. The gate electrode 117 further includes a gate dielectric layer 133 and a gate metal layer 135. The gate dielectric layer 133 is directly coupled to the channel region 131, while the gate metal layer 135 is disposed on the gate dielectric layer 133. Similarly, the second transistor 126 includes a second gate electrode 118, a channel region 132, and two S / D regions 128a and 128b. The second gate electrode 118 is part of a gate structure 103 located in the second circuit region 122. The second gate electrode 118 is disposed on and in contact with the channel region 132. The two S / D regions 128a and 128b respectively form opposite sides of the second gate electrode 118 and are connected to the channel region 132. The gate electrodes 117 and 118 have a width W0, where W0 refers to the distance between opposite sides along the X direction.

[0020] The second gate electrode 118 further includes a gate dielectric layer 134 and a gate metal layer 136. The gate dielectric layer 134 is directly coupled to the channel region 132, while the gate metal layer 136 is disposed on the gate dielectric layer 134. Exemplary materials for the gate metal layers 135 and 136 include metals or polycrystalline silicon. In some embodiments, the metals of the gate electrodes 117 and 118 may be work function metals, such as tungsten (W), titanium nitride (TiN), titanium oxide (TiO), nickel silicon (NiSi), cobalt silicon (CoSi), hafnium (Hf), zirconium (Zr), aluminum (Al), and tantalum oxide (TaO). Other materials are also within the scope of various embodiments. In some embodiments, the metals of the gate electrodes 117 and 118 have relatively high resistivity, for example, at least 30 µΩ·cm, at least 50 µΩ·cm, or at least 80 µΩ·cm. Non-limiting examples of gate dielectric layers 133 and 134 include silicon dioxide, hafnium dioxide, aluminum oxide, and silicon oxynitride (SiON). In some embodiments, the first transistor 125 and the second transistor 126 are substantially aligned in the Y direction. In some embodiments, two or more transistors are formed in the first circuit region 121 and the second circuit region 122, respectively.

[0021] In some embodiments, two spacers (not shown) are formed and disposed along the side (or boundary) of the gate structure 103. The spacers may also be disposed on opposite sides of the gate electrodes 117 and 118, i.e., on opposite sides of the low-resistance portion 140. The spacers may include one or more dielectric materials for electrically isolating them from the corresponding gate electrodes and preventing unintended electrical contact. Exemplary dielectric materials for the spacers include, but are not limited to, silicon nitride, silicon oxynitride, and silicon carbide. In at least one embodiment, one or more spacers have a tapered profile.

[0022] In some embodiments, the first transistor 125 and the second transistor 126 are FinFETs. For example, a first fin 161 and a second fin 162 (as shown in Figure 1A) may be formed in a first circuit region 121 and a second circuit region 122, respectively. Fins 161 and 162 may extend in the X direction. A gate structure 103 may interconnect fins 161 and 162. A channel region 131 and two S / D regions 127a and 127b may be formed in the first fin 161, while a channel region 132 and two S / D regions 128a and 128b may be formed in the second fin 162. In some embodiments, two or more fins may be formed in the first circuit region 121 and the second circuit region 122, respectively, and the resulting FinFET may be a multiple-fin (MF-FinFET). The configuration described in this disclosure is an example, and other configurations are also within the scope of various embodiments. For example, in one or more embodiments, transistors 125 and 126 may be GAA transistors comprising nanowires or nanosheets surrounded by gate electrodes, and channel regions and S / D regions are formed on the respective nanowires or nanosheets.

[0023] One or more shallow trench isolation (STI) structures 102 are formed on substrate 101. Exemplary materials for the STI structure 102 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric materials, and / or combinations thereof. In one example, the formation of the STI structure 102 includes filling the trenches between the fins with a dielectric material, for example, by a chemical vapor deposition (CVD) process. In some embodiments, the filled trenches have a multilayer structure, for example, filled with a thermal oxide liner layer of silicon nitride or silicon oxide.

[0024] Semiconductor device 100A further includes an interlayer dielectric (ILD) layer located above the STI. In the configuration shown in Figures 1A to 1B, semiconductor device 100A includes an interlayer dielectric (ILD) layer 107 above the STI structure 102. Exemplary materials for the ILD layer 107 include, but are not limited to, SiNx, SiOx, SiON, SiC, SiBN, SiCBN, or combinations thereof. In some embodiments, the composition of the ILD layer 107 is homogeneous and consists of a material having a relatively high dielectric constant and / or a relatively low dielectric strength. In some embodiments, the ILD layer 107 includes a dielectric material with a dielectric constant of 2 to 9, 3 to 8, or 4 to 7. In some embodiments, the ILD layer 107 includes a dielectric material with a dielectric strength of 0.001 V / µm to 0.02 V / µm, 0.005 V / µm to 0.015 V / µm, or 0.005 V / µm to 0.01 V / µm. In other embodiments, the composition of the ILD layer 107 is heterogeneous and may be composed of different materials surrounding different elements of the semiconductor device (e.g., the example shown in Figure 1F). In some embodiments, the ILD layer 107 is embedded in a gate structure 103. The ILD layer 107 is also embedded in a first circuit region 121 and a second circuit region 122 of the active regions 111 and 112.

[0025] The semiconductor device 100A may further include one or more through-hole contacts, and the through-hole contacts are disposed on the gate structure 103. As shown in Figure 1A, the through-hole contact 151 may be disposed on the low-resistance portion 140. The through-hole contact 151 allows electrical connection between different layers or regions in the semiconductor device 100A.

[0026] Gate structure 103 extends along the Y direction and spans active regions 111 and 112. Gate structure 103 may include a plurality of gate electrodes, which are separated and isolated by a low-resistance portion 140. For example, gate structure 103 may include a first gate electrode 117 and a second gate electrode 118. As mentioned above, the first gate electrode 117 or a portion thereof is located in the first circuit region 121, and the first gate electrode 117 or that portion thereof constitutes part of the first transistor 125. Similarly, the second gate electrode 118 or a portion thereof is located in the second circuit region 122, and the second gate electrode 118 or that portion thereof constitutes part of the second transistor 126.

[0027] In the gate structure 103 of Figure 1A, a low-resistance portion 140 is located between the first gate electrode 117 and the second gate electrode 118, thus separating and isolating the first gate electrode 117 and the second gate electrode 118. In some embodiments, the low-resistance portion 140 extends across the boundary between the first active region 111 and the second active region 112. The low-resistance portion 140 extends along the Y direction from the first end (or the top end of Figure 1A) 143 to the second end (or the bottom end of Figure 1A) 144, and along the X direction from the first side (or the first boundary) 141 to the second side (or the second boundary) 142. The length of the low-resistance portion 140 refers to the distance between the first end 143 and the second end 144 in the Y direction, while the width W refers to the distance between the first side 141 and the second side 142 in the X direction. The low-resistance portion 140 is at a distance D1 from the interconnected transistors 125 / 126, and the distance D1 refers to the distance between the first end 143 and the S / D regions 127a / 127b of the first transistor 125, or the distance between the second end 144 and the S / D regions 128a or 128b of the second transistor 126.

[0028] In the example illustrated in Figure 1, the width (W) of the low-resistance portion 140 is greater than the width W0 of the gate electrodes 117 and 118. In some embodiments, the width W is at least 10% larger than the width W0. In some embodiments, the ratio of width W to width W0 (W / W0) is at least 2, at least 3, at least 4, or at least 5. In some embodiments, W / W0 is equal to or less than 5. In some embodiments, W / W0 is between 1.1 and 5. In some embodiments, the ratio of length L to width W0 (L / W0) is at least 5, at least 10, or at least 20. In some embodiments, the ratio of D1 to W0 (D1 / W0) is at least 2, at least 3, or at least 5. The minimum distance between the low-resistance portion and the interconnected transistors minimizes interference to the transistors and ensures the proper functioning of the transistor's gate electrodes.

[0029] As described above, the low-resistance portion 140 and gate electrodes 117 and 118 are components of the gate structure 103. In some embodiments, the low-resistance portion 140 is composed of the same or similar material as the gate electrodes 117 and 118. However, due to the larger width of the low-resistance portion 140, its cross-sectional dimension (i.e., cross-sectional area in the XZ plane) is larger than that of the first gate electrode 117 and the second gate electrode 118. Therefore, the resistance of the heterogeneous gate structure 103 having the low-resistance portion 140 can be significantly reduced compared to a homogeneous gate structure without the low-resistance portion 140 between the two gate electrodes. In some embodiments, the resistance of the heterogeneous gate structure 103 having the low-resistance portion 140 has a resistance reduction rate compared to a homogeneous gate structure without the low-resistance portion 140, and the resistance reduction rate is at least 10%, at least 23%, at least 30%, at least 40%, at least 50%, or at least 75%.

[0030] Figure 1D is a top view of the layout of a semiconductor device 100D according to some embodiments. Figure 1E is a cross-sectional view of the semiconductor device 100D along the imaginary line 120 of section BB' in the Y direction. Semiconductor device 100D is an approximate variant of semiconductor device 100A. In the examples shown in Figures 1D to 1E, the low-resistivity portion 140 of semiconductor device 100D comprises a material different from the materials of gate electrodes 117 and 118. The low-resistivity portion 140 may be composed of a low-resistivity material, such as a metal, metal alloy, or metal compound. Non-limiting examples of low-resistivity materials include gold (Au), silver (Ag), rhodium (Rh), tungsten (W), molybdenum (Mo), zinc (Zn), cobalt (Co), ruthenium (Ru), niobium (Nb), titanium (Ti), zirconium (Zr), brass, titanium nitride (TiN), phosphor bronze, and cast steel. Other materials with relatively low resistivity are also within the scope of the embodiments disclosed herein.

[0031] In some embodiments, gate electrodes 117 and 118 are composed of a first material, and the low-resistance portion 140 is composed of a second material, which is different from the first material. In some embodiments, the first material has a first resistivity, the second material has a second resistivity, and the second resistivity is less than the first resistivity. In some embodiments, the second resistivity is less than 100 μΩ·cm, less than 50 μΩ·cm, less than 30 μΩ·cm, or less than 10 μΩ·cm.

[0032] In the example of Figure 1D, the low-resistivity portion 140 has an enlarged cross-sectional dimension and is made of a low-resistivity material. Therefore, the overall resistance of the gate structure 103 can be reduced to a greater extent compared to a conventional gate structure without the low-resistivity portion 140.

[0033] Figure 1F illustrates a top view of the layout of another semiconductor device 100F according to some embodiments. Figure 1G is a cross-sectional view of the semiconductor device 100F along an imaginary line 110 of section AA' in the X direction. Semiconductor device 100F is an approximate variant of semiconductor devices 100A and 100D. In the examples shown in Figures 1F to 1G, ILD layer 107 is heterogeneous, and ILD layer 107 further includes a first ILD structure 108 and a second ILD structure 109. A first gate electrode 117 and a second gate electrode 118 are respectively surrounded by the first ILD structure 108, that is, the first ILD structure 108 isolates the first gate electrode 117 and the second gate electrode 118 from other conductive elements in semiconductor device 100F, respectively. A low-resistance portion 140 is surrounded by the second ILD structure 109, that is, the second ILD structure 109 isolates the low-resistance portion 140 from other conductive elements in semiconductor device 100F. As described above, the first ILD structure 108 may be composed of silicon dioxide. The second ILD structure 109 may be composed of a material different from that of the first ILD structure 108. In some embodiments, the second ILD structure 109 includes a material having a relatively low dielectric constant (κ) and / or a relatively high dielectric strength. Non-limiting examples of materials for the second ILD structure 109 include fluorine-doped silicon dioxide, carbon-doped silicon dioxide, organosilicon glass, porous silicon dioxide, fused silicon dioxide, mica, polyethylene, alumina, borosilicate glass, and air gaps, etc.

[0034] In some embodiments, the first ILD structure 108 has a first dielectric constant and a first dielectric strength, while the second ILD structure 109 has a second dielectric constant and a second dielectric strength. In some embodiments, the second dielectric constant is lower than the first dielectric constant. In some embodiments, the second dielectric strength is higher than the first dielectric constant. In some embodiments, the second dielectric constant is lower than the dielectric constant of silicon dioxide. In some embodiments, the second dielectric constant is less than 4, less than 3.9, less than 3, or less than 2. In some embodiments, the second dielectric strength is greater than 0.001 V / μm, greater than 1 V / μm, greater than 10 V / μm, or greater than 100 V / μm or greater than 400 V / μm. The low dielectric constant and / or high dielectric strength of the second ILD structure 109 surrounding the low-resistance portion 140 can help reduce or prevent parasitic capacitance between the low-resistance portion 140 and another conductive element (e.g., another low-resistance element) adjacent to or near the resistive portion or metal contact of the low-resistance portion 140. Therefore, the combination of the low dielectric constant of the second ILD structure 109 and the low resistivity material of the low resistance portion 140 can further improve the overall performance of the semiconductor device 100F.

[0035] Figure 2A is a top view of the layout of a semiconductor device 200A according to some embodiments. Semiconductor device 200A is an approximate variant of semiconductor device 100A. In the example shown, semiconductor device 200A includes a first transistor 125, a second transistor 126, and a gate structure 203 interconnecting the first and second transistors 125 / 126. Gate structure 203 includes a first gate electrode 117 corresponding to the first transistor 125, a second gate electrode 118 corresponding to the second transistor 126, and a low-resistance portion 240 located between the first gate electrode 117 and the second gate electrode 118. The low-resistance portion 240 has a width W, and this width W is substantially the same as the width W0 of the gate electrodes 117 and 118. In other words, gate structure 203 has a substantially uniform width in the Y direction. However, the low-resistance portion 240 is composed of a material different from that of the gate electrodes 117 and 118. In some embodiments, the material of the low-resistivity portion 240 has a lower resistivity than the materials of the gate electrodes 117 and 118. Compared to a conventional gate structure without the low-resistivity portion 240, the overall resistance of the gate structure 203 can be reduced due to the low-resistivity material of the low-resistivity portion 240.

[0036] Figure 2B is a top view of the layout of a semiconductor device 200B according to some embodiments. Semiconductor device 200B is an approximate variant of semiconductor device 200A. In the illustrated example, similar to semiconductor device 100F, the ILD layer 107 of semiconductor device 200B further includes a first ILD structure 108 and a second ILD structure 109. Gate electrodes 117 and 118 are respectively surrounded by the first ILD structure 108, while the low-resistivity portion 240 is surrounded by the second ILD structure 109. The second ILD structure 109 is composed of a material having a relatively low dielectric constant. In some embodiments, the first ILD structure 108 has a first dielectric constant, while the second ILD structure 109 has a second dielectric constant. The second dielectric constant is lower than the first dielectric constant. The combination of the low dielectric constant of the second ILD structure 109 and the low resistivity material of the low-resistivity portion 240 can further improve the overall performance of semiconductor device 200B.

[0037] Figure 2C is a top view of the layout of a semiconductor device 200C according to some embodiments. Semiconductor device 200C is an approximate variant of semiconductor devices 200A and 200B. In the example shown, semiconductor device 200C further includes metal contacts 250. Metal contacts used in this disclosure are sometimes also referred to as "metal on operation domain" or "MD". Metal contacts 250 extend across the boundary (i.e., line 110) between the first active region 111 and the second active region 112 in the same direction (i.e., the Y direction) as the gate structure 203. Metal contacts 250 are configured to interconnect first and second transistors 125 and 126, and are configured such that the S / D regions below the first and second transistors 125 and 126 are electrically coupled to each other or to other circuitry of semiconductor device 200C. Metal contacts 250 are adjacent to the gate structure 203. In some embodiments, the metal contact 250 is adjacent to an adjacent gate structure 203, and there is a narrow distance D2 between the metal contact 250 and the adjacent gate structure 203. In some embodiments, the ratio of D2 / W0 is no more than 5, no more than 3, no more than 2, or no more than 1. In some embodiments, the ratio of D2 / W0 is 0.5 to 3 or 1 to 2. Because the metal contact 250 and the gate structure 203 are quite close, the low-resistivity portion 240 may not have an enlarged dimension (i.e., W is no greater than W0). However, the overall resistance of the gate structure 203 can still be reduced by using a low-resistivity material in the low-resistivity portion 240.

[0038] In some embodiments, the low-resistance portion 240 is surrounded by a second ILD structure 109, and the second ILD structure 109 is composed of a dielectric material different from that of the first ILD structure 108. As shown in the example of Figure 1F, the dielectric material of the second ILD structure 109 can have a relatively low dielectric constant and a relatively high dielectric strength, which can help reduce or prevent parasitic capacitance between the low-resistance portion 240 and the adjacent metal contact 250. Additionally, the relatively high dielectric strength of the second ILD structure 109 can also effectively prevent dielectric breakdown between the low-resistance portion 240 and the metal contact 250.

[0039] Figure 2D is a top view of the layout of a semiconductor device 200D according to some embodiments. Semiconductor device 200D is an approximate variant of semiconductor device 200C. In the example shown, among other components, semiconductor device 200D further includes a plurality of transistors 125a, 125b, 125c (collectively referred to as transistors 125) located in a first circuit region 221, a plurality of transistors 126a, 126b, 126c (collectively referred to as transistors 126) located in a second circuit region 222, a plurality of gate structures 203a, 203b, 203c (collectively referred to as gate structures 203), and a plurality of metal contacts 250a and 250b (collectively referred to as metal contacts 250).

[0040] Multiple gate structures 203a, 203b, and 203c interconnect transistors 125a and 126a, transistors 125b and 126b, and transistors 125c and 126c, respectively. Gate structure 203a further includes two gate electrodes 117a and 118a and a low-resistance portion 240a located between the two gate electrodes 117a and 118a. Similarly, gate structure 203b further includes two gate electrodes 117b and 118b and a low-resistance portion 240b located between the two gate electrodes 117b and 118b. Furthermore, gate structure 203c further includes two gate electrodes 117c and 118c and a low-resistance portion 240c located between the two gate electrodes 117c and 118c. Gate electrodes 117a, 117b and 117c are collectively referred to as gate electrode 117, and gate electrodes 118a, 118b and 118c are collectively referred to as gate electrode 118.

[0041] Multiple metal contacts 250a and 250b are respectively disposed between gate structures 203a and 203b and between gate structures 203b and 203c. As shown, due to the proximity between each pair of adjacent gate structures 203 (e.g., gate structures 203a and 203b, or gate structures 203b and 203c), the width of the low-resistance portion 240 may be limited so that the metal contacts 250 can be accommodated between two adjacent gate structures 203. In some embodiments, the low-resistance portion 240 may have a width substantially the same as the width of the gate electrodes 117 and 118.

[0042] In the example shown in Figure 2D, the dielectric material of the second ILD structure 109 can have a relatively low dielectric constant and a relatively high dielectric strength, which can help reduce or prevent two low-resistance portions (e.g., low-resistance portions 240a / 240b) and the metal contact (e.g., metal contact 250a) disposed between the two low-resistance portions.

[0043] Figure 3 is a top view of the layout of a semiconductor device 300 according to some embodiments. Semiconductor device 300 is an approximate variation of semiconductor devices 100A, 100D, and 100F. In the example shown, among other components, semiconductor device 300 further includes a plurality of transistors 125a, 125b, 125c, and 125d (collectively referred to as transistors 125) located in a first circuit region 321, a plurality of transistors 126a, 126b, 126c, and 126d (collectively referred to as transistors 126) located in a second circuit region 322, and a plurality of gate structures 103a, 103b, 103c, and 103d (collectively referred to as gate structures 103). For simplicity, some components, such as spacers and via contacts, are not shown in Figure 3. It should be noted that the number of gate structures 103 can vary according to design requirements.

[0044] Multiple gate structures 103a, 103b, 103c, and 103d extend in the Y direction and interconnect transistors 125a and 126a, transistors 125b and 126b, transistors 125c and 126c, and transistors 125d and 126d, respectively. Gate structure 103a further includes two gate electrodes 117a and 118a and a low-resistance portion 140a located between the two gate electrodes 117a and 118a. Similarly, gate structure 103b further includes two gate electrodes 117b and 118b and a low-resistance portion 140b located between the two gate electrodes 117b and 118b. Gate structure 103c further includes two gate electrodes 117c and 118c and a low-resistance portion 140c located between the two gate electrodes 117c and 118c. The gate structure 103d further includes two gate electrodes 117d and 118d and a low-resistance portion 140d located between the two gate electrodes 117d and 118d. Gate electrodes 117a, 117b, 117c, and 117d are collectively referred to as gate electrodes 117. Gate electrodes 118a, 118b, 118c, and 118d are collectively referred to as gate electrodes 118. Low-resistance portions 140a, 140b, 140c, and 140d are collectively referred to as low-resistance portions 140. Low-resistance portions 140 are similar to those shown in Figures 1A to 1G.

[0045] In some embodiments, the two low-resistance portions 140 are substantially aligned in the X direction. Each pair of adjacent gate structures 103 (e.g., gate structures 103b and 103c) may have a distance S0, where S0 refers to the distance in the X direction between corresponding gate electrode portions (e.g., gate electrodes 117b and 117c in the first circuit region 321). Each pair of adjacent gate structures 103 corresponding to the low-resistance portions 140 may have a spacing S, where S refers to the distance between the low-resistance portions 140 (e.g., low-resistance portions 140b and 140c). As previously mentioned, the gate electrodes of the gate structure 103 may have a width W0 in the X direction. The width (W) of the low-resistance portion 140 may be represented by the distance between two opposite sides of the low-resistance portion 140. In some embodiments, W is at least 10% greater than W0. In some embodiments, the ratio of W to W0 (W / W0) is at least 2, at least 3, at least 4, or at least 5. In some embodiments, W / W0 is equal to or less than 5. In some embodiments, W / W0 is between 1.1 and 5. In some embodiments, S is at least 10% less than S0. In some embodiments, the ratio of S / S0 is no more than 0.9, no more than 0.6, or no more than 0.3. In some embodiments, S is equal to or greater than W0. In some embodiments, the ratio of S / W0 is at least 1, at least 2, or at least 3. In some embodiments, S0, W0, and S satisfy the following relationship: 0.9*S0 ≥ S ≥ W0. In some embodiments, S is at least 3 nm, at least 5 nm, at least 10 nm, or at least 15 nm. The minimum distance between every two adjacent low-resistance portions ensures the normal functioning of the gate structure and minimizes the risk of dielectric breakdown between adjacent low-resistance portions.

[0046] It should be noted that the values ​​of W0, W0, S0, and S can vary according to design requirements. In some embodiments, the values ​​of W0, W0, S0, and S can be consistent or substantially consistent throughout the semiconductor device 300. In some embodiments, the values ​​of W0, S0, and S0 of the low-resistance portion (e.g., low-resistance portion 140d) can be a constant (e.g., the sum of W0 of the gate electrode portion 117d and S0 between the two corresponding gate electrode portions 117c and 117d). In other words, for each substantially identical heterogeneous gate structure 103 and its adjacent spacing S, the W0, W0, S0, and S of the heterogeneous gate structure 103 and its adjacent spacing S can satisfy the following relationship: W + S = constant, or W + S = W0 + S0.

[0047] In some embodiments, the low-resistivity portion 140 may be composed of the same or similar material as the gate electrodes 117 and 118. In some embodiments, the material of the low-resistivity portion 140 may be a different material from the materials of the gate electrodes 117 and 118. In some embodiments, the material of the low-resistivity portion 140 may be a low-resistivity material. In some embodiments, the materials of the gate electrodes 117 and 118 have a first resistivity, and the material of the low-resistivity portion 140 has a second resistivity. The second resistivity is less than the first resistivity.

[0048] In some embodiments, similar to semiconductor device 100F, the ILD layer 107 of semiconductor device 300 further includes a first ILD structure 108 and a second ILD structure 109. Gate electrodes 117 and 118 are respectively surrounded by the first ILD structure 108, while the low-resistance portion 140 is surrounded by the second ILD structure 109. The second ILD structure 109 is composed of a material different from that of the first ILD structure 108. In some embodiments, the second ILD structure 109 includes a material having a relatively low dielectric constant (κ) and / or a relatively high dielectric strength.

[0049] In some embodiments, the first ILD structure 108 has a first dielectric constant and a first dielectric strength, while the second ILD structure 109 has a second dielectric constant and a second dielectric strength. In some embodiments, the second dielectric constant is lower than the first dielectric constant. In some embodiments, the second dielectric strength is higher than the first dielectric constant. In some embodiments, the second dielectric constant is lower than the dielectric constant of silicon dioxide. In some embodiments, the second dielectric constant is less than 3.9. In some embodiments, the second dielectric strength is higher than 0.001 V / μm. In some embodiments, the low dielectric constant and / or high dielectric strength of the second ILD structure 109 between two adjacent low-resistivity portions (e.g., low-resistivity portions 140a and 140b) can help reduce or prevent parasitic capacitance between two low-resistivity portions 140 that are close to each other. In addition, the relatively high dielectric strength of the second ILD structure 109 can also effectively prevent dielectric breakdown between two adjacent low-resistivity portions 140. Therefore, the combination of the low dielectric constant of the second ILD structure 109 and the low resistivity material of the low-resistivity portion 140 can further improve the overall performance of the semiconductor device 300.

[0050] Figure 4 is a top view of the layout of a semiconductor device 400 according to some embodiments. Semiconductor device 400 is a variation of semiconductor devices 200D and 300, and semiconductor device 400 may include various configurations and combinations of the elements as described above. In the example shown, among other components, semiconductor device 400 further includes a plurality of transistors 125a, 125b, 125c, and 125d (collectively referred to as transistors 125) located in a first circuit region 421, a plurality of transistors 126a, 126b, 126c, and 126d (collectively referred to as transistors 126) located in a second circuit region 422, a plurality of gate structures 403a, 403b, 403c, and 403d (collectively referred to as gate structures 403), and metal contacts 250 disposed between gate structures 403a and 403b.

[0051] Multiple gate structures 403a, 403b, 403c, and 403d extend in the Y direction, and the multiple gate structures 403a, 403b, 403c, and 403d interconnect transistors 125a and 126a, transistors 125b and 126b, transistors 125c and 126c, and transistors 125d and 126d, respectively. Gate structures 403a and 403b are similar to gate structure 203 in Figure 2A. For example, gate structure 403a further includes two gate electrodes 117a and 118a and a low-resistance portion 440a located between the two gate electrodes 117a and 118a. Similarly, gate structure 403b further includes two gate electrodes 117b and 118b and a low-resistance portion 440b located between the two gate electrodes 117b and 118b. Gate structures 403c and 403d are similar to gate structure 103 in Figure 1A. For example, gate structure 403c further includes two gate electrodes 117c and 118c and a low-resistance portion 440c located between the two gate electrodes 117c and 118c. Gate structure 403d further includes two gate electrodes 117d and 118d and a low-resistance portion 440d located between the two gate electrodes 117d and 118d. Gate electrodes 117a, 117b, 117c, and 117d are collectively referred to as gate electrode 117. Gate electrodes 118a, 118b, 118c, and 118d are collectively referred to as gate electrode 118. Low-resistance portions 440a, 440b, 440c, and 440d are collectively referred to as low-resistance portion 440.

[0052] Metal contacts 250 are disposed between gate structures 403a and 403b. Similar to the metal contacts 250 in Figure 2C, the metal contacts 250 in Figure 4 are configured to interconnect transistors 125a / 125b and 126a / 126b, and to electrically couple the S / D regions below transistors 125a / 125b and 126a / 126b to each other or to other circuits of the semiconductor device 400. The metal contacts 250 are adjacent to the gate structures 403a and 403b. Due to the proximity of the metal contacts 250 to the gate structures 403a and 403b, the low-resistivity portions 440a and 440b may not have enlarged dimensions (i.e., W is not greater than W0). However, the overall resistance of the gate structures 403a and 403b can still be reduced by the low-resistivity material of the low-resistivity portions 440a and 440b. As described in the example of Figure 2D, the dielectric material of the second ILD structure 109 can have a relatively low dielectric constant and a relatively high dielectric strength, which can help reduce or prevent parasitic capacitance of the two low-resistance portions 440a / 440b and the metal contact 250 disposed between the two low-resistance portions 440a / 440b.

[0053] Conversely, the low-resistance portions 440c and 440d of the gate structures 403c and 403d have enlarged widths (e.g., W > W0) and enlarged cross-sectional dimensions. In some embodiments, the low-resistance portions 440c and 440d may further comprise a material different from the material of the gate electrodes 117 and 118 (e.g., a material with a relatively low resistivity). Due to the close proximity of the low-resistance portions 440d and 440d, no metal contacts are provided between the low-resistance portions 440d and 440d. The overall performance of the semiconductor device 400 can be significantly improved due to the multiple low-resistance portions 440.

[0054] In some embodiments, the layout of the semiconductor device described herein is presented through multiple masks generated by one or more processors, and / or multiple masks stored in one or more non-transitory computer-readable media. Other forms for presenting the layout of the semiconductor device are also within the scope of various embodiments. Examples of non-transitory computer-readable media include, but are not limited to, external / removable and / or internal / embedded storage or memory units, such as one or more optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), and semiconductor memories (e.g., ROM, RAM, memory cards), etc. For example, the layout of the semiconductor device 400 is presented by at least one first mask corresponding to the active regions 111 and 112, at least one second mask corresponding to the gate structures 403a and 403b, at least one third mask corresponding to the gate structures 403c and 403d, at least one fourth mask corresponding to the low resistance portions 440a and 440b, at least one fifth mask corresponding to the low resistance portions 440a and 440b, at least one sixth mask corresponding to the low resistance portions 440c and 440d, and at least one seventh mask corresponding to the metal contact 250.

[0055] According to some embodiments of this disclosure, a semiconductor device is provided. In one example, the semiconductor device includes: a substrate, a first circuit region and a second circuit region formed above the substrate and extending along a first direction, and a first transistor located in the first circuit region. The first transistor includes a first gate electrode extending along a second direction, and the second direction is substantially perpendicular to the first direction. The semiconductor device further includes a second transistor located in the second circuit region. The second transistor includes a second gate electrode extending in the second direction, and the second gate electrode is aligned with the first gate electrode in the second direction. The semiconductor device further includes a low-resistance portion extending in the second direction and interconnecting the first gate electrode and the second gate electrode. The low-resistance portion is substantially aligned with the first gate electrode and the second gate electrode in the second direction. The first gate electrode and the second gate electrode have a first width W0 along the first direction, the low-resistance portion has a second width W along the first direction, and the ratio of W to W0 (W / W0) is at least 1.1.

[0056] In another example, the semiconductor device includes a substrate, a first circuit region and a second circuit region formed above the substrate and extending along a first direction, and a gate structure extending along a second direction, which is substantially perpendicular to the first direction. The gate structure includes two gate electrode portions located in the first and second circuit regions, respectively, and a low-resistance portion located between the two gate electrode portions and interconnecting them. The two gate electrode portions are configured to serve as gate electrodes for two transistors in the first and second circuit regions, respectively, and the two transistors are located in the first and second circuit regions, respectively. The two gate electrode portions include a first material having a first resistivity, and the low-resistance portion includes a second material having a second resistivity, which is less than the first resistivity.

[0057] In another example, the semiconductor device includes a substrate, a first circuit region and a second circuit region formed above the substrate and extending along a first direction, and a plurality of gate structures extending along a second direction substantially perpendicular to the first direction. The plurality of gate structures include a first gate structure and a second gate structure adjacent to each other. The first gate structure includes: a first gate electrode portion and a second gate electrode portion respectively located in the first circuit region and the second circuit region, and a first low-resistance portion located between the first gate electrode portion and the second gate electrode portion and interconnecting the first gate electrode portion and the second gate electrode portion. The first gate electrode portion and the second gate electrode portion are configured to be located in the first circuit region and the second circuit region respectively, and the first gate electrode portion is configured to serve as the gate electrode of a first transistor in the first circuit region, while the second gate electrode portion is configured to serve as the gate electrode of a second transistor in the second circuit region. The second gate structure includes a third gate electrode portion and a fourth gate electrode portion located in the first circuit region and the second circuit region, respectively, and a second low-resistance portion located between the third gate electrode portion and the fourth gate electrode portion and interconnecting the third gate electrode portion and the fourth gate electrode portion. The third gate electrode portion is configured to serve as the gate electrode of a third transistor in the first circuit region, and the fourth gate electrode portion is configured to serve as the gate electrode of a fourth transistor in the second circuit region. The first gate electrode portion and the second gate electrode portion of the first gate structure, and the third gate electrode portion and the fourth gate electrode portion of the second gate structure, each have a first width W0 along a first direction, and the first low-resistance portion and the second low-resistance portion each have a second width W along the first direction, and the ratio of W to W0 (W / W0) is at least 1.1.

[0058] This disclosure outlines various embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0059] 100A, 100D, 100F: Semiconductor devices 101:Substrate 102: Shallow Trench Isolation Structure / STI Structure 103: Heterogeneous gate structure / gate structure 103a, 103b, 103c, 103d: Gate structure 107: Interlayer dielectric layer / ILD layer 108: First ILD Structure 109: Second ILD Structure 110, 120: Imaginary lines / lines 111: First Active Zone / Active Zone 112: Second Active Zone / Active Zone 113: Well region / n well regions 114: Tunnel / p-tunnel 117: First gate electrode / gate electrode 117a, 117b, 117c, 117d: Gate electrodes 118: Second gate electrode / gate electrode 118a, 118b, 118c, 118d: Gate electrodes 120: Imaginary Line 121: First Circuit Region 122: Second Circuit Area 125: First Transistor / Transistor 125a, 125b, 125c, 125d: Transistors 126: Second transistor / transistor 126a, 126b, 126c, 126d: Transistors 127a, 127b: S / D region / source / drain region 128a, 128b: S / D region / source / drain region 131, 132: Passage Area 133, 134: Gate dielectric layer 135, 136: Gate metal layer 140: Low resistance section 140a, 140b, 140c, 140d: Low resistance section 141: First side / first boundary 142: Second side / Second boundary 143: First End 144: Second End 151: Through-hole contact 161: First fin / fin 162: Second fin / fin 200A, 200B, 200C, 200D: Semiconductor devices 203: Gate Structure 203a, 203b, 203c: Gate structure 221: First Circuit Region 222: Second Circuit Region 240: Low resistance section 240a, 240b, 240c: Low resistance section 250: Metal Contact 250a, 250b: Metal contacts 300, 400: Semiconductor devices 321: First Circuit Region 322: Second Circuit Region 403a, 403b, 403c, 403d: Gate structure 421: First Circuit Region 422: Second Circuit Region 440: Low resistance section 440a, 440b, 440c, 440d: Low resistance section AA', BB': Sections D 1: Distance D 2: Distance L: Length W 0: Width / First Width W: Width / Second Width S 0: Distance S: Spacing X, Y, Z: Direction

[0060] Domestic storage information (please note the order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device, comprising: One substrate; A first circuit region and a second circuit region are formed above the substrate and extend along a first direction; A first transistor, located in the first circuit region, wherein the first transistor includes a first channel region and a first gate electrode that contacts the first channel region and extends along a second direction, wherein the second direction is substantially perpendicular to the first direction; a second transistor, located in the second circuit region, wherein the second transistor includes a second channel region and a second gate electrode that contacts the second channel region and extends along the second direction, wherein the second gate electrode is aligned with the first gate electrode along the second direction; a shallow trench isolation structure, located between the first channel region and the second channel region; a low-resistance portion extending along the second direction and interconnecting the first gate electrode and the second gate electrode, wherein the low-resistance portion is substantially aligned with the first gate electrode and the second gate electrode along the second direction; The material includes an interlayer dielectric layer, comprising: a first interlayer dielectric structure surrounding the first gate electrode and the second gate electrode; and a second interlayer dielectric structure surrounding the low-resistance portion, wherein a material of the second interlayer dielectric structure is different from a material of the first interlayer dielectric structure, wherein a bottom surface of the low-resistance portion contacts a top surface of each of the shallow trench isolation structures, and wherein the first gate electrode and the second gate electrode have a first width (W0) along the first direction, the low-resistance portion has a second width (W) along the first direction, and the ratio of W to W0 (W / W0) is at least 1.

1.

2. The semiconductor device as claimed in claim 1, wherein the low-resistance portion has a length (L) along the second direction, and the ratio of L to W0 (L / W0) is at least 10.

3. The semiconductor device as claimed in claim 1, wherein the low-resistance portion extends from a first end to a second end in a direction from the first transistor to the second transistor, the first transistor including two source / drain regions located on opposite sides of the first gate electrode, the low-resistance portion having a distance (D1) from the first end to the two source / drain regions in the second direction, and the ratio of D1 to W0 (D1 / W0) is at least 3.

4. The semiconductor device as claimed in claim 1, wherein the first gate electrode and the second gate electrode comprise a first material having a first resistivity, the low-resistivity portion comprises a second material having a second resistivity that is less than the first resistivity.

5. The semiconductor device as claimed in claim 1, wherein the first circuit region is located in a first active region, the second circuit region is located in a second active region, and the low-resistance portion extends across a boundary between the first active region and the second active region.

6. A semiconductor device, comprising: One substrate; A first circuit region and a second circuit region are formed above the substrate and extend along a first direction; A gate structure extending along a second direction substantially perpendicular to a first direction, wherein the gate structure includes: two channel regions located in a first circuit region and a second circuit region, respectively; a shallow trench isolation structure located between the two channel regions; two gate electrode portions located in the first circuit region and the second circuit region, respectively, wherein the two gate electrode portions are configured to serve as gate electrodes for two transistors in the first circuit region and the second circuit region, respectively, and the two transistors are located in the first circuit region and the second circuit region, and wherein the two gate electrode portions are in contact with the two channel regions; and a low-resistance portion located between the two gate electrode portions and interconnecting the two gate electrode portions, wherein a bottom surface of the low-resistance portion is in contact with a top surface of the shallow trench isolation structure; and an interlayer dielectric layer including: a first interlayer dielectric structure surrounding the two gate electrode portions; and a second interlayer dielectric structure surrounding the low-resistance portion. The material of the second interlayer dielectric structure is different from the material of the first interlayer dielectric structure. The two gate electrode portions include a first material with a first resistivity, and the low-resistivity portion includes a second material with a second resistivity that is less than the first resistivity.

7. A semiconductor device, comprising: One substrate; A first circuit region and a second circuit region are formed above the substrate and extend along a first direction; A plurality of gate structures extend along a second direction, which is substantially perpendicular to the first direction, wherein the gate structures include a first gate structure and a second gate structure adjacent to each other, wherein the first gate structure includes: a first channel region and a second channel region, respectively located in the first circuit region and the second circuit region; and a first shallow trench isolation structure located between the first channel region and the second channel region; A first gate electrode portion and a second gate electrode portion are respectively located in the first circuit region and the second circuit region, wherein the first gate electrode portion is configured to serve as the gate electrode of a first transistor in the first circuit region, and the second gate electrode portion is configured to serve as the gate electrode of a second transistor in the second circuit region, wherein the first gate electrode portion contacts the first channel region, and the second gate electrode portion contacts the second channel region; and a first low-resistance portion is located between the first gate electrode portion and the second gate electrode portion and interconnects the first gate electrode portion and the second gate electrode portion, wherein a bottom surface of the first low-resistance portion contacts a top surface of the first shallow trench isolation structure; a first interlayer dielectric layer includes: a first interlayer dielectric structure surrounding the first gate electrode portion and the second gate electrode portion; and a second interlayer dielectric structure surrounding the first low-resistance portion, wherein a material of the second interlayer dielectric structure is different from a material of the first interlayer dielectric structure. The second gate structure includes: a third channel region and a fourth channel region, respectively located in the first circuit region and the second circuit region; a second shallow trench isolation structure located between the third channel region and the fourth channel region; a third gate electrode portion and a fourth gate electrode portion, respectively located in the first circuit region and the second circuit region, wherein the third gate electrode portion is configured as the gate electrode of a third transistor in the first circuit region, and the fourth gate electrode portion is configured as the gate electrode of a fourth transistor in the second circuit region, wherein the third gate electrode portion is in contact with the third channel region, and the fourth gate electrode portion is in contact with the fourth channel region; and a second low-resistance portion located between the third gate electrode portion and the fourth gate electrode portion and interconnecting the third gate electrode portion and the fourth gate electrode portion, wherein a bottom surface of the second low-resistance portion is in contact with a top surface of the second shallow trench isolation structure; and a second interlayer dielectric layer, including: A third interlayer dielectric structure surrounds the third gate electrode portion and the fourth gate electrode portion;And a fourth interlayer dielectric structure surrounding the first low-resistance portion, wherein a material of the third interlayer dielectric structure is different from a material of the fourth interlayer dielectric structure, wherein the first gate electrode portion and the second gate electrode portion of the first gate structure, and the third gate electrode portion and the fourth gate electrode portion of the second gate structure, each have a first width (W0) along the first direction, the first low-resistance portion and the second low-resistance portion each have a second width (W) along the first direction, and the ratio of W to W0 (W / W0) is at least 1.

1.

8. The semiconductor device as claimed in claim 7, wherein the first low-resistance portion and the second low-resistance portion are substantially aligned in the first direction.

9. The semiconductor device as claimed in claim 7, wherein the first gate structure and the second gate structure are separated from each other by a first distance (S0) and a second distance (S), wherein the first distance (S0) is the distance between corresponding first gate electrode portions, second gate electrode portions, third gate electrode portions and fourth gate electrode portions in a first direction, and the second distance (S) is the distance between the first low-resistance portion and the second low-resistance portion in the first direction, wherein the ratio of S to S0 (S / S0) is not greater than 0.

9.

10. The semiconductor device as claimed in claim 7, wherein the gate structures include: A third gate structure, adjacent to the first gate structure and extending along the second direction, wherein the third gate structure has the first width (W0) along the second direction, and includes: a fifth gate electrode portion and a sixth gate electrode portion, respectively located in the first circuit region and the second circuit region, wherein the fifth gate electrode portion is configured as the gate electrode of a fifth transistor in the first circuit region, and the sixth gate electrode portion is configured as the gate electrode of a sixth transistor in the second circuit region; and a third low-resistance portion, located between the fifth gate electrode portion and the sixth gate electrode portion and interconnecting the fifth gate electrode portion and the sixth gate electrode portion, wherein the third low-resistance portion is substantially aligned with the first low-resistance portion and the second low-resistance portion in the first direction, wherein the fifth gate electrode portion and the sixth gate electrode portion of the third gate structure include a first material, and the third low-resistance portion includes a second material.

Images