Totem PFC Driver Architecture

Abstract

A totem-pole PFC drive architecture is electrically connected to a low-frequency bridge arm circuit unit and a high-speed bridge arm circuit unit. The totem-pole PFC drive architecture includes at least a detection circuit unit, an analog PFC control circuit unit, and a logic drive circuit unit. The detection circuit unit receives an AC signal and outputs an AC positive half-cycle detection signal, an AC negative half-cycle detection signal, and an AC output signal. The analog PFC control circuit unit receives the AC output signal and outputs a PFC drive control signal. The logic drive circuit unit receives the AC positive half-cycle detection signal, the AC negative half-cycle detection signal, and the PFC drive control signal, and outputs a first drive signal and a second drive signal to the low-frequency bridge arm circuit unit according to a truth table to drive the first switch and the second switch.

Description

[Technical Field]

[0001] This invention relates to a totem pole PFC driver architecture, and more particularly to a totem pole PFC driver architecture that can be controlled using an analog control IC. [Previous Technology]

[0002] In recent years, the demand for AI and HPC has increased significantly, resulting in a surge in power consumption in this field, from the traditional 1000W requirement for servers to 3KW~7KW.

[0003] Therefore, efficiency and heat dissipation have become issues that power supply developers must face. Generally speaking, power supply products must be equipped with power factor correction (PFC). However, traditional boost power factor correctors have a bridge rectifier, so efficiency and heat dissipation are caused by bridge rectification by more than 1%.

[0004] Therefore, Totem PFC has become mainstream, but its control is very complex. If analog control is to be used, its design will be very difficult. Therefore, at present, DSP-level MCUs are used as controllers to control and operate.

[0005] However, since DSP-level MCUs are required, solution providers must provide several firmware and hardware engineers, along with the original manufacturer of the digital DSP MCU, to complete the design and implementation. Therefore, the use of MCUs as controllers in Totem PFC limits the development of the industry, and its cost is also very high. This drawback is very obvious.

[0006] Therefore, through long-term research and development, this case has designed a totem pole PFC drive architecture, which uses an analog PFC control IC and is paired with a logic control circuit. It can achieve effective control through analog control, thus saving a lot of costs. Therefore, this case should be the best solution. [Summary of the Invention]

[0007] The totem pole PFC drive architecture of the present invention is electrically connected to a low-frequency bridge arm circuit unit and a high-speed bridge arm circuit unit. The low-frequency bridge arm circuit unit includes at least a first switch and a second switch, and the high-speed bridge arm circuit unit includes at least a third switch and a fourth switch. The totem pole PFC drive architecture includes at least a detection circuit unit, which is electrically connected to the high-speed bridge arm circuit unit and an AC power supply terminal. The detection circuit unit is used to receive an AC signal, and the detection circuit unit outputs an AC positive half-cycle detection signal, an AC negative half-cycle detection signal, and an AC output signal based on the AC signal. The AC positive half-cycle detection signal can drive the fourth switch, and the AC negative half-cycle detection signal can drive the fourth switch. The third switch; an analog PFC control circuit unit electrically connected to the detection circuit unit, used to receive the AC output signal and output a PFC drive control signal; and a logic drive circuit unit electrically connected to the detection circuit unit and the analog PFC control circuit unit, the logic drive circuit unit used to receive the AC positive half-cycle detection signal, the AC negative half-cycle detection signal and the PFC drive control signal, and the logic drive circuit unit used to output a first drive signal and a second drive signal to the low-frequency bridge arm circuit unit according to the AC positive half-cycle detection signal, the AC negative half-cycle detection signal and the PFC drive control signal, wherein the first drive signal is used to drive the first switch and the second drive signal is used to drive the second switch.

[0008] More specifically, when the AC positive half-cycle detection signal is at a high potential, the AC negative half-cycle detection signal is at a low potential, and the PFC drive control signal is in one working cycle, the first drive signal is in one working cycle (D), the second drive signal is in one other working cycle (1-D), the signal driving the third switch is at a low potential, and the signal driving the fourth switch is at a high potential.

[0009] More specifically, when the AC positive half-cycle detection signal is at a low potential, the AC negative half-cycle detection signal is at a high potential, and the PFC drive control signal is in one working cycle, the first drive signal is in another working cycle (1-D), the second drive signal is in that working cycle (D), the signal driving the third switch is at a high potential, and the signal driving the fourth switch is at a low potential.

[0010] More specifically, the logic drive circuit unit is also able to receive an enable signal, and when the enable signal is at a low potential, the first switch, the second switch, the third switch and the fourth switch are turned off.

[0011] More specifically, the analog PFC control circuit unit includes an analog PFC control IC.

[0012] More specifically, the first switch and the second switch of the low-frequency bridge arm circuit unit are connected in series, and the connection point of the first switch and the second switch is coupled to one end of the AC power supply through an inductor; the third switch and the fourth switch of the high-speed bridge arm circuit unit are connected in series, the high-speed bridge arm circuit unit is connected in parallel with the low-frequency bridge arm circuit unit, and the connection point of the third switch and the fourth switch is coupled to the other end of the AC power supply.

Implementation Method

[0014] Other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings.

[0015] Please refer to Figures 1 and 2A~2B, which are schematic diagrams of the architecture of the totem pole PFC drive architecture of the present invention and schematic diagrams of the simplified circuit connection of the first implementation, wherein the totem pole PFC drive architecture 2 is electrically connected to the AC power supply terminal 1, the low frequency bridge arm circuit unit 3, and the high speed bridge arm circuit unit 4.

[0016] The AC power supply terminal 1 has a live terminal (ACN) and a neutral terminal (ACL).

[0017] The low-frequency bridge arm circuit unit 3 includes at least a low-frequency isolation driver 31, a first switch (QLF) and a second switch (QHF), wherein the first switch (QLF) and the second switch (QHF) are electrically connected to the low-frequency isolation driver 31.

[0018] The first switch (QLF) and the second switch (QHF) of the low-frequency bridge arm circuit unit 3 are connected in series, and the connection point (midpoint) between the first switch (QLF) and the second switch (QHF) is coupled to one end of the AC power supply terminal 1 through an inductor 5 (L1).

[0019] The high-speed bridge arm circuit unit 4 includes at least a high-speed isolation driver 41, a third switch (QHL) and a fourth switch (QLL), wherein the third switch (QHL) and the fourth switch (QLL) are electrically connected to the high-speed isolation driver 41.

[0020] The third and fourth switches of the high-speed bridge arm circuit unit 4 are connected in series. The high-speed bridge arm circuit unit 4 is connected in parallel with the low-frequency bridge arm circuit unit 3. The connection point (midpoint) between the third and fourth switches is coupled to the other end of the AC power supply terminal 1.

[0021] The totem pole PFC drive architecture 2 includes at least a detection circuit unit 21, an analog PFC control circuit unit 22, and a logic drive circuit unit 23. The totem pole PFC drive architecture 2 is further electrically connected to the AC power supply terminal 1, the low-frequency bridge arm circuit unit 3, and the high-speed bridge arm circuit unit 4.

[0022] The detection circuit unit 21 is electrically connected to the high-speed bridge arm circuit unit 4 and the AC power supply terminal 1. The detection circuit unit 21 is used to receive an AC signal and output an AC positive half-cycle detection signal, an AC negative half-cycle detection signal and an AC output signal according to the AC signal.

[0023] As shown in Figures 2A-2B, the connection terminals of the detection circuit unit 21 are described as follows: (a) Connection terminal (1), used to connect to the live terminal (ACN). (b) Connection terminal (2), used to connect to the neutral terminal (ACL). (c) Connection terminal (3), used to output the AC positive half-cycle detection signal (ACNHLOGIC) to the logic drive circuit unit 23. (d) Connection terminal (4), used to output the AC negative half-cycle detection signal (ACLHLOGIC) to the logic drive circuit unit 23. (e) Connection terminal (5), used to output the AC output signal (ACIN) to the analog PFC control circuit unit 22. (f) The implementation circuit of the detection circuit unit 21 is shown in Figure 3. After receiving the AC signal from the AC power supply terminal 1, the detection circuit unit 21 can determine the AC polarity and provide three signals according to the polarity.

[0024] The analog PFC control circuit unit 22 is electrically connected to the detection circuit unit 21 to receive the AC output signal and output a PFC drive control signal.

[0025] The analog PFC control circuit unit 22 includes an analog PFC control IC.

[0026] As shown in Figures 2A-2B, the connection terminals of the analog PFC control circuit unit 22 are described as follows: (a) Connection terminal (1), used to output the PFC drive control signal (PFC DRIVER, D (D represents the positive half-cycle of PWM (PWM)) or 1-D (1-D represents the negative half-cycle of PWM ( / PWM))) to the logic drive circuit unit 23. (b) Connection terminal (2), used to detect current. (c) Connection terminal (5), used to connect to the connection terminal (5) of the detection circuit unit 21.

[0027] The implementation circuit of the analog PFC control circuit unit 22 is shown in Figures 4A to 4D.

[0028] The logic drive circuit unit 23 is electrically connected to the detection circuit unit 21 and the analog PFC control circuit unit 22. The logic drive circuit unit 23 is used to receive the AC positive half-cycle detection signal, the AC negative half-cycle detection signal and the PFC drive control signal.

[0029] The logic drive circuit unit 23 outputs a first drive signal and a second drive signal to the low-frequency bridge arm circuit unit 3 based on the AC positive half-cycle detection signal, the AC negative half-cycle detection signal and the PFC drive control signal.

[0030] As shown in Figures 2A-2B, the connection terminals of the logic drive circuit unit 23 are described as follows: (a) Connection terminal (1) is used to output a second drive signal (Q2, 1-D for the positive half-cycle and D for the negative half-cycle) to the isolation driver 31 of the low-frequency bridge arm circuit unit 3. The second drive signal is used to drive the second switch (QHF). (b) Connection terminal (2) is used to output a first drive signal (Q1, D for the positive half-cycle and 1-D for the negative half-cycle) to the isolation driver 31 of the low-frequency bridge arm circuit unit 3. The first drive signal is used to drive the first switch (QLF). (c) Connection terminal (3) is used to receive a driver enable signal. When the enable signal is low, the first switch, the second switch, the third switch, and the fourth switch are turned off. (d) Connection terminal (7), used to connect to connection terminal (1) of analog PFC control circuit unit 22 to receive PFC drive control signal (PFC DRIVER, D (D represents the positive half-cycle of PWM (PWM)) or 1-D (1-D represents the negative half-cycle of PWM ( / PWM))). (e) Connection terminal (8), used to receive AC positive half-cycle detection signal (ACNHLOGIC). (f) Connection terminal (9), used to receive AC negative half-cycle detection signal (ACLHLOGIC).

[0031] The implementation circuit of the logic drive circuit unit 23 is shown in Figures 5A to 5C.

[0032] As shown in Figures 2A-2B, the connection terminals of the isolation driver 31 are described as follows: (a) Connection terminal (1), used to connect and receive the second drive signal (Q2, positive half-cycle is 1-D, negative half-cycle is D). (b) Connection terminal (2), used to connect and receive the first drive signal (Q1, positive half-cycle is D, negative half-cycle is 1-D).

[0033] As shown in Figures 2A-2B, the connection terminals of the isolation driver 41 are described as follows: (a) Connection terminal (1), used to receive the AC negative half-cycle detection signal (ACLHLOGIC) and to turn on the third switch (QHL) during the negative half-cycle. (b) Connection terminal (2), used to receive the AC positive half-cycle detection signal (ACNHLOGIC) and to turn on the fourth switch (QLL) during the positive half-cycle.

[0034] As shown in Table 1 below, the logic drive circuit unit 23 outputs the first drive signal and the second drive signal to the low-frequency bridge arm circuit unit 3 according to the truth table. ACN ACL DRIVER ENABLE ACNHLOGIC (positive half-circle) ACLHLOGIC (Negative half-cycle) PFC DRIVER Q1 / QLF Q2 / QHF QHL(GATE) (Negative half-cycle) QLL(GATE) (positive half-circle) H L H H L D D 1-D L H L H H L H D 1-D D H L X X L X X L L L L L Table 1: Logical Truth Table

[0035] In Table 1 above, Q1 / Q2 will be interchanged between D / 1-D due to the switching between the positive and negative half-cycles.

[0036] In Table 1 above, D represents the positive half-cycle of PWM (PWM), and 1-D represents the negative half-cycle of PWM ( / PWM).

[0037] In Table 1 above, X represents an unknown state. When both ACNHLOGIC and ACLHLOGIC are L (Low) or both are H (High) (defined as an uncertain state), in order to achieve the protection effect, all switches are set to L (Low), the enable signal is set to a low potential, and the first switch (QLF), the second switch (QHF), the third switch (QHL) and the fourth switch (QLL) are closed.

[0038] As shown in Figures 6A to 6F, this is a schematic diagram of the implementation circuit of the isolation driver 31. The isolation driver 41 is similar to the isolation driver 31, so it will not be described again.

[0039] As shown in Figure 7, this is a schematic diagram of the AC signal, the first drive signal, and the second drive signal of the totem pole PFC drive architecture. The different waveforms are explained as follows: (1) As shown in (A) of Figure 7, this is the AC signal; (2) As shown in (B) and (C) of Figure 7, (B) represents the output of the first drive signal, and (C) represents the output of the second drive signal. (3) When ACN is H, ACL is L, ACNHLOGIC is H, and ACLHLOGIC is L, the first drive signal is the positive half-cycle of PWM, and the second drive signal is the negative half-cycle of PWM. (4) When ACL is H, ACH is L, ACLHLOGIC is H, and ACNHLOGIC is L, the first drive signal is the negative half-cycle of PWM, and the second drive signal is the positive half-cycle of PWM.

[0040] As shown in Figure 8, the AC output signal (ACIN, full-wave rectified analog signal) is output from the detection circuit unit 21 to the analog PFC control circuit unit 22 (analog PFC control IC), where the vertical axis is voltage (V) and the horizontal axis is time (seconds).

[0041] The operating principle of the first embodiment of this case is as follows: When AC power is input, the MOS components (first switch, second switch, third switch, and fourth switch) and the inductor work together in rectification and boost mode. By tracking the AC signal, the logic drive circuit unit can generate corresponding PWM drive signals according to the truth table to realize the PFC function. The current flow at different times is as follows: (a) During the positive half-cycle of AC power, the first switch (QLF) is driven by the duty cycle (D) to determine the boost ratio, and the second switch (QHF) is complementary to it and driven by (1-D); at the same time, the fourth switch (QLL) is always on, while the third switch (QHL) is always off. (b) During the negative half-cycle of AC power, the second switch (QHF) is driven by the duty cycle (D) to determine the boost ratio, and the first switch (QLF) is complementary to it and driven by (1-D); at the same time, the third switch (QHL) is always on, while the fourth switch (QLL) is always off.

[0042] Furthermore, the implementation of this case can be designed to drive multiple groups, as shown in Figures 9A to 9C, by adding a logic drive circuit unit 24 and a low-frequency bridge arm circuit unit 7 connected in series, wherein the logic drive circuit unit 24 is electrically connected to the low-frequency bridge arm circuit unit 7.

[0043] In high-wattage applications, in order to reduce the heat generated by the high-frequency switching loss of Q1 / Q2, a pair of Q1 / Q2 currents will be added to distribute the current. SIN1 / SIN2 (logic drive circuit unit 23 / logic drive circuit unit 24) are used to control the operation of that pair of Q1 / Q2 respectively.

[0044] As shown in Figures 9A-9C, the connection terminals of the detection circuit unit 21 are described as follows: (a) Connection terminal (1), used to connect to the live terminal (ACN). (b) Connection terminal (2), used to connect to the neutral terminal (ACL). (c) Connection terminal (3), used to output the AC positive half-cycle detection signal (ACNHLOGIC) to the logic drive circuit unit 23. (d) Connection terminal (4), used to output the AC negative half-cycle detection signal (ACLHLOGIC) to the logic drive circuit unit 23. (e) Connection terminal (5), used to output the AC output signal (ACIN) to the analog PFC control circuit unit 22.

[0045] As shown in Figures 9A-9C, the connection terminals of the analog PFC control circuit unit 22 are described as follows: (a) Connection terminal (1), used to output PFC drive control signals (PFC DRIVER1, D1 (D1 represents the positive half-cycle of PWM (PWM1)) or 1-D1 (1-D1 represents the negative half-cycle of PWM ( / PWM1))) to the logic drive circuit unit 23. (b) Connection terminal (2), used to detect current. (c) Connection terminal (3), used to output another PFC drive control signal (PFC DRIVER2, D2 (D2 represents the positive half-cycle of PWM (PWM2)) or 1-D2 (1-D2 represents the negative half-cycle of PWM ( / PWM2))) to the logic drive circuit unit 24. (d) Connection terminal (4), used to detect voltage. (e) Connection terminal (5), used to connect to the connection terminal (5) of the detection circuit unit 21.

[0046] As shown in Figures 9A-9C, the connection terminals of the logic drive circuit unit 23 are described as follows: (a) Connection terminal (1), used to output a second drive signal (Q2, 1-D1 for the positive half-cycle and D1 for the negative half-cycle) to the isolation driver 31 of the low-frequency bridge arm circuit unit 3, the second drive signal being used to drive the second switch (QHF1) of the low-frequency bridge arm circuit unit 3. (b) Connection terminal (2), used to output a first drive signal (Q1, D1 for the positive half-cycle and 1-D1 for the negative half-cycle) to the isolation driver 31 of the low-frequency bridge arm circuit unit 3, the first drive signal being used to drive the first switch (QLF1) of the low-frequency bridge arm circuit unit 3. (c) Connection terminal (3), used to receive an enable signal (DRIVER ENABLE, Driver EN1). (d) Connection terminal (4), used to receive another enable start signal ((1-D1)DRIVER ENABLE, (1-D1)EN1). (e) Connection terminal (5), used to output the AC positive half-cycle detection signal (ACNHLOGIC) to the isolation driver 41. (f) Connection terminal (6), used to output the AC negative half-cycle detection signal (ACLHLOGIC) to the isolation driver 41. (g) Connection terminal (7), used to connect to the connection terminal (1) of the analog PFC control circuit unit 22 to receive the PFC drive control signal (PFC DRIVER1, D1 (D1 represents the positive half-cycle of PWM (PWM)) or 1-D1 (1-D1 represents the negative half-cycle of PWM ( / PWM))). (h) Connection terminal (8), used to receive the AC positive half-cycle detection signal (ACNHLOGIC). (i) Connection terminal (9), used to receive the AC negative half-cycle detection signal (ACLHLOGIC).

[0047] As shown in Figure 9C, the connection terminals of the logic drive circuit unit 24 are described as follows: (a) Connection terminal (1), used to output a second drive signal (Q2, positive half-cycle is 1-D2, negative half-cycle is D2) to the isolation driver 71 of the low-frequency bridge arm circuit unit 7, the second drive signal being used to drive the second switch (QHF2) of the low-frequency bridge arm circuit unit 7. (b) Connection terminal (2), used to output a first drive signal (Q1, positive half-cycle is D2, negative half-cycle is 1-D2) to the isolation driver 71 of the low-frequency bridge arm circuit unit 7, the first drive signal being used to drive the first switch (QLF2) of the low-frequency bridge arm circuit unit 7. (c) Connection terminal (3), used to receive an enable start signal (DRIVER ENABLE, Driver EN2). (d) Connection terminal (4), used to receive another enable start signal ((1-D2)DRIVER ENABLE, (1-D2)EN2). (e) Connection terminal (5) is used to receive the AC positive half-cycle detection signal (ACNHLOGIC). (f) Connection terminal (6) is used to receive the AC negative half-cycle detection signal (ACLHLOGIC). (g) Connection terminal (7) is used to receive another PFC drive control signal (PFC DRIVER2, D2 (D2 represents the positive half-cycle of PWM (PWM)) or 1-D2 (1-D2 represents the negative half-cycle of PWM ( / PWM))).

[0048] As shown in Figures 9A to 9C, the low-frequency bridge arm circuit unit 3 and the low-frequency bridge arm circuit unit 7 share the high-speed bridge arm circuit unit 4.

[0049] The first switch (QLF2) and the second switch (QHF2) of the low-frequency bridge arm circuit unit 3 are connected in series, and the connection point (midpoint) between the first switch (QLF2) and the second switch (QHF2) is coupled to one end of the AC power supply terminal 1 through an inductor 5 (L3).

[0050] As shown in Figures 9A-9C, the connection terminals of the isolation driver 31 are described as follows: (a) Connection terminal (1), used to connect and receive the second drive signal (Q2, positive half-cycle is 1-D1, negative half-cycle is D1) transmitted by the logic drive circuit unit 23. (b) Connection terminal (2), used to connect and receive the first drive signal (Q1, positive half-cycle is D1, negative half-cycle is 1-D1) transmitted by the logic drive circuit unit 23.

[0051] The first switch (QLF2) and the second switch (QHF2) are connected in series, and the connection point (midpoint) between the first switch (QLF2) and the second switch (QHF2) is coupled to one end of the AC power supply terminal 1 through an inductor 6 (L4).

[0052] As shown in Figures 9A-9C, the connection terminals of the isolation driver 71 are described as follows: (a) Connection terminal (1), used to connect and receive the second drive signal (Q2, positive half-cycle is 1-D2, negative half-cycle is D2) transmitted by the logic drive circuit unit 24. (b) Connection terminal (2), used to connect and receive the first drive signal (Q1, positive half-cycle is D2, negative half-cycle is 1-D2) transmitted by the logic drive circuit unit 24.

[0053] The third and fourth switches of the high-speed bridge arm circuit unit 4 are connected in series, the high-speed bridge arm circuit unit 4 is connected in parallel with the low-frequency bridge arm circuit unit 3, and the connection point (midpoint) of the third and fourth switches is coupled to the other end of the AC power supply terminal 1.

[0054] As shown in Figures 9A-9C, the connection terminals of the isolation driver 41 are described as follows: (a) Connection terminal (1), used to connect to receive the AC negative half-cycle detection signal (ACLHLOGIC). (b) Connection terminal (2), used to connect to receive the AC positive half-cycle detection signal (ACNHLOGIC).

[0055] As shown in Table 2 below, the logic drive circuit unit 23 outputs the first drive signal and the second drive signal to the low-frequency bridge arm circuit unit 3 according to the truth table. Half-circle negative half-cycle Phase 1 negative half-cycle Half-circle ACN ACL Driver EN1 (1-D1) EN1 ACNHLOGIC ACLHLOGIC PFC Driver1 Q1 / QLF1 Q2 / QHF1 QHL1 QLL1 H L H H H L PWM1 PWM1 / PWM1 L H L H H H L H / PWM1 PWM1 H L H L H L H L L / PWM1 L H L H H L L H / PWM1 L H L X X L X X X X L L L L Table 2 Logic Truth Table

[0056] As shown in Table 3 below, the logic drive circuit unit 24 outputs the first drive signal and the second drive signal to the low frequency bridge arm circuit unit 7 according to the truth table. Half-circle Negative half week Phase 2 ACN ACL Driver EN2 (1-D2) EN2 ACNHLOGIC ACLHLOGIC PFC Driver2 Q1 / QLF2 Q2 / QHF2 H L H H H L PWM2 PWM2 / PWM2 L H H H L H / PWM2 PWM2 H L H L H L L / PWM2 L H H L L H / PWM2 L X X L X X X X L L Table 3 Logic Truth Table

[0057] In Tables 2 and 3 above, X represents an unclear state. When both ACNHLOGIC and ACLHLOGIC show L (Low) or both show H (High) (defined as an uncertain state).

[0058] The totem pole PFC driver architecture provided by this invention has the following advantages compared with other conventional technologies: 1. Through long-term research and development, this invention has designed a totem pole PFC driver architecture, which uses an analog PFC control IC and is paired with a logic control circuit to achieve effective control through analog control, thus saving a lot of costs. 2. This invention does not require a DSP or other MCU to complete complex PFC algorithms and drive control signals. Only basic LOGIC circuits are needed to complete the drive signals, and basic PFC operations can be completed using traditional PFC ICs. Therefore, this invention can complete complex TOTEMPOLE PFC using existing components.

[0059] The present invention has been disclosed above through the above embodiments, but it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements after understanding the foregoing technical features and embodiments of the present invention, without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention shall be determined by the claims attached to this specification. [Simplified Explanation of the Diagram]

[0013] [Figure 1] is a schematic diagram of the architecture of the totem pole PFC driver architecture of the present invention. [Figures 2A-2B] are schematic diagrams of the simplified circuit connection of the first embodiment of the totem pole PFC driver architecture of the present invention. [Figure 3] is a schematic diagram of the circuit implementation of the low-frequency isolation driver of the totem pole PFC driver architecture of the present invention. [Figures 4A-4D] are schematic diagrams of the circuit implementation of the analog PFC control circuit unit of the totem pole PFC driver architecture of the present invention. [Figures 5A-5C] are schematic diagrams of the circuit implementation of the logic drive circuit unit of the totem pole PFC driver architecture of the present invention. [Figures 6A-6F] are schematic diagrams of the circuit implementation of the isolation driver of the totem pole PFC driver architecture of the present invention. [Figure 7] is a schematic diagram of the signal waveforms of the AC signal, the first drive signal, and the second drive signal of the totem pole PFC driver architecture of the present invention. [Figure 8] is a schematic diagram of the signal waveform of the AC output signal of the totem pole PFC driver architecture of the present invention. [Figures 9A-9C] are simplified circuit connection diagrams of the second embodiment of the totem pole PFC driving architecture of the present invention.

Claims

1. A totem pole PFC drive architecture, electrically connected to a low-frequency bridge arm circuit unit and a high-speed bridge arm circuit unit, wherein the low-frequency bridge arm circuit unit includes at least a first switch and a second switch, and the high-speed bridge arm circuit unit includes at least a third switch and a fourth switch, and the totem pole PFC drive architecture includes at least: a detection circuit unit electrically connected to the high-speed bridge arm circuit unit and an AC power supply terminal, wherein the detection circuit unit is used to receive an AC signal, and the detection circuit unit outputs an AC positive half-cycle detection signal, an AC negative half-cycle detection signal and an AC output signal according to the AC signal, wherein the AC positive half-cycle detection signal can drive the fourth switch, and the AC negative half-cycle detection signal can drive the third switch; An analog PFC control circuit unit, electrically connected to the detection circuit unit, is used to receive the AC output signal and output a PFC drive control signal; and a logic drive circuit unit, electrically connected to the detection circuit unit and the analog PFC control circuit unit, is used to receive the AC positive half-cycle detection signal, the AC negative half-cycle detection signal, and the PFC drive control signal, and the logic drive circuit unit is used to output a first drive signal and a second drive signal to the low-frequency bridge arm circuit unit according to the AC positive half-cycle detection signal, the AC negative half-cycle detection signal, and the PFC drive control signal, wherein the first drive signal is used to drive the first switch, and the second drive signal is used to drive the second switch; wherein... When the AC positive half-cycle detection signal is high, the AC negative half-cycle detection signal is low, and the PFC drive control signal is in one working cycle (D), the first drive signal is in that working cycle (D), the second drive signal is in one other working cycle (1-D), the signal driving the third switch is low, and the signal driving the fourth switch is high; wherein, when the AC positive half-cycle detection signal is low, the AC negative half-cycle detection signal is high, and the PFC drive control signal is in one working cycle (D), the first drive signal is in one other working cycle (1-D), the second drive signal is in that working cycle (D), the signal driving the third switch is high, and the signal driving the fourth switch is low.

2. The totem pole PFC drive architecture as described in claim 1, wherein the logic drive circuit unit is further capable of receiving an enable signal, and when the enable signal is at a low potential, the first switch, the second switch, the third switch and the fourth switch are turned off.

3. The totem pole PFC drive architecture as described in claim 1, wherein the analog PFC control circuit unit includes an analog PFC control IC.

4. The totem pole PFC drive architecture as described in claim 1, wherein the first and second switches of the low-frequency bridge arm circuit unit are connected in series, and the connection point of the first and second switches is coupled to one end of the AC power supply through an inductor; the third and fourth switches of the high-speed bridge arm circuit unit are connected in series, the high-speed bridge arm circuit unit is connected in parallel with the low-frequency bridge arm circuit unit, and the connection point of the third and fourth switches is coupled to the other end of the AC power supply.

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