Semiconductor devices and manufacturing methods thereof

Abstract

This invention provides a semiconductor device for suppressing pixel aperture reduction. The semiconductor device of this invention includes: a first gate electrode; an oxide semiconductor layer disposed above the first gate electrode and comprising a first oxide semiconductor having a polycrystalline structure; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; and a second gate electrode disposed above the source electrode and the drain electrode and overlapping the first gate electrode and the oxide semiconductor layer; the second gate electrode comprising a second oxide semiconductor having a polycrystalline structure, and the second gate electrode being electrically connected to the first gate electrode.

Description

Semiconductor Device and Method for Manufacturing the Same One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor having a polycrystalline structure. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device using an oxide semiconductor having a polycrystalline structure. In recent years, a semiconductor device using an oxide semiconductor film as a channel instead of a silicon semiconductor film such as amorphous silicon, low-temperature polycrystalline silicon, and single-crystalline silicon has been developed (for example, refer to Patent Documents 1 to 6). The semiconductor device including the oxide semiconductor film has a simple structure like the semiconductor device including the amorphous silicon film and can be formed by a low-temperature process. Also, it is known that the semiconductor device including the oxide semiconductor film has a higher field-effect mobility than the semiconductor device including the amorphous silicon film. [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Patent Application Laid-Open No. 2021-141338 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-099601 [Patent Document 3] Japanese Patent Application Laid-Open No. 2021-153196 [Patent Document 4] Japanese Patent Application Laid-Open No. 2018-006730 [Patent Document 5] Japanese Patent Application Laid-Open No. 2016-184771 [Patent Document 6] Japanese Patent Application Laid-Open No. 2021-108405 [Problems to be Solved by the Invention] A semiconductor device is formed, for example, in a pixel of a display device. As the display device becomes high-definition, the semiconductor device not only needs to have a relatively high field-effect mobility but also needs to suppress a decrease in the aperture ratio of the pixel. One object of an embodiment of the present invention is to provide a semiconductor device that suppresses a decrease in the aperture ratio of the pixel. Another object of an embodiment of the present invention is to provide a method for manufacturing a semiconductor device that suppresses a decrease in the aperture ratio of the pixel. [Technical Means for Solving the Problems] A semiconductor device according to an embodiment of the present invention includes: a first gate electrode; an oxide semiconductor layer located above the first gate electrode and including a first oxide semiconductor having a polycrystalline structure; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; and a second gate electrode located above the source electrode and the drain electrode and overlapping the first gate electrode and the oxide semiconductor layer; the second gate electrode includes a second oxide semiconductor having a polycrystalline structure, and the second gate electrode is electrically connected to the first gate electrode. A method for manufacturing a semiconductor device according to an embodiment of the present invention forms a first gate electrode, forms an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure over the first gate electrode, forms a source electrode and a drain electrode in contact with the oxide semiconductor layer, forms a first oxide semiconductor film over the source electrode and the drain electrode, performs a heat treatment on the first oxide semiconductor film, forms a second gate electrode including a second oxide semiconductor having a polycrystalline structure, and forms a nitride layer covering the second gate electrode. Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following disclosure is merely an example. While ensuring the gist of the invention, configurations that can be easily conceived by those skilled in the art by appropriately changing the configurations of the embodiments are of course included in the scope of the present invention. To make the description clearer, compared with the actual aspect, the width, film thickness, shape, etc. of the constituent elements may be schematically shown in the drawings. However, the illustrated shape is merely an example and does not limit the interpretation of the present invention. In this specification and the drawings, the same reference numerals are given to the same constituent elements as those described above with respect to the already shown drawings, and the detailed description may be appropriately omitted sometimes. In this specification and the like, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". Thus, for convenience of explanation, the terms "above" or "below" are used for explanation, but the vertical relationship between the substrate and the oxide semiconductor layer may also be arranged in the opposite orientation to that shown in the drawings. Also, the expression "oxide semiconductor layer on the substrate" only explains the vertical relationship between the substrate and the oxide semiconductor layer, and other components may be arranged between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure having a plurality of stacked layers. In the case of expressing "a pixel electrode above the semiconductor device", it may also be a positional relationship where the semiconductor device and the pixel electrode do not overlap in a plan view. On the other hand, in the case of expressing "a pixel electrode vertically above the semiconductor device", it means a positional relationship where the semiconductor device and the pixel electrode overlap in a plan view. Furthermore, a plan view means observing from a direction perpendicular to the surface of the substrate. In this specification and the like, regarding the expressions "α includes A, B, or C", "α includes any one of A, B, and C", and "α includes one selected from the group consisting of A, B, and C", unless otherwise specified, the case where α includes a plurality of combinations of A to C is not excluded. Furthermore, these expressions do not exclude the case where α includes other constituent elements. In this specification and the like, the "semiconductor device" refers to all devices that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are included in one form of semiconductor devices. The semiconductor devices in the embodiments shown below can also be, for example, display devices, integrated circuits (ICs) such as micro-processing units (MPUs), or transistors used in memory circuits. In this specification and the like, the "display device" refers to a structure that displays an image using a photoelectric layer. For example, the term "display device" sometimes refers to a display panel including a photoelectric layer, or sometimes also refers to a structure formed by mounting other optical components (such as a polarizing component, a backlight, a touch panel, etc.) on a display unit. As long as there is no technical contradiction, the "photoelectric layer" can include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. In this specification and the like, the term "film" and the term "layer" can be interchangeably used as appropriate. Furthermore, as long as there is no technical contradiction, the following embodiments can be combined with each other. <First Embodiment> [1. Configuration of Display Device 1] Referring to FIGS. 1 and 2, a display device 1 including a semiconductor device 10 according to an embodiment of the present invention will be described. FIG. 1 is a schematic exploded perspective view showing the configuration of the display device 1. FIG. 2 is a schematic plan view showing the circuit configuration of the display device 1. As shown in FIG. 1, the display device 1 includes a display unit 2 and a light source unit 3. In the display device 1, the light source unit 3 emits light toward the display unit 2. The light source unit 3 includes, for example, a light emitting diode (LED). A plurality of LEDs can be used in the light source unit 3. When a plurality of LEDs are used in the light source unit 3, LEDs of the same color or different colors can be used. Furthermore, the light source unit 3 is not limited to a configuration including LEDs. The light source unit 3 only needs to include an element or a device that can emit light. Also, the light source unit 3 can include a light guide plate or an optical sheet, etc. In the display device 1 shown in FIG. 1, the light source unit 3 is disposed below the display unit 2, but the light source unit 3 can also be disposed beside the display unit 2. The display unit 2 includes a first substrate 100 and a second substrate 300. A liquid crystal layer (not shown) is sandwiched between the first substrate 100 and the second substrate 300. Also, as shown in FIG. 2, a display portion DP, a scanning line driving circuit GD (the scanning line driving circuit is sometimes referred to as a gate driver), a signal line driving circuit SD (the signal line driving circuit is sometimes referred to as a source driver), and a terminal portion TP are provided on the first substrate 100. The display portion DP is provided at the central portion of the first substrate 100. The scanning line driving circuit GD is provided outside the display portion DP in the y direction. The signal line driving circuit SD is provided outside the display portion DP in the x direction. The terminal portion TP is provided at the end of the first substrate 100. The scanning line driving circuit GD and the signal line driving circuit SD are electrically connected to the terminal portion TP. A flexible printed circuit board FPC is connected to the terminal portion TP, and signals from the driving element DRV are input to the terminal portion TP (refer to FIG. 1). That is, signals from the driving element DRV are input to the scanning line driving circuit GD and the signal line driving circuit SD via the terminal portion TP. The display portion DP includes a plurality of pixels PX, a plurality of scanning lines GL (the scanning lines are sometimes referred to as gate lines), and a plurality of signal lines SL (the signal lines are sometimes referred to as source lines). Each of the plurality of pixels PX is provided in a region surrounded by the scanning line GL and the signal line SL. The scanning line GL is electrically connected to the scanning line driving circuit GD and extends in the x direction. A first signal generated by the scanning line driving circuit GD is input to the scanning line GL. The signal line SL is electrically connected to the signal line driving circuit SD and extends in the y direction. A second signal generated by the signal line driving circuit SD is input to the signal line SL. Each of the plurality of pixels PX is controlled based on the first signal and the second signal. Each of the plurality of pixels PX includes a semiconductor device 10 and a liquid crystal element 20. The semiconductor device 10 shown in FIG. 2 is a so-called transistor, but the configuration of the semiconductor device 10 is not limited to the transistor itself. The semiconductor device 10 only needs to be a configuration including a transistor. In each of the plurality of pixels PX, the semiconductor device 10 is controlled based on the first signal and the second signal to drive the liquid crystal element 20. Furthermore, in the present embodiment, the semiconductor device 10 included in the pixel PX of the display device 1 is described, but the semiconductor device 10 can also be used in the scanning line driving circuit GD and the signal line driving circuit SD. Also, the display device 1 is a so-called liquid crystal display device, but it can also be other display devices. [2. Configuration of the semiconductor device 10] Referring to FIGS. 3 and 4, a semiconductor device 10 according to an embodiment of the present invention will be described. FIG. 3 is a schematic plan view showing the configuration of the semiconductor device 10 according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view showing the configuration of the semiconductor device 10 according to an embodiment of the present invention. FIG. 4 is a cross-sectional view of the semiconductor device 10 cut along the line A1-A2 in FIG. 3. As shown in FIG. 4, the semiconductor device 10 includes a first substrate 100, a first gate electrode 110, a scanning line 120, a first insulating layer 130, an oxide semiconductor layer 140, a source electrode 150, a drain electrode 160, a connection electrode 170, a second insulating layer 180, a second gate electrode 190, and a nitride layer 200. The first gate electrode 110 and the scanning line 120 are provided on the first substrate 100. The first insulating layer 130 covers the upper surfaces and end faces of the first gate electrode 110 and the scanning line 120, and is provided on the first gate electrode 110 and the scanning line 120. The first insulating layer 130 has a first opening OP1 that exposes a part of the upper surface of the scanning line 120. The oxide semiconductor layer 140 is provided on the first insulating layer 130 so as to overlap with the first gate electrode 110. Each of the source electrode 150 and the drain electrode 160 covers a part of the upper surface and a part of the end face of the oxide semiconductor layer 140, and is provided on the first insulating layer 130. The connection electrode 170 is provided on the first insulating layer 130 and is connected to the scanning line 120 via the first opening OP1. The second insulating layer 180 covers the upper surface of the oxide semiconductor layer 140, the upper surfaces and end faces of the source electrode 150, the upper surfaces and end faces of the drain electrode 160, and the upper surfaces and end faces of the connection electrode 170, and is provided on the first insulating layer 130. The second insulating layer 180 has a second opening OP2 that exposes a part of the connection electrode 170. The second gate electrode 190 is provided on the second insulating layer 180 so as to overlap with the oxide semiconductor layer 140 and the connection electrode 170. The second gate electrode 190 is connected to the connection electrode 170 via the second opening OP2. The nitride layer 200 covers the upper surface and end face of the second gate electrode 190, and is provided on the second insulating layer 180. As shown in FIG. 3, the first gate electrode 110 is provided so as to protrude in the y direction from the scanning line 120 extending in the x direction, and is continuously formed with the scanning line 120. In other words, the first gate electrode is formed in the same layer as the scanning line 120. Also, the source electrode 150, the drain electrode 160, and the connection electrode 170 are separately provided, but the source electrode 150, the drain electrode 160, and the connection electrode 170 are formed in the same layer. The first gate electrode 110 is continuously formed with the scanning line 120. In this case, the first gate electrode 110 may also be electrically connected to the scanning line. The second gate electrode 190 is electrically connected to the first gate electrode 110 via the connection electrode 170. Therefore, the voltage included in the signal input to the scanning line 120 is applied to both the first gate electrode 110 and the second gate electrode 190. The source electrode 150 is electrically connected to the signal line (the signal line here corresponds to the signal line SL in FIG. 2 and is not shown in FIGS. 3 and 4). The drain electrode 160 is electrically connected to a pixel electrode (not shown) provided in the pixel PX. The liquid crystal layer provided between the first substrate 100 and the second substrate 300 is driven by the electric field generated between the pixel electrode provided on the first substrate 100 and the counter electrode (not shown) provided on the second substrate 300. By driving the liquid crystal layer in each of the plurality of pixels PX, the transmission of light emitted from the light source unit 3 in each of the plurality of pixels PX is controlled. In the pixel PX, a part of the components of the semiconductor device 10 shields the light emitted from the light source unit 3. Depending on the configuration of the semiconductor device, there is a case where the aperture ratio of the pixel PX decreases. In particular, if the size of the pixel PX becomes smaller, the ratio of the semiconductor device to the size of the pixel PX becomes larger, so the aperture ratio of the pixel PX will decrease significantly. However, in the semiconductor device 10, since the second gate electrode 190 has light-transmitting properties, the decrease in the aperture ratio of the pixel PX can be suppressed. In a plan view, the second gate electrode 190 includes a region overlapping with any one of the first gate electrode 110, the scanning line 120, the source electrode 150, and the drain electrode 160 (hereinafter referred to as the "overlapping region"), and on the other hand, also includes a region not overlapping with the first gate electrode 110, the scanning line 120, the source electrode 150, and the drain electrode 160 (hereinafter referred to as the "non-overlapping region"). The non-overlapping region is the region through which the light emitted from the light source unit 3 passes. Therefore, if the non-overlapping region has light-shielding properties, the aperture ratio of the pixel PX decreases. However, in the semiconductor device 10, since the non-overlapping region of the second gate electrode 190 has light-transmitting properties, the degree of freedom in the arrangement of the second gate electrode 190 can be ensured and the decrease in the aperture ratio of the pixel PX can be suppressed. Here, each of the above-described components of the semiconductor device 10 will be described in more detail. Furthermore, the detailed configurations of the oxide semiconductor layer 140 and the second gate electrode 190 will be described below. The first substrate 100 can support the respective layers constituting the semiconductor device 10. For example, as the first substrate 100, a rigid substrate having translucency such as a glass substrate, a quartz substrate, or a sapphire substrate can be used. Also, as the first substrate 100, a rigid substrate without translucency such as a silicon substrate can be used. Further, as the first substrate 100, a flexible substrate having translucency such as a polyimide resin substrate, an acrylic resin substrate, a silicone resin substrate, or a fluororesin substrate can be used. In order to improve the heat resistance of the first substrate 100, impurities can also be introduced into the above flexible substrate. Furthermore, the second substrate 300 can use the same substrate as the first substrate 100. Each of the first insulating layer 130 and the second insulating layer 180 can function as a gate insulating layer. For example, as each of the first insulating layer 130 and the second insulating layer 180, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), or aluminum oxynitride (AlO x N y ) and other oxides, or silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum nitride (AlN x ), or aluminum oxynitride (AlN x O y ) and other nitrides can be used. Each of the first insulating layer 130 and the second insulating layer 180 can have a single-layer structure or a laminated structure. Here, silicon oxynitride (SiO x N y ) and aluminum oxynitride (AlO x N y ) are oxides containing nitrogen (N) in a ratio less than that of oxygen (O) (x > y), respectively. Also, silicon oxynitride (SiN x O y ) and aluminum oxynitride (AlN x O y ) is a nitride containing oxygen at a ratio less than nitrogen (x > y). Furthermore, for convenience of explanation, sometimes silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) are abbreviated as "silicon oxide", and silicon nitride (SiN x ) and silicon oxynitride (SiN x O y ) are abbreviated as "silicon nitride". Similarly, sometimes aluminum oxide (AlO x ) and aluminum oxynitride (AlO x N y ) are abbreviated as "aluminum oxide", and aluminum nitride (AlN x ) and aluminum oxynitride (AlN x O y ) are abbreviated as "aluminum nitride". The oxide semiconductor layer 140 is preferably in contact with the oxide. If the oxide semiconductor layer 140 is in contact with the oxide, oxygen can be supplied to the oxide semiconductor layer 140 from the oxide by heat treatment. Therefore, when each of the first insulating layer 130 and the second insulating layer 180 has a single-layer structure, it is preferable that each of the first insulating layer 130 and the second insulating layer 180 uses silicon oxide. Also, when the first insulating layer 130 has a stacked structure, the first insulating layer 130 preferably has a structure in which silicon oxide is stacked on silicon nitride in a manner of being in contact with the oxide semiconductor layer 140. Similarly, when the second insulating layer 180 has a stacked structure, the second insulating layer 180 preferably has a structure in which silicon nitride is stacked on silicon oxide in a manner of being in contact with the oxide semiconductor layer 140. The first gate electrode 110 preferably not only has conductivity but also has a function of reflecting or absorbing light emitted from the light source unit 3. That is, the first gate electrode 110 preferably has a light-shielding function. In a plan view, the first gate electrode 110 overlaps the entire oxide semiconductor layer 140 (see FIG. 3). Therefore, if the first gate electrode 110 has a light-shielding function, the light incident on the oxide semiconductor layer 140 can be blocked. As described above, the first gate electrode 110 is formed on the same layer as the scanning line 120. That is, the first gate electrode 110 is formed of the same material as the scanning line 120. For example, as the first gate electrode 110 and the scanning line 120, metals such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys or compounds thereof can be used. The first gate electrode 110 and the scanning line 120 may have a single-layer structure or a laminated structure. The source electrode 150, the drain electrode 160, and the connection electrode 170 have conductivity. As described above, the source electrode 150, the drain electrode 160, and the connection electrode 170 are formed on the same layer. That is, the source electrode 150, the drain electrode 160, and the connection electrode 170 are formed of the same material. As the source electrode 150, the drain electrode 160, and the connection electrode 170, the same materials as the first gate electrode 110 and the scanning line 120 can be used. The nitride layer 200 can function as an interlayer insulating layer. Also, as will be described in detail below, the nitride layer 200 can also function as a hydrogen supply layer for the second gate electrode 190. For example, as the nitride layer 200, silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum nitride (AlN x ), or aluminum oxynitride (AlN x O y ) and other nitrides can be used. [3. Structure of the oxide semiconductor layer 140] [3-1. Composition of the oxide semiconductor layer 140] As the oxide semiconductor layer 140, an oxide semiconductor containing two or more metal elements including indium (In) can be used. As the metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanide elements can be used. The oxide semiconductor layer 140 has translucency and has a polycrystalline structure including a plurality of crystal grains. In order for the oxide semiconductor layer 140 to have a polycrystalline structure, it is preferable to use an oxide semiconductor in which the ratio of indium to all metal elements is 50% or more in atomic ratio. When the ratio of indium becomes larger, the oxide semiconductor layer 140 is likely to crystallize. Also, as a metal element other than indium, it is preferable to include gallium. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer 140 is hardly hindered by gallium. The oxide semiconductor layer 140 has properties different from those of a conventional oxide semiconductor having a polycrystalline structure, and the details will be described below. Therefore, in order to distinguish the oxide semiconductor contained in the oxide semiconductor layer 140 from a conventional oxide semiconductor having a polycrystalline structure, hereinafter, the oxide semiconductor contained in the oxide semiconductor layer 140 will be referred to as Poly-OS (Poly-crystalline Oxide Semiconductor) for explanation. The Poly-OS contained in the oxide semiconductor layer 140 can be formed by a sputtering method and heat treatment. Here, the method for forming the oxide semiconductor layer 140 will be described. First, an oxide semiconductor film is formed by a sputtering method. The formed oxide semiconductor film has an amorphous structure. Here, the amorphous structure means a structure in which there is no long-range ordered structure and no periodic lattice arrangement is observed. For example, when an oxide semiconductor film having an amorphous structure is observed by an X-ray Diffraction (XRD) method, a specific peak based on a crystal structure cannot be obtained in the diffraction pattern. Furthermore, an oxide semiconductor film having an amorphous structure sometimes has a short-range ordered structure in a minute region. However, since such an oxide semiconductor film does not exhibit the characteristics of Poly-OS, it can be classified as an oxide semiconductor film having an amorphous structure. The oxide semiconductor film having an amorphous structure is formed at a low temperature. For example, the temperature of the substrate for forming the oxide semiconductor film is 150°C or lower, preferably 100°C or lower, and more preferably 50°C or lower. If the temperature of the substrate is high, microcrystals are likely to be generated in the oxide semiconductor to be formed. Also, the oxygen partial pressure in the chamber during film formation is 1% or more and 10% or less, preferably 1% or more and 5% or less, and more preferably 2% or more and 4% or less. If the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor film due to the excessive oxygen contained in the oxide semiconductor. On the other hand, under the condition that the oxygen partial pressure is less than 1%, the oxygen composition in the oxide semiconductor film becomes non-uniform, and an oxide semiconductor film containing a large amount of microcrystals or an oxide semiconductor film that does not crystallize even after heat treatment is formed. Next, the oxide semiconductor film formed by the sputtering method is heat-treated. The heat treatment is performed in the atmosphere, but the environment of the heat treatment is not limited thereto. The temperature of the heat treatment is 300°C or higher and 500°C or lower, preferably 350°C or higher and 450°C or lower. Also, the time of the heat treatment is 15 minutes or longer and 120 minutes or shorter, preferably 30 minutes or longer and 60 minutes or shorter. By performing the heat treatment, the oxide semiconductor film having an amorphous structure is crystallized to form an oxide semiconductor layer 140 containing Poly-OS. The composition of the oxide semiconductor layer 140 is substantially the same as the composition of the sputtering target. Therefore, the composition of the metal elements of the oxide semiconductor layer 140 can be specified based on the composition of the metal elements of the sputtering target. Also, the composition of the oxide semiconductor layer 140 can be specified using the XRD method. Specifically, the composition of the metal elements of the oxide semiconductor layer 140 can be specified based on the crystal structure and lattice constant of the oxide semiconductor layer 140 obtained from the XRD method. Furthermore, the composition of the metal elements of the oxide semiconductor layer 140 can also be specified using fluorescence X-ray analysis or electron probe micro analyzer (EPMA) analysis, etc. Moreover, the oxygen contained in the oxide semiconductor layer 140 varies depending on the process conditions of the sputtering method, etc., and thus is not limited thereto. [3-2. Characteristics of the oxide semiconductor layer 140] Next, the characteristics of the oxide semiconductor layer 140 containing Poly-OS are described. The oxide semiconductor layer 140 has excellent etching resistance. Specifically, the etching rate of the oxide semiconductor layer 140 when etched with an etching solution for wet etching is extremely small. This means that the oxide semiconductor layer 140 is hardly etched by the etching solution. When the oxide semiconductor layer 140 is etched at 40°C with an etching solution containing phosphoric acid as a main component (hereinafter referred to as "mixed acid etching solution"), the etching rate is less than 3 nm / min, less than 2 nm / min, or less than 1 nm / min. The ratio of phosphoric acid in the mixed acid etching solution is 50% or more, 60% or more, or 70% or more. The mixed acid etching solution may contain acetic acid and nitric acid in addition to phosphoric acid. Regarding an oxide semiconductor film not including Poly-OS, for example, an amorphous oxide semiconductor film before heat treatment, the etching rate when the oxide semiconductor film is etched with the mixed acid etching solution at 40°C is 100 nm / min or more. Also, when the oxide semiconductor layer 140 is etched with a 0.5% hydrofluoric acid solution at room temperature, the etching rate is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. Furthermore, regarding an oxide semiconductor film not including Poly-OS, the etching rate when the oxide semiconductor film is etched with a 0.5% hydrofluoric acid solution at room temperature is 15 nm / min or more. Here, "40°C" means 40 ± 5°C, which can be the temperature of the etching solution or the set temperature of the etching solution. Also, "room temperature" means 25 ± 5°C. Examples of the oxide semiconductor layer 140 are shown in Table 1. Table 1 shows the etching rates of each sample produced with respect to the mixed acid etching solution ("Mixed Acid AT-2F" manufactured by RASA Industries Co., Ltd. with a phosphoric acid ratio of 65% in the mixed acid etching solution) and a 0.5% hydrofluoric acid solution. Also, when etching each sample, the temperature of the mixed acid etching solution is 40°C, and the temperature of the 0.5% hydrofluoric acid solution is room temperature (22°C). In Table 1, Sample 1 is the oxide semiconductor layer 140 including Poly-OS, Sample 2 is an amorphous oxide semiconductor film before heat treatment, and Sample 3 is an oxide semiconductor film of indium gallium zinc oxide (IGZO) with an indium ratio of less than 50%. [Table 1] As shown in Table 1, regarding Sample 1 (including the oxide semiconductor layer 140 of Poly-OS), it was hardly etched when using a mixed acid etching solution. Even when using a 0.5% hydrofluoric acid solution, the etching rate was at most only 2 nm / min. In the etching using the mixed acid etching solution, the etching rate of Sample 1 was 1 / 100 or less of the etching rate of Sample 2 (the oxide semiconductor film with an amorphous structure before heat treatment). In the etching using a 0.5% hydrofluoric acid solution, the etching rate of Sample 1 was approximately 1 / 10 of the etching rate of Sample 2. Also, in the etching using the mixed acid etching solution, the etching rate of Sample 1 was 1 / 100 or less of the etching rate of Sample 3 (the oxide semiconductor film of IGZO with an indium ratio of less than 50%). That is, the etching resistance of Sample 1 was significantly superior to that of Sample 2 and Sample 3. This excellent etching resistance of the oxide semiconductor layer 140 including Poly-OS is a characteristic that cannot be obtained by the previously made oxide semiconductor with a polycrystalline structure through a process at 500°C or lower. Regarding the excellent etching resistance of the oxide semiconductor layer 140 including Poly-OS, the detailed mechanism is unclear, but it is considered that Poly-OS has a polycrystalline structure different from the previous ones. As described above, the etching rate of the oxide semiconductor layer 140 including Poly-OS with respect to the etching solution is very small. Therefore, patterning of the oxide semiconductor layer 140 is very difficult. Therefore, when forming the island-shaped oxide semiconductor layer 140, the oxide semiconductor film with an amorphous structure before heat treatment is patterned into an island shape, and then heat treatment is performed to crystallize it. Thereby, an island-shaped oxide semiconductor layer 140 including Poly-OS can be formed. [4. Configuration of the second gate electrode 190] If there are many oxygen defects in Poly-OS, carriers will be generated. Also, even if hydrogen is trapped in the oxygen defects, carriers will be generated. Thus, Poly-OS containing oxygen defects and hydrogen has conductivity. Also, the conductive Poly-OS has light transmissivity. Therefore, the conductive Poly-OS can be used as a transparent conductive material. In this embodiment, as the second gate electrode 190, conductive Poly-OS is used. As the second gate electrode 190, the same material as the oxide semiconductor layer 140 can be used. That is, as the second gate electrode 190, an oxide semiconductor containing two or more metal elements including indium (In) is used. Also, the second gate electrode 190 has a polycrystalline structure. The second gate electrode 190 including Poly-OS with conductivity can be formed by generating oxygen defects and supplying hydrogen, and the details will be described below. The sheet resistance of the second gate electrode 190 is 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq. or less. The film thickness of the second gate electrode 190 is, for example, 30 nm or more and 200 nm or less, preferably 50 nm or more and 180 nm or less, and more preferably 100 nm or more and 150 nm or less. If the film thickness of the second gate electrode 190 is less than 30 nm, the resistance of the second gate electrode 190 cannot be sufficiently reduced. Also, if the film thickness of the second gate electrode 190 is greater than 200 nm, the second gate electrode 190 includes a region where oxygen defects are not generated, and there is a case where the resistance of the second gate electrode 190 cannot be sufficiently reduced. Therefore, the film thickness of the second gate electrode 190 is preferably within the above range. [4. Manufacturing Method of Semiconductor Device 10] Referring to FIGS. 5 to 16, the manufacturing method of the semiconductor device 10 will be described. FIG. 5 is a flowchart illustrating the manufacturing method of the semiconductor device 10 according to an embodiment of the present invention. FIGS. 6 to 16 are schematic cross-sectional views illustrating the manufacturing method of the semiconductor device 10 according to an embodiment of the present invention. Hereinafter, each step of the flowchart shown in FIG. 5 will be described in order. In step S100, the first conductive film CF1 (refer to FIG. 6) is formed on the first substrate 100 using a sputtering method. In step S110, patterning of the first conductive film CF1 is performed using photolithography to form the first gate electrode 110 and the scanning line 120 (refer to FIG. 7). In step S120, the first insulating layer 130 covering the first gate electrode 110 and the scanning line 120 is formed using a CVD method (refer to FIG. 8). In step S130, an oxide semiconductor film OS1 is formed on the first insulating layer 130 using a sputtering method. The film formation conditions of the oxide semiconductor film OS1 are as described above. Since the oxide semiconductor film OS1 has an amorphous structure, it is easy to etch the oxide semiconductor film OS1. Therefore, patterning of the oxide semiconductor film OS1 is performed using photolithography (refer to FIG. 9). In step S140, a first heat treatment is performed on the oxide semiconductor film OS1. The conditions of the first heat treatment are as described above. By the first heat treatment, the oxide semiconductor film OS1 is crystallized to form an oxide semiconductor layer 140 including Poly-OS (refer to FIG. 10). In step S150, a first opening OP1 is formed in the first insulating layer 130 using photolithography (refer to FIG. 11). In the first opening OP1, a part of the scanning line 120 is exposed. In step S160, a second conductive film CF2 (see FIG. 12) covering the oxide semiconductor layer 140 and the first opening OP1 is formed by sputtering. For example, the second conductive film CF2 is a laminated film (Ti / Al / Ti film) containing titanium and aluminum. In step S170, the second conductive film CF2 is patterned by photolithography to form a source electrode 150, a drain electrode 160, and a connection electrode 170 (see FIG. 13). The source electrode 150 and the drain electrode 160 are in contact with the oxide semiconductor layer 140, and the connection electrode 170 is in contact with the scanning line 120 through the first opening OP1. The etching of the second conductive film CF2 is preferably wet etching using an etching solution. As described above, the oxide semiconductor layer 140 containing Poly-OS has excellent etching resistance. Therefore, when the second conductive film CF2 is etched using an etching solution, the oxide semiconductor layer 140 is hardly etched. Therefore, in the oxide semiconductor layer 140, the difference between the film thickness of the first region in contact with one of the source electrode 150 and the drain electrode and the film thickness of the second region not in contact with the source electrode 150 and the drain electrode is 3 nm or less. Furthermore, by adjusting the etching conditions, the difference between the film thickness of the first region and the film thickness of the second region can also be 2 nm or less, preferably 1 nm or less, and more preferably 0.5 nm or less. In step S180, the second insulating layer 180 is formed by CVD. Also, a second opening OP2 is formed in the second insulating layer 180 by photolithography. In the second opening OP2, a part of the connection electrode 170 is exposed. In step S190, an oxide semiconductor film OS2 is formed on the second insulating layer 180 by sputtering. The film formation conditions of the oxide semiconductor film OS2 are as described above. Since the oxide semiconductor film OS2 has an amorphous structure, it is easy to etch the oxide semiconductor film OS2. Therefore, the oxide semiconductor film OS2 is patterned by photolithography (see FIG. 15). In step S200, a second heat treatment is performed on the oxide semiconductor layer 140 and the oxide semiconductor film OS2. Depending on the process after forming the oxide semiconductor layer 140, oxygen defects may be generated in the oxide semiconductor layer 140. By performing the second heat treatment, oxygen is supplied to the oxide semiconductor layer 140 from the first insulating layer 130 and the second insulating layer 180 to repair the oxygen defects. In particular, during the second heat treatment, since the oxide semiconductor film OS2 is formed on the second insulating layer 180 so as to overlap with the oxide semiconductor layer 140, the oxide semiconductor film OS2 inhibits the release of oxygen in the second insulating layer 180 to the outside, thereby enabling efficient supply of oxygen to the oxide semiconductor layer 140. Also, by the second heat treatment, the oxide semiconductor film OS2 is crystallized to form the second gate electrode 190 (see FIG. 16) including Poly-OS. However, the resistance of the second gate electrode 190 formed in step S200 may not be sufficiently low. Therefore, step S210 is performed to make the resistance of the second gate electrode 190 sufficiently low. In step S210, a nitride layer 200 is formed by CVD method, sputtering method, or ALD method. As the nitride layer 200, silicon nitride is preferably used. Silicon nitride is formed by CVD method, but due to the reactive gas present in the chamber, oxygen defects are generated in the second gate electrode 190. Also, most of the gases used in the CVD method contain hydrogen, and a large amount of hydrogen exists in the chamber during film formation. Further, in the CVD method, the first substrate 100 is heated. Therefore, when silicon nitride is formed on the second gate electrode 190 in step S210, oxygen defects are generated in the second gate electrode 190, and hydrogen diffuses into the second gate electrode 190 and is trapped in the oxygen defects. Thereby, the resistance of the second gate electrode 190 is made sufficiently low. When the resistance of the second gate electrode 190 cannot be made sufficiently low only by forming the nitride layer 200, heat treatment may also be performed after step S210. Since the second gate electrode 190 is in contact with the nitride layer 200, by heat treatment, oxygen in the second gate electrode 190 is taken away by the nitride layer 200, and oxygen defects are generated in the second gate electrode 190. Also, by heat treatment, hydrogen contained in the nitride layer 200 diffuses into the second gate electrode 190. Thereby, the resistance of the second gate electrode 190 becomes lower. By the above steps, the semiconductor device 10 shown in FIGS. 3 and 4 is manufactured. The semiconductor device 10 thus manufactured has a 2 high field-effect mobility of 30 cm / Vs or more. According to the semiconductor device 10, since the second gate electrode 190 has light transmissivity, a reduction in the aperture ratio of the pixel PX can be suppressed. Further, according to the manufacturing method of the semiconductor device 10, repair of oxygen defects in the oxide semiconductor layer 140 containing Poly-OS and reduction of the resistance of the second gate electrode 190 containing Poly-OS can be performed by one heat treatment. Therefore, the manufacturing cost of the semiconductor device 10 can be suppressed. Furthermore, since the oxide semiconductor layer 140 contains Poly-OS and has excellent etching resistance, it has stable properties not only during the manufacture of the semiconductor device 10 but also after manufacture. Therefore, the semiconductor device 10 has high reliability. <Variation 1 of the First Embodiment> With reference to FIGS. 17 to 19, a variation of the manufacturing method of the semiconductor device 10 will be described. Further, hereinafter, the description of the configuration identical to that of the semiconductor device 10 may be omitted. FIG. 17 is a flowchart for explaining the manufacturing method of the semiconductor device 10 according to an embodiment of the present invention. FIGS. 18 and 19 are schematic cross-sectional views for explaining the manufacturing method of the semiconductor device 10 according to an embodiment of the present invention. Hereinafter, each step of the flowchart shown in FIG. 17 will be described in order. Steps S100 to S190 are the same as the steps described with reference to FIG. 5, and thus the description thereof is omitted here. In this variation, step S210 is performed after step S190 and before step S200. In step S210, a nitride layer 200 (see FIG. 18) is formed using a CVD method, a sputtering method, or an ALD method. In step S210 of this variation, the nitride layer 200 is formed on the amorphous oxide semiconductor film OS2. By forming the nitride layer 200, oxygen defects are generated in the oxide semiconductor film OS2, and hydrogen is trapped in the generated oxygen defects. After step S210, step S200 is performed. In step S200, a second heat treatment is performed on the oxide semiconductor layer 140 and the oxide semiconductor film OS2. In the second heat treatment, since the oxide semiconductor film OS2 is formed on the second insulating layer 180 so as to overlap with the oxide semiconductor layer 140, the oxide semiconductor film OS2 suppresses oxygen in the second insulating layer 180 from being released to the outside, and thus oxygen can be efficiently supplied to the oxide semiconductor layer 140. By the second heat treatment, the oxide semiconductor film OS2 is crystallized to form the second gate electrode 190 containing Poly-OS (see FIG. 19). In step S200 of this variation, since hydrogen is trapped in the oxygen defects of the oxide semiconductor film OS2, it is difficult to repair the oxygen defects. Therefore, the resistance of the second gate electrode 190 becomes low. By the above steps, the semiconductor device 10 shown in FIGS. 3 and 4 is manufactured. The semiconductor device 10 manufactured in this way also has 30 cm 2 A higher field-effect mobility of more than / Vs. In the semiconductor device 10 manufactured in this modification example, since the second gate electrode 190 has translucency, a reduction in the aperture ratio of the pixel PX can be suppressed. Further, according to the manufacturing method of the semiconductor device 10 in this modification example, the repair of the oxygen defects in the oxide semiconductor layer 140 containing Poly-OS and the reduction of the resistance of the second gate electrode 190 containing Poly-OS can be performed by one heat treatment. Therefore, the manufacturing cost of the semiconductor device 10 can be suppressed. Further, since the oxide semiconductor layer 140 contains Poly-OS and has excellent etching resistance, it has stable properties not only during the manufacturing of the semiconductor device 10 but also after manufacturing. Therefore, the semiconductor device 10 has high reliability. <Modification Example 2 of the First Embodiment> Referring to FIGS. 20 and 21, another modification example of the manufacturing method of the semiconductor device 10 will be described. Further, the description of the same configuration as that of the semiconductor device 10 may be omitted hereinafter. FIG. 20 is a flowchart for explaining the manufacturing method of the semiconductor device 10 according to an embodiment of the present invention. FIG. 21 is a schematic cross-sectional view for explaining the manufacturing method of the semiconductor device 10 according to an embodiment of the present invention. Hereinafter, each step of the flowchart shown in FIG. 20 will be described in order. Steps S100 to S190 and step S210 are the same as the steps described with reference to FIG. 17, and thus the description thereof will be omitted here. In this modification example, step S220 is performed after step S210 and before step S200. In step S220, an impurity element is added to the oxide semiconductor film OS2 using an ion implantation method to form an oxide semiconductor film OS3 (refer to FIG. 21) containing the impurity element and having an amorphous structure. The impurity element is added to the oxide semiconductor film OS2 via the nitride layer 200. For example, the impurity element is boron (B) or phosphorus (P), but is not limited thereto. Oxygen defects are generated in the oxide semiconductor film OS3 to which the impurity element is added. After step S220, step S200 is performed. In step S200, a second heat treatment is performed on the oxide semiconductor layer 140 and the oxide semiconductor film OS3. By the second heat treatment, the oxide semiconductor film OS2 is crystallized to form the second gate electrode 190 containing Poly-OS. Further, the second gate electrode 190 contains an impurity element. In Poly-OS in which oxygen defects are generated and which contains an impurity element, it is difficult to repair the oxygen defects due to the impurity element. Further, since hydrogen is trapped in the oxygen defects, the oxygen defects in Poly-OS are stabilized. Therefore, the conductivity of the second gate electrode 190 containing Poly-OS containing the impurity element is stable. By the above steps, the semiconductor device 10 shown in FIGS. 3 and 4 is manufactured. The semiconductor device 10 manufactured in this way also has a high field-effect mobility of 30 cm 2 / Vs or more. In the semiconductor device 10 manufactured in this modification, the second gate electrode 190 also has translucency, so that a reduction in the aperture ratio of the pixel PX can be suppressed. Further, according to the manufacturing method of the semiconductor device 10 in this modification, the repair of the oxygen defects of the oxide semiconductor layer 140 including Poly-OS and the low resistance of the second gate electrode 190 including Poly-OS can be performed by one heat treatment. Therefore, the manufacturing cost of the semiconductor device 10 can be suppressed. Further, since the oxide semiconductor layer 140 includes Poly-OS and has excellent etching resistance, it has stable properties not only during the manufacture of the semiconductor device 10 but also after manufacture. Further, the conductivity of the second gate electrode 190 is also stable. Therefore, the semiconductor device 10 has high reliability. <Variation 3 of the First Embodiment> Referring to FIGS. 22 and 23, a semiconductor device 10A as a variation of the semiconductor device 10 will be described. Further, the description of the same configuration as that of the semiconductor device 10 may be omitted hereinafter. FIG. 22 is a schematic plan view showing the configuration of a semiconductor device 10A according to an embodiment of the present invention. FIG. 23 is a schematic cross-sectional view showing the configuration of a semiconductor device 10A according to an embodiment of the present invention. In a plan view, the second gate electrode 190A is located between the source electrode 150 and the drain electrode 160. The second gate electrode 190A is spaced apart from the source electrode 150 by a gap g s and is arranged, and is spaced apart from the drain electrode 160 by a gap g d and is arranged. Here, the gap g s is the distance from one end face of the second gate electrode 190 to the end face of the source electrode 150, and the gap g d is the distance from the other end face of the second gate electrode 190A to the end face of the drain electrode 160. The gap g s may be the same as the gap g d or may be different from the gap g d The gap g s and the gap g dEach is 0.1 μm or more and 2.0 μm or less, preferably 0.3 μm or more and 1.5 μm or less, and more preferably 0.5 μm or more and 1.0 μm or less. In the semiconductor device 10A, by having the gap g s and the gap g d , it is possible to suppress an electrode short circuit between the second gate electrode 190A and the source electrode 150 or the drain electrode 160. In the semiconductor device 10A, due to the gap g s between the first gate electrode 110 and the oxide semiconductor layer 140 d and the gap g s , the corresponding regions overlap, so a channel is also formed in this region. If the gap g d and the gap g s are each less than 0.1 μm, an electrode short circuit is likely to occur between the second gate electrode 190A and the source electrode 150 or the drain electrode 160. Also, if the gap g d and the gap g s are each greater than 2.0 μm, the current flowing through the channel decreases, and thus the field effect mobility decreases. Therefore, the range of the gap g d is preferably the above range. As described above, in order to suppress an electrode short circuit between the second gate electrode 190A and the source electrode 150 or the drain electrode 160, in a plan view, the second gate electrode 190A does not overlap with the source electrode 150 and the drain electrode 160. As shown in FIG. 22, the second gate electrode 190A extends so as to surround the end portion of the drain electrode 160. Furthermore, the second gate electrode 190A may be electrically connected to the scanning line 120 as long as it extends so as to surround the end portion of one of the source electrode 150 and the drain electrode 160. According to the semiconductor device 10A, in a plan view, the second gate electrode 190A surrounds the end portion of the source electrode 150 or the drain electrode 160. Even when the area of the non-overlapping region is large, since the second gate electrode 190A has translucency, a decrease in the aperture ratio of the pixel PX can be suppressed. Also, in a plan view, the second gate electrode 190A does not overlap with the source electrode 150 and the drain electrode 160 and is arranged with a gap from the source electrode 150 and the drain electrode 160, whereby an electrode short circuit can be suppressed. Therefore, the semiconductor device 10A has high reliability. <Example 4 of the First Embodiment> Referring to FIG. 24, a semiconductor device 10B, which is another example of variation of the semiconductor device 10, will be described. Furthermore, the description of the same components as those of the semiconductor device 10 may be omitted hereinafter. FIG. 24 is a schematic plan view showing the configuration of a semiconductor device 10B according to an embodiment of the present invention. The semiconductor device 10B includes a plurality of oxide semiconductor layers 140 (a first oxide semiconductor layer 140-1, a second oxide semiconductor layer 140-2, and a third oxide semiconductor layer 140-3). Each of the first oxide semiconductor layer 140-1 to the third oxide semiconductor layer 140-3 is formed in an island shape. That is, the first oxide semiconductor layer 140-1 to the third oxide semiconductor layer 140-3 are arranged separately from each other. In the semiconductor device 10B having a high field-effect mobility, since a large current flows in the channel formed in the oxide semiconductor layer 140, the oxide semiconductor layer 140 may generate heat. In particular, the larger the area of the oxide semiconductor layer 140, the more significantly the oxide semiconductor layer 140 generates heat. Therefore, in the semiconductor device 10B, the area of one oxide semiconductor layer 140 is reduced, and a plurality of oxide semiconductor layers 140 are arranged. Thereby, the amount of current flowing in the channel can be maintained and the heat generation of the oxide semiconductor layer 140 can be suppressed. According to the semiconductor device 10B, since the second gate electrode 190 has translucency, a reduction in the aperture ratio of the pixel PX can be suppressed. Also, heat generation of the oxide semiconductor layer 140 can be suppressed in the semiconductor device 10B. Therefore, the semiconductor device 10B has high reliability. <Second Embodiment> The crystallinity of Poly-OS can be controlled by using a buffer layer. Therefore, in the present embodiment, a semiconductor device 11 including a buffer layer will be described. Furthermore, the description of the same components as those of the semiconductor device 10 may be omitted hereinafter. [1. Configuration of Semiconductor Device 11] Referring to FIG. 25, a semiconductor device 11 according to an embodiment of the present invention will be described. FIG. 25 is a schematic cross-sectional view showing the configuration of a semiconductor device 11 according to an embodiment of the present invention. As shown in FIG. 25, the semiconductor device 11 includes a first substrate 100, a first gate electrode 110, a scanning line 120, a first insulating layer 130, an oxide semiconductor layer 140, a source electrode 150, a drain electrode 160, a connection electrode 170, a second insulating layer 180, a metal oxide layer 210, a second gate electrode 190, and a nitride layer 200. The metal oxide layer 210 is disposed on the second insulating layer 180 so as to overlap with the oxide semiconductor layer 140. The second insulating layer 180 and the metal oxide layer 210 have a second opening OP2 that exposes a part of the upper surface of the connection electrode 170. The second gate electrode 190 is disposed on the metal oxide layer 210 in contact with the metal oxide layer 210. The second gate electrode 190 has a plan view shape substantially the same as that of the metal oxide layer 210. That is, the end face of the second gate electrode 190 substantially coincides with the end face of the metal oxide layer 210. The second gate electrode 190 is connected to the connection electrode 170 via the second opening OP2. The nitride layer 200 covers the end face of the metal oxide layer 210 and the upper surface and end face of the second gate electrode 190, and is disposed on the second insulating layer 180. The metal oxide layer 210 can function as a buffer layer for improving the crystallinity of the Poly-OS contained in the second gate electrode 190. The second gate electrode 190 including the Poly-OS with improved crystallinity has a lower resistance. As the metal oxide layer 210, for example, a metal oxide mainly composed of aluminum can be used. The ratio of aluminum contained in the metal oxide layer 210 can be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer 210. The above ratio can be a mass ratio or a weight ratio. The film thickness of the metal oxide layer 210 is 1 nm or more and 10 nm or less, preferably 1 nm or more and 5 nm or less. As the metal oxide layer 210, alumina is preferably used. Alumina has a high barrier property against gases such as oxygen or hydrogen. Here, the barrier property refers to the function of suppressing the permeation of gases such as oxygen or hydrogen. Furthermore, as the metal oxide layer 210, a metal oxide mainly composed of a metal other than aluminum can also be used. For example, as the metal oxide layer 210, indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO) can be used. [2. Manufacturing method of the semiconductor device 11] Referring to FIGS. 26 to 31, the manufacturing method of the semiconductor device 11 will be described. FIG. 26 is a flowchart for explaining a method of manufacturing a semiconductor device 11 according to an embodiment of the present invention. FIGS. 27 to 31 are schematic cross-sectional views for explaining a method of manufacturing a semiconductor device 11 according to an embodiment of the present invention. Hereinafter, each step of the flowchart shown in FIG. 26 will be described in order. Steps S100 to S170 are the same as the steps described with reference to FIG. 5 in the first embodiment, and thus the description thereof is omitted here. In the manufacture of the semiconductor device 11, after step S170, step S181 is carried out. In step S181, a second insulating layer 180 and a metal oxide film MO (refer to FIG. 27) are sequentially formed. The second insulating layer 180 is formed by a CVD method. The metal oxide film MO is formed by a sputtering method or an atomic layer deposition method (ALD method). For example, the second insulating layer 180 contains silicon oxide in contact with the oxide semiconductor layer 140. Also, for example, alumina is used as the metal oxide film MO. After step S181, step S182 is carried out. In step S182, a second opening OP2 (refer to FIG. 28) is formed in the second insulating layer 180 and the metal oxide film MO by photolithography. In the second opening OP2, a part of the connection electrode 170 is exposed. After step S182, step S190 is carried out. In step S190, an oxide semiconductor film OS2 is formed on the metal oxide film MO by a sputtering method. The film formation conditions of the oxide semiconductor film OS2 are as described above. Since the oxide semiconductor film OS2 has an amorphous structure, it is easy to etch the oxide semiconductor film OS2. Therefore, the oxide semiconductor film OS2 is patterned by photolithography (refer to FIG. 29). The oxide semiconductor film OS2 is in contact with the connection electrode 170 through the second opening OP2. After step S190, step S200 is carried out. In step S200, a second heat treatment is performed on the oxide semiconductor layer 140 and the oxide semiconductor film OS2. In the second heat treatment, since the metal oxide film MO covering the second insulating layer 180 is formed, the metal oxide film MO inhibits the release of oxygen in the second insulating layer 180 to the outside, so that oxygen can be efficiently supplied to the oxide semiconductor layer 140. Also, by the second heat treatment, the oxide semiconductor film OS2 is crystallized to form a second gate electrode 190 including Poly-OS (refer to FIG. 30). The metal oxide film MO functions as a buffer layer to control the crystallinity of the second gate electrode 190. Specifically, the size of the crystal grains contained in the second gate electrode 190 increases, and the crystallinity of the second gate electrode 190 increases. After step S200, step S230 is carried out. In step S230, using the second gate electrode 190 as a mask, the metal oxide film MO is patterned to form a metal oxide layer 210 (refer to FIG. 31). The second gate electrode 190 including Poly-OS has excellent etching resistance. Therefore, even when etching the metal oxide film MO during the patterning of the metal oxide film MO, the second gate electrode 190 used as a mask is not etched. In the semiconductor device 11, the second gate electrode 190 can be used as a mask during the formation of the metal oxide layer 210, so the photolithography process can be omitted. After step S230, step S210 is implemented. In step S210, a nitride layer 200 is formed by a CVD method, a sputtering method, or an ALD method. If the nitride layer 200 is formed on the second gate electrode 190, oxygen defects are generated in the second gate electrode 190, and hydrogen diffuses into the second gate electrode 190 and is trapped in the oxygen defects. Thereby, the resistance of the second gate electrode 190 is made sufficiently low. Through the above steps, the semiconductor device 11 shown in FIG. 25 is manufactured. The semiconductor device 11 manufactured in this way has 30 cm 2 / Vs or higher field-effect mobility. According to the semiconductor device 11, since the second gate electrode 190 has light transmittance, a reduction in the aperture ratio of the pixel PX can be suppressed. Also, according to the manufacturing method of the semiconductor device 11, the repair of the oxygen defects of the oxide semiconductor layer 140 including Poly-OS and the low-resistance conversion of the second gate electrode 190 including Poly-OS can be performed by one heat treatment. Therefore, the manufacturing cost of the semiconductor device 11 can be suppressed. Furthermore, the crystallinity of the second gate electrode 190 is increased by the metal oxide layer 210 and is relatively stable. Therefore, the semiconductor device 11 has high reliability. <Variation Example of the Second Embodiment> Referring to FIGS. 32 to 39, a semiconductor device 11C as a variation example of the semiconductor device 11 will be described. Furthermore, the description of the same configuration as that of the semiconductor device 10 may be omitted hereinafter. Also, hereinafter, for convenience of explanation, the connection electrode 170 described in the first embodiment will be described as the first connection electrode 170. [1. Configuration of the Semiconductor Device 11C] FIG. 32 is a schematic plan view showing the configuration of a semiconductor device 11C according to an embodiment of the present invention. FIG. 33 is a schematic cross-sectional view showing the configuration of a semiconductor device 11C according to an embodiment of the present invention. FIG. 33 is a cross-sectional view of the semiconductor device 11C cut along the line B1-B2 in FIG. 32. As shown in FIG. 33, the semiconductor device 11C includes a first substrate 100, a first gate electrode 110, a scanning line 120, a first insulating layer 130, an oxide semiconductor layer 140, a source electrode 150, a drain electrode 160, a first connection electrode 170, a second insulating layer 180, a metal oxide layer 210C, a second gate electrode 190C, a nitride layer 200, a third insulating layer 220, and a second connection electrode 230. The metal oxide layer 210C is disposed on the second insulating layer 180 so as to overlap with the oxide semiconductor layer 140. The second gate electrode 190C is disposed on the metal oxide layer 210C so as to be in contact with the metal oxide layer 210C. The second gate electrode 190C has a plan view shape substantially the same as that of the metal oxide layer 210C. That is, the end surface of the second gate electrode 190C substantially coincides with the end surface of the metal oxide layer 210C. In plan view, the metal oxide layer 210C and the second gate electrode 190C do not overlap with the first connection electrode 170. The nitride layer 200 covers the end surface of the metal oxide layer 210C, the upper surface and the end surface of the second gate electrode 190C, and is disposed on the second insulating layer 180. The third insulating layer 220 is disposed on the nitride layer 200. The second insulating layer 180, the nitride layer 200, and the third insulating layer 220 have a second opening OP2 that exposes a part of the upper surface of the first connection electrode 170. Further, the nitride layer 200 and the third insulating layer 220 have a third opening OP3 that exposes a part of the upper surface of the second gate electrode 190. The second connection electrode 230 is disposed on the third insulating layer 220. The second connection electrode 230 is connected to the first connection electrode 170 via the second opening OP2 and is connected to the second gate electrode 190C via the third opening OP3. As shown in FIG. 32, the second gate electrode 190C is separately provided from the first connection electrode 170. However, as described above, the second connection electrode 230 is connected to the first connection electrode 170 and the second gate electrode 190C. Therefore, the second gate electrode 190C is electrically connected to the first gate electrode 110 via the first connection electrode 170 and the second connection electrode 230. Accordingly, the voltage included in the signal input to the scanning line 120 is applied to both the first gate electrode 110 and the second gate electrode 190C. The third insulating layer 220 can function as an interlayer insulating layer. For example, as the third insulating layer 220, the same material as that of the first insulating layer 130 and the second insulating layer 180 can be used. Also, the third insulating layer 220 can also function as a planarization layer. In this case, for example, as the third insulating layer 220, a resin such as polyimide or acrylic resin can be used. This resin can also be a photosensitive resin. When a photosensitive resin is used as the third insulating layer 220, a photoresist does not need to be coated, and the photosensitive resin can be directly exposed to light and etched, so the process using photolithography is simplified. Also, the third insulating layer 220 can have a single-layer structure or a laminated structure. When the third insulating layer 220 has a laminated structure, the third insulating layer 220 can also have a structure in which a resin is laminated on an oxide or a nitride. The second connection electrode 230 has conductivity. As the second connection electrode 230, the same material as that of the first connection electrode 170 can be used. Also, as the second connection electrode 230, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) can be used. The second connection electrode 230 is disposed not only overlapping with the source electrode 150 or the drain electrode 160, but also overlapping with the scanning line 120, so the aperture ratio of the pixel PX is hardly reduced. Therefore, as the second connection electrode 230, not only a material having light transmissivity can be used, but also a material not having light transmissivity can be used. [2. Manufacturing method of semiconductor device 11C] Referring to FIGS. 34 to 39, the manufacturing method of the semiconductor device 11C will be described. FIG. 34 is a flowchart illustrating a manufacturing method of a semiconductor device 11C according to an embodiment of the present invention. FIGS. 35 to 39 are schematic cross-sectional views illustrating a manufacturing method of a semiconductor device 11C according to an embodiment of the present invention. Hereinafter, each step of the flowchart shown in FIG. 34 will be described in sequence. Steps S100 to S170 and step S181 are the same as the steps described with reference to FIG. 26, so the description thereof is omitted here. In the manufacturing of the semiconductor device 11C, after step S170, step S190 is implemented. In step S190, an oxide semiconductor film OS2 is formed on the metal oxide film MO by a sputtering method. The film formation conditions of the oxide semiconductor film OS2 are as described above. Since the oxide semiconductor film OS2 has an amorphous structure, it is easy to etch the oxide semiconductor film OS2. Therefore, the oxide semiconductor film OS2 is patterned using photolithography (refer to FIG. 35). After step S190, step S200 is implemented. In step S200, a second heat treatment is performed on the oxide semiconductor layer 140 and the oxide semiconductor film OS2. In the second heat treatment, since the metal oxide film MO covering the second insulating layer 180 is formed, the metal oxide film MO suppresses the release of oxygen in the second insulating layer 180 to the outside, so that oxygen can be efficiently supplied to the oxide semiconductor layer 140. Also, by the second heat treatment, the oxide semiconductor film OS2 is crystallized to form the second gate electrode 190C (refer to FIG. 36) including Poly-OS. The metal oxide film MO functions as a buffer layer to control the crystallinity of the second gate electrode 190C. Specifically, the size of the crystal grains included in the second gate electrode 190C increases, and the crystallinity of the second gate electrode 190C increases. After step S200, step S230 is implemented. In step S230, using the second gate electrode 190C as a mask, the metal oxide film MO is patterned to form the metal oxide layer 210C (refer to FIG. 37). The second gate electrode 190C including Poly-OS has excellent etching resistance. Therefore, even when the metal oxide film MO is etched in the patterning of the metal oxide film MO, the second gate electrode 190C used as a mask is not etched. In the semiconductor device 11C, in the formation of the metal oxide layer 210C, the second gate electrode 190C can be used as a mask, so the photolithography process can be omitted. After step S230, step S210 is implemented. In step S210, the nitride layer 200 (refer to FIG. 38) is formed by CVD method, sputtering method, or ALD method. Oxygen defects are generated in the second gate electrode 190C, and hydrogen diffuses into the second gate electrode 190C and is trapped in the oxygen defects. Thereby, the resistance of the second gate electrode 190C is made sufficiently low. After step S210, step S240 is implemented. In step S240, using the coating method, the third insulating layer 220 is formed on the second insulating layer 180. Also, using the photolithography method, the second opening OP2 penetrating the second insulating layer 180, the nitride layer 200, and the third insulating layer 220 and the third opening OP3 penetrating the nitride layer 200 and the third insulating layer 220 are formed (refer to FIG. 39). When the third insulating layer 220 has photosensitivity, the second opening OP2 and the third opening OP3 can be formed without using a photoresist. In the second opening OP2, a part of the first connection electrode 170 is exposed. In the third opening OP3, a part of the second gate electrode 190C is exposed. After step S240, step S250 is implemented. In step S250, a fourth conductive film is formed on the third insulating layer 220 by sputtering, and the fourth conductive film is patterned by photolithography to form the second connection electrode 230. The second connection electrode 230 is connected to the first connection electrode 170 via the second opening OP2 and is connected to the second gate electrode 190C via the third opening OP3. Through the above steps, the semiconductor device 11C shown in FIGS. 32 and 33 is manufactured. The semiconductor device 11C manufactured in this way has a length of 30 cm 2 / Vs or higher field effect mobility. In the semiconductor device 11C, since the second gate electrode 190 has light transmissivity, a decrease in the aperture ratio of the pixel PX can be suppressed. Further, in the manufacturing method of the semiconductor device 11C, repair of oxygen defects in the oxide semiconductor layer 140 including Poly-OS and reduction of the resistance of the second gate electrode 190 including Poly-OS can be performed by one heat treatment. Therefore, the manufacturing cost of the semiconductor device 11C can be suppressed. Furthermore, the crystallinity of the second gate electrode 190 is increased by the metal oxide layer 210 and is more stable. Therefore, the semiconductor device 11C has high reliability. As long as the above-described embodiments and variations of the embodiments of the present invention are not mutually contradictory, they can be appropriately combined and implemented. Also, those obtained by appropriately adding, deleting, or changing the design of components, or those obtained by adding, omitting, or changing conditions of processes based on the embodiments and variations, as long as they have the gist of the present invention, are also included in the scope of the present invention. Even if there are other effects different from the effects brought about by the aspects of the above-described embodiments, those clearly described in this specification or those that can be easily predicted by those skilled in the art can of course be understood as the effects brought about by the present invention. 1: Display device 2: Display unit 3: Light source unit 10, 10A, 10B, 11, 11C: Semiconductor device 20: Liquid crystal element 100: First substrate 110: First gate electrode 120: Scan line 130: First insulating layer 140: Oxide semiconductor layer 140-1: First oxide semiconductor layer 140-2: Second oxide semiconductor layer 140-3: Third oxide semiconductor layer 150: Source electrode 160: Drain electrode 170: Connection electrode (first connection electrode) 180: Second insulating layer 190, 190A, 190C: Second gate electrode 200: Nitride layer 210, 210C: Metal oxide layer 220: Third insulating layer 230: Second connection electrode 300: Second substrate CF1: First conductive film CF2: Second conductive film DP: Display section DRV: Driving element FPC: Flexible printed circuit board GD: Scan line driving circuit GL: Scan line g s , g d : Gap MO: Metal oxide film OP1: First opening OP2: Second opening OP3: Third opening OS1, OS2, OS3: Oxide semiconductor film PX: Pixel SD: Signal line driving circuit SL: Signal line S100~S250: Steps TP: Terminal section x: Direction y: Direction z: Direction FIG. 1 is a schematic exploded perspective view showing the configuration of a display device. FIG. 2 is a schematic top view showing the circuit configuration of the display device. FIG. 3 is a schematic top view showing the configuration of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. FIG. 5 is a flowchart for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 7 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 8 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 10 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 11 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 12 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 13 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 14 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 15 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 16 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 17 is a flowchart for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 18 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the invention. FIG. 19 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the invention. FIG. 20 is a flowchart for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 21 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the invention. FIG. 22 is a schematic top view showing the configuration of a semiconductor device according to an embodiment of the present invention. FIG. 23 is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. FIG. 24 is a schematic top view showing the configuration of a semiconductor device according to an embodiment of the present invention. FIG. 25 is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. FIG. 26 is a flowchart for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 27 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 28 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 29 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 30 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.FIG. 31 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 32 is a schematic plan view showing the configuration of a semiconductor device according to an embodiment of the present invention. FIG. 33 is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. FIG. 34 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 35 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 36 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 37 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 38 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 39 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 10: Semiconductor device 100: First substrate 110: First gate electrode 120: Scan line 130: First insulating layer 140: Oxide semiconductor layer 150: Source electrode 160: Drain electrode 170: Connection electrode (first connection electrode) 180: Second insulating layer 190: Second gate electrode 200: Nitride layer OP1: First opening OP2: Second opening

Claims

1. A semiconductor device comprising: a first gate electrode; an oxide semiconductor layer disposed above the first gate electrode and comprising a first oxide semiconductor having a polycrystalline structure; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; and a second gate electrode disposed above the source electrode and the drain electrode and overlapping the first gate electrode and the oxide semiconductor layer; wherein the second gate electrode comprises a second oxide semiconductor having a polycrystalline structure, the second gate electrode is electrically connected to the first gate electrode, and in plan view, the second gate electrode overlaps with at least one of the source electrode and the drain electrode.

2. The semiconductor device of claim 1, wherein the sheet resistance of the second gate electrode is 1000 Ω / sq. or less.

3. The semiconductor device of claim 1, wherein, in plan view, the second gate electrode is disposed with a gap between it and each of the source electrode and the drain electrode.

4. The semiconductor device of claim 3, wherein, in the above top view, the second gate electrode extends in a manner that surrounds the end of one of the source electrode and the drain electrode.

5. The semiconductor device of claim 1, further comprising a metal oxide layer connected to the second gate electrode below the second gate electrode.

6. The semiconductor device of claim 5, further comprising a connection electrode connected to the second gate electrode on the second gate electrode, and the second gate electrode being electrically connected to the first gate electrode via the connection electrode.

7. The semiconductor device of claim 1, wherein the oxide semiconductor layer comprises: a first region connected to one of the source electrode and the drain electrode; and a second region overlapping the second gate electrode between the source electrode and the drain electrode; wherein the difference between the thickness of the first region and the thickness of the second region is 3 nm or less.

8. The semiconductor device of claim 1, wherein the etching rate when etching the oxide semiconductor layer at 40°C using an etchant containing phosphoric acid as the main component does not reach 3 nm / min.

9. The semiconductor device of claim 8, wherein the etching solution comprises nitric acid and acetic acid.

10. The semiconductor device of claim 8, wherein the oxide semiconductor layer is formed by heat treatment of an oxide semiconductor film having an amorphous structure, and the etching rate when the oxide semiconductor film is etched at the aforementioned etch solution at the aforementioned 40°C is 100 nm / min or more.

11. The semiconductor device of claim 1, wherein the etching rate when etching the oxide semiconductor layer at room temperature using a 0.5% hydrofluoric acid solution does not reach 5 nm / min.

12. A method for manufacturing a semiconductor device, comprising the steps of: forming a first gate electrode; forming an oxide semiconductor layer comprising a first oxide semiconductor having a polycrystalline structure on the first gate electrode; forming a source electrode and a drain electrode in contact with the oxide semiconductor layer; forming a first oxide semiconductor film on the source electrode and the drain electrode; performing a heat treatment on the first oxide semiconductor film to form a second gate electrode comprising a second oxide semiconductor having a polycrystalline structure; forming a nitride layer covering the second gate electrode, wherein the oxide semiconductor layer comprises: a first region in contact with one of the source electrode and the drain electrode; and a second region overlapping the second gate electrode between the source electrode and the drain electrode; wherein the difference in film thickness between the first region and the second region is 3 nm or less.

13. The method for manufacturing a semiconductor device as claimed in claim 12, wherein the etching rate when etching the oxide semiconductor layer at 40°C using an etchant containing phosphoric acid as the main component does not reach 3 nm / min.

14. The method for manufacturing a semiconductor device as claimed in claim 13, wherein the etching solution comprises nitric acid and acetic acid.

15. The method for manufacturing a semiconductor device as claimed in claim 13, wherein the oxide semiconductor layer is formed by heat treatment of an oxide semiconductor film having an amorphous structure, and the etching rate when etching the oxide semiconductor film with the etching solution at the aforementioned 40°C is 100 nm / min or higher.

16. The method for manufacturing a semiconductor device as claimed in claim 12, wherein the etching rate when etching the oxide semiconductor layer at room temperature using a 0.5% hydrofluoric acid solution does not reach 5 nm / min.

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