Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a source region in the substrate, a drain region in the substrate, a gate structure on the substrate, and a first well region in the substrate. The drain region has a drain sidewall facing the source region. The gate structure is located between the source region and the drain region. The gate structure has a first gate sidewall facing the drain region. The first well region is below the drain region. The first well region has a well region sidewall facing the source region. A first distance between the first gate sidewall and the drain sidewall is less than or equal to a second distance between the first gate sidewall and the well region sidewall.

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices including electrostatic discharge protection structures. [Previous Technology]

[0002] Electrostatic discharge (ESD) is the phenomenon of static charge transfer between different objects. ESD typically generates current for a short time, and this current flowing into semiconductor components can damage them. ESD protection structures help mitigate or avoid the damage caused by static electricity by providing a path for the ESD discharge to occur. ESD protection structures typically require low breakdown voltage (VBD) and low trigger voltage (Vt1) to ensure their efficiency and reliability. During ESD, if the breakdown voltage and trigger voltage of the ESD protection structure are high, the ESD discharge may pass through the protected component before the protection structure activates, causing damage. [Summary of the Invention]

[0003] The present invention provides a semiconductor device comprising an electrostatic discharge protection structure with low breakdown voltage and low trigger voltage, which has good efficiency and reliability.

[0004] According to one embodiment, a semiconductor device is provided. The semiconductor device includes a substrate, a source region in the substrate, a drain region in the substrate, a gate structure on the substrate, and a first well region in the substrate. The drain region has a drain sidewall facing the source region. The gate structure is located between the source region and the drain region. The gate structure has a first gate sidewall facing the drain region. The first well region is below the drain region. The first well region has a well region sidewall facing the source region. A first distance between the first gate sidewall and the drain sidewall is less than or equal to a second distance between the first gate sidewall and the well region sidewall.

[0005] According to one embodiment, a semiconductor device is provided. The semiconductor device includes a substrate, a source region in the substrate, a drain region in the substrate, a gate structure on the substrate, and a first well region in the substrate. The gate structure is located between the source region and the drain region. The gate structure has a gate sidewall facing the drain region. The first well region is below the drain region. The first well region has a well region sidewall facing the source region. The well region sidewall is aligned with or substantially aligned with the gate sidewall.

[0006] In order to better understand the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.

Implementation Method

[0008] The drawings are simplified to clearly illustrate the embodiments, and the dimensions in the drawings are not drawn to scale with the actual product. In the following manufacturing methods, there may be one or more additional operations between the operations, and the order of the operations may vary. Therefore, the specification and drawings are for illustrative purposes only and are not intended to limit the scope of protection of the invention. The following description uses the same / similar symbols to denote the same / similar elements.

[0009] The ordinal numbers used to modify elements in the specification and claims, such as "first," "second," etc., do not imply or represent a specific position, arrangement, or manufacturing order in the structure; these ordinal numbers are merely used to clearly distinguish multiple elements with the same name. Spatial terms used in the specification and claims, such as "above," "above," "above," "higher than," "top," "below," "below," "below," "lower than," "bottom," etc., are used to describe the relative spatial or positional relationship between one element and another element in the drawings, and these spatial or positional relationships can be direct or indirect (with other elements disposed between the two elements), unless otherwise specified. Spatial terms may cover structures shown in other orientations, not limited to the orientation shown in the drawings. Structures can be flipped or rotated at various angles, and the spatial descriptions used herein can be interpreted accordingly. The singular forms "a" and "the" used in the specification and claims are also intended to include the plural forms, unless the context clearly indicates otherwise. The use of "and / or" in the specification and claims includes any and all combinations of one or more of the listed items. The term "adjacent" in the specification and accompanying claims means "adjacent and in contact".

[0010] Please refer to Figures 1 and 2. Figure 1 is a schematic diagram illustrating the layout of a semiconductor device 10 according to an embodiment of the present invention. The cross-sectional structure of the semiconductor device 10 drawn along the cross-sectional line AA' shown in Figure 1 may have the structure shown in Figure 2. The semiconductor device 10 includes a substrate 10S and an electrostatic discharge protection structure 10E. The substrate 10S may be formed of a semiconductor material, such as single-crystal silicon, polycrystalline silicon, germanium, diamond, gallium arsenide, silicon carbide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, or any combination thereof. For example, the substrate 10S may be a silicon substrate or a silicon on insulator (SOI) substrate. The substrate 10S may selectively include one or more layers formed on the semiconductor substrate. The substrate 10S includes dopants, such as electron donors or electron acceptors. Depending on the type of dopant, the substrate 10S may have a first conductivity type or a second conductivity type different from the first conductivity type. For example, the first conductivity type is N-type, and the second conductivity type is P-type. An electrostatic discharge (ESD) protection structure 10E is located in the substrate 10S. The ESD protection structure 10E may be an extended-drain metal-oxide-semiconductor field-effect transistor (MOSFET) or a laterally diffused MOSFET. The present invention is described below using a substrate 10S having a second conductivity type (P-type) and an N-type extended-drain MOSFET as an example, but the present invention is not limited thereto.

[0011] The electrostatic discharge protection structure 10E includes a source region 114a, a drain region 116, a gate structure 112a, and a first well region 132. The source region 114a is in the substrate 10S. The drain region 116 is in the substrate 10S. The gate structure 112a is on the substrate 10S. The gate structure 112a is located between the source region 114a and the drain region 116. The first well region 132 is in the substrate 10S. At least a portion of the first well region 132 is below the drain region 116. The drain region 116 has a drain sidewall 116S facing the source region 114a. The gate structure 112a has a first gate sidewall 112S1 facing the drain region 116. The first well region 132 has a well sidewall 132S facing the source region 114a. The first distance D1 (in the lateral direction) between the first gate sidewall 112S1 and the drain sidewall 116S is less than the second distance D2 (in the lateral direction) between the first gate sidewall 112S1 and the well site sidewall 132S. The second distance D2 may be less than or equal to 2 micrometers. The second distance D2 may be greater than or equal to 0 and less than or equal to 2 micrometers. The gate structure 112a may also have a second gate sidewall 112S2 relative to the first gate sidewall 112S1. The second gate sidewall 112S2 may face the source region 114a. The third distance D3 (in the lateral direction) between the second gate sidewall 112S2 and the drain sidewall 116S is less than the fourth distance D4 (in the lateral direction) between the second gate sidewall 112S2 and the well site sidewall 132S.

[0012] In this embodiment, the first well region 132 is completely below the drain region 116, and the width of the drain region 116 in the lateral direction is greater than the width of the first well region 132 in the lateral direction. The lower surface 116L of the drain region 116 is not completely covered by the first well region 132. The drain sidewall 116S of the drain region 116 may not contact the first well region 132.

[0013] The drain sidewall 116S of the drain region 116 may be located between the well sidewall 132S of the first well region 132 and the first gate structure sidewall 112S1 of the gate structure 112a. The gate structure 112a and the first well region 132 do not overlap in the longitudinal direction. The arrangement of the first well region 132 allows the current to flow downwards and away from the surface, thereby improving the electrostatic discharge protection capability.

[0014] The electrostatic discharge protection structure 10E may further include a second well region 134a, a third well region 104, a deep well region 102, a doped region 118a, an isolation structure 141, a guard ring 160, an isolation structure 143, a guard ring 162, and a spacer element 151a. The second well region 134a, the third well region 104, and the deep well region 102 are in the substrate 10S. The third well region 104 is in the deep well region 102. As shown in Figure 1, the deep well region 102 surrounds the third well region 104. The deep well region 102 surrounds the source region 114a and the drain region 116. The drain region 116, the source region 114a, the doped region 118a, the first well region 132, and the second well region 134a are in the third well region 104. A portion of the lower surface 116L of the drain region 116 may contact the third well region 104. The drain sidewall 116S of drain region 116 and the well sidewall 132S of first well region 132 can contact the third well region 104. The third well region 104 isolates drain region 116 from the first well region 132 on substrate 10S. Doped region 118a and source region 114a are located in second well region 134a. Doped region 118a may be adjacent to source region 114a. Source region 114a may be located between gate structure 112a and doped region 118a. Second well region 134a isolates doped region 118a and source region 114a from third well region 104. Isolation structure 141 may be located between doped region 118a and guard ring 160. Part of isolation structure 141 is located in second well region 134a. Part of isolation structure 141 is located in third well region 104. Part of isolation structure 141 is located in deep well region 102. As shown in Figure 1, the isolation structure 141 may be annular.

[0015] A guard ring 160 is in the substrate 10S. The guard ring 160 includes a doped region 120 and a fourth well region 136. The fourth well region 136 is in the deep well region 102. The doped region 120 is in the fourth well region 136. As shown in Figure 1, the guard ring 160 may be annular. The guard ring 160 may surround the gate structure 112a, the drain region 116, the source region 114a, the doped region 118a, and the isolation structure 141. A guard ring 162 is in the substrate 10S. The guard ring 162 includes a doped region 122 and a fifth well region 138. The fifth well region 138 is in the substrate 10S. The doped region 122 is in the fifth well region 138. As shown in Figure 1, the guard ring 162 may be annular. The guard ring 162 may surround the guard ring 160. An isolation structure 143 is located between the doped region 120 of the guard ring 160 and the doped region 122 of the guard ring 162. A portion of the isolation structure 143 is in the fourth well region 136. A portion of the isolation structure 143 is in the deep well region 102. A portion of the isolation structure 143 is in the substrate 10S. A portion of the isolation structure 143 is in the fifth well region 138. As shown in Figure 1, the isolation structure 143 may be annular. Spacer elements 151a may be formed on the first gate sidewall 112S1 and the second gate sidewall 112S2 of the gate structure 121a. Isolation structures 141 and 143 are, for example, shallow trench isolation (STI) structures.

[0016] In this embodiment, the source region 114a, drain region 116, first well region 132, deep well region 102, doped region 120, and fourth well region 136 have a first conductivity type (N-type); the second well region 134a, third well region 104, doped region 118a, doped region 122, and fifth well region 138 have a second conductivity type (P-type). Dopant can be implanted into the substrate S to define the source region 114a, drain region 116, first well region 132, second well region 134a, third well region 104, fourth well region 136, fifth well region 138, deep well region 102, doped region 118a, doped region 120, and doped region 122 in the substrate S. The source region 114a, drain region 116, doped region 118a, doped region 120, and doped region 122 can be heavily doped regions.

[0017] The semiconductor device 10 may further include an electrostatic discharge (ESD) protection structure 10E' in the substrate 10S. The ESD protection structure 10E' includes a source region 114b, a drain region 116, a gate structure 112b, a first well region 132, a second well region 134b, a third well region 104, a deep well region 102, a doped region 118b, an isolation structure 141, a guard ring 160, an isolation structure 143, a guard ring 162, and a spacer element 151b. The component configuration of the ESD protection structure 10E' may be symmetrical to the component configuration of the ESD protection structure 10E. The ESD protection structure 10E' shares the drain region 116, the first well region 132, the third well region 104, the deep well region 102, the isolation structure 141, the guard ring 160, the isolation structure 143, and the guard ring 162 with the ESD protection structure 10E. The source region 114b of the electrostatic discharge (ESD) protection structure 10E' can be similar to the source region 114a of the ESD protection structure 10E. The gate structure 112b of the ESD protection structure 10E' can be similar to the gate structure 112a of the ESD protection structure 10E. The second well region 134b of the ESD protection structure 10E' can be similar to the second well region 134a of the ESD protection structure 10E. The doped region 118b of the ESD protection structure 10E' can be similar to the doped region 118a of the ESD protection structure 10E. The spacer element 151b of the ESD protection structure 10E' can be similar to the spacer element 151a of the ESD protection structure 10E. The ESD protection structure 10E' can be used together with the ESD protection structure 10E for ESD discharge.

[0018] The electrostatic discharge protection structure of the present invention is not limited to the configurations shown in Figures 1 and 2. In other embodiments, the drain sidewall of the drain region may be aligned with or substantially aligned with the well sidewall of the first well region, as shown in Figure 3. In Figure 3, the semiconductor device 20 includes a substrate 10S and an electrostatic discharge protection structure 20E in the substrate. The drain sidewall 116S of the drain region 116 in the electrostatic discharge protection structure 20E is aligned with or substantially aligned with the well sidewall 332S of the first well region 332 in the longitudinal direction. The first well region 332 is completely below the drain region 116. The width of the drain region 116 in the lateral direction is equal to or substantially equal to the width of the first well region 332 in the lateral direction. The lower surface 116L of the drain region 116 is completely covered by the first well region 332. The drain sidewall 116S of the drain region 116 may not contact the first well region 332. The drain sidewall 116S of the drain region 116 can contact the third well region 104. The gate structure 112a does not overlap with the first well region 332 in the longitudinal direction. The first distance D1 (in the lateral direction) between the first gate sidewall 112S1 and the drain sidewall 116S is equal to or substantially equal to the second distance D2' (in the lateral direction) between the first gate sidewall 112S1 and the well region sidewall 332S. The second distance D2' may be less than or equal to 2 micrometers. The second distance D2' may be greater than or equal to 0 and less than or equal to 2 micrometers. The third distance D3 (in the lateral direction) between the second gate sidewall 112S2 and the drain sidewall 116S is equal to or substantially equal to the fourth distance D4' (in the lateral direction) between the second gate sidewall 112S2 and the well region sidewall 332S. The first well region 332 has a first conductivity type (N-type). The semiconductor device 20 may also include an electrostatic discharge protection structure 20E' in the substrate 10S. The component configuration of the electrostatic discharge protection structure 20E' is symmetrical to that of the electrostatic discharge protection structure 20E. The electrostatic discharge protection structure 20E' shares the drain region 116, the first well region 332, the third well region 104, the deep well region 102, the isolation structure 141, the protection ring 160, the isolation structure 143, and the protection ring 162 with the electrostatic discharge protection structure 20E.

[0019] In other embodiments, the well sidewall of the first well region may be aligned with or substantially aligned with the first gate sidewall of the gate structure, as shown in Figure 4. In Figure 4, the semiconductor device 30 includes a substrate 10S and an electrostatic discharge protection structure 30E in the substrate, wherein the well sidewall 432S of the first well region 432 in the electrostatic discharge protection structure 30E is aligned with or substantially aligned with the first gate sidewall 112S1 of the gate structure 112a in the longitudinal direction. The second distance (in the lateral direction) between the well sidewall 432S and the first gate sidewall 112S1 may be equal to or substantially equal to 0. A portion of the first well region 432 is below the drain region 116, and another portion of the first well region 432 is on the drain sidewall 116S of the drain region 116. The drain sidewall 116S of the drain region 116 may be covered by the first well region 432. The drain sidewall 116S of the drain region 116 may not contact the first well region 432. The drain sidewall 116S of the drain region 116 can contact the third well region 104. The width of the drain region 116 in the lateral direction is smaller than the width of the first well region 432 in the lateral direction. The lower surface 116L of the drain region 116 is completely covered by the first well region 432. The gate structure 112a does not overlap with the first well region 432 in the longitudinal direction. The first well region 432 has a first conductivity type (N-type). The semiconductor device 30 may also include an electrostatic discharge protection structure 30E' in the substrate 10S. The component configuration of the electrostatic discharge protection structure 30E' may be symmetrical to the component configuration of the electrostatic discharge protection structure 30E. The electrostatic discharge protection structure 30E' shares the drain region 116, the first well region 432, the third well region 104, the deep well region 102, the isolation structure 141, the guard ring 160, the isolation structure 143, and the guard ring 162 with the electrostatic discharge protection structure 30E.

[0020] The electrostatic discharge protection structure of the present invention can reduce the breakdown voltage and trigger voltage by adjusting the size of the first well region. For example, the breakdown voltage and trigger voltage can be reduced by adjusting the second distance between the well region sidewall and the first gate sidewall of the gate structure. The following provides a detailed explanation through several experimental and comparative examples, but the present invention is not limited thereto.

[0021] Experiments 1 to 4 are semiconductor devices shown in any of Figures 2 to 4. In Experiment 1, the second distance (in the lateral direction) between the first gate sidewall of the gate structure of the semiconductor device and the well sidewall of the first well region is equal to 0 micrometers, that is, the first gate sidewall is aligned with or substantially aligned with the well sidewall. In Experiment 2, the second distance (in the lateral direction) between the first gate sidewall of the gate structure of the semiconductor device and the well sidewall of the first well region is equal to 0.5 micrometers, and the gate structure and the first well region do not overlap in the longitudinal direction, that is, the first well region is completely on one side of the gate structure. In Experiment 3, the second distance (in the lateral direction) between the first gate sidewall of the gate structure of the semiconductor device and the well sidewall of the first well region is equal to 1 micrometer, and the gate structure and the first well region do not overlap in the longitudinal direction, that is, the first well region is completely on one side of the gate structure. In Experiment 4, the second distance (in the lateral direction) between the first gate sidewall of the gate structure and the well sidewall of the first well region of the semiconductor device is equal to 2 micrometers, and the gate structure and the first well region do not overlap in the longitudinal direction, that is, the first well region is completely on one side of the gate structure. In Comparative Example 1, the first well region of the semiconductor device covers the drain sidewall of the drain region, and the first well region extends to the bottom of the gate structure, that is, a part of the first well region overlaps with the gate structure in the longitudinal direction; the distance (in the lateral direction) between the first gate sidewall of the gate structure and the well sidewall of the first well region is equal to 0.3 micrometers. A direct current (DC) bias voltage was applied to the semiconductor devices of Experiments 1 to 4 and Comparative Example 1 to obtain their breakdown voltage (VBD). A Transmission Line Pulse (TLP) test was performed on the semiconductor devices of Experiments 1 to 4 and Comparative Example 1 to obtain their trigger voltage (Vt1) and secondary breakdown current (It2), and the results are listed in Table 1 below. In addition, the electrostatic discharge protection capabilities of the semiconductor devices of Experimental Examples 1 to 4 and Comparative Example 1 were tested under human body model (HBM) and machine model (MM), and the results are listed in Table 1 below.

[0022] [Table 1] DC TLP ESD V BD (V) V t1 (V) I t2 (A) HBM (kV) MM (V) Experimental Example 1 25.3 26.3 4.54 7.2 200 Experimental Example 2 24.4 25.2 4.32 7 225 Experimental Example 3 twenty two 25.1 4.35 4.6 250 Experiment Example 4 21.4 24.2 4.53 4.6 225 Comparative Example 1 27.4 28.3 4.22 5.4 325

[0023] As shown in Table 1, the breakdown voltage of the semiconductor devices in Experimental Examples 1 to 4 is lower than that of Comparative Example 1, and the breakdown voltage decreases with increasing second distance. The trigger voltage of the semiconductor devices in Experimental Examples 1 to 4 is lower than that of Comparative Example 1, and the trigger voltage decreases with increasing second distance. The semiconductor devices in Experimental Examples 1 to 4 still exhibit high secondary breakdown current, indicating that they possess good electrostatic discharge protection capabilities. The values ​​measured by the semiconductor devices in Experimental Examples 1 to 4 under human body electrostatic discharge mode are all greater than 2 kV, and the values ​​measured under mechanical electrostatic discharge mode do not decrease significantly, indicating that the semiconductor device of the present invention possesses good electrostatic discharge protection capabilities.

[0024] The configuration of the semiconductor device of the present invention can effectively reduce the breakdown voltage and trigger voltage, while maintaining good electrostatic discharge protection capability, thereby improving the efficiency and reliability of the electrostatic discharge protection structure.

[0025] It should be noted that the diagrams, structures, and steps described above are for illustrating some embodiments or applications of the present invention, and the present invention is not limited to the scope and application of the above structures and steps. Other embodiments with different structural forms, such as known components of different internal components, can be applied, and the illustrative structures and steps can be adjusted according to the needs of actual applications. Therefore, the structures in the diagrams are only for illustrative purposes and are not intended to limit the present invention. Those skilled in the art will generally understand that the related structures and steps of the present invention, such as the arrangement or configuration of related elements and layers in a semiconductor device, or the details of manufacturing steps, may be adjusted and varied according to the needs of actual applications.

[0026] In summary, although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0007] Figure 1 illustrates a schematic layout of a semiconductor device according to an embodiment of the present invention; Figure 2 illustrates a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention; Figure 3 illustrates a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention; and Figure 4 illustrates a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

Claims

1. A semiconductor device comprising: a substrate; a source region in the substrate; a drain region in the substrate and having a drain sidewall facing the source region; a gate structure on the substrate and between the source region and the drain region, the gate structure having a first gate sidewall facing the drain region; a first well region in the substrate and below the drain region, the first well region having a well region sidewall facing the source region; a second well region in the substrate, with the source region in the second well region; a third well region in the substrate, with the drain region, the source region, the first well region, and the second well region in the third well region, a lower surface of the first well region contacting the third well region; and a deep well region in the substrate, with the third well region in the deep well region, a portion of the deep well region on a sidewall of the third well region. The gate structure contacts the third well region, and a first distance between the first gate sidewall and the drain sidewall is less than or equal to a second distance between the first gate sidewall and the well region sidewall. The source region, the drain region, the first well region, and the deep well region have a first conductivity type, and the second well region and the third well region have a second conductivity type. The first conductivity type is different from the second conductivity type.

2. The semiconductor device as claimed in claim 1, wherein the drain sidewall of the drain region is located between the well sidewall of the first well region and the first gate structure sidewall of the gate structure.

3. The semiconductor device as claimed in claim 1, wherein the gate structure has a second gate sidewall, the second gate sidewall being relative to the first gate sidewall, and a third distance between the second gate sidewall and the drain sidewall being less than or equal to a fourth distance between the second gate sidewall and the well sidewall.

4. The semiconductor device as claimed in claim 1, wherein the first well region is completely below the drain region.

5. The semiconductor device as claimed in claim 4, wherein a width of the drain region is greater than or equal to a width of the first well region.

6. The semiconductor device as claimed in claim 1, wherein the drain sidewall of the drain region is aligned with or substantially aligned with the well sidewall of the first well region.

7. The semiconductor device as claimed in claim 1 further includes a first guard ring and a second guard ring, the first guard ring being in the substrate and surrounding the source region, the drain region and the gate structure, the second guard ring being in the substrate and surrounding the first guard ring, the first guard ring having the first conductivity type and the second guard ring having the second conductivity type.

8. The semiconductor device as claimed in claim 7 further includes an isolation structure located between the first guard ring and the second guard ring.

9. The semiconductor device as claimed in claim 1, wherein the drain sidewall of the drain region contacts the third well region.

10. The semiconductor device as claimed in claim 1, wherein the deep well region surrounds the third well region, the source region, and the drain region.

11. The semiconductor device as claimed in claim 1, wherein a portion of a lower surface of the drain region contacts the third well region.

12. The semiconductor device as claimed in claim 1, wherein the gate structure does not overlap with the first well region.

13. The semiconductor device as claimed in claim 1, wherein the second distance is less than or equal to 2 micrometers.

14. A semiconductor device comprising: a substrate; a source region in the substrate; a drain region in the substrate and having a drain sidewall facing the source region; a gate structure on the substrate and between the source region and the drain region, the gate structure having a gate sidewall facing the drain region; a first well region in the substrate and below the drain region, the first well region having a well region sidewall facing the source region; a second well region in the substrate, and the source region is in the second well region; a third well region in the substrate, and the drain region, the source region, the first well region, and the second well region are in the third well region, a lower surface of the first well region contacting the third well region; and a deep well region in the substrate, the third well region being in the deep well region, a portion of the deep well region being on a sidewall of the third well region. The gate structure contacts the third well region, and the sidewall of the well region is aligned with or substantially aligned with the gate sidewall. The drain sidewall is aligned with or substantially aligned with the well region sidewall. The source region, the drain region, the first well region, and the deep well region have a first conductivity type. The second well region and the third well region have a second conductivity type. The first conductivity type is different from the second conductivity type.

15. The semiconductor device as claimed in claim 14, wherein the third well region isolates the drain region from the first well region on the substrate.

16. The semiconductor device as claimed in claim 14, wherein the deep well region surrounds the third well region, the source region, and the drain region.

17. The semiconductor device as claimed in claim 14 further includes a first guard ring, a second guard ring, and an isolation structure, the first guard ring being in the substrate and surrounding the source region, the drain region, and the gate structure, the second guard ring being in the substrate and surrounding the first guard ring, the first guard ring having the first conductivity type, the second guard ring having the second conductivity type, the isolation structure being between the first guard ring and the second guard ring, a portion of the isolation structure being in the deep well region, and another portion of the isolation structure being in the substrate.

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