Display system with automatic bitplane adjustment

Abstract

Displaying an image as a sequence of bit planes may include storing that sequence of bit planes in a buffer. The utilization of this buffer can vary when the image being displayed is compressed. Images with lower compressibility may generate more bit planes in the buffer than images with higher compressibility. Some compressed images may not fit in the buffer when the buffer is reduced in size to decrease its power consumption. For such compressed images, the disclosed display can determine which bit planes should be stored to balance a limited buffer size with the reduced quality of the displayed image.

Description

Display system with automatic bit plane adjustment The present disclosure relates to a display, and more particularly to a display configured to display images based on bit planes. A color or grayscale image can be represented as a weighted series (i.e., sequence) of bit planes. To generate the sequence of bit planes, a binary number is determined based on the grayscale level of each pixel. Each binary number has a number of bits corresponding to the bit depth of the display. A bit plane can be generated for each bit of the binary number. The sequence of bit planes can be arranged from a most significant bit plane including the most significant bit (MSB) of the binary number for each pixel to a least significant bit plane including the least significant bit (LSB) of the binary number for each pixel. Using bit planes to present images on a display can help reduce the power and size of the display, making such displays useful for mobile and / or body-worn applications. The display can adjust the number of bit planes used to present an image based on the compressed size of the image. This adjustability allows for efficient use of the buffer associated with the display, which can result in a smaller buffer and thus reduce the power consumed by the display. In some aspects, the technology described herein relates to a display comprising: a preprocessor configured to: receive an image; remove a portion of pixels from the image to generate a compressed image; and determine a data length of the compressed image; and a bit-plane generator configured to: receive the compressed image and the data length of the compressed image, the bit-plane generator configured to: generate a sequence of bit-planes representing the compressed image, each bit-plane having the data length of the compressed image; compare the data length to a threshold value; designate a group of bit-planes (i.e., at least one bit-plane) as disabled when the data length is greater than the threshold value; and disable the group of bit-planes designated as disabled from being stored in a buffer such that a portion of the sequence of bit-planes is stored in the buffer without overlapping. In some aspects, the technology described herein relates to a display comprising: a preprocessor configured to: receive an image comprising pixels; remove a portion of the pixels in the image to generate a compressed image; and determine a data length of the compressed image; a buffer configured to store a sequence of bit planes representing the compressed image, the buffer being divided into segments having segment lengths that increase from a first segment to a last segment of the buffer; and a bit plane generator configured to generate a bit plane. The device receives the compressed image and the data length of the compressed image, the bit-plane generator being configured to: generate bit-planes in the bit-plane sequence, each bit-plane in the bit-plane sequence having the data length of the compressed image; compare the data length with progressively larger threshold values, each threshold value being associated with a (different) data segment; and when the data length exceeds at least one of the threshold values, disable at least one bit-plane from being stored in the buffer, so that a portion of the bit-plane sequence can be stored in the segments without overlapping. In some aspects, the technology described herein relates to a method for displaying an image, the method comprising: receiving an image for display; generating a compressed image; determining a data length of the compressed image; generating a sequence of bit planes representing the compressed image, each bit plane having the data length of the compressed image; comparing the data length to a threshold value corresponding to a segment length of a buffer; when the data length exceeds the threshold value, designating at least one bit plane in the sequence of bit planes as disabled; and not storing the at least one bit plane designated as disabled in the buffer, such that a portion of the sequence of bit planes can be stored in the buffer without overlapping. The foregoing illustrative summary, as well as other exemplary objects and / or advantages of the present disclosure and the manner in which they are achieved, are further explained in the following detailed description and its accompanying drawings. CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63 / 587,795, filed on October 4, 2023, which is hereby incorporated by reference in its entirety. An image can be presented using a sequence of bit planes. Each bit plane has a significance based on its corresponding bit in the binary grayscale level of the pixel. More significant bit planes carry more visual information than less significant bit planes. Therefore, less significant bit planes can be removed and still present the image at a reasonable quality. A buffer memory (e.g., a buffer) can store the remaining bit planes so that they can be recalled to present the image on the pixel array by progressively displaying the recalled bit planes for different durations corresponding to the significance of the bit planes. For some applications (e.g., mobile devices), power consumption and physical size are strictly constrained. In such applications, it may be desirable to use image compression to reduce buffer memory size. A technical problem with this approach is that compression can vary for each image, which can make the buffer too large for highly compressed images, an inefficient use of power and size, and can make the buffer undersized for less compressed images, leading to errors when bit planes overlap in the buffer. The display of the present disclosure solves this technical problem by adjusting how a sequence of bit planes is stored in a buffer. This adjustment may include disabling at least one of the less significant bit planes from being stored in the buffer when the compressibility of the image is low. This adjustment may reduce image quality to some extent, but prevents data corruption in the buffer. The technical effect of the proposed solution is that a smaller buffer can be used, resulting in a display that consumes less power and has a smaller mechanical size. These features facilitate the use of the disclosed display in body-worn devices (e.g., augmented reality glasses, augmented reality goggles, smart watches, smart glasses, etc.). FIG1 is a schematic block diagram of a display according to a possible embodiment of the present disclosure. The display 100 includes a plurality of pixels arranged in a 2D grid (i.e., a pixel array 120). Each pixel 121 includes a micro-LED configured to generate light when conducting a drive current from a drive current module 140. Each pixel 121 further includes a memory cell (e.g., an SRAM cell) for setting and maintaining the illumination state of the micro-LED as on / off. The state of the SRAM cell of the pixel can be controlled (i.e., set / reset) by a signal (e.g., a bit line signal) transmitted via a row conductor (i.e., a bit line) coupled to the SRAM cell. The SRAM cell of the pixel is coupled to the bit line based on a signal (e.g., a word line signal) transmitted to the pixel via a column conductor (i.e., a word line). Therefore, the display 100 further includes a word line driver 112 configured to transmit the word line signal to the word line (i.e., column) of the pixel array 120. A word line signal may activate a row so that each pixel in the active row is coupled to its respective bit line. As shown in FIG1 , the display 100 further includes a bitline driver 113 configured to transmit a bitline signal to the bitlines of the pixels in the active row. The bitline signal can change or maintain the state of the SRAM in the active row based on the image being displayed. In one embodiment, the bitline signal is a differential signal. In this case, each bitline can include a positive bitline (BL+) configured to carry a positive bitline signal and a negative bitline (BL-) configured to carry a negative bitline signal. In this differential configuration, the positive and negative bitlines can be collectively referred to as bitlines. The display 100 further includes a controller 400 configured to control the operation of the word line driver 112 and the bit line driver 113 to present an image on the pixel array 120. For example, the controller may transmit a word line signal (i.e., ROW) to activate a row and then transmit image data (i.e., DATA(COLUMN)) to the row of activated rows. The controller 400 can be configured to address and write to the SRAM of the pixel array so that the micro-LEDs are illuminated to produce an image. Each image can be presented on the pixel array 120 on a row-by-row basis until each row required to present the image has been activated. In one possible embodiment, the presentation process includes transmitting a word line signal for activating the row. After being activated, the bit line signal for each pixel in the row controls the pixel on / off based on the image data for each pixel in the active row. After the bit line signal is configured (i.e., written to) the pixels of the active row, the row can be deactivated and another row can be activated until all rows of the frame have been activated. The SRAM cell for the pixels in the deactivated row can keep the pixels of the deactivated row on (illuminated) or off (unilluminated) while the other rows of the frame are activated. After the frame is written to the SRAM cell of the pixel array 120, the SRAM cell can retain its value (e.g., 0, 1) until it is changed. Thus, updating the value in the SRAM display may require only a portion of the SRAM cells to change their state (ie, flip) relative to the previous frame (ie, bit plane). The on / off control of pixels described above can be used to present binary images, where each pixel is either on (e.g., binary 1) or off (e.g., binary 0). A sequence of binary images (i.e., bit planes) can be displayed at a high rate to produce a grayscale image perceived by a viewer. FIG. 2 illustrates a bit plane sequence of an image according to a possible embodiment of the present disclosure. In this example, image 201 has four pixels. Each pixel defines a position and a grayscale level. The grayscale level of each pixel of image 201 can be represented as a binary number. The binary number has a number of bits corresponding to the bit depth of the display. As shown, each pixel in the binary representation of image 201 is a four-bit binary number. The bit plane sequence 220 can be generated to have a bit plane for each bit of the binary number. As shown, the bit plane sequence 220 includes four bit planes. The first bit plane represents the image of the most significant bit (MSB) of each pixel (i.e., the most significant bit plane 221). The second bit plane 222 is less significant than the most significant bit plane 221. The third bit plane 223 is less significant than the second bit plane 222, but more significant than the least significant bit plane 224, which represents the least significant bit (LSB) of each pixel. The bit plane sequence 220 can be divided into two halves to form a first group 231 including the more significant bit planes of the sequence and a second group 232 including the less significant bit planes. When there are an odd number of bit planes, the mid-significant bit plane can have a significance between the first group 231 and the second group 232 in the sequence. Displaying a grayscale image may include writing each bit plane sequentially to a pixel array (i.e., SRAM). When each bit plane is displayed at the same intensity, each bit plane may be weighted by the duration it is displayed relative to the other bit planes. As shown, the weight (W) of the bit plane may be doubled for each bit plane from the least significant bit plane 224 to the most significant bit plane 221. The quality of an image can be determined by how well a sequence of bit planes represents the binary value of each pixel. The significance of a bit plane corresponds to the degree to which its bits contribute to the binary value. FIG3 illustrates the contribution of each bit to a binary number representing a grayscale level according to a possible implementation of the present disclosure. As shown, the binary number 11111111 represents a grayscale level value of 255. The binary number includes eight bits ranging from the most significant bit (b7) to the least significant bit (b0) (i.e., having a bit depth of 8). The graph illustrates how each bit contributes to this grayscale level value. As shown, half of the grayscale level value is determined by the most significant bit. The bits can be considered to include two groups, where bits b0, b1, b2, and b3 have lower significance than bits b4, b5, b6, and b7. As shown, bits b4, b5, b6, and b7 can contribute 94% to the grayscale level value. Therefore, these bits (i.e., this first half) can be referred to as the most significant bits of the binary number. As shown, bits b0, b1, b2, and b3 can only contribute 6% to the grayscale level value. Therefore, these bits (i.e., this second 1 / 2 portion) can be referred to as the least significant bits of the binary number. This implies that ignoring some of the least significant bits can still provide a reasonable approximation of the grayscale level value 255. For example, if bits b0 and b1 are ignored, the grayscale level value obtained from the remaining bits (i.e., b7, b6, b5, b4, b3, b2) will be 252, which in some cases can be a reasonable approximation of the grayscale level 255. Because each bit plane corresponds to a bit, a partial bit plane sequence can be a reasonable approximation of a complete bit plane sequence. FIG4 is a system block diagram of a controller for a display according to a possible embodiment of the present disclosure. The controller can be implemented as an integrated device or as part of a distributed computing system. Controller 400 includes digital processing, logic, and memory to perform operations associated with controlling pixels in a pixel array to render (i.e., display) an image. These operations can be performed by modules that may include circuitry and / or software for performing one or more of the operations. As shown in FIG4 , controller 400 includes a display preprocessor module (i.e., display preprocessor 410 ). Display preprocessor 410 can be configured to receive an image for display. The image can be a grayscale image or a color image. A color image for display can include three color channels, each represented by a grayscale image. Therefore, an example of a grayscale image for display will be discussed in detail. The display preprocessor 410 can be configured to generate a compressed image based on the received image. In one embodiment, the display preprocessor 410 can detect compressible portions of pixels, which can be groups (e.g., segments, groups, rows, regions, lines, etc.) of pixels having a grayscale level (i.e., intensity) of zero (i.e., zero pixels). In other words, the display preprocessor 410 can process the image to detect portions of the image that do not contain visual information. The display preprocessor 410 can further be configured to discard (i.e., remove) pixels in these compressible portions to generate the compressed image. The compressed image may still include zero pixels, but these pixels are not removed because they are included in the visual information (i.e., they are not compressible). The compressed image can have a reduced size (i.e., data length) compared to the received image. A highly compressible image (e.g., text on a dark background) can have a very short data length (i.e., length) compared to the received image, while a less compressible image (e.g., a picture or video frame) can have a data length that is almost as long as the received image. The bit plane generated from the compressed image can have the same data length as the compressed image. This reduced length allows the buffer 450 that stores the bit planes to be smaller, which can reduce its size and power consumption. FIG5 is a block diagram illustrating a system for compressing and storing bit planes in a buffer according to a possible implementation of the present disclosure. As shown, a portion of the pixels in image 510 can be removed to generate a compressed image 520 having a reduced size (i.e., data length). Compressed image 520 has a compressed data length (Lc) that is shorter than the (uncompressed) data length (L) of image 510. A sequence of bit planes can be generated to represent compressed image 520. As shown in FIG5 , each bit plane in a sequence of bit planes can be stored in a corresponding memory location (i.e., a segment) of buffer 450. A segment can be an address that can include a first location (e.g., a starting address), a second location (e.g., an ending address), and a pointer that specifies the direction in which the data is to be written. Each bit plane can be written to the buffer according to its corresponding segment. For example, the first segment 530 (i.e., segment 1) can be configured to store the least significant bit plane of the sequence, and the last segment 531 (i.e., segment N) can be configured to store the most significant bit plane. However, the segments need not be sorted sequentially by significance. For example, in a possible embodiment, segments used to store less significant bit planes can be interleaved with segments used to store more significant bit planes. As shown in FIG5 , each segment may have a segment length 535. When the compressed data length (Lc) of the generated bit plane is less than the segment length 535 of the segment, all N bit planes can be stored in the buffer without error. In other words, each bit plane is contained within its designated segment in the buffer. If the image 510 is not very compressible, the compressed length may exceed the segment length 535, resulting in more than one segment being written to the same location in the buffer (i.e., an overwrite error), which may corrupt the bit plane. Without the features of the disclosed display, the buffer would have to be large enough to accommodate all possible compressed image sizes. For example, the buffer could be large enough to store N uncompressed bit planes without risk of overwrite errors. However, this approach can be wasteful (e.g., large size, high power consumption) and can use each segment inefficiently. For example, it may be desirable to minimize the unused portion 536 of each segment. Returning to FIG4 , the pre-processor 410 is shown to further include a compression mapping module (i.e., zero mapper 420). The zero mapper 420 can be configured to generate a map that locates the compressible portions of the image. The map can specify the locations of zero pixels to be removed from the image so that these zero pixels can be replaced to regenerate the image. Display pre-processor 410 further includes a data length measurement module (i.e., data length counter 430). The data length counter is configured to determine the data length (Lc) of the compressed image. The data length may vary depending on the image. For example, data length counter 430 may count pixels (e.g., non-zero pixels) in the compressed image to determine the data length. Controller 400 further includes a bitplane generator 440. Bitplane generator 440 is configured to receive a compressed image and a data length. Bitplane generator 440 is configured to generate a sequence of bitplanes based on the compressed image and the data length. By default, bitplane generator 440 can be configured to generate a plurality (N) of bitplanes, where N is the bit depth of the display. In a possible implementation, bit-plane generator 440 is further configured to compare the data length (Lc) with a threshold value corresponding to the fragment length of buffer 450. For example, when the data length of each bit-plane is greater than the threshold value (i.e., greater than the fragment), bit-plane generator 440 may disable one or more of the bit-planes. FIG6 illustrates the deactivation of bit planes in a buffer according to a first possible implementation of the present disclosure. As shown, a bit plane sequence 610 is generated. The sequence includes eight bit planes, but any number can be generated. The eight bit planes include the four most significant bit planes (MSB, MSB-1, MSB-1, MSB-3) and the four least significant bit planes (LSB, LSB+1, LSB+2, LSB+3). The bit planes are designated for storage in corresponding segments of a buffer 650. The buffer 650 is equally divided into a number (e.g., 8) of segments equal to the number of bit planes (e.g., 8). As shown in FIG6 , buffer 650 is configured such that even-numbered segments store the most significant bit plane, while odd-numbered segments store the least significant bit plane 620. A first segment 651 of buffer 650 is configured to store the most significant bit plane 611 (MSB). A second segment 652 of buffer 650 is configured to store the least significant bit plane 612 (LSB). A third segment 653 of buffer 650 is configured to store the second most significant bit plane 613 (MSB-1). A fourth segment 654 of buffer 650 is configured to store the second least significant bit plane 614 (LSB+1). A fifth segment 655 of buffer 650 is configured to store the third most significant bit plane 615 (MSB-2). A sixth segment 656 of buffer 650 is configured to store the third least significant bit plane 616 (LSB+2). The seventh segment 657 of the buffer 650 is configured to store the fourth most significant bit plane 617 (MSB-3). The eighth segment 658 of the buffer 650 is configured to store the fourth least significant bit plane 618 (LSB+3). As shown in FIG6 , the bit plane generator can be configured to convert the data length (L C ) and the threshold length (L TH ) is compared, the threshold length is equal to the length of each segment in the buffer. C ) is less than the threshold value (L TH ), then all bit planes can be stored in their respective segments. When the data length (L) of the bit plane (i.e., each bit plane) is C ) is greater than the threshold value (L TH), the least significant bit plane 620 of the bit plane sequence 610 may be designated not to be stored in the buffer (i.e., disabled). Disabling bit planes may include not generating the bit planes designated as disabled or generating such bit planes by not writing the disabled bit planes to the buffer. As shown in FIG6 , disabling the least significant bit plane 620 frees up the second segment 652, the fourth segment 654, the sixth segment 656, and the eighth segment 658, allowing the most significant bit plane 611, the second most significant bit plane 613, the third most significant bit plane 615, and the fourth most significant bit plane 617 (i.e., a partial set of bit planes) to be written to the buffer without overlapping with any other bit planes (i.e., without error). In other words, the most significant bits of a sequence can be written to the buffer such that each bit plane occupies its corresponding odd-numbered segment and the adjacent even-numbered segment. The display can be configured to recall the partial set of bit planes stored in the buffer to present the image. In a possible implementation, the data length (LC) and the maximum length threshold (L MAX ) is compared. For example, in this first embodiment, in which half of the bit planes can be disabled, the maximum length is the length of two segments. When the data length exceeds the maximum length threshold, some other action can be taken. For example, only one of the bit planes (i.e., the most significant bit plane) can be written to the buffer. Returning to FIG4 , the controller 400 further includes a display postprocessor module (i.e., display postprocessor 460). The display postprocessor 460 is configured to receive bit planes from the buffer 450 and to receive a map from the zero mapper 420. The display postprocessor 460 can be configured to recall bit planes from the buffer 450 and, based on the map, add back the portions removed by the display preprocessor 410 (i.e., zero pixels). The display postprocessor 460 can further be configured to address the columns and rows of the pixel array 120 (see FIG1 ) to present the decompressed bit planes. The display postprocessor 460 can further be configured to generate an approximation of the bit planes for any disabled bit planes. FIG7 illustrates an approximate bit plane used to replace a set of bit planes that are disabled and not stored in a buffer, according to a possible implementation of the present disclosure. When the least significant bit plane 620 is not stored in the buffer (i.e., disabled), it can be replaced with an approximate bit plane so that the grayscale values ​​generated by the bit plane are approximate. As shown, the grayscale value 169 (i.e., 1010001 in binary) is illustrated. In the first embodiment 701, the disabled bit plane (ie, the least significant bit plane 620) is ignored, and the remaining bit planes are weighted according to their bit positions. In this case, an approximate grayscale value of 160 (ie, 1010xxxx) can be obtained. In the second embodiment 702, the disabled bit plane (ie, the least significant bit plane 620) is replaced with an approximate bit plane having all zero pixels. In this case, an approximate grayscale value of 160 (ie, 10100000) is obtained. In the third embodiment 703, the disabled bit plane (ie, the least significant bit plane 620) is replaced with an approximate bit plane having all 1 pixels. In this case, an approximate grayscale value of 175 (ie, 10101111) is obtained. In the fourth embodiment 704, the disabled bit plane (i.e., the least significant bit plane 620) is replaced with an approximate bit plane having pixels that match one of the bit planes in the partial bit plane sequence stored in the buffer. For example, the least significant bit plane 620 can be made to match the next bit plane in significance order (i.e., MSB-3). In this case, the approximate bit plane will have 1s and 0s. In this case, the approximate grayscale value of 160 (i.e., 10100000) or 175 (i.e., 10101111) can be obtained depending on the corresponding pixel value in the least significant bit plane (i.e., MSB-3 bit plane) in the partial bit plane set. FIG8 illustrates the deactivation of bit planes in a buffer according to a second possible implementation of the present disclosure. This implementation includes multiple threshold values ​​to increase the options for how bit planes are stored in the buffer. As shown, a sequence of bit planes 810 is generated. The sequence includes four bit planes, but any number can be generated. The four bit planes include two most significant bit planes (MSB, MSB-1) and two least significant bit planes (LSB+1, LSB). The bit planes are designated for storage in corresponding segments of buffer 850. Buffer 650 is unequally divided into a number (e.g., 4) of segments equal to the number (e.g., 4) of bit planes. The length of the segments increases from a first segment 851 configured to store the least significant bit plane 811 to a fourth segment 854 configured to store the most significant bit plane 814. As shown in Figure 8, the segments are sized so that when combined with each segment of a lower significance, the length of the segment doubles. For example, the length of the fourth segment doubles when combined with the third length of the third segment 853, the second length of the second segment 852, and the first length of the first segment 851. Similarly, the third length of the third segment 853 doubles when combined with the second length of the second segment 852 and the first length of the first segment 851. Similarly, the second length of the second segment 852 doubles when combined with the first length of the first segment 851. A plurality of threshold values ​​corresponding to unequal segment lengths of the buffer may be used to determine which bit planes to store in the buffer. The threshold values ​​may be doubled. For example, the second threshold value (L TH2 ) is the first threshold value (L TH1 ) is twice the length of the third threshold (L TH3 ) is the second threshold value (L TH2 ) is twice the length of the buffer 850. In this case, the third threshold is half the size (i.e., length) of the buffer 850. MAX ) can also be used to determine when the length of a bit plane is too large to store. A threshold value may be associated with a segment. For example, a maximum threshold value (L MAX ) may be associated with a fourth segment 854 configured to store the most significant bit plane 814 (MSB) in the bit plane sequence 810. The third threshold (L TH3 ) may be associated with the third segment 853, which is the second most significant bit plane 813 (MSB-1) in the bit plane sequence 810. The second threshold (L TH2 ) may be associated with the second segment 852, which is the second least significant bit plane 812 (LSB+1) in the bit plane sequence 810. The first threshold (L TH1 ) can be associated with the first fragment 851, which is the least significant bit plane 811 (LSB) in the bit plane sequence 810. In other words, the segments increase in size from the first segment 851 to the fourth segment 854 (i.e., the last segment) of the buffer 850. As shown in FIG8 , the first segment 851 corresponds to the least significant bit plane 811 in the bit plane sequence 810 and has a first segment length, which is the shortest segment length among the segment lengths. The fourth segment 854 (i.e., the last segment) of the buffer 850 corresponds to the most significant bit plane 814 in the bit plane sequence 810 and has a last segment length, which is the longest segment length among the segment lengths. The threshold values ​​correspond to each of the segments and are incremented from the first threshold value (L ) corresponding to the first segment 851. TH1 ) to the maximum threshold value (ie, the last threshold value) corresponding to the fourth segment 854 (ie, the last segment) and gradually doubled. The data length (L C ) (i.e., the length of the compressed image) is compared with a plurality of thresholds to determine which bit planes to store and in which segments they are stored. When the data length exceeds a particular threshold corresponding to a particular segment, the bit plane corresponding to the particular segment and all bit planes corresponding to any shorter segments are disabled. As shown in Figure 8, the data length (L C ) is greater than the second threshold value (L TH2 ) (and the first threshold value (L TH1 )). Therefore, the second least significant bit plane 812 (LSB+1) corresponding to the second segment 852 and the least significant bit plane 811 (LSB) corresponding to the first segment 851 (i.e., the least significant bit plane 820) can be disabled so as not to be stored in the buffer 850. Therefore, the third segment 853 (and the fourth segment 854) are freed to store the second most significant bit plane 813, which overflows the second segment 852. Data length (L C ) does not exceed the third threshold or the maximum threshold, so the storage of the most significant bit plane 814 in the fourth segment 854 continues without adjustment. This approach has several advantages. For example, more bit planes can be stored for longer data lengths because bit planes are gradually deactivated as the data length of the compressed image increases. Furthermore, the more significant bit planes, which carry the majority of the visual information, are allocated more memory, making them less likely to be deactivated. Another advantage of this approach is that it allows for computationally efficient implementations that compare data lengths to a series of thresholds that double from one threshold to the next. FIG9 illustrates a subsystem for comparing data length to a plurality of threshold values ​​according to a possible implementation of the present disclosure. As shown, the data length can be calculated using a data length counter 430 to count the number of pixels (e.g., non-zero pixels) in the compressed image so that the data length is equal to the count (CNT). During the counting period, the count can be compared to a first threshold value (LNT) using a digital comparator 910. TH1 ) for comparison. The digital comparator can be configured to gradually change the threshold value when the count exceeds the threshold value. When the count exceeds the first threshold value, the first threshold value can be converted to the second threshold value (i.e., doubled) by bit shifting. Next, when the count exceeds the second threshold value (L TH2 ), the second threshold value can be converted to the third threshold value (i.e., doubled) by bit shifting. This process can continue until the data length is fully counted. Bit shifting reduces the memory and circuitry required to store and compare threshold values, thereby further reducing the power and size of the display. In the description and / or drawings, exemplary embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. The use of the term "and / or" includes any and all combinations of one or more of the associated listed items. The figures are schematic representations and are therefore not necessarily drawn to scale. Unless otherwise indicated, specific terms are used in a generic and descriptive sense and not for purposes of limitation. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure. As used in the specification and the accompanying claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly indicates otherwise. As used herein, the terms "comprise" and "include" and their variations are used synonymously with the terms "include" and their variations and are open, non-restrictive terms. As used herein, the terms "optional" or "optional" mean that the subsequently described feature, event, or circumstance may or may not occur, and the description includes both instances where the feature, event, or circumstance occurs and instances where it does not occur. Ranges may be expressed herein as "about" one particular value and / or to "about" another particular value. When expressing such a range, aspects include from one particular value and / or to another particular value. Similarly, when values ​​are expressed as approximations, by use of the antecedent "about," it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. Certain embodiments may be implemented using various semiconductor processing and / or packaging technologies. Certain embodiments may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, such as, but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and the like. Although certain features of the described embodiments are illustrated as described herein, those skilled in the art will now recognize numerous modifications, substitutions, changes, and equivalents. It should be understood, therefore, that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that they are presented by way of example only and not limitation, and that various changes in form and detail may be made. Any portion of the apparatus and / or method described herein may be combined in any combination, except mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described. It will be understood that in the foregoing description, when an element is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to the other element, or one or more intermediate elements may be present. In contrast, when an element is referred to as being directly on, directly connected to, or directly coupled to another element, there are no intermediate elements. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, an element shown as being directly on, directly connected to, or directly coupled to may be referred to as being directly on, directly connected to, or directly coupled to. The claims of this application, if any, may be revised to list the exemplary relationships described in the specification or shown in the figures. As used in this specification, the singular may include the plural unless the context clearly indicates otherwise. Spatially relative terms (e.g., above, over, upper, under, below, below, lower, etc.) are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. In some embodiments, the relative terms above and below may include vertically above and vertically below, respectively. In some embodiments, the term adjacent may include laterally adjacent or horizontally adjacent. 100: Display 112: Wordline Driver 113: Bitline Driver 120: Pixel Array 121: Pixel 140: Driving Current Module 201: Image 220: Bitplane Sequence 221: Most Significant Bitplane 222: Second Bitplane 223: Third Bitplane 224: Least Significant Bitplane 231: First Group 232: Second Group 400: Controller 410: Display Preprocessor 420: Zero Mapper 430: Data Length Counter 440: Bitplane Generator 4 50: Buffer 460: Display Post-Processor 510: Image 520: Compressed Image 530: First Segment 531: Last Segment 535: Segment Length 536: Unused Portion of Segment 610: Bit Plane Sequence 611: Most Significant Bit Plane 612: Least Significant Bit Plane 613: Second Most Significant Bit Plane 614: Second Least Significant Bit Plane 615: Third Most Significant Bit Plane 616: Third Least Significant Bit Plane 617: Fourth Most Significant Bit Plane 61 8: Fourth least significant bit plane 620: Least significant bit plane 650: Buffer 651: First segment 652: Second segment 653: Third segment 654: Fourth segment 655: Fifth segment 656: Sixth segment 657: Seventh segment 658: Eighth segment 701: First implementation 702: Second implementation 703: Third implementation 704: Fourth implementation 810: Bit plane sequence 811: Least significant bit plane 812: Second least significant bit plane 813 : Second most significant bit plane 814: Most significant bit plane 820: Least significant bit plane 850: Buffer 851: First segment 852: Second length 853: Third length 854: Fourth segment 910: Digital comparator b0: Least significant bit / bit b1: Bit b2: Bit b3: Bit b4: Bit b5: Bit b6: Bit b7: Most significant bit / bit CNT: Count DATA (COLUMN): Image data Lc: Compressed data length / data length L MAX : Maximum length threshold / maximum threshold L TH :Threshold length / threshold L TH1 : The first threshold value L TH2 : Second threshold value L TH3 :Third threshold ROW: word line signal FIG1 is a system block diagram of a display according to a possible implementation scheme of the present disclosure. FIG2 illustrates a sequence of bit planes of an image according to a possible implementation scheme of the present disclosure. FIG3 illustrates the contribution of each bit to a binary number representing a grayscale level according to a possible implementation scheme of the present disclosure. FIG4 is a system block diagram of a controller for a display according to a possible implementation scheme of the present disclosure. FIG5 is a system block diagram illustrating compression and storage of bit planes in a buffer according to a possible implementation scheme of the present disclosure. FIG6 illustrates the deactivation of bit planes in a buffer according to a first possible implementation scheme of the present disclosure. FIG7 illustrates an approximate bit plane for replacing a set of bit planes that are deactivated and not stored in a buffer according to a possible implementation scheme of the present disclosure. FIG8 illustrates the deactivation of bit planes in a buffer according to a second possible implementation scheme of the present disclosure. FIG9 illustrates a subsystem for comparing data length to a plurality of threshold values ​​according to a possible implementation scheme of the present disclosure. The components in the drawings are not necessarily drawn to scale relative to each other. Like reference numerals indicate corresponding parts throughout the several views. 400:Controller 410: Display Preprocessor 420: Zero Mapper 430: Data length counter 440:Bitplane generator 450: Buffer 460: Display postprocessor

Claims

1. A display comprising: a preprocessor configured to: receive an image; remove a portion of pixels from the image to generate a compressed image; and determine a data length of the compressed image; and a bit plane generator receiving the compressed image and the data length of the compressed image, the bit plane generator being configured to: generate a sequence of bit planes representing the compressed image, each bit plane having the data length of the compressed image; compare the data length with a threshold value; when the data length is greater than the threshold value, designate a set of bit planes as disabled; and prevent the set of bit planes designated as disabled from being stored in a buffer such that a partial sequence of bit planes is stored in the buffer without overlap.

2. As in request item 1, the display, wherein: The buffer is deactivated to prevent the bit plane group stored in the buffer from being less significant in the bit plane sequence than the partial bit plane sequence stored in the buffer; and the display is configured to present the image based on the partial bit plane sequence.

3. As in request item 1 or 2, the display, wherein: The buffer is equally divided into a certain number of segments, the number of which is equal to the number of bit planes in the bit plane sequence, and each segment has a segment length equal to the threshold value.

4. As in request item 3, the display, wherein: The buffer has several odd-numbered segments that correspond to the higher significant bit plane, and several even-numbered segments that correspond to the lower significant bit plane.

5. The display as requested in item 4, wherein the bit plane generator is further configured to: write the partial bit plane sequence to the odd segments of the buffer such that each bit plane in the partial bit plane sequence occupies a corresponding odd segment and an adjacent corresponding even segment of the buffer.

6. The display as requested in item 1 or 2, wherein the bit plane generator is further configured to: when the data length is less than the threshold value, enable all bit planes in the bit plane sequence to be stored in the buffer; and write the bit plane sequence to the buffer such that each bit plane occupies a corresponding segment of the buffer.

7. As in request item 1 or 2, wherein, in order to disable the bit plane group so as not to store it in the buffer, the bit plane generator is configured to: not generate the bit plane group designated as disabled.

8. As in request 1 or 2, wherein, in order to disable the bit plane group so as not to store it in the buffer, the bit plane generator is configured to: generate the bit plane group designated as disabled; and not write the bit plane group designated as disabled to the buffer.

9. As requested in item 1 or 2, the display, wherein: The portion of the image from which pixels have been removed is zero pixels.

10. The display of claim 9, wherein the preprocessor is further configured to: generate a mapping of the image, the mapping including the positions of the zero pixels in the image; and transmit the mapping to a postprocessor, the postprocessor being configured to replace the removed zero pixels based on the mapping.

11. A display comprising: a preprocessor configured to: receive an image comprising a plurality of pixels; remove a portion of the pixels in the image to generate a compressed image; and determine a data length of the compressed image; a buffer configured to store a sequence of bit planes representing the compressed image, the buffer being divided into a plurality of segments having progressively increasing segment lengths; and a bit plane generator receiving the compressed image and the data length of the compressed image, the bit plane generator being configured to: generate bit planes in the sequence of bit planes, each bit plane in the sequence of bit planes having the data length of the compressed image; compare the data length with a plurality of progressively increasing threshold values; and when the data length exceeds at least one of the threshold values, deactivate at least one bit plane to prevent it from being stored in the buffer, such that a portion of the bit plane sequence can be stored in the segments without overlapping.

12. As in request item 11, the display, wherein: The partial bit plane sequence stored in the buffer includes bit planes that are more efficient than the at least one deactivated bit plane; and the display is configured to display a rendered image based on the partial bit plane sequence.

13. The display of claim 11 or 12 further includes a display post-processor configured to: generate an approximate bit plane for the at least one bit plane not stored in the buffer.

14. The display of claim 13, wherein the approximate bit planes are bit planes having all pixels that are one or all pixels that are zero.

15. The display of claim 13, wherein the approximate bit planes are bit planes of pixels that match one of the bit planes in the partial bit plane sequence.

16. The display as requested in item 11 or 12, wherein: One of the buffer's first segments corresponds to one of the least significant bit planes in the bit plane sequence and has a first segment length, which is the shortest segment length among the segment lengths; the last segment of the buffer corresponds to one of the most significant bit planes in the bit plane sequence and has a last segment length, which is the longest segment length among the segment lengths; and the threshold values ​​correspond to each of the segments and gradually double from a first threshold value corresponding to the first segment to a maximum threshold value corresponding to the last segment.

17. The display as requested in item 11 or 12, wherein: When the length of the data exceeds a specific threshold corresponding to a specific segment, a specific bit plane corresponding to that specific segment is deactivated; and when the length of the data exceeds the specific threshold corresponding to that specific segment, any bit plane corresponding to a segment shorter than that specific segment is also deactivated.

18. A method for displaying an image, the method comprising: receiving the image for display; generating a compressed image; determining a data length of the compressed image; generating a sequence of bit planes representing the compressed image, each bit plane having the data length of the compressed image; comparing the data length with a threshold value corresponding to a segment length of a buffer; when the data length exceeds the threshold value, designating at least one bit plane in the bit plane sequence as disabled; and not storing the at least one bit plane designated as disabled in the buffer such that a portion of the bit plane sequence can be stored in the buffer without overlapping.

19. The method for displaying the image as described in claim 18, wherein the at least one bit plane designated as disabled in the bit plane sequence includes: The least significant bit plane in this bit plane sequence.

20. The method for displaying the image as claimed in claim 18 or 19, further comprising: storing the partial bit plane sequence in the buffer; recalling the partial bit plane sequence from the buffer; generating approximate bit planes for the at least one bit plane not stored in the buffer; and displaying the image using the partial bit plane sequence and the approximate bit planes.

Images