Memory device and method for manufacturing the same

Abstract

A memory device may include a memory array, a first computing unit, and a second computing unit. The memory array may include a plurality of memory cells for storing weights of a neural network. The first computing unit is configured to receive the stored weights from the memory cells and generate a first partial sum based on the stored weights. The second computing unit is configured to receive the stored weights and the first partial sum from the memory cells and generate a second partial sum based on the stored weights and the first partial sum. The second computing unit may be sequentially coupled to the first computing unit.

Description

Floorplanning of a Hybrid Sequential Accumulator for In-Memory Computation none Memory devices are components of electronic systems that store data in a manner that allows for rapid access and modification. Traditionally, memory devices are designed to store binary information in the form of "0"s and "1s" in an array of memory cells. Due to manufacturing variations and design limitations, these cells often exhibit an unbalanced physical structure, resulting in variations in electrical characteristics. Compute-in-memory (CIM) technology integrates processing functions directly into the memory array, enabling faster data calculations by shortening the distance data must travel between storage and processing units. none The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features so that the first and second features may not be in direct contact. In addition, the disclosed embodiments may repeat element symbols and / or letters in various examples. This repetition is for simplicity and clarity and does not, in itself, specify a relationship between the various embodiments or configurations discussed. Furthermore, for ease of description, spatially relative terms, such as "below," "beneath," "beneath," "above," and "above," may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. In traditional compute-in-memory (CIM) macro floorplanning, design layout often poses significant challenges for routing accumulators (e.g., global and local accumulators). This layout often leads to severe routing congestion because the electrical connection paths between various components become too complex and intertwined. Congestion not only hinders signal integrity, but also may increase crosstalk between circuits and lead to inefficient use of metal layers. This inefficiency increases the need for more metal layers or more complex metal stack configurations to accommodate dense routing requirements. This not only complicates the manufacturing process and increases production costs, but may also have a negative impact on the overall performance and scalability of the CIM system. Therefore, optimizing floorplanning to alleviate routing congestion and reduce the use of metal layers are key design considerations for improving CIM architecture. To enhance the design of compute-in-memory (CIM) circuits, addressing the challenge of routing congestion is crucial, which can be alleviated by adopting a simpler floorplan that promotes efficient routing. By restructuring the layout, signal transmission paths can be simplified, thereby reducing the routing complexity and overlap that cause congestion. In addition, this optimization work aims to reduce the reliance on multiple metal layers for local and global routing, thereby not only simplifying the manufacturing process but also potentially reducing the physical thickness of the chip and manufacturing cost. Striking a careful balance between circuit density and routing simplicity can make CIM designs more scalable and cost-effective, while significantly reducing the number of metal layers required. The disclosed embodiments not only alleviate routing congestion but also enhance the overall performance and reliability of the CIM architecture. Routability in integrated circuit (IC) design refers to the ease with which electrical connections can be successfully and effectively made between the various components on a chip during the layout phase. It measures how easily and effectively metal lines (also known as "routing") can be placed within the IC layers without causing signal integrity issues, manufacturing problems, or violating design rules. For example, a design with high routability means there is enough space to accommodate all necessary connections with minimal risk of shorts, crosstalk, or other issues that can arise from dense or poorly organized routing. Factors that influence routability include the number of tracks within a metal layer, the complexity of the circuit, the number of layers available for routing, the precision of the manufacturing process, and the effectiveness of the design tools used to create the layout. Improving routability is crucial to ensuring that semiconductor chips can be reliably manufactured at scale and to optimizing their performance and power efficiency. This is particularly important as memory circuits become increasingly complex and dense with continuous advances in semiconductor technology. In a standard floorplan for compute-in-memory (CIM) macros, local accumulators (LACs) are strategically placed between CIM banks to facilitate multiply-accumulate (MAC) operations, which form the basis of the macro's computational tasks. Despite the presence of positioning logic, these LACs operate by performing parallel accumulations, which can lead to a significant challenge: routing congestion. This congestion arises because multiple parallel signals need to converge on the LACs, resulting in a dense and complex interconnect network. Consequently, more metal layers are typically required to accommodate all the necessary routing paths. For example, the design may require up to 84 tracks for some routing paths and 70 tracks for others, demonstrating the high metal layer usage required to maintain signal integrity and functionality in these dense routing environments. This not only increases chip design complexity but also impacts the manufacturing process, potentially leading to higher costs and scalability issues. The present disclosure provides various embodiments of memory devices to address such issues (e.g., routing). For example, a memory device disclosed herein includes a memory array, a first computation unit, and a second computation unit. The second computation unit is sequentially coupled to the first computation unit. In some embodiments, using a fully sequential floorplan can optimize the total routing tracks to 36 tracks, and can use fewer metal layers. In some embodiments, using a hybrid (e.g., partially sequential and partially parallel floorplan) floorplan can reduce the total routing tracks to 52 tracks, and can use fewer metal layers. FIG1 illustrates a block diagram of a memory device 100 according to some embodiments of the present disclosure. Memory device 100 may include a memory array 120, a first computing unit 140, and a second computing unit 160. In some embodiments, memory device 100 may include memory array 120, first computing unit 140, second computing unit 160, and a global computing unit 180. The memory array 120 may include a plurality of memory cells. These memory cells may store weights of a neural network. One or more peripheral circuits (not shown) may be located in one or more areas around or within the memory array 120. The memory cells and the peripheral circuits may be coupled via word lines and / or complementary bit lines BL and BLB, and data may be read from and written to the memory bit cells via the complementary bit lines BL and BLB. Different voltage combinations applied to the word lines and bit lines may define read, erase, or write (program) operations on the memory bit cells. In some embodiments, the memory array 120 architecture may combine various types of non-volatile or volatile memory technologies, including but not limited to static random-access memory (SRAM), resistive random-access memory (ReRAM), magnetoresistive random-access memory (MRAM), and phase-change random-access memory (PCRAM). Deep learning uses neural networks to achieve artificial intelligence. These networks consist of interconnected processing nodes that facilitate machine learning by analyzing example data. For example, a system designed to recognize objects might process thousands of images of objects, such as trucks, to discern and learn the visual patterns that correspond to objects in new images. Neural networks are typically structured in layers, with data flowing through these layers in a single forward pass. Each node in the network may be connected to multiple nodes in subsequent layers, which send data to it, as well as to numerous nodes in previous layers that receive data. In a neural network, nodes attribute numerical values ​​called "weights" to their connections. Upon activation, the node multiplies incoming data by this weight and sums the products across all connections to produce a single numerical output. If the output falls below a certain threshold, the node can be prevented from proceeding to the next layer. Conversely, if the output exceeds the threshold, the node can pass the sum to connected nodes in the next layer. In a deep learning system, the neural network model is stored in memory, and computational logic in the processor performs multiply-accumulate (MAC) calculations on the parameters (e.g., weights) stored in memory. In some embodiments, the weights may be stored in the memory cells within the memory array 120. In some embodiments, the first computation unit 140 may be configured to receive a plurality of inputs 122a, 122b from the memory cells 120. The inputs 122a, 122b may include at least one of stored weights or input activation vector elements from the memory cells 120. In some embodiments, the first computation unit 140 may be at least one of a local accumulator, a full adder, a half adder, a sum register, a partial sum register, or an accumulation circuit. In some embodiments, the weights (W) or input activation vector elements may be stored in a subarray of the memory array 120. Each output of the subarray may be an input to the computation unit 140. For example, the first computation unit 140 may be configured to receive stored weights from the memory cells 120. In some embodiments, the first computation unit 140 is interposed between the subarrays of the memory cells 120. The first computation unit 140 and the subarrays may be connected on a plurality of local bit lines. In certain embodiments, at least one additional computation unit may be interposed between the memory array 120 and the first computation unit 140. In some embodiments, first computation unit 140 may be configured to generate first partial sum 142 based on stored weights 122a, 122b. In some embodiments, first computation unit 140 may be configured to generate first partial sum 142 based on stored weights and partial sums from at least one additional computation unit. In some embodiments, the second computation unit 160 may be configured to receive a plurality of inputs 122c and 122d from the memory cells 120. The second computation unit 160 may be configured to receive the first partial sum 142 from the first computation unit 140. The inputs 122c and 122d may include at least one of stored weights or input activation vector elements from the memory cells 120. In some embodiments, the second computation unit 160 may be at least one of a local accumulator, a full adder, a half adder, a sum register, a partial sum register, or an accumulation circuit. In some embodiments, the weights (W) or input activation vector elements may be stored in a subarray of the memory array 120. Each output of the subarray may be an input to the computation unit 160. For example, the second computation unit 160 may be configured to receive stored weights from the memory cells 120. In some embodiments, the second computation unit 160 is interposed between the subarrays of the memory cells 120. The second computation unit 160 and the subarrays may be connected on a plurality of local bit lines. In some embodiments, at least one additional computing unit may be inserted between the memory array 120 and the second computing unit 160. In some embodiments, the second computing unit 160 may be configured to generate the second partial sum 162 based on the stored weights 122 c, 122 d and the first partial sum 142. In some embodiments, the second computing unit 160 may be configured to generate the second partial sum 162 based on the stored weights, the first partial sum 142, and the partial sum from the at least one additional computing unit. In some embodiments, the first calculation unit 140 may generate a first partial sum 142 by multiplying the input activation vector elements by the weights stored in the subarrays of the memory cells 120. The second calculation unit 160 may generate a second partial sum 162 by multiplying the input activation vector elements by the weights stored in the subarrays of the memory cells 120. In some embodiments, each of the memory cells 120 may include a plurality of wordlines. The multiplication of the input activation vector elements on one of the wordlines by the weights stored in the memory cells may be calculated by accessing the memory cell subarrays via the wordlines. In some embodiments, the second computing unit 160 can be sequentially coupled to the first computing unit 140. In some embodiments, the first computing unit 140 and the second computing unit 160 can be sequentially coupled in the same metallization / metal layer. In some embodiments, the first computing unit 140 can be directly interconnected to the second computing unit 160. In some embodiments, memory device 100 may utilize a fully sequential floorplan. By employing a fully sequential floorplan in the design of a memory device, routing tracks can be more optimally utilized. By arranging components in a sequential manner, the total number of required routing tracks can be significantly reduced. This simplified approach facilitates a more organized, less congested routing scheme, allowing for the use of fewer metal layers in the circuit. Furthermore, with fewer layers, electrical path lengths are shortened, which enhances signal integrity and potentially increases circuit speed. In some embodiments, the memory device 100 may implement a hybrid floorplan (e.g., partially sequential floorplan and partially parallel floorplan). By implementing a hybrid floorplan that combines sequential and parallel elements in an integrated circuit design, substantial improvements in routing and layer usage can be provided. By selectively employing sequential routing when feasible and parallel routing when necessary, the total number of routing tracks can be effectively reduced. This balanced approach alleviates the routing congestion typically associated with parallel design while still maintaining the design compactness that may be affected by a purely sequential floorplan. The result is a layout that requires fewer metal layers, which can significantly reduce manufacturing complexity and cost. Therefore, this hybrid floorplan provides an effective way to optimize the chip routing infrastructure, helping to simplify the manufacturing process and improve overall circuit performance. In some embodiments, the global computation unit 180 may be configured to accumulate at least one multiplied partial sum 182 (e.g., the first partial sum 142 and / or the second partial sum 162) from the first computation unit 140 and the second computation unit 160. In some embodiments, the global computation unit 180 may be at least one of a global accumulator, a full adder, a half adder, a sum register, a partial sum register, or an accumulation circuit. In some embodiments, at least one additional computation unit may be inserted between the global computation unit 180 and the second computation unit 160. In certain embodiments, the global computation unit 180 may be sequentially coupled to the first computation unit 140, the second computation unit 160, and the at least one additional computation unit. FIG. 2 illustrates a detailed schematic diagram of the memory device 100 of FIG. 1 according to some embodiments of the present disclosure. FIG. 4 illustrates a detailed schematic diagram of the memory device 100 of FIG. 2 according to some embodiments of the present disclosure. Memory device 100 may include a memory array 120, a first computation unit 140, a second computation unit 160, and a third computation unit 220. In some embodiments, memory device 100 may include memory array 120, first computation unit 140, second computation unit 160, third computation unit 220, and a global computation unit 180. The memory devices 100 of FIG. 2 and FIG. 4 are substantially similar to the memory device 100 of FIG. For the sake of brevity, the detailed operations of similar elements discussed in detail in the preceding paragraphs are omitted unless necessary to describe their cooperative relationship with the elements shown in FIG. 2 and FIG. In FIG. 2 and FIG. 4, it is assumed that 16 partial sums are to be accumulated from 16 CIM banks, each of which is 16 bits. In some embodiments, the third computation unit 220 may be configured to receive a plurality of inputs 122e, 122f from the memory cells 120. The third computation unit 220 may be configured to receive the second partial sum 162 from the second computation unit 160. The inputs 122e, 122f may include at least one of stored weights or input activation vector elements from the memory cells 120. In some embodiments, the third computation unit 220 may be at least one of a local accumulator, a full adder, a half adder, a sum register, a partial sum register, or an accumulation circuit. In some embodiments, the weights (W) or input activation vector elements may be stored in a subarray of the memory array 120. Each output of the subarray may be an input to the computation unit 220. For example, the third computation unit 220 may be configured to receive stored weights from the memory cells 120. In some embodiments, the third computation unit 220 is interposed between subarrays of the memory cells 120. The third computation unit 220 and the subarrays may be connected to a plurality of local bit lines. In some embodiments, at least one additional computing unit may be inserted between the memory array 120 and the third computing unit 220. In some embodiments, the third computing unit 220 may be configured to generate a third partial sum 222 based on the stored weights 122e, 122f and the second partial sum 162. In some embodiments, the third computing unit 220 may be configured to generate the third partial sum 222 based on the stored weights, the second partial sum 162, and the partial sum from the at least one additional computing unit. In some embodiments, the third computing unit 220 may be sequentially coupled to the first computing unit 140 and the second computing unit 160. In some embodiments, the third computing unit 220, the first computing unit 140, and the second computing unit 160 may be sequentially coupled in the same metallization / metal layer. In some embodiments, the third computing unit 220 may be directly interconnected to the second computing unit 160. In some embodiments, the memory device 100 may employ a fully sequential floorplan (e.g., 140, 160, and 220). By employing a fully sequential floorplan in the design of the memory device, routing tracks may be more optimally utilized. By arranging components in a sequential manner, the total number of required routing tracks may be significantly reduced (e.g., 36 routing tracks). This simplified approach facilitates a more organized and less congested routing scheme, thereby allowing the use of fewer metal layers in the circuit. Additionally, with fewer layers, electrical path lengths are shortened, which enhances signal integrity and potentially increases the operating speed of the circuit. As illustrated in Figures 2 and 4 , a first memory unit 120a (e.g., CIM 0) may use 16 routing tracks to send / transmit neural network data to a first local accumulator 140. A second memory unit 120b (e.g., CIM 1) may use 16 routing tracks to send / transmit neural network data to the first local accumulator 140. The first local accumulator 140 may receive / compile the neural network data from the first and second memory units 120a, 120b. The first local accumulator 140 may generate a first partial sum 142 and send the first partial sum 142 to the second local accumulator 160 using 17 routing tracks. A third memory unit 120c (e.g., CIM 2) may use 16 routing tracks to send / transmit neural network data to the second local accumulator 160. The fourth memory unit 120d (e.g., CIM 3) can use 16 routing tracks to send / transmit the neural network data to the second local accumulator 160. The second local accumulator 160 can receive the neural network data from the third memory unit 120c and the fourth memory unit 120d. The second local accumulator 160 can generate a second partial sum 162. The second local accumulator 160 can send the second partial sum 162 to a subsequent element (e.g., the third local accumulator 220) by using 18 routing tracks. The third local accumulator 220 can receive the neural network data from the memory unit. The third local accumulator 220 can generate a third partial sum 222. The third local accumulator 220 can send the third partial sum 222 to the following element by using 19 routing tracks. In this case, for CIM 7 210, the maximum number of routing tracks in this system is 36. Compared to conventional routing floorplan designs that use up to 84 routing tracks, the disclosed embodiments provide a memory device that reduces routing congestion and minimizes the use of metal layers. In some embodiments, the first computing unit 140 can be sequentially coupled to the second computing unit 160 using routing tracks within the same metallization layer (e.g., metal layer N). In some embodiments, multiple metal layers (e.g., metal layers N+1 and N+2) can be used. The first memory unit 120a and the second memory unit 120b can be located in the same metal layer. The first memory unit 120a and the first computing unit 140 can be located in different metallization layers. For example, the first memory unit 120a and the second memory unit 120b can be formed in metal layer N. The first computing unit 140, the second computing unit 160, and the third computing unit 220 can be formed in metal layer N+1. FIG3 illustrates a detailed schematic diagram of the memory device 100 of FIG1 according to some embodiments of the present disclosure. FIG5 illustrates a detailed schematic diagram of the memory device 100 of FIG3 according to some embodiments of the present disclosure. Memory device 100 may include a memory array 120, a first computing unit 140, a second computing unit 160, a fourth computing unit 320, and a fifth computing unit 340. In some embodiments, memory device 100 may include a memory array 120, a first computing unit 140, a second computing unit 160, a fourth computing unit 320, a fifth computing unit 340, and a global computing unit 180. The memory devices 100 of FIG3 and FIG5 are substantially similar to the memory device 100 of FIG1. ​​For the sake of brevity, the specific operations of similar components discussed in detail in the preceding paragraphs are omitted unless necessary to describe their cooperative relationship with the components shown in FIG3 and FIG5. In FIG3 and FIG5, it is assumed that 16 partial sums are to be accumulated from 16 CIM banks, each of which is 16 bits. In some embodiments, the fourth computation unit 320 may be configured to receive multiple inputs 122a, 122b from the memory cells 120. These inputs 122a, 122b may include at least one of stored weights or input activation vector elements from the memory cells 120. In some embodiments, the fourth computation unit 320 may be at least one of a local accumulator, a full adder, a half adder, a sum register, a partial sum register, or an accumulation circuit. In some embodiments, the weights (W) or input activation vector elements may be stored in a subarray of the memory array 120. Each output of the subarray may be an input to the computation unit 320. For example, the fourth computation unit 320 may be configured to receive stored weights from the memory cells 120. In some embodiments, the fourth computation unit 320 is interposed between subarrays of the memory cells 120. The fourth computation unit 320 and the subarrays may be connected on a plurality of local bit lines. In certain embodiments, at least one additional computation unit may be interposed between the memory array 120 and the fourth computation unit 320. In some embodiments, fourth computation unit 320 may be configured to generate fourth partial sum 322 based on stored weights 122a, 122b. In some embodiments, fourth computation unit 320 may be configured to generate fourth partial sum 322 based on stored weights and partial sums from at least one additional computation unit. In some embodiments, the fifth computation unit 340 may be configured to receive multiple inputs 122c and 122d from the memory cells 120. These inputs 122c and 122d may include at least one of stored weights or input activation vector elements from the memory cells 120. In some embodiments, the fifth computation unit 340 may be at least one of a local accumulator, a full adder, a half adder, a summation register, a partial summation register, or an accumulation circuit. In some embodiments, the weights (W) or input activation vector elements may be stored in a subarray of the memory array 120. Each output of the subarray may be an input to the computation unit 340. For example, the fifth computation unit 340 may be configured to receive stored weights from the memory cells 120. In some embodiments, the fifth computation unit 340 is interposed between subarrays of the memory cells 120. The fifth computation unit 340 and the subarrays may be connected on a plurality of local bit lines. In certain embodiments, at least one additional computation unit may be interposed between the memory array 120 and the fifth computation unit 340. In some embodiments, fifth calculation unit 340 may be configured to generate fifth partial sum 342 based on stored weights 122c, 122d. In some embodiments, fifth calculation unit 340 may be configured to generate fifth partial sum 342 based on stored weights and partial sums from at least one additional calculation unit. In some embodiments, first computing unit 140 may be coupled in parallel to fourth computing unit 320 and fifth computing unit 340 to receive fourth partial sum 322 and fifth partial sum 342. First computing unit 140 may receive fourth partial sum 322 from fourth computing unit 320 and fifth partial sum 342 from fifth computing unit 340. First computing unit 140 may generate first partial sum 142 based on fourth partial sum 322 and fifth partial sum 342. In some embodiments, fourth computing unit 320 and first computing unit 140 may be located in different metallization / metal layers. Fourth computing unit 320 and fifth computing unit 340 may be located in the same metallization / metal layer. In some embodiments, fourth computing unit 320 may be interconnected with first computing unit 140 using via structure 360. Fifth computing unit 340 may be interconnected with first computing unit 140 via via structure 360. In some embodiments, the second computation unit 160 may be configured to receive a plurality of inputs 122e, 122f, 122g, and 122h from the memory cells 120. The second computation unit 160 may be configured to receive the first partial sum 142 from the first computation unit 140. The inputs 122e, 122f, 122g, and 122h may include at least one of stored weights or input activation vector elements from the memory cells 120. In some embodiments, the second computation unit 160 may be at least one of a local accumulator, a full adder, a half adder, a sum register, a partial sum register, or an accumulation circuit. In some embodiments, the weights (W) or input activation vector elements may be stored in a subarray of the memory array 120. Each output of the subarray may be an input to the computation unit 160. For example, the second computation unit 160 may be configured to receive the stored weights 122e, 122f, 122g, and 122h from the memory cells 120. In some embodiments, a second computation unit 160 is inserted between subarrays of memory cells 120. Second computation unit 160 and the subarrays may be connected to a plurality of local bit lines. In some embodiments, at least one additional computation unit may be inserted between memory array 120 and second computation unit 160. In some embodiments, second computation unit 160 may be configured to generate a second partial sum 162 based on stored weights 122e, 122f, 122g, 122h and first partial sum 142. In some embodiments, second computation unit 160 may be configured to generate second partial sum 162 based on stored weights, first partial sum 142, and partial sums from at least one additional computation unit. In some embodiments, second computing unit 160 can be sequentially coupled to first computing unit 140. In some embodiments, first computing unit 140 and second computing unit 160 can be sequentially coupled within the same metallization / metal layer (e.g., metal layer N, N+1, or N+2). In some embodiments, first computing unit 140 can be directly interconnected to second computing unit 160. In some embodiments, the memory device 100 may implement a hybrid floorplan (e.g., partially sequential floorplan and partially parallel floorplan). By implementing a hybrid floorplan that combines sequential (e.g., the fourth computation unit 320, the fifth computation unit 340, and the first computation unit 140) and parallel (e.g., the first computation unit 140 and the second computation unit 160) elements in an integrated circuit design, substantial improvements in routing and layer usage may be provided. By selectively employing sequential routing when feasible and employing parallel routing when necessary, the total number of routing tracks may be effectively reduced (e.g., 52 routing tracks). This balanced approach alleviates routing congestion typically associated with parallel designs while still maintaining the design compactness that may be compromised by a purely sequential floorplan. The result is a layout that requires fewer metal layers, which can significantly reduce manufacturing complexity and cost. Therefore, this hybrid floorplan provides an effective method for optimizing chip routing infrastructure, helping to simplify the manufacturing process and improve overall circuit performance. As shown in Figures 3 and 5, the first memory cell 120a (e.g., CIM 0) can use 16 routing tracks to send / transmit neural network data to the fourth local accumulator 320. The second memory cell 120b (e.g., CIM 1) can use 16 routing tracks to send / transmit neural network data to the fourth local accumulator 320. The fourth local accumulator 320 can receive / compile neural network data from the first memory cell 120a and the second memory cell 120b. The fourth local accumulator 320 can generate a fourth partial sum 322 and send the fourth partial sum 3222 to the first local accumulator 140 using 17 routing tracks on different metal layers. The third memory cell 120c (e.g., CIM 2) can use 16 routing tracks to send / transmit neural network data to the fifth local accumulator 340. The fifth memory unit 120d (e.g., CIM 3) may send / transmit the neural network data to the fifth local accumulator 340 using 16 routing tracks. The fifth local accumulator 340 may receive the neural network data from the third memory unit 120c and the fourth memory unit 120d. The fifth local accumulator 340 may generate a fifth partial sum 342. The fifth local accumulator 342 may send the fifth partial sum 342 to the first computation unit 140 using 17 routing tracks. The first local accumulator 140 may receive the neural network data from the memory unit 120. The first local accumulator 140 may generate a first partial sum 142 based on the fourth partial sum 322 and the fifth partial sum 342. The first local accumulator 140 may send the first partial sum 142 to the following components (e.g., the second computation unit 160) using 18 routing tracks. Second local accumulator 160 can receive first partial sum 142 and neural network data from the memory cell. Second local accumulator 160 can generate second partial sum 162. Second local accumulator 160 can send second partial sum 162 to a subsequent element (e.g., global accumulator 180) using 19 routing tracks. In this case, for CIM 6 310, the maximum number of routing tracks in this system is 52. Compared to conventional routing floorplan designs that use up to 84 routing tracks, the disclosed embodiments provide a memory device that reduces routing congestion and minimizes the use of metal layers. In some embodiments, the first computing unit 140 can be coupled to the fourth computing unit 320 and the fifth computing unit 340 in parallel using routing tracks and via structures 360. In some embodiments, the fourth computing unit 320 and the first computing unit 140 can be located on different metallization layers (e.g., metal layers N, N+1, and N+2). The fourth computing unit 320 and the fifth computing unit 340 can be located on the same metallization layer (e.g., metal layer N). In some embodiments, the first computing unit 140, the fourth computing unit 320, and the fifth computing unit 340 can be located on the same metallization layer (e.g., metal layer N). In some embodiments, the first computing unit 140 can be coupled to the second computing unit 160 sequentially using routing tracks within the same metallization layer (e.g., metal layer N). In some embodiments, multiple metal layers (e.g., metal layers N+1, N+2) can be used. The first memory unit 120a and the second memory unit 120b can be located in the same metal layer. The first memory cell 120a and the fourth computing cell 320 (or the fifth computing cell 340) may be located in different metallization layers. For example, the first memory cell 120a and the second memory cell 120b may be formed in metal layer N. The fourth computing cell 320 and the fifth computing cell 340 may be formed in metal layer N+1. The first computing cell 140 and the second computing cell 160 may be formed in metal layer N+2. FIG. 6 is a flow chart illustrating an exemplary method 600 for manufacturing the memory device 100 of FIG. 1 , according to some embodiments of the present disclosure. It should be understood that FIG. 6 has been simplified to facilitate a better understanding of the concepts of the present disclosure. Therefore, it should be noted that additional processes may be performed before, during, and after the method of FIG. 6 , and only some of these additional processes are briefly described herein. Referring now to FIG. 6 , operation 602 may provide a substrate. The substrate may have a front side and a back side opposite each other. The substrate may be a semiconductor substrate, such as a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate, which may be doped (e.g., with a p-type or n-type dopant) or undoped. Next, method 600 proceeds to operation 604: forming a memory cell array 120 having a plurality of memory cell subarrays on the front surface of the substrate. The memory cell subarrays may be placed adjacent to each other. In some embodiments, the subarrays of memory array 120 may store weights (W) or elements of an input activation vector for a neural network. Each output of the subarray may be an input to a computational unit. Next, method 600 proceeds to operation 606 : forming a first local accumulator 140 on the first metal layer on the front side of the substrate. The first local accumulator 140 can generate a first partial sum 142 by multiplying the input activation vector elements with the stored weights of the subarray of memory cells 120 . Next, method 600 proceeds to operation 608: forming a second local accumulator 160 on the first metal layer. The first computation unit 140 may be at least one of a local accumulator, a full adder, a half adder, a sum register, a partial sum register, or an accumulation circuit. The first local accumulator 140 may be sequentially coupled to the second local accumulator 160 on the first metal layer. The second computation unit 160 may be at least one of a local accumulator, a full adder, a half adder, a sum register, a partial sum register, or an accumulation circuit. In some embodiments, the first computation unit 140 may be directly interconnected to the second computation unit 160. The second computation unit 160 may be configured to receive a plurality of inputs from the plurality of memory cells 120. The second computation unit 160 may be configured to receive the first partial sum 142 from the first computation unit 140. In some embodiments, the second computation unit 160 may be configured to generate a second partial sum based on the stored weights and the first partial sum. Next, method 600 may proceed to forming a third local accumulator on the first metal layer. The third local accumulator may be sequentially coupled to the first local accumulator and the second local accumulator on the first metal layer. The third computation unit may be at least one of a local accumulator, a full adder, a half adder, a summation register, a partial summation register, or an accumulation circuit. In some embodiments, the third computation unit may be sequentially coupled to the first computation unit 140 and the second computation unit 160. In some embodiments, the third computation unit may be coupled in parallel to the first computation unit 140. In some embodiments, method 600 may include forming an interconnect structure on the backside of the substrate. The interconnect structure may be coupled to the array of memory cells 120, the first local accumulator 140, and the second local accumulator 160 on the frontside of the substrate. A plurality of first via structures may extend vertically through the substrate from the backside to the frontside. In some embodiments, the array of memory cells 120, the first local accumulator 140, and the second local accumulator 160 may also be formed on the backside of the substrate. The first local accumulator 140 may be sequentially coupled to the second local accumulator 160 within the interconnect structure. FIG7 is a flow chart of an exemplary method 700 for manufacturing memory device 100 according to some embodiments of the present disclosure. It is understood that FIG7 has been simplified to facilitate a better understanding of the concepts of the present disclosure. Therefore, it should be noted that additional processes may be performed before, during, and after the method of FIG7 , and only some of these additional processes are briefly described herein. Referring now to FIG. 7 , operation 705 may provide a substrate. The substrate may have a first side and a second side opposite each other. The substrate may be a semiconductor substrate, such as a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate, which may be doped (e.g., with a p-type or n-type dopant) or undoped. Next, method 700 proceeds to operation 710: forming a plurality of first transistors and second transistors on the first side of the substrate. The first transistors may be hardware components for storing data. Each of the first transistors may have p-type conductivity or n-type conductivity. In one aspect, the first transistors may be embodied as a semiconductor memory device or an array of memory cells 120. In some embodiments, the second transistors may be used in a head device on the first side of the substrate. The second transistors may have p-type conductivity or n-type conductivity. Next, method 700 proceeds to operation 715: forming metal structures (e.g., word lines and / or bit lines, interconnects) on the first side of the substrate. The first transistors and metal structures (e.g., word lines and / or bit lines) may be used for a plurality of memory cells 120 on the first side of the substrate. In some embodiments, a conductor structure may be formed on the first side of the substrate. The conductor structure may be used to provide a supply voltage to the first transistors. A plurality of via structures may be formed on the first side of the substrate. The via structures may be used to electrically couple the source / drain terminals of the transistors to the conductor structure. In some embodiments, a first local accumulator 140 and a second local accumulator 160 may also be formed within the metal structure. The first local accumulator 140 may be sequentially coupled to the second local accumulator 160 within the interconnect structure. In the disclosed embodiments, accumulators in compute-in-memory (CIM) circuits are strategically placed in sequential floorplanning / layout, enabling them to efficiently aggregate partial sums (PSUMs). This arrangement alleviates routing congestion by simplifying the paths that signals must traverse, thereby reducing network complexity. Furthermore, reducing reliance on multiple metal layers facilitates a more straightforward and cost-effective manufacturing process and potentially improves signal integrity due to shorter interconnect lengths. The disclosed embodiments also introduce a hybrid floorplanning approach that combines sequential and parallel placement of accumulators used to collect PSUMs. This design also aims to alleviate routing congestion by combining the advantages of a sequential system (reduced complexity and metal usage) with the higher connectivity of a parallel configuration. This hybrid model offers a balanced approach that can adapt to varying design constraints and performance requirements, providing a versatile framework that maintains signal integrity and reduces crosstalk even in dense circuit architectures. As used herein, the terms "about" and "substantially" generally refer to a value of a given quantity that may vary depending on the particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., +10%, ±20%, or ±30% of the value). The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the disclosed embodiments. Those skilled in the art will understand that they can easily use the disclosed embodiments as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the disclosed embodiments, and that various changes, substitutions, and modifications may be made to these equivalent constructions without departing from the spirit and scope of the disclosed embodiments. 100: Memory device 120: Memory array 120a: First memory unit 120b: Second memory unit 120c: Third memory unit 120d: Fourth memory unit 122a-122h: Input 140: First calculation unit 142: First partial sum 160: Second calculation unit 162: Second partial sum 180: Global calculation unit 182: Partial sum 200: Third local accumulator 210: CIM 7 220: Third calculation unit 222: Third partial sum 310: CIM 6 320: Fourth calculation unit 322: Fourth partial sum 340: Fifth calculation unit 342: Fifth partial sum 600, 700: Methods 602, 604, 606, 608, 705, 710, 715: Operations The various aspects of the present disclosure may be best understood from the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion. FIG1 illustrates a block diagram of a memory device 100 according to some embodiments of the present disclosure. FIG2 illustrates a detailed schematic diagram of the memory device 100 of FIG1 according to some embodiments of the present disclosure. FIG3 illustrates a detailed schematic diagram of the memory device 100 of FIG1 according to some embodiments of the present disclosure. FIG4 illustrates a detailed schematic diagram of the memory device 100 of FIG2 according to some embodiments of the present disclosure. FIG5 illustrates a detailed schematic diagram of the memory device 100 of FIG3 according to some embodiments of the present disclosure. FIG6 is a flow chart of an exemplary method for manufacturing the memory device 100 of FIG1 according to some embodiments of the present disclosure. FIG7 is a flow chart of an exemplary method for manufacturing the memory device 100 according to some embodiments of the present disclosure. Domestic deposit information (please note in the order of deposit organization, date, and number) None Foreign deposit information (please note in the order of deposit country, organization, date, and number) None 100:Memory device 120:Memory array 122a~122d: Input 140: First computing unit 142: Part I and 160: Second computing unit 162: Part II and 180: Global Computing Unit 182: Partial Sum

Claims

1. A memory device comprising: a memory array including a plurality of memory cells for storing a plurality of weights of a neural network; a first computing unit for receiving the stored weights from the memory cells and generating a first partial sum based on the stored weights; and a second computing unit for receiving the stored weights and the first partial sum from the memory cells and generating a second partial sum based on the stored weights and the first partial sum, wherein the second computing unit is sequentially coupled to the first computing unit; A first route selection track group is used to send the first part from the first computing unit to the second computing unit; A second route selection track group is used to send the second part from the second computing unit, wherein the number of route selection tracks in the first route selection track group is less than the number of route selection tracks in the second route selection track group; And a global computing unit for accumulating multiple multiplied partial sums from the first computing unit and the second computing unit, wherein the global computing unit is inserted and located between the complex memory cell subarrays of the memory array.

2. The memory device as claimed in claim 1, wherein the first computing unit and the second computing unit are directly interconnected.

3. The memory device as claimed in claim 1, comprising: a third computing unit for receiving the storage weights and the second partial sum from the memory units, and generating a third partial sum based on the storage weights and the second partial sum, wherein the third computing unit is sequentially coupled to the first computing unit and the second computing unit, wherein the third computing unit and the first computing unit are located in the same metallization layer.

4. The memory device as claimed in claim 1, comprising: a fourth computing unit for receiving storage weights from the memory units and generating a fourth partial sum based on the storage weights; and a fifth computing unit for receiving the storage weights from the memory units and generating a fifth partial sum based on the storage weights, wherein the first computing unit is coupled in parallel to the fourth computing unit and the fifth computing unit to receive the fourth partial sum and the fifth partial sum, and to generate the first partial sum.

5. The memory device as claimed in claim 4, wherein the fourth computing unit and the first computing unit are located in different metallization layers, and the fourth computing unit and the fifth computing unit are located in the same metallization layer.

6. The memory device as claimed in claim 1, wherein the first computing unit is inserted between the memory cell subarrays, and the second computing unit is inserted between the memory cell subarrays.

7. The memory device as claimed in claim 1, wherein the first computing unit generates the first partial sum by multiplying an input activation vector element with the storage weights in one of the memory cell subarrays.

8. A memory device comprising: a substrate; a memory cell array having a plurality of memory cell subarrays formed on the substrate and for storing a plurality of weights of a neural network; a first local accumulator formed on a first metal layer and for receiving the stored weights from the memory cell subarrays and generating a first partial sum based on the stored weights; a second local accumulator formed on the first metal layer and for receiving the stored weights from the memory cell subarrays and the first partial sum, and generating a second partial sum based on the stored weights and the first partial sum, wherein the second local accumulator is sequentially coupled to the first local accumulator on the first metal layer; and a fourth local accumulator formed on a second metal layer and for receiving the stored weights from the memory cell subarrays and generating a fourth partial sum based on the stored weights. A fifth local accumulator, formed on the second metal layer, is used to receive the memory weights from the memory cell subarrays and generate a fifth partial sum based on the memory weights, wherein the first local accumulator is coupled in parallel to the fourth local accumulator and the fifth local accumulator to receive the fourth partial sum and the fifth partial sum, and generate the first partial sum; and a global computing unit is used to accumulate multiple multiplied partial sums from the first local accumulator and the second local accumulator, wherein the global computing unit is inserted and located between the memory cell subarrays.

9. The memory device as claimed in claim 8, wherein the fourth local accumulator and the first local accumulator are located in different metal layers, and the fourth local accumulator and the fifth local accumulator are located in the same metallization layer, wherein the fourth local accumulator is interconnected with the first local accumulator via a via structure, and wherein the fifth local accumulator is interconnected with the first local accumulator via the via structure.

10. A method of manufacturing a memory device, comprising the steps of: providing a substrate; forming a memory cell array having a plurality of memory cell subarrays on a front side of the substrate; forming a first local accumulator on a first metal layer on the front side of the substrate; forming a second local accumulator on the first metal layer, wherein the first local accumulator is sequentially coupled to the second local accumulator on the first metal layer; forming a fourth local accumulator and a fifth local accumulator on a second metal layer different from the first metal layer; forming a via structure, wherein the fourth local accumulator is interconnected with the first local accumulator via the via structure, and the fifth local accumulator is interconnected with the first local accumulator via the via structure; and a global computing unit for accumulating a plurality of multiplied partial sums from the first local accumulator and the second local accumulator, wherein the global computing unit is inserted and located between the memory cell subarrays.

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