Semiconductor device and method of forming the same

Abstract

In a method for fabricating a nano-field-effect transistor, source and drain first trenches are formed in a fin, the fin comprising a plurality of first nanostructures and a plurality of second nanostructures alternately formed thereon. A first semiconductor layer is disposed at the bottom portion of the source and drain first trenches and extends to the bottommost nanostructure. A sidewall passivation layer is formed in the source and drain first trenches above the sidewalls of the plurality of first nanostructures, and internal spacers are formed on the sidewalls of the plurality of second nanostructures. A second semiconductor layer is deposited in the source and drain first trenches above the first semiconductor layer to cover the sidewall passivation layer of the first nanostructures.

Description

Technical Field

[0001] none Prior Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using lithography to pattern these material layers to form circuit components and elements. The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, with the reduction of the minimum feature size, additional problems have emerged that need to be addressed. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 illustrates an example of a nano-structured field-effect transistor (nano-FET) in a three-dimensional view according to some embodiments of this disclosure. Figures 2, 3, 4, and 5 are cross-sectional views A-A' (shown in Figure 1) of an intermediate stage in the fabrication of a nano-FET according to some embodiments of the present disclosure. Figures 6A and 6B are cross-sectional views B-B' of an intermediate stage in the fabrication of a nano-FET according to some embodiments of the present disclosure (shown in Figure 1). Figures 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 11C, 12A, 12B, 12C, 12D, 12E, 12F, 12G, 13A, 13B, 13C, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 18C, 19A, 19B, 19C, 20A, 20B, and 20C are cross-sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments of this disclosure. Figures 21A, 21B, and 21C are cross-sectional views of nano-FETs according to some embodiments of the present disclosure. Figures 22A and 22B are cross-sectional views of nano-FETs according to some embodiments of the present disclosure. Figures 23A, 23B, and 23C illustrate cross-sectional views of intermediate stages in the fabrication of source / drain regions of two or more nano-FETs on a substrate according to some embodiments of the present disclosure. Figures 24A, 24B, 25A, 25B, 26A, 26B, 27A, and 27B illustrate cross-sectional views of passivation layers in the source / drain regions of a nano-FET according to some embodiments of the present disclosure. Figure 28 illustrates a process flow diagram for manufacturing a nano-FET according to some embodiments of this disclosure. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature depicted in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0007] In various embodiments, in a nano-FET, fabricating a passivation layer between the source / drain regions and one or more channels (e.g., nanosheets) can reduce the source-drain current of the nano-FET. Different nano-FETs with varying numbers of passivation layers fabricated between the source / drain regions and channels can be generated at different locations on the substrate. Therefore, the source-drain current of the nano-FET may differ at different locations on the substrate.

[0008] Additionally, when deposition and / or etching are used in the fabrication of source / drain regions, elements in the source / drain regions may migrate into the channel region during deposition, or etching may alter the channel region size, thereby affecting the critical dimension. Therefore, a passivation layer can be used between the source / drain regions and the channel region to prevent element migration between the source / drain regions and / or to prevent modification of the critical dimension.

[0009] The following embodiments describe a specific scenario involving a chip including a nano-FET. However, various embodiments can also be applied to chips including other types of transistors (e.g., fin field-effect transistors, planar transistors, or the like) that replace or are combined with nano-FETs.

[0010] Figure 1 illustrates an example of a nano-structured field-effect transistor (nano-FET) in a three-dimensional view according to some embodiments of the present disclosure. Figure 1 shows an example nano-FET (e.g., nanowire FET, nanosheet FET, or similar) in a three-dimensional view, wherein some features of the nano-FET are omitted for ease of illustration. The nano-FET may be a nanosheet field-effect transistor (NSFET), a nanowire field-effect transistor (NWFET), a gate-all-around field-effect transistor (GAAFET), or similar.

[0011] A nano-FET includes a nanostructure 55 (e.g., a nanosheet, nanowire, or similar) above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region for the nano-FET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. An isolation region 68 is disposed between adjacent fins 66, and the fins may protrude above and from adjacent isolation regions 68. Although the isolation region 68 is described / illustrated as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Additionally, although the bottom portion of the fin 66 is illustrated as a single material continuous with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent isolation regions 68.

[0012] A gate dielectric layer 100 is located above the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 55. A gate electrode 102 (e.g., an electrode) is located above the gate dielectric layer 100 to form a gate structure. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102. The epitaxial source / drain regions 92 may refer to a source or a drain, individually or collectively, depending on the context.

[0013] Figure 1 further illustrates the reference cross-sections used in the following figures. Cross-section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nano-FET. Cross-section B-B' is perpendicular to cross-section A-A' and parallel to the longitudinal axis of the nano-FET fin 66, and in a direction, for example, between the epitaxial source / drain regions 92 of the nano-FET. Cross-section C-C' is parallel to cross-section A-A' and extends through the epitaxial source / drain regions of the nano-FET. For clarity, the following figures refer to these reference cross-sections.

[0014] Some of the embodiments described herein are discussed in the context of nano-FETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Additionally, some embodiments are envisioned for use in planar devices such as planar FETs, or in fin field-effect transistors (finFETs).

[0015] Figures 2, 3, 4, and 5 are cross-sectional views A-A' (shown in Figure 1) of an intermediate stage in the fabrication of a nano-FET according to some embodiments of the present disclosure. In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on the substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0016] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nano-FET; the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nano-FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0017] Further, in Figure 2, a multilayer stack 64 may be formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A, 51B, and 51C (collectively referred to as first semiconductor layer 51) and second semiconductor layers 53A, 53B, and 53C (collectively referred to as second semiconductor layer 53). For illustrative purposes and as discussed in more detail below, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region for a nano-FET in the p-type region 50P. Alternatively, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form a channel region for a nano-FET in the n-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region for a nano-FET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region for a nano-FET in the p-type region 50P.

[0018] In other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form channel regions for a nano-FET in both the n-type region 50N and the p-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form non-FET channel regions in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon, or another semiconductor material) and may be formed simultaneously.

[0019] For illustrative purposes, the multilayer stack 64 is illustrated as three layers including each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each of the layers in the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for use in a p-type nano-FET (such as silicon germanium, or the like), and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for use in an n-type nano-FET (such as silicon, silicon carbon, or the like). For illustrative purposes, the multilayer stack 64 is illustrated as having a bottom semiconductor layer suitable for use in a p-type nano-FET. In some embodiments, a multilayer stack 64 may be formed such that the bottom layer is a semiconductor layer suitable for use with an n-type nano-FET.

[0020] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity to each other. Thus, in the n-type region 50N, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type nano-FET. Similarly, in the p-type region 50P, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type nano-FET.

[0021] As shown in Figure 3, according to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar, or combinations thereof. Etching can be anisotropic. The nanostructures 55 formed by etching multilayer stack 64 can further define first nanostructures 52A, 52B, and 52C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and second nanostructures 54A, 54B, and 54C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be further collectively referred to as nanostructure 55.

[0022] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, one or more optical lithography processes (including dual patterning or multi-patterning processes) can be used to pattern the fins 66 and nanostructures 55. Generally, dual or multi-patterning processes combine optical lithography with self-alignment processes, thereby allowing the production of patterns with, for example, smaller pitches than that achievable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0023] For illustrative purposes, Figure 3 shows the fins 66 in the n-type region 50N and the p-type region 50P as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or thinner than the width of the fins 66 in the p-type region 50P. Furthermore, although the fins 66 and the nanostructures 55 are shown to always have a consistent width, in other embodiments, the fins 66 and / or the nanostructures 55 may have tapered sidewalls, such that the width of the fins 66 and / or the nanostructures 55 increases continuously in the direction toward the substrate 50. In such embodiments, the nanostructures 55 may have different widths and be trapezoidal in shape.

[0024] In Figure 4, a shallow trench isolation (STI) region 68 may be formed adjacent to the fin 66. The STI region 68 may be formed by depositing an insulating material over the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66. The insulating material may be an oxide, nitride, or similar compound of silicon oxide, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), similar methods, or combinations thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In this embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is depicted as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the surfaces of the substrate 50, fins 66, and nanostructures 55. A filler material, such as those described above, may then be formed over the liner.

[0025] Next, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back process, a combination thereof, or similar, may be used. The planarization process exposes the nanostructure 55 such that the nanostructure 55 is flush with the top surface of the insulating material after the planarization process is completed.

[0026] Next, the insulating material is recessed to form STI regions 68. The recessed insulating material causes the upper portions of the fins 66 in the n-type region 50N and p-type region 50P to protrude from between adjacent STI regions 68. Furthermore, the top surface of the STI region 68 may have a flat surface, a convex surface, a concave surface (such as a dish shape), or a combination thereof, as shown in the figure. The top surface of the STI region 68 can be formed into a flat, convex, and / or concave shape by appropriate etching. Acceptable etching processes, such as those selectively etching the insulating material (e.g., etching the insulating material at a faster rate than etching the fins 66 and the nanostructure 55), can be used to recess the STI region 68. For example, an oxide removal process using, for instance, dilute hydrofluoric acid (dHF) can be used.

[0027] The above is only one example of how the process described in Figures 2 through 4 forms the fins 66 and nanostructures 55. In some embodiments, the fins 66 and / or nanostructures 55 may be formed using a masking process and an epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trenches, and the dielectric layer may be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure may include the alternating semiconductor materials described above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be in-situ doped during growth, which avoids prior and / or subsequent implantation, although in-situ doping and implantation doping may be used together.

[0028] Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and the resulting nanostructure 52) and the second semiconductor layer 53 (and the resulting nanostructure 54) are illustrated and discussed herein as containing the same material in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be made of different materials, or may be formed in different orders in the p-type region 50P and the n-type region 50N.

[0029] Further, in Figure 4, suitable wells (not shown separately) can be formed in fin 66, nanostructure 55, and / or STI region 68. In embodiments with different well types, photoresist or other masks (not shown separately) can be used to achieve different implantation steps for n-type region 50N and p-type region 50P. For example, photoresist can be formed over fin 66 and STI region 68 in n-type region 50N and p-type region 50P. The photoresist is patterned to expose p-type region 50P. The photoresist can be formed using spin-on techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurity implantation in n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, or the like implanted in the region, with a concentration in the range of about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. After implantation, the photoresist is removed, for example by an acceptable ashing process.

[0030] Before or after implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin-on techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from implanting into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, or the like implanted in the region, with a concentration in the range of about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. After implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0031] Following implantation in the n-type region 50N and p-type region 50P, an annealing process can be performed to repair implantation damage and reactivate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which avoids implantation, although in-situ doping and implantation doping can be used together. In some embodiments, initially, a dummy gate structure is created over the channel region to protect the channel region from etching. The removal of the dummy gate structure and the fabrication of the gate structure will be discussed below with reference to Figures 16A, 16B, 17A, 17B, 18A, and 18C. To create the dummy gate structure, a dummy dielectric layer is patterned using a masking layer. Then, the dielectric and possible layers are retained over the channel region, and the masking layer and dielectric layer are etched from other regions.

[0032] In Figure 5, the mask layer 78 is patterned using acceptable optical lithography techniques. The pattern of the mask layer 78 can then be transferred to the dummy gate layer 76 and the dummy dielectric layer 71 to form dummy gates and dummy gate dielectrics, respectively. The dummy gates cover individual channel regions of the fins 66. The patterned mask layer 78 can be used to separate each dummy gate from adjacent dummy gate entities. The dummy gates may also have a length direction substantially perpendicular to the length direction of the individual fins 66.

[0033] A dummy dielectric layer 71 may be formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 71 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 76 is formed over the dummy dielectric layer 71, and a masking layer 78 is formed over the dummy gate layer 76. The dummy gate layer 76 may be deposited over the dummy dielectric layer 71, followed by planarization, for example, by CMP. The masking layer 78 may be deposited over the dummy gate layer 76. The dummy gate layer 76 may be a conductive or non-conductive material and may be selected from the group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (polySiGe), metal nitrides, metal silicates, metal oxides, and metals. The dummy gate layer 76 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 76 can be made of other materials that have high etch selectivity for etching the isolation region. The mask layer 78 can include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 76 and a single mask layer 78 are formed across the n-type region 50N and the p-type region 50P. It should be noted that, for illustrative purposes only, the dummy dielectric layer 71 is shown covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 71 can be deposited such that the dummy dielectric layer 71 covers the STI region 68, thereby extending the dummy dielectric layer 71 between the dummy gate layer 76 and the STI region 68.

[0034] Figures 6A and 6B are cross-sectional B-B' views (shown in Figure 1) of an intermediate stage in the fabrication of a nano-FET according to some embodiments of this disclosure. As shown in Figure 6A and as described with respect to Figure 5, a dummy dielectric layer 71, a dummy gate layer 76, and a masking layer 78 are formed over the nanostructure 55 of the fin 66. As shown in Figure 6B, after photolithography, the dummy dielectric layer 71, the dummy gate layer 76, and the masking layer 78 remain only over the channel region and are removed from the other regions of both the n-type region 50N and the p-type region 50P.

[0035] Figures 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 11C, 12A, 12B, 12C, 12D, 12E, 12F, 12G, 13A, 13B, 13C, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 18C, 19A, 19B, 19C, 20A, 20B, and 20C are cross-sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments of this disclosure. Figures 13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A illustrate the reference section A-A' shown in Figure 1. Figures 7B, 8B, 9B, 10B, 11B, 11C, 12A, 12B, 12C, 12D, 12E, 13B, 14B, 15B, 16B, 17B, 18B, 19B, and 20B illustrate the reference section B-B' shown in Figure 1. Figures 7A, 8A, 9A, 10A, 11A, 12A, 12C, 12F, 12G, 13C, 18C, 19C, and 20C illustrate the reference section C-C' shown in Figure 1. Figures 7A, 8A, 9A, 10A, 11A, 12A, 12C, 12F, 12G, 13C, 18C, 19C, and 20C illustrate sections of both the n-type region 50N and the p-type region 50P.

[0036] In Figures 7A and 7B, a first spacer layer 80 and a second spacer layer 82 are formed over the structures shown in Figure 5 and either Figure 6A or Figure 6B. The first spacer layer 80 and the second spacer layer 82 are then patterned to serve as spacers for forming self-aligned source / drain regions. In Figures 7A and 7B, the first spacer layer 80 is formed on the top surface of the STI region 68; on the top surface and sidewalls of the fin 66, nanostructure 55, and masking layer 78; and on the sidewalls of the dummy gate layer 76 and the dummy dielectric layer 71. The second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed from silicon oxide, silicon nitride, silicon oxynitride, or the like using techniques such as thermal oxidation, or deposited by CVD, ALD, or the like. The second spacer layer 82 may be formed of a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.

[0037] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, implantation for the lightly doped source / drain (LDD) region (not shown separately) can be performed. In embodiments with different device types, similar to the implantation described in Figure 4 above, a mask such as a photoresist can be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type (e.g., p-type) of impurity can be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. Subsequently, a mask such as a photoresist can be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type (e.g., n-type) of impurity can be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the previously described n-type impurities, and the p-type impurity can be any of the previously described p-type impurities. Lightly doped source / drain regions can have impurity concentrations ranging from about 1 x 10¹⁵ atoms / cm³ to about 1 x 10¹⁹ atoms / cm³. Annealing can be used to repair implant damage and activate implanted impurities.

[0038] In Figures 8A and 8B, a first spacer layer 80 and a second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 serve to self-align the subsequently formed source / drain regions and to protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. Suitable etching processes can be used to etch the first spacer layer 80 and the second spacer layer 82, such as isotropic etching processes (e.g., wet etching processes), anisotropic etching processes (e.g., dry etching processes), or the like. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, such that the first spacer layer 80 can be used as an etch stop layer when the second spacer layer 82 is patterned, and that the second spacer layer 82 can be used as a mask when the first spacer layer 80 is patterned. For example, an anisotropic etching process can be used to etch the second spacer layer 82, where the first spacer layer 80 serves as the etch stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83, as shown in Figure 8A. Subsequently, the exposed portion of the first spacer layer 80 is etched, while the second spacer 83 acts as a mask, thereby forming the first spacer 81, as shown in Figure 8A.

[0039] As shown in Figure 8A, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. As shown in Figure 8B, in some embodiments, the second spacer layer 82 may be removed above the first spacer layer 80 adjacent to the masking layer 78, the dummy gate layer 76, and the dummy dielectric layer 71, and the first spacer 81 is disposed on the sidewalls of the masking layer 78, the dummy gate layer 76, and the dummy dielectric layer 71. In other embodiments, a portion of the second spacer layer 82 may remain above the first spacer layer 80 adjacent to the masking layer 78, the dummy gate layer 76, and the dummy dielectric layer 71.

[0040] It should be noted that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences may also be used. For example, fewer or additional spacers may be used, steps in a different sequence may be used (e.g., the first spacer 81 may be patterned before the deposition of the second spacer layer 82), additional spacers may be formed and removed, and / or the like. Furthermore, different structures and steps may be used to form n-type and p-type devices.

[0041] In Figures 9A and 9B, according to some embodiments, a trench 86 is formed in the fin 66, nanostructure 55, and substrate 50. The trench 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. As shown in Figure 9A, the top surface of the STI region 68 may be flush with the bottom surface of the trench 86. In various embodiments, the fin 66 may be etched such that the bottom surface of the trench 86 is disposed below the top surface of the STI region 68; or similarly. The trench 86 may be formed by etching the fin 66, nanostructure 55, and substrate 50 using anisotropic etching processes, such as RIE, NBE, or similar methods. During the etching process used to form the trench 86, a first spacer 81, a second spacer 83, and a masking layer 78 shield portions of the fin 66, nanostructure 55, and substrate 50. Each layer and / or fin 66 in the nanostructure 55 can be etched using a single etching process or multiple etching processes. A timed etching process can be used to stop etching the trench 86 after it has reached the desired depth.

[0042] In Figures 10A and 10B, the exposed portions of the sidewalls of the layer formed of the first semiconductor material (e.g., the first nanostructure 52) in the multilayer stack 64 are etched to form a sidewall recess 88 in the n-type region 50N. Similarly, the exposed portions of the sidewalls of the layer formed of the second semiconductor material (e.g., the second nanostructure 54) in the multilayer stack 64 are etched to form a sidewall recess 88 in the p-type region 50P. Although the sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall recess 88 are shown as straight in Figure 10B, the sidewalls may be concave or convex. Isotropic etching processes, such as wet etching, or similar methods, can be used to etch the sidewalls. A mask (not shown) can be used to protect the p-type region 50P, while an etchant selective for the first semiconductor material is used to etch the first nanostructure 52 in the n-type region 50N, such that the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52. Similarly, a mask (not shown) can be used to protect the n-type region 50N, while an etchant selective for the second semiconductor material is used to etch the second nanostructure 54 in the p-type region 50P, such that the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, a dry etching process having tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to etch the sidewalls of the first nanostructure 52 in the n-type region 50N, and a wet or dry etching process having hydrogen fluoride, another fluorine-based etchant, or the like can be used to etch the sidewalls of the second nanostructure 54 in the p-type region 50P.

[0043] In Figures 11A, 11B, and 11C, a first internal spacer 90 is formed in the sidewall groove 88. The first internal spacer 90 can be formed by depositing an internal spacer layer (not shown separately) over the structure shown in Figures 10A and 10B. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the trench 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced by the corresponding gate structures.

[0044] The internal spacer layer can be deposited using conformal deposition processes such as CVD, ALD, or similar. The internal spacer layer may comprise materials such as silicon nitride or silicon oxynitride, although any suitable material may be used, such as low-k materials having a k value less than about 3.5. The internal spacer layer can then be etched anisotropically to form the first internal spacer 90. Although the outer sidewalls of the first internal spacer 90 are shown flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and the sidewalls of the first nanostructure 52 in the p-type region 50P, the outer sidewalls of the first internal spacer 90 may extend beyond or recess from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0045] Furthermore, although the outer sidewall of the first internal spacer 90 is shown as straight in Figure 11B, the outer sidewall of the first internal spacer 90 may be concave or convex. As an example, Figure 11C illustrates an embodiment where the sidewall of the first nanostructure 52 is concave, the outer sidewall of the first internal spacer 90 is concave, and the first internal spacer 90 is recessed from the sidewall of the second nanostructure 54 in the n-type region 50N. An embodiment is also illustrated where the sidewall of the second nanostructure 54 is concave, the outer sidewall of the first internal spacer 90 is concave, and the first internal spacer 90 is recessed from the sidewall of the first nanostructure 52 in the p-type region 50P. The internal spacer layer can be etched by anisotropic etching processes such as RIE, NBE, or similar methods. The first internal spacer 90 can be used to prevent subsequent etching processes (such as etching processes used to form gate structures) from damaging the subsequently formed source / drain regions (such as the epitaxial source / drain regions 92 described below with respect to Figures 12A, 12B, 12C, 12D and 12E).

[0046] As shown in Figures 12A, 12B, 12C, 12D, and 12E, the bottom portion 230 (e.g., the bottom layer) of the trench 86 (source / drain recess or source / drain trench) is filled with semiconductor material, and the bottom portion 230 is filled up to the bottommost nanostructure 54 and the bottommost internal spacer 90 of the nanostructure 54. In some embodiments, the bottom portion 230 is a mesa or portion of a mesa connecting two or more semiconductor fins 66 and is filled with SiGe semiconductor material, such as Si 1-xGe x, where x is between 0.1 and 0.4, for example, 0.35. In some embodiments, the SiGe semiconductor material of the bottom portion 230 includes doped material. In some embodiments, the bottom portion 230 is filled up to the bottommost nanostructure, for example, the bottommost nanostructure 52 in the n-type region 50N and the p-type region 50P. The internal spacer 90 has a concave, convex, or flat shape on the sidewall of the groove 86.

[0047] In some embodiments, in the n-type region 50N, the nanostructure 52 is subsequently removed and replaced with a gate structure surrounding the nanostructure 54. In the p-type region 50P, the nanostructure 54 can then be removed and replaced with a gate structure surrounding the nanostructure 52 (see gate structure 195 in Figure 19B). As shown below, the nanostructure 54 disposed between adjacent pairs of epitaxial source / drain regions 92 serves as a channel region (nanoline or nanosheet) or channel, and the gate structure surrounds the channel region in the n-type region 50N. The nanostructure 52 can serve as the channel region in the p-type region 50P.

[0048] In Figure 12B, the source / drain trench 86 is exposed to plasma material 120, such as a oriented plasma material or plasma bundle, thereby creating a passivation layer 232, such as a sidewall passivation layer, over the nanostructure 54 of the n-type region 50N and the nanostructure 52 of the p-type region 50P. Another layer 234, i.e., a passivation layer, is created over the bottom portion 230. The passivation layer 232 prevents etching of the nanostructures 54 or 52 and prevents material migration from the bottom portion 230 into the nanostructures 54 or 52, thus maintaining the critical dimension (CD) of the nano-FET. In some embodiments, the plasma material 120 includes one of silicon, carbon, oxygen, nitrogen, or combinations thereof, and the passivation layer 232 can be fabricated from materials such as silicon nitride, silicon dioxide, silicon carbide, amorphous silicon, polycrystalline silicon, or crystalline silicon. In some embodiments, the passivation layer 232 prevents the nanostructure 54 from acting as a channel region, thereby reducing the current of the nano-FET. In some embodiments as shown in Figure 12B, the plasma material 120 may be oriented, and the direction may change from downward to tilted to the right or left, such that the plasma material impacts the sidewalls of the nanostructure or the top of the bottom portion 230. In some embodiments, the passivation layer 232 is formed over the n-type region 50N nanostructure 54 or the p-type region 50P nanostructure 52 by atomic layer deposition of silicon, carbon, oxygen, nitrogen, or combinations thereof, followed by thermal annealing at at least 900 degrees Celsius. Additionally, layer 234 may be formed over the bottom portion 230 by atomic layer deposition followed by thermal annealing as described above. In some embodiments, plasma-based nitrogen diffuses into the nanostructure 54 and, together with silicon in the nanostructure 54, forms a passivation layer 232. The passivation layer 232 is a crystalline SiN barrier layer that prevents Ge diffusion into the nanostructure 54. Additionally, the SiN barrier layer prevents etching of the nanostructure 54 and maintains critical dimensions. In some embodiments where plasma-based nitrogen diffuses into the nanostructure 54, polycrystalline SiN and / or amorphous SiN are formed in the passivation layer 232.

[0049] As shown in Figure 12C, layer 234 is removed from the material above bottom portion 230, and then another semiconductor layer 240 is deposited above bottom portion 230. By removing layer 234, bottom portion 230 and semiconductor layer 240 become electrically connected to each other. Semiconductor layer 240 may cover one or more of an n-type region 50N nanostructure 54 or a p-type region 50P nanostructure 52, for example, one or both. Semiconductor layer 240 also covers passivation layer 232. The nanostructure 54 or 52 with passivation layer 232 covered by semiconductor layer 240 may not contribute to the current of nano-FET, thus reducing the current of nano-FET. Therefore, depending on how much current the nano-FET requires, one or more of the nanostructure 54 or 52 with passivation layer 232 may be covered by semiconductor layer 240. In some embodiments, nanostructures 54 or 52 may not have a passivation layer 232, or nanostructures 54 or 52 may not be covered by semiconductor layer 240. The passivation layer may be formed at a temperature between 300°C and 700°C. In some embodiments, semiconductor layer 240 comprises a SiGe semiconductor material, such as Si 1-xGe x, where x is between 0.1 and 0.3, for example, 0.25. In some embodiments, the SiGe semiconductor material of semiconductor layer 240 comprises a doped material. In some embodiments, after layer 234 is removed, residual elements, such as nitrogen residue, remain on top of bottom portion 230. Bottom portion 230, semiconductor layer 240, and epitaxial source / drain regions 92 may have an n-type (e.g., arsenic or phosphorus) doping concentration or a p-type (e.g., boron) doping concentration. In some embodiments, the doping concentration of the epitaxial source / drain region 92 is between about 10¹⁹ cm⁻³ and about 10²¹ cm⁻³, and the doping concentration of the bottom portion 230 and the semiconductor layer 240 is between about 10¹⁴ cm⁻³ and about 10¹⁶ cm⁻³.

[0050] As shown in Figure 12D, the passivation layer 232 not covered by the semiconductor layer 240 is removed by an etching process, such as a wet or dry etching process, for example, anisotropic or directional dry etching. As shown in Figure 12E, after removing the passivation layer 232 not covered by the semiconductor layer 240, an epitaxial source / drain region 92 is grown over the semiconductor layer 240 in the source / drain trench 86. The epitaxial source / drain region 92 covers the remaining nanostructures 54 or 52 that do not have the passivation layer 232 and is in electrical contact with the nanostructures 54 and 52. In some embodiments, the semiconductor fin 66 includes up to 10 nanostructures 54 or 52. Of the 10 nanostructures 54 or 52, there may be none, one, two, or up to nine nanostructures 54 or 52 that have the passivation layer 232 (closed channel) and can be covered by the semiconductor layer 240, and therefore may not contribute to the current of the nano-FET. The remaining nanostructures 54 or 52 may not have a passivation layer 232 (open channel) and may be in contact with the epitaxial source / drain region 92, thus potentially contributing to the current of the nano-FET. The number of open and closed channels in the nano-FET can be determined depending on how much current may be required in the location of the semiconductor / integrated circuit. In some embodiments, the epitaxial source / drain region 92 comprises a SiGe semiconductor material, such as Si 1-xGe x, where x is between 0.1 and 0.3, for example, 0.2, and may include doped materials.

[0051] As shown in Figure 12E, epitaxial source / drain regions 92 are formed in trench 86. In some embodiments, the epitaxial source / drain regions 92 can apply stress to the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. As shown in Figure 12E, the epitaxial source / drain regions 92 are formed in trench 86 such that each dummy gate layer 76 is disposed between individual adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gate layers 76, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit with the gate of the subsequently formed nano-FET.

[0052] The epitaxial source / drain region 92 in the n-type region 50N (e.g., an NMOS region) can be formed by shielding the p-type region 50P (e.g., a PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a trench 86 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nano-FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 92 may have a surface protruding from an individual upper surface of the nanostructure 55 and may have facets.

[0053] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by shielding the n-type region 50N (e.g., an NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a trench 86 in the p-type region 50P. The epitaxial source / drain region 92 can include any acceptable material suitable for a p-type nano-FET. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 can include a material that applies compressive strain to the first nanostructure 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain region 92 can also have a surface protruding from an individual surface of the multilayer stack 64 and can have a facet.

[0054] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 may be implanted with dopants to form the source / drain region, similar to the previously described process for forming lightly doped source / drain regions, followed by annealing. The source / drain region may have an impurity concentration between approximately 1 x 10¹⁹ atoms / cm³ and approximately 1 x 10²¹ atoms / cm³. The n-type and / or p-type impurities used for the source / drain region may be any of the impurities described previously. In some embodiments, the epitaxial source / drain region 92 may be in-situ doped during growth.

[0055] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has small planes that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these small planes cause adjacent epitaxial source / drain regions 92 of the same two or more nano-FETs to merge, as shown in Figure 12F. In other embodiments, as shown in Figure 12G, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed. In one embodiment, a first spacer 81 may be formed to the top surface of the STI region 68 to block epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewalls of the nanostructure 55 to further block epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 can be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 68, as shown in Figures 12F and 12G, which are cross-sections C-C' and also show the bottom portion 230 in the trench 86 and the semiconductor layer 240.

[0056] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used in the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different doping concentrations. In some embodiments, the first semiconductor material layer 92A may have a doping concentration lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0057] In Figures 13A, 13B, and 13C, a first interlayer dielectric (ILD) 96 is deposited over the structure shown in Figure 5. The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include silicon phosphorus glass (PSG), borosilicate glass (BSG), borosilicate phosphorus glass (BPSG), silica-free glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, the mask layer 78, and the first spacer 81. CESL 94 may include dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which have a different etch rate than the material overlying the first ILD 96.

[0058] In Figures 14A and 14B, a planarization process such as CMP can be performed to align the top surface of the first ILD 96 with the top surface of the dummy gate layer 76 or the masking layer 78. The planarization process can also remove portions of the masking layer 78 and the first spacer 81 along the sidewalls of the masking layer 78 on the dummy gate layer 76. After the planarization process, the top surfaces of the dummy gate layer 76, the first spacer 81, and the first ILD 96 are flush within the process variation. Therefore, the top surface of the dummy gate layer 76 is exposed through the first ILD 96. In some embodiments, the masking layer 78 can be retained, in which case the planarization process aligns the top surface of the first ILD 96 with the top surfaces of the masking layer 78 and the first spacer 81.

[0059] In Figures 15A and 15B, a dummy gate layer 76 and a masking layer 78 (if present) are removed in one or more etching steps to form a recess 98. A portion of the dummy dielectric layer 71 in the recess 98 is also removed. In some embodiments, the dummy gate layer 76 and the dummy dielectric layer 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (multiple) reactive gases to selectively etch the dummy gate layer 76 at a faster rate than etching the first ILD 96 or the first spacer 81. Each recess 98 exposes and / or covers a portion of the nanostructure 55, which serves as a channel region in the subsequently completed nano-FET. The portion of the nanostructure 55 serving as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 71 may serve as an etch stop layer while the dummy gate layer 76 is etched. Then, after removing the dummy gate layer 76, the dummy dielectric layer 71 can be removed.

[0060] In Figures 16A and 16B, the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed, thereby extending the groove 98. The first nanostructure 52 can be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process (such as wet etching or the like) using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructures 54A, 54B, and 54C comprise, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH₄OH), or the like can be used to remove the first nanostructure 52 in the n-type region 50N.

[0061] The second nanostructure 54 in the p-type region 50P can be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process (such as wet etching or the like) using an etchant selective for the material of the second nanostructure 54, while the first nanostructure 52, the substrate 50, and the STI region 68 remain relatively unetched compared to the second nanostructure 54. In embodiments where the second nanostructure 54 comprises, for example, SiGe and the first nanostructure 52 comprises, for example, Si or SiC, hydrogen fluoride, another fluorine-based etchant, or the like can be used to remove the second nanostructure 54 in the p-type region 50P.

[0062] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P can be formed simultaneously, for example, by removing the first nanostructure 52 from both the n-type region 50N and the p-type region 50P, or by removing the second nanostructure 54 from both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions of the n-type nano-FET and the p-type nano-FET can have the same material composition, such as silicon, silicon germanium, or the like. Figures 21A, 21B, and 21C illustrate structures resulting from such embodiments, wherein the channel regions in both the p-type region 50P and the n-type region 50N are provided by the second nanostructure 54 and include, for example, silicon.

[0063] Figures 17A and 17B show a gate dielectric layer 100 and a gate electrode 102, which can be formed for replacing the gate. The gate dielectric layer 100 is conformally deposited in a recess 98. In the n-type region 50N, the gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the second nanostructure 54; in the p-type region 50P, the gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 100 can also be deposited on the top surface of the first ILD 96, CESL 94, the first spacer 81, and the STI region 68.

[0064] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. Methods for forming the gate dielectric layer 100 may include molecular-beam deposition (MBD), ALD, PECVD, and the like.

[0065] Gate electrodes 102 are deposited above gate dielectric layer 100 and fill the remaining portion of groove 98. Gate electrodes 102 may include metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode 102 is shown in Figures 17A and 17B, gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler material. Any combination of layers constituting gate electrode 102 may be deposited between adjacent layers in the second nanostructure 54 and between the second nanostructure 54A and substrate 50 in n-type region 50N, and between adjacent layers in the first nanostructure 52 in p-type region 50P.

[0066] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material; the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers; and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0067] After filling the recess 98, a planarization process such as CMP can be performed to remove excess material from the gate dielectric layer 100 and the gate electrode 102 above the top surface of the first ILD 96. The remaining material of the gate electrode 102 and the gate dielectric layer 100 thus form an alternative gate structure for the resulting nano-FET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure". In some embodiments, the nanostructure 54 in the n-type region 50N is configured (e.g., formed or designed) to serve as a channel for the nano-FET; the nanostructure 52 in the p-type region 50P is configured (e.g., formed or designed) to serve as a channel for the nano-FET. Additionally, the nanostructures 52 in the n-type region 50N, including the gate electrode 102, are electrically connected to each other and are formed or designed to serve as part of the gate structure. The nanostructures 54 in the p-type region 50P, including the gate electrode 102, are electrically connected to each other, forming or being designed to serve as part of the gate structure.

[0068] Figures 18A, 18B, and 18C show a gate structure (including a gate dielectric layer 100 and a corresponding overlying gate electrode 102) that can be recessed to form a groove directly above the gate structure and between opposing portions of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or the like) is filled into the groove, followed by a planarization process to remove excess dielectric material extending above the first ILD 96. The subsequently formed gate contacts penetrate the gate mask 104 to contact the top surface of the recessed gate electrode 102.

[0069] As further shown in Figures 18A, 18B, and 18C, a second ILD 106 is deposited over the first ILD 96 and the gate shield 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable method such as CVD, PECVD, or the like.

[0070] Figures 19A, 19B, and 19C show that a second ILD 106, a first ILD 96, a CESL 94, and a gate mask 104 can be etched to form a recess 108 exposing the surfaces of the epitaxial source / drain regions 92 and / or the gate structure. The recess 108 can be formed by etching using an anisotropic etching process (such as RIE, NBE, or similar). In some embodiments, a first etching process can be used to etch the recess 108 through the second ILD 106 and the first ILD 96; a second etching process can be used to etch through the gate mask 104; and then a third etching process can be used to etch through the CESL 94. A mask, such as a photoresist, can be formed and patterned over the second ILD 106 to mask portions of the second ILD 106 from the first and second etching processes. In some embodiments, the etching process may over-etch, so that the groove 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the groove 108 may be flush with (e.g., at the same level, or at the same distance from the substrate) or below (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or gate structure. Although Figure 19B illustrates the groove 108 as exposing the epitaxial source / drain region 92 and gate structure in the same cross-section, in various embodiments, the epitaxial source / drain region 92 and gate structure may be exposed in different cross-sections, thereby reducing the risk of short circuits in subsequently formed contacts. After forming the groove 108, a siliconized region 110 is formed above the epitaxial source / drain region 92. In some embodiments, the silicate region 110 is formed by first depositing a metal (not shown) (such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof) capable of reacting with the underlying epitaxial source / drain region 92 semiconductor material (e.g., silicon, silicon-germanium, germanium) over the exposed portion of the epitaxial source / drain region 92 to form a silicate or germanide region, followed by performing a thermal annealing process to form the silicate region 110. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicate region 110 is referred to as a silicate region, it may also be a germanide region or a germanide-siliconized region (e.g., a region containing both silicate and germanide). In an embodiment, the silicate region 110 comprises TiSi and has a thickness ranging from about 2 nm to about 10 nm. As shown in Figure 19B, in the n-type region 50N, the nanostructure 52 can be removed and replaced with a gate structure 195 surrounding the nanostructure 54. In the p-type region 50P, the nanostructure 54 can be removed and replaced with a gate structure 195 surrounding the nanostructure 52. Each gate structure 195 includes a gate electrode 102 in contact with the gate dielectric layer 100. In each nano-FET, the gate structures 195, for example, the gate electrodes 102 of the gate structures 195 are in contact with each other.In the p-type region 50P, the gate structure 195 contacts the nanostructure 52, allowing the gate electrode 102 to be connected to the nanostructure 52 through the gate dielectric layer 100. In the n-type region 50N, the gate structure 195 contacts the nanostructure 54, allowing the gate electrode 102 to be connected to the nanostructure 54 through the gate dielectric layer 100.

[0071] Figures 20A, 20B, and 20C show contacts 112 and 114 (also referred to as contact plugs) that may be formed in the recess 108. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material and are electrically coupled to an underlying conductive feature (e.g., the gate electrode 102 and / or the silicate region 110 in the illustrated embodiment). Contact 114 is electrically coupled to the gate electrode 102 and may be referred to as a gate contact; contact 112 is electrically coupled to the silicate region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. Planarization processes such as CMP can be performed to remove excess material from the surface of the second ILD 106.

[0072] Figures 21A, 21B, and 21C are cross-sectional views of nano-FETs according to some embodiments of the present disclosure. Figure 21A illustrates a reference cross-section A-A' shown in Figure 1. Figure 21B illustrates a reference cross-section B-B' shown in Figure 1. Figure 21C illustrates a reference cross-section C-C' shown in Figure 1. In Figures 21A, 21B, and 21C, the same reference numerals indicate the same devices formed by the same process as those in Figures 22A, 22B, and 22C. However, in Figures 21A to 21C, the channel regions in the n-type region 50N and the p-type region 50P include the same material. For example, a second nanostructure 54 comprising silicon provides channel regions for the p-type nano-FET in the p-type region 50P and the n-type nano-FET in the n-type region 50N. The structures shown in Figures 21A, 21B, and 21C can be formed, for example, by simultaneously removing the first nanostructure 52 from both the p-type region 50P and the n-type region 50N; depositing a gate dielectric layer 100 and a gate electrode 102P (e.g., suitable for a gate in a p-type nano-FET) around the second nanostructure 54 in the p-type region 50P; and depositing a gate dielectric layer 100 and a gate electrode 102N (e.g., suitable for a gate in an n-type nano-FET) around the second nanostructure 54 in the n-type region 50N. In such embodiments, as described above, the material of the epitaxial source / drain region 92 may differ in the n-type region 50N compared to the p-type region 50P. Figure 21B also shows a portion 225 of the source / drain trench 86. For different passivation layers, part 225 is described in Figures 24A, 24B, 25A, 25B, 26A, 26B, 27A, and 27B.

[0073] Figures 22A and 22B are cross-sectional views of a nano-FET according to some embodiments of the present disclosure. Figure 22A is identical to Figure 20B, except that in Figure 22A, two channels are closed, for example, closed, and only one channel is open. Figure 22B is identical to Figure 20B, except that in Figure 22B, no channels are closed, and all channels are open and conducting.

[0074] Figures 23A, 23B, and 23C illustrate cross-sectional views of intermediate stages of the source / drain regions of two or more nano-FETs 222 (e.g., semiconductor devices) fabricated on a substrate according to some embodiments of the present disclosure. Figures 23A, 23B, and 23C show two or more nano-FETs 222 on substrate 50 located at different positions in the semiconductor circuit. Figure 23A shows one nano-FET 222 having more open channels than closed channels, and another nano-FET 222 at another location having more closed channels than open channels. Figure 23B shows one nano-FET 222 with no closed channels and all channels open, and another nano-FET 222 at another location having one closed channel and two open channels. Figure 23C shows one nano-FET 222 with one closed channel and two open channels, and another nano-FET 222 at another location having two closed channels and one open channel. Each nano-FET 222 is either in the n-type region 50N or in the p-type region 50P.

[0075] Figures 24A, 24B, 25A, 25B, 26A, 26B, 27A, and 27B illustrate cross-sectional views of a passivation layer in the source / drain region of a nano-FET according to some embodiments of the present disclosure. Figure 24A shows a portion 225 of Figure 23B and shows a bottom portion 230, a semiconductor layer 240, and an epitaxial source / drain region 92. Figures 24A and 24B also show a passivation layer 232 having a rectangular shape, a height 233 between 3 nm and 20 nm, and a thickness 243 between 0.2 nm and 5 nm. Figure 24B shows a portion 235 of Figure 24A. The bottom portion 230, the semiconductor layer 240, and the epitaxial source / drain region 92 have the same width 237 between 10 nm and 50 nm, and the semiconductor layer 240 has a height 231 between 3 nm and 90 nm. The height 239 of nanostructure 54 and the height 241 of internal spacers 90 with the same height as nanostructure 54 are between 3 nm and 15 nm. The distance 249 between the individual bottom of the upper internal spacer 90 and the bottom of the epitaxial source / drain region 92 is between 5 nm and 10 nm. The distance 247 between the individual bottom of the lower internal spacer 90 and the bottom of the semiconductor layer 240 is between 5 nm and -10 nm relative to the bottom of the lower internal spacer 90, which serves as a reference line. The edge 2304 of the passivation layer 232 is between 5 nm and -10 nm relative to the edge 2302 of the semiconductor layer 240 (as a reference point) (e.g., a 10 nm recess). In addition, the angles 2306 and 2308 between the top surface of the passivation layer 232 and the face of the passivation layer 232 are between 80 degrees and 110 degrees. In addition, the height 239 of the nanostructure 54 is smaller than the height 233 of the passivation layer 232, so that the passivation layer 232 effectively covers the nanostructure 54.

[0076] Figures 25A and 25B show the same items as Figures 24A and 24B, such that the same element symbols are used for the same features, and have the same values ​​or value ranges. The difference is that the passivation layer 232 has a pointed shape pointing towards the center of the semiconductor layer 240. In addition, angle 2308 is between 130 degrees and 150 degrees, and angle 2306 is between 40 degrees and 60 degrees.

[0077] Figures 26A and 26B show the same items as Figures 24A and 24B, such that the same element symbols are used for the same features, and have the same values ​​or value ranges. The difference is that the passivation layer 232 has a lens shape. Additionally, angle 2308 is between 70 and 90 degrees, and angle 2306 is between 70 and 90 degrees. Angles 2306 and 2308 are calculated from the bottom surface of the epitaxial source / drain region 92 to the surface tangent to the lens shape, as shown in the figure.

[0078] Figures 27A and 27B show the same items as Figures 24A and 24B, such that the same element symbols are used for the same features, and have the same values ​​or value ranges. The difference is that the passivation layer 232 has a dish shape. Additionally, angle 2308 is between 90 degrees and 130 degrees, and angle 2306 is between 50 degrees and 90 degrees. Angles 2306 and 2308 are calculated from the bottom surface of the epitaxial source / drain region 92 to the surface tangent to the lens shape, as shown in the figure.

[0079] Figure 28 illustrates a flow chart of a process 2800 for fabricating a nano-FET according to some embodiments of this disclosure. The steps in the process are shown in Figures 11A, 11B, 11C, 12A, 12B, 12C, 13A, 13B, 13C, 22A, 22B, 23A, 23B, and 23C. At step 2810, source and drain trenches are formed in a first fin. As shown in Figure 13A, source and drain trenches 86 are formed in a semiconductor fin 66. In some embodiments, the first fin includes a plurality of first nanostructures 54 and a plurality of second nanostructures 52 arranged alternately with each other.

[0080] At step 2820, internal spacers are formed on the sidewalls of the plurality of second nanostructures. As shown in Figure 11C, internal spacers 90 may be formed on the sidewalls of the plurality of second nanostructures 52 in the n-type region 50N, and internal spacers 90 are not formed on the sidewalls of the plurality of first nanostructures 54 in the n-type region 50N. As described above, in the n-type region, the second nanostructures 52 may be removed and replaced with the gate structure 195 of the nano-FET. The first nanostructures 54 may be used as channels for the nano-FET, and the gate structure 195 surrounds the channels.

[0081] In step 2830, a first semiconductor layer is deposited at the bottom portion of the source and drain trenches. As shown in Figure 22A, the first semiconductor layer is deposited at the bottom portion 230 of the source and drain trenches 86.

[0082] At step 2840, a sidewall passivation layer is formed above the sidewalls of the plurality of first nanostructures in the source and drain trenches. As shown in Figure 22B, the passivation layer 232 is formed above the sidewalls of the plurality of first nanostructures 54 in the source and drain trenches 86.

[0083] At step 2850, a second semiconductor layer is deposited over the first semiconductor layer in the source and drain trenches. As shown in Figure 22C, semiconductor layer 240 is deposited over bottom portion 230. Semiconductor layer 240 covers one of the first nanostructure 54 and passivation layer 232. The uncovered passivation layer 232 is then removed.

[0084] As described in the above embodiments, a passivation layer can be fabricated between the source / drain region and the channel. The passivation layer prevents current from flowing through one or more channels, thereby reducing the source-drain current of the nano-FET. The passivation layer also prevents element migration between the channel and the source / drain region during deposition and etching, and prevents etching of the channel region, thus maintaining critical dimensions.

[0085] According to an embodiment, a method includes forming source and drain first trenches in a first fin, such that the first fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed thereon. The method also includes forming internal spacers on the sidewalls of the plurality of second nanostructures and depositing a first semiconductor layer at the bottom portion of the source and drain first trenches, such that the first semiconductor layer extends to the bottommost nanostructure. The method also includes forming a sidewall passivation layer over the sidewalls of the plurality of first nanostructures in the source and drain first trenches, and depositing a second semiconductor layer over the first semiconductor layer in the source and drain first trenches, such that the second semiconductor layer covers the sidewall passivation layer of the first nanostructures at the sidewalls of the source and drain first trenches.

[0086] In one embodiment, a top passivation layer is formed over the first semiconductor layer, and the method further includes removing the top passivation layer from the first semiconductor layer before depositing the second semiconductor layer. In another embodiment, a first fin is formed over a semiconductor substrate, and the method further includes forming source and drain second trenches in a second fin formed over the semiconductor substrate, wherein the second fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed thereon; depositing a third semiconductor layer at the bottom portion of the source and drain second trenches, wherein the third semiconductor layer extends to the bottommost nanostructure; forming a sidewall passivation layer over the sidewalls of the plurality of first nanostructures in the source and drain second trenches; and depositing a fourth semiconductor layer over the third semiconductor layer in the source and drain second trenches, the fourth semiconductor layer covering the sidewall passivation layers of zero or more first nanostructures in the source and drain second trenches. In an embodiment, the method further includes guiding nitrogen plasma to the sidewalls of a plurality of first nanostructures in source and drain trenches to form a sidewall passivation layer comprising crystalline silicon nitride. The sidewall passivation layer has a rectangular shape, covers at least the sidewalls of the plurality of first nanostructures, and has a thickness between 1 nm and 3 nm. In an embodiment, the method further includes removing the sidewall passivation layer above the sidewalls of the group of a plurality of first nanostructures not covered by the second semiconductor layer, and epitaxially growing source and drain regions above the second semiconductor layer, wherein the source and drain regions are electrically connected to the first nanostructures not covered by the second semiconductor layer. Additionally, the third semiconductor layer has an n-type doping concentration of approximately 10¹⁵ cm⁻³, the second semiconductor layer has an n-type doping concentration of approximately 10¹⁶ cm⁻³, and the source and drain regions have an n-type doping concentration of approximately 10²⁰ cm⁻³. In one embodiment, the second semiconductor layer covers one or more additional sidewall passivation layers of the first nanostructure, and the epitaxially grown source and drain regions are in electrical contact with the first nanostructure not covered by the second semiconductor layer. In another embodiment, the second semiconductor layer covers the sidewall passivation layers of two or more first nanostructures at the sidewalls of the source and drain trenches, and the source and drain regions are not electrically connected to the two or more first nanostructures covered by the second semiconductor layer.

[0087] According to an embodiment, a method includes forming a source / drain trench in a semiconductor fin, wherein the semiconductor fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed thereon. The method further includes depositing a first SiGe layer at the bottom portion of the source / drain trench, wherein the first SiGe layer extends to the bottommost nanostructure, and forming a sidewall passivation layer on the sidewalls of the plurality of first nanostructures in the source / drain trench. The method further includes depositing a second SiGe layer over the first SiGe layer in the source / drain trench, wherein the second SiGe layer covers the sidewall passivation layers of one or more of the first nanostructures at the sidewalls of the source / drain trench.

[0088] In one embodiment, semiconductor fins are formed above a semiconductor substrate, and source / drain trenches extend into the semiconductor substrate. In another embodiment, a top passivation layer is formed above a first SiGe layer, the method further comprising: removing the top passivation layer from above the first SiGe layer before depositing a second SiGe layer. In another embodiment, internal spacers are formed on the sidewalls of a plurality of second nanostructures in the source / drain trenches before depositing the first SiGe layer. In another embodiment, the method further comprises guiding one of nitrogen plasma, silicon plasma, carbon plasma, or oxygen plasma to the sidewalls of the plurality of first nanostructures in the source / drain trenches to form a sidewall passivation layer. The passivation layer is formed at a temperature between 300°C and 700°C. In another embodiment, the sidewall passivation layer covering the sidewalls of the plurality of first nanostructures is recessed by approximately 10 nm. In an embodiment, the first nanostructure is a gate channel, and the method further includes epitaxially growing a source and a drain region above the second SiGe layer in a source / drain trench, and replacing the second nanostructure with the gate structure.

[0089] According to an embodiment, the semiconductor device includes a first semiconductor fin above a semiconductor substrate, wherein the first semiconductor fin includes a plurality of first nanostructures. The semiconductor device also includes a gate electrode surrounding each of the plurality of first nanostructures and a source and drain region in the first semiconductor fin, wherein each of the source and drain regions includes a first semiconductor layer covering at least one of the plurality of first nanostructures and a sidewall passivation layer on the sidewall of the at least one of the plurality of first nanostructures. The sidewall passivation layer is located between the first semiconductor layer and the at least one of the plurality of first nanostructures.

[0090] In an embodiment, each of the source and drain regions further includes a mesa above the semiconductor substrate, wherein the first semiconductor fin is above the mesa, and the mesa includes SiGe. In an embodiment, the plurality of first nanostructures includes up to six first nanostructures, wherein up to two first nanostructures include a sidewall passivation layer and are covered by a first semiconductor layer. In an embodiment, the first nanostructure includes a semiconductor gate channel. In an embodiment, the sidewall passivation layer includes one or more of silicon nitride, silicon dioxide, amorphous silicon, or silicon carbide. In an embodiment, the plurality of first nanostructures in the first semiconductor fin are n-type semiconductors, and the semiconductor device further includes: a second semiconductor fin, which includes a plurality of second nanostructures that are p-type semiconductors, wherein no first nanostructure in the first semiconductor fin includes a sidewall passivation layer, and wherein at least one of the second nanostructures of the second semiconductor fin includes a sidewall passivation layer.

[0091] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0092] 20: Divider 50:Substrate 50N: n-type region 50P: p-type area 51: First semiconductor layer 51A~51C: First semiconductor layer 52: First nanostructure 52A~52C: First nanostructure 53: Second semiconductor layer 53A~53C: Second semiconductor layer 54: Second nanostructure 54A~54C: Second nanostructure 55: Nanostructure 64: Multi-layer stacking 66: Fins 68: Quarantine Zone 71: Dummy Dielectric Layer 76: Virtual gate layer 78: Masking layer 80: First Spacing Layer 81: First spacer 82: Second spacer layer 83: Second spacer 86: Trench 88: Sidewall Groove 90: First internal spacer 92: Epitaxial Source / Drain Region 92A: First semiconductor material layer 92B: Second semiconductor material layer 92C: Third semiconductor material layer 94:CESL 96: First ILD 98: Groove 100: Gate dielectric layer 102: Gate electrode 102N: Gate electrode 102P: Gate electrode 104: Gate shield 106: Second ILD 108: Groove 110: Silicone region 112: Source / Drain Contact 114: Gate Contact 120: Plasma Materials 222: nano-FET 225: Part 230: Bottom section 231: Altitude 232: Passivation layer 233: Height 234: Layer 235: Part 237: Width 239: Altitude 240: Semiconductor layer 241: Altitude 243: Thickness 247: Distance 249: Distance 2302~2304: Edge 2306~2308: Angle 2800: Process 2810~2850: Steps

[0093] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of forming a semiconductor device, comprising: forming a plurality of source and drain first trenches in a first fin, wherein the first fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed thereon, wherein the first fin is formed above a semiconductor substrate; forming a plurality of source and drain second trenches in a second fin formed above the semiconductor substrate, wherein the second fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed thereon; forming a plurality of internal spacers on a plurality of sidewalls of the second nanostructures; depositing a first semiconductor layer at a plurality of bottom portions of the source and drain first trenches, wherein the first semiconductor layer extends to a bottommost nanostructure; and forming a plurality of sidewall passivation layers above the plurality of sidewalls of the first nanostructures in the source and drain first trenches; A second semiconductor layer is deposited above the first semiconductor layer in the first source and drain trenches, wherein the second semiconductor layer covers the sidewall passivation layers in a first nanostructure at multiple sidewalls of the first source and drain trenches; a third semiconductor layer is deposited at multiple bottom portions of the second source and drain trenches, wherein the third semiconductor layer extends to a bottommost nanostructure; multiple sidewall passivation layers are formed above the sidewalls of the first nanostructures in the second source and drain trenches; and a fourth semiconductor layer is deposited above the third semiconductor layer in the second source and drain trenches, wherein the fourth semiconductor layer covers the sidewall passivation layers in zero or more first nanostructures at multiple sidewalls of the second source and drain trenches.

2. The method as claimed in claim 1, wherein a top passivation layer is formed over the first semiconductor layer, the method further comprising: removing the top passivation layer from over the first semiconductor layer before depositing the second semiconductor layer.

3. The method as described in claim 1, wherein the sidewall passivation layers comprise crystalline silicon nitride.

4. A method of forming a semiconductor device, comprising: forming a source / drain first trench in a first semiconductor fin, wherein the first semiconductor fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed thereon; forming a source / drain second trench in a second semiconductor fin, wherein the second semiconductor fin includes a plurality of first nanostructures and a plurality of second nanostructures alternately formed thereon; depositing a first SiGe layer at a bottom portion of one of the source / drain first trenches, wherein the first SiGe layer extends to a bottommost nanostructure; forming a plurality of sidewall passivation layers above a plurality of sidewalls of the first nanostructures in the source / drain first trench; and depositing a second SiGe layer above the first SiGe layer in the source / drain first trench, wherein the second SiGe layer covers the sidewall passivation layers of one or more first nanostructures at a plurality of sidewalls of the source / drain first trench; A third SiGe layer is deposited at the bottom portion of one of the source / drain second trenches, wherein the third SiGe layer extends to a bottommost nanostructure; a plurality of sidewall passivation layers are formed above the plurality of sidewalls of the first nanostructures in the source / drain second trench; and a fourth SiGe layer is deposited above the third SiGe layer in the source / drain second trench, wherein the fourth SiGe layer covers the sidewall passivation layers in zero or more of the first nanostructures at the plurality of sidewalls of the source / drain second trench.

5. The method as described in claim 4, wherein a top passivation layer is formed over the first SiGe layer, the method further comprising: removing the top passivation layer from over the first SiGe layer before depositing the second SiGe layer.

6. The method as described in claim 4, wherein, prior to depositing the first SiGe layer, a plurality of internal spacers are formed on the plurality of sidewalls of the second nanostructures in the source / drain first trench.

7. The method as described in claim 4 further comprises: guiding one of nitrogen plasma, silicon plasma, carbon plasma, or oxygen plasma to the sidewalls of the first nanostructures in the source / drain first trench to form the sidewall passivation layers, wherein the sidewall passivation layers are formed at a temperature between 300 degrees Celsius and 700 degrees Celsius.

8. A semiconductor device comprising: a first semiconductor fin above a semiconductor substrate, wherein the first semiconductor fin includes a plurality of first nanostructures; a second semiconductor fin including a plurality of second nanostructures; a gate electrode surrounding each of the first nanostructures; a plurality of first source and drain regions respectively in a plurality of source and drain first trenches of the first semiconductor fin, wherein each of the first source and drain regions includes: a first semiconductor layer located at the bottom portion of one of the source and drain first trenches; a second semiconductor layer located on the first semiconductor layer, wherein the second semiconductor layer covers at least one of the first nanostructures; a plurality of first sidewall passivation layers on a plurality of sidewalls of the at least one of the first nanostructures, wherein the first sidewall passivation layers are between the second semiconductor layer and the at least one of the first nanostructures; A plurality of second source and drain regions are respectively located in a plurality of source and drain second trenches of the second semiconductor fin, wherein each of the second source and drain regions comprises: a third semiconductor layer located at the bottom portion of one of the source and drain second trenches; a plurality of second sidewall passivation layers on a plurality of sidewalls of at least one of the second nanostructures; and a fourth semiconductor layer located on the third semiconductor layer, wherein the fourth semiconductor layer covers zero or more of the second sidewall passivation layers in the second nanostructures at the plurality of sidewalls of the source and drain second trenches.

9. The semiconductor device as claimed in claim 8, wherein the first nanostructures comprise a maximum of six first nanostructures, and wherein a maximum of two first nanostructures include the sidewall passivation layers and are covered by the first semiconductor layer.

10. The semiconductor device as claimed in claim 8, wherein the first nanostructures in the first semiconductor fin are n-type semiconductors, and the second nanostructures in the second semiconductor fin are p-type semiconductors.

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